drivers/hwtracing/intel_th/intel_th.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Intel(R) Trace Hub data structures
   4  *
   5  * Copyright (C) 2014-2015 Intel Corporation.
   6  */
   7
   8 #ifndef __INTEL_TH_H__
   9 #define __INTEL_TH_H__
  10
  11 #include <linux/irqreturn.h>
  12
  13 /* intel_th_device device types */
  14 enum {
  15         /* Devices that generate trace data */
  16         INTEL_TH_SOURCE = 0,
  17         /* Output ports (MSC, PTI) */
  18         INTEL_TH_OUTPUT,
  19         /* Switch, the Global Trace Hub (GTH) */
  20         INTEL_TH_SWITCH,
  21 };
  22
  23 struct intel_th_device;
  24
  25 /**
  26  * struct intel_th_output - descriptor INTEL_TH_OUTPUT type devices
  27  * @port:       output port number, assigned by the switch
  28  * @type:       GTH_{MSU,CTP,PTI}
  29  * @scratchpad: scratchpad bits to flag when this output is enabled
  30  * @multiblock: true for multiblock output configuration
  31  * @active:     true when this output is enabled
  32  * @wait_empty: wait for device pipeline to be empty
  33  *
  34  * Output port descriptor, used by switch driver to tell which output
  35  * port this output device corresponds to. Filled in at output device's
  36  * probe time by switch::assign(). Passed from output device driver to
  37  * switch related code to enable/disable its port.
  38  */
  39 struct intel_th_output {
  40         int             port;
  41         unsigned int    type;
  42         unsigned int    scratchpad;
  43         bool            multiblock;
  44         bool            active;
  45 };
  46
  47 /**
  48  * struct intel_th_drvdata - describes hardware capabilities and quirks
  49  * @tscu_enable:        device needs SW to enable time stamping unit
  50  * @multi_is_broken:    device has multiblock mode is broken
  51  * @has_mintctl:        device has interrupt control (MINTCTL) register
  52  * @host_mode_only:     device can only operate in 'host debugger' mode
  53  */
  54 struct intel_th_drvdata {
  55         unsigned int    tscu_enable        : 1,
  56                         multi_is_broken    : 1,
  57                         has_mintctl        : 1,
  58                         host_mode_only     : 1;
  59 };
  60
  61 #define INTEL_TH_CAP(_th, _cap) ((_th)->drvdata ? (_th)->drvdata->_cap : 0)
  62
  63 /**
  64  * struct intel_th_device - device on the intel_th bus
  65  * @dev:                device
  66  * @drvdata:            hardware capabilities/quirks
  67  * @resource:           array of resources available to this device
  68  * @num_resources:      number of resources in @resource array
  69  * @type:               INTEL_TH_{SOURCE,OUTPUT,SWITCH}
  70  * @id:                 device instance or -1
  71  * @host_mode:          Intel TH is controlled by an external debug host
  72  * @output:             output descriptor for INTEL_TH_OUTPUT devices
  73  * @name:               device name to match the driver
  74  */
  75 struct intel_th_device {
  76         struct device           dev;
  77         struct intel_th_drvdata *drvdata;
  78         struct resource         *resource;
  79         unsigned int            num_resources;
  80         unsigned int            type;
  81         int                     id;
  82
  83         /* INTEL_TH_SWITCH specific */
  84         bool                    host_mode;
  85
  86         /* INTEL_TH_OUTPUT specific */
  87         struct intel_th_output  output;
  88
  89         char            name[];
  90 };
  91
  92 #define to_intel_th_device(_d)                          \
  93         container_of((_d), struct intel_th_device, dev)
  94
  95 /**
  96  * intel_th_device_get_resource() - obtain @num'th resource of type @type
  97  * @thdev:      the device to search the resource for
  98  * @type:       resource type
  99  * @num:        number of the resource
 100  */
 101 static inline struct resource *
 102 intel_th_device_get_resource(struct intel_th_device *thdev, unsigned int type,
 103                              unsigned int num)
 104 {
 105         int i;
 106
 107         for (i = 0; i < thdev->num_resources; i++)
 108                 if (resource_type(&thdev->resource[i]) == type && !num--)
 109                         return &thdev->resource[i];
 110
 111         return NULL;
 112 }
 113
 114 /*
 115  * GTH, output ports configuration
 116  */
 117 enum {
 118         GTH_NONE = 0,
 119         GTH_MSU,        /* memory/usb */
 120         GTH_CTP,        /* Common Trace Port */
 121         GTH_LPP,        /* Low Power Path */
 122         GTH_PTI,        /* MIPI-PTI */
 123 };
 124
 125 /**
 126  * intel_th_output_assigned() - if an output device is assigned to a switch port
 127  * @thdev:      the output device
 128  *
 129  * Return:      true if the device is INTEL_TH_OUTPUT *and* is assigned a port
 130  */
 131 static inline bool
 132 intel_th_output_assigned(struct intel_th_device *thdev)
 133 {
 134         return thdev->type == INTEL_TH_OUTPUT &&
 135                 (thdev->output.port >= 0 ||
 136                  thdev->output.type == GTH_NONE);
 137 }
 138
 139 /**
 140  * struct intel_th_driver - driver for an intel_th_device device
 141  * @driver:     generic driver
 142  * @probe:      probe method
 143  * @remove:     remove method
 144  * @assign:     match a given output type device against available outputs
 145  * @unassign:   deassociate an output type device from an output port
 146  * @enable:     enable tracing for a given output device
 147  * @disable:    disable tracing for a given output device
 148  * @irq:        interrupt callback
 149  * @activate:   enable tracing on the output's side
 150  * @deactivate: disable tracing on the output's side
 151  * @fops:       file operations for device nodes
 152  * @attr_group: attributes provided by the driver
 153  *
 154  * Callbacks @probe and @remove are required for all device types.
 155  * Switch device driver needs to fill in @assign, @enable and @disable
 156  * callbacks.
 157  */
 158 struct intel_th_driver {
 159         struct device_driver    driver;
 160         int                     (*probe)(struct intel_th_device *thdev);
 161         void                    (*remove)(struct intel_th_device *thdev);
 162         /* switch (GTH) ops */
 163         int                     (*assign)(struct intel_th_device *thdev,
 164                                           struct intel_th_device *othdev);
 165         void                    (*unassign)(struct intel_th_device *thdev,
 166                                             struct intel_th_device *othdev);
 167         void                    (*enable)(struct intel_th_device *thdev,
 168                                           struct intel_th_output *output);
 169         void                    (*trig_switch)(struct intel_th_device *thdev,
 170                                                struct intel_th_output *output);
 171         void                    (*disable)(struct intel_th_device *thdev,
 172                                            struct intel_th_output *output);
 173         /* output ops */
 174         irqreturn_t             (*irq)(struct intel_th_device *thdev);
 175         void                    (*wait_empty)(struct intel_th_device *thdev);
 176         int                     (*activate)(struct intel_th_device *thdev);
 177         void                    (*deactivate)(struct intel_th_device *thdev);
 178         /* file_operations for those who want a device node */
 179         const struct file_operations *fops;
 180         /* optional attributes */
 181         struct attribute_group  *attr_group;
 182
 183         /* source ops */
 184         int                     (*set_output)(struct intel_th_device *thdev,
 185                                               unsigned int master);
 186 };
 187
 188 #define to_intel_th_driver(_d)                                  \
 189         container_of((_d), struct intel_th_driver, driver)
 190
 191 #define to_intel_th_driver_or_null(_d)          \
 192         ((_d) ? to_intel_th_driver(_d) : NULL)
 193
 194 /*
 195  * Subdevice tree structure is as follows:
 196  * + struct intel_th device (pci; dev_{get,set}_drvdata()
 197  *   + struct intel_th_device INTEL_TH_SWITCH (GTH)
 198  *     + struct intel_th_device INTEL_TH_OUTPUT (MSU, PTI)
 199  *   + struct intel_th_device INTEL_TH_SOURCE (STH)
 200  *
 201  * In other words, INTEL_TH_OUTPUT devices are children of INTEL_TH_SWITCH;
 202  * INTEL_TH_SWITCH and INTEL_TH_SOURCE are children of the intel_th device.
 203  */
 204 static inline struct intel_th_device *
 205 to_intel_th_parent(struct intel_th_device *thdev)
 206 {
 207         struct device *parent = thdev->dev.parent;
 208
 209         if (!parent)
 210                 return NULL;
 211
 212         return to_intel_th_device(parent);
 213 }
 214
 215 static inline struct intel_th *to_intel_th(struct intel_th_device *thdev)
 216 {
 217         if (thdev->type == INTEL_TH_OUTPUT)
 218                 thdev = to_intel_th_parent(thdev);
 219
 220         if (WARN_ON_ONCE(!thdev || thdev->type == INTEL_TH_OUTPUT))
 221                 return NULL;
 222
 223         return dev_get_drvdata(thdev->dev.parent);
 224 }
 225
 226 struct intel_th *
 227 intel_th_alloc(struct device *dev, struct intel_th_drvdata *drvdata,
 228                struct resource *devres, unsigned int ndevres);
 229 void intel_th_free(struct intel_th *th);
 230
 231 int intel_th_driver_register(struct intel_th_driver *thdrv);
 232 void intel_th_driver_unregister(struct intel_th_driver *thdrv);
 233
 234 int intel_th_trace_enable(struct intel_th_device *thdev);
 235 int intel_th_trace_switch(struct intel_th_device *thdev);
 236 int intel_th_trace_disable(struct intel_th_device *thdev);
 237 int intel_th_set_output(struct intel_th_device *thdev,
 238                         unsigned int master);
 239 int intel_th_output_enable(struct intel_th *th, unsigned int otype);
 240
 241 enum th_mmio_idx {
 242         TH_MMIO_CONFIG = 0,
 243         TH_MMIO_SW = 1,
 244         TH_MMIO_RTIT = 2,
 245         TH_MMIO_END,
 246 };
 247
 248 #define TH_POSSIBLE_OUTPUTS     8
 249 /* Total number of possible subdevices: outputs + GTH + STH */
 250 #define TH_SUBDEVICE_MAX        (TH_POSSIBLE_OUTPUTS + 2)
 251 #define TH_CONFIGURABLE_MASTERS 256
 252 #define TH_MSC_MAX              2
 253
 254 /* Maximum IRQ vectors */
 255 #define TH_NVEC_MAX             8
 256
 257 /**
 258  * struct intel_th - Intel TH controller
 259  * @dev:        driver core's device
 260  * @thdev:      subdevices
 261  * @hub:        "switch" subdevice (GTH)
 262  * @resource:   resources of the entire controller
 263  * @num_thdevs: number of devices in the @thdev array
 264  * @num_resources:      number of resources in the @resource array
 265  * @irq:        irq number
 266  * @num_irqs:   number of IRQs is use
 267  * @id:         this Intel TH controller's device ID in the system
 268  * @major:      device node major for output devices
 269  */
 270 struct intel_th {
 271         struct device           *dev;
 272
 273         struct intel_th_device  *thdev[TH_SUBDEVICE_MAX];
 274         struct intel_th_device  *hub;
 275         struct intel_th_drvdata *drvdata;
 276
 277         struct resource         resource[TH_MMIO_END];
 278         int                     (*activate)(struct intel_th *);
 279         void                    (*deactivate)(struct intel_th *);
 280         unsigned int            num_thdevs;
 281         unsigned int            num_resources;
 282         int                     irq;
 283         int                     num_irqs;
 284
 285         int                     id;
 286         int                     major;
 287 #ifdef CONFIG_MODULES
 288         struct work_struct      request_module_work;
 289 #endif /* CONFIG_MODULES */
 290 #ifdef CONFIG_INTEL_TH_DEBUG
 291         struct dentry           *dbg;
 292 #endif
 293 };
 294
 295 static inline struct intel_th_device *
 296 to_intel_th_hub(struct intel_th_device *thdev)
 297 {
 298         if (thdev->type == INTEL_TH_SWITCH)
 299                 return thdev;
 300         else if (thdev->type == INTEL_TH_OUTPUT)
 301                 return to_intel_th_parent(thdev);
 302
 303         return to_intel_th(thdev)->hub;
 304 }
 305
 306 /*
 307  * Register windows
 308  */
 309 enum {
 310         /* Global Trace Hub (GTH) */
 311         REG_GTH_OFFSET          = 0x0000,
 312         REG_GTH_LENGTH          = 0x2000,
 313
 314         /* Timestamp counter unit (TSCU) */
 315         REG_TSCU_OFFSET         = 0x2000,
 316         REG_TSCU_LENGTH         = 0x1000,
 317
 318         REG_CTS_OFFSET          = 0x3000,
 319         REG_CTS_LENGTH          = 0x1000,
 320
 321         /* Software Trace Hub (STH) [0x4000..0x4fff] */
 322         REG_STH_OFFSET          = 0x4000,
 323         REG_STH_LENGTH          = 0x2000,
 324
 325         /* Memory Storage Unit (MSU) [0xa0000..0xa1fff] */
 326         REG_MSU_OFFSET          = 0xa0000,
 327         REG_MSU_LENGTH          = 0x02000,
 328
 329         /* Internal MSU trace buffer [0x80000..0x9ffff] */
 330         BUF_MSU_OFFSET          = 0x80000,
 331         BUF_MSU_LENGTH          = 0x20000,
 332
 333         /* PTI output == same window as GTH */
 334         REG_PTI_OFFSET          = REG_GTH_OFFSET,
 335         REG_PTI_LENGTH          = REG_GTH_LENGTH,
 336
 337         /* DCI Handler (DCIH) == some window as MSU */
 338         REG_DCIH_OFFSET         = REG_MSU_OFFSET,
 339         REG_DCIH_LENGTH         = REG_MSU_LENGTH,
 340 };
 341
 342 /*
 343  * Scratchpad bits: tell firmware and external debuggers
 344  * what we are up to.
 345  */
 346 enum {
 347         /* Memory is the primary destination */
 348         SCRPD_MEM_IS_PRIM_DEST          = BIT(0),
 349         /* XHCI DbC is the primary destination */
 350         SCRPD_DBC_IS_PRIM_DEST          = BIT(1),
 351         /* PTI is the primary destination */
 352         SCRPD_PTI_IS_PRIM_DEST          = BIT(2),
 353         /* BSSB is the primary destination */
 354         SCRPD_BSSB_IS_PRIM_DEST         = BIT(3),
 355         /* PTI is the alternate destination */
 356         SCRPD_PTI_IS_ALT_DEST           = BIT(4),
 357         /* BSSB is the alternate destination */
 358         SCRPD_BSSB_IS_ALT_DEST          = BIT(5),
 359         /* DeepSx exit occurred */
 360         SCRPD_DEEPSX_EXIT               = BIT(6),
 361         /* S4 exit occurred */
 362         SCRPD_S4_EXIT                   = BIT(7),
 363         /* S5 exit occurred */
 364         SCRPD_S5_EXIT                   = BIT(8),
 365         /* MSU controller 0/1 is enabled */
 366         SCRPD_MSC0_IS_ENABLED           = BIT(9),
 367         SCRPD_MSC1_IS_ENABLED           = BIT(10),
 368         /* Sx exit occurred */
 369         SCRPD_SX_EXIT                   = BIT(11),
 370         /* Trigger Unit is enabled */
 371         SCRPD_TRIGGER_IS_ENABLED        = BIT(12),
 372         SCRPD_ODLA_IS_ENABLED           = BIT(13),
 373         SCRPD_SOCHAP_IS_ENABLED         = BIT(14),
 374         SCRPD_STH_IS_ENABLED            = BIT(15),
 375         SCRPD_DCIH_IS_ENABLED           = BIT(16),
 376         SCRPD_VER_IS_ENABLED            = BIT(17),
 377         /* External debugger is using Intel TH */
 378         SCRPD_DEBUGGER_IN_USE           = BIT(24),
 379 };
 380
 381 #endif