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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / iio / adc / ingenic-adc.c
blob34c03a264f746a6d86baec7b1a13a120a72a6a52
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ADC driver for the Ingenic JZ47xx SoCs
4 * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
5 *
6 * based on drivers/mfd/jz4740-adc.c
7 */
8
9 #include <dt-bindings/iio/adc/ingenic,adc.h>
10 #include <linux/clk.h>
11 #include <linux/iio/buffer.h>
12 #include <linux/iio/iio.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/iopoll.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/mutex.h>
20 #include <linux/platform_device.h>
21
22 #define JZ_ADC_REG_ENABLE 0x00
23 #define JZ_ADC_REG_CFG 0x04
24 #define JZ_ADC_REG_CTRL 0x08
25 #define JZ_ADC_REG_STATUS 0x0c
26 #define JZ_ADC_REG_ADSAME 0x10
27 #define JZ_ADC_REG_ADWAIT 0x14
28 #define JZ_ADC_REG_ADTCH 0x18
29 #define JZ_ADC_REG_ADBDAT 0x1c
30 #define JZ_ADC_REG_ADSDAT 0x20
31 #define JZ_ADC_REG_ADCMD 0x24
32 #define JZ_ADC_REG_ADCLK 0x28
33
34 #define JZ_ADC_REG_ENABLE_PD BIT(7)
35 #define JZ_ADC_REG_CFG_AUX_MD (BIT(0) | BIT(1))
36 #define JZ_ADC_REG_CFG_BAT_MD BIT(4)
37 #define JZ_ADC_REG_CFG_SAMPLE_NUM(n) ((n) << 10)
38 #define JZ_ADC_REG_CFG_PULL_UP(n) ((n) << 16)
39 #define JZ_ADC_REG_CFG_CMD_SEL BIT(22)
40 #define JZ_ADC_REG_CFG_TOUCH_OPS_MASK (BIT(31) | GENMASK(23, 10))
41 #define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0
42 #define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB 16
43 #define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB 8
44 #define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB 16
45
46 #define JZ_ADC_REG_ADCMD_YNADC BIT(7)
47 #define JZ_ADC_REG_ADCMD_YPADC BIT(8)
48 #define JZ_ADC_REG_ADCMD_XNADC BIT(9)
49 #define JZ_ADC_REG_ADCMD_XPADC BIT(10)
50 #define JZ_ADC_REG_ADCMD_VREFPYP BIT(11)
51 #define JZ_ADC_REG_ADCMD_VREFPXP BIT(12)
52 #define JZ_ADC_REG_ADCMD_VREFPXN BIT(13)
53 #define JZ_ADC_REG_ADCMD_VREFPAUX BIT(14)
54 #define JZ_ADC_REG_ADCMD_VREFPVDD33 BIT(15)
55 #define JZ_ADC_REG_ADCMD_VREFNYN BIT(16)
56 #define JZ_ADC_REG_ADCMD_VREFNXP BIT(17)
57 #define JZ_ADC_REG_ADCMD_VREFNXN BIT(18)
58 #define JZ_ADC_REG_ADCMD_VREFAUX BIT(19)
59 #define JZ_ADC_REG_ADCMD_YNGRU BIT(20)
60 #define JZ_ADC_REG_ADCMD_XNGRU BIT(21)
61 #define JZ_ADC_REG_ADCMD_XPGRU BIT(22)
62 #define JZ_ADC_REG_ADCMD_YPSUP BIT(23)
63 #define JZ_ADC_REG_ADCMD_XNSUP BIT(24)
64 #define JZ_ADC_REG_ADCMD_XPSUP BIT(25)
65
66 #define JZ_ADC_AUX_VREF 3300
67 #define JZ_ADC_AUX_VREF_BITS 12
68 #define JZ_ADC_BATTERY_LOW_VREF 2500
69 #define JZ_ADC_BATTERY_LOW_VREF_BITS 12
70 #define JZ4725B_ADC_BATTERY_HIGH_VREF 7500
71 #define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS 10
72 #define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986)
73 #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12
74 #define JZ4770_ADC_BATTERY_VREF 1200
75 #define JZ4770_ADC_BATTERY_VREF_BITS 12
76
77 #define JZ_ADC_IRQ_AUX BIT(0)
78 #define JZ_ADC_IRQ_BATTERY BIT(1)
79 #define JZ_ADC_IRQ_TOUCH BIT(2)
80 #define JZ_ADC_IRQ_PEN_DOWN BIT(3)
81 #define JZ_ADC_IRQ_PEN_UP BIT(4)
82 #define JZ_ADC_IRQ_PEN_DOWN_SLEEP BIT(5)
83 #define JZ_ADC_IRQ_SLEEP BIT(7)
84
85 struct ingenic_adc;
86
87 struct ingenic_adc_soc_data {
88 unsigned int battery_high_vref;
89 unsigned int battery_high_vref_bits;
90 const int *battery_raw_avail;
91 size_t battery_raw_avail_size;
92 const int *battery_scale_avail;
93 size_t battery_scale_avail_size;
94 unsigned int battery_vref_mode: 1;
95 unsigned int has_aux2: 1;
96 const struct iio_chan_spec *channels;
97 unsigned int num_channels;
98 int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
99 };
100
101 struct ingenic_adc {
102 void __iomem *base;
103 struct clk *clk;
104 struct mutex lock;
105 struct mutex aux_lock;
106 const struct ingenic_adc_soc_data *soc_data;
107 bool low_vref_mode;
108 };
109
110 static void ingenic_adc_set_adcmd(struct iio_dev *iio_dev, unsigned long mask)
111 {
112 struct ingenic_adc *adc = iio_priv(iio_dev);
113
114 mutex_lock(&adc->lock);
115
116 /* Init ADCMD */
117 readl(adc->base + JZ_ADC_REG_ADCMD);
118
119 if (mask & 0x3) {
120 /* Second channel (INGENIC_ADC_TOUCH_YP): sample YP vs. GND */
121 writel(JZ_ADC_REG_ADCMD_XNGRU
122 | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
123 | JZ_ADC_REG_ADCMD_YPADC,
124 adc->base + JZ_ADC_REG_ADCMD);
125
126 /* First channel (INGENIC_ADC_TOUCH_XP): sample XP vs. GND */
127 writel(JZ_ADC_REG_ADCMD_YNGRU
128 | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
129 | JZ_ADC_REG_ADCMD_XPADC,
130 adc->base + JZ_ADC_REG_ADCMD);
131 }
132
133 if (mask & 0xc) {
134 /* Fourth channel (INGENIC_ADC_TOUCH_YN): sample YN vs. GND */
135 writel(JZ_ADC_REG_ADCMD_XNGRU
136 | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
137 | JZ_ADC_REG_ADCMD_YNADC,
138 adc->base + JZ_ADC_REG_ADCMD);
139
140 /* Third channel (INGENIC_ADC_TOUCH_XN): sample XN vs. GND */
141 writel(JZ_ADC_REG_ADCMD_YNGRU
142 | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
143 | JZ_ADC_REG_ADCMD_XNADC,
144 adc->base + JZ_ADC_REG_ADCMD);
145 }
146
147 if (mask & 0x30) {
148 /* Sixth channel (INGENIC_ADC_TOUCH_YD): sample YP vs. YN */
149 writel(JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
150 | JZ_ADC_REG_ADCMD_YPADC,
151 adc->base + JZ_ADC_REG_ADCMD);
152
153 /* Fifth channel (INGENIC_ADC_TOUCH_XD): sample XP vs. XN */
154 writel(JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
155 | JZ_ADC_REG_ADCMD_XPADC,
156 adc->base + JZ_ADC_REG_ADCMD);
157 }
158
159 /* We're done */
160 writel(0, adc->base + JZ_ADC_REG_ADCMD);
161
162 mutex_unlock(&adc->lock);
163 }
164
165 static void ingenic_adc_set_config(struct ingenic_adc *adc,
166 uint32_t mask,
167 uint32_t val)
168 {
169 uint32_t cfg;
170
171 mutex_lock(&adc->lock);
172
173 cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask;
174 cfg |= val;
175 writel(cfg, adc->base + JZ_ADC_REG_CFG);
176
177 mutex_unlock(&adc->lock);
178 }
179
180 static void ingenic_adc_enable_unlocked(struct ingenic_adc *adc,
181 int engine,
182 bool enabled)
183 {
184 u8 val;
185
186 val = readb(adc->base + JZ_ADC_REG_ENABLE);
187
188 if (enabled)
189 val |= BIT(engine);
190 else
191 val &= ~BIT(engine);
192
193 writeb(val, adc->base + JZ_ADC_REG_ENABLE);
194 }
195
196 static void ingenic_adc_enable(struct ingenic_adc *adc,
197 int engine,
198 bool enabled)
199 {
200 mutex_lock(&adc->lock);
201 ingenic_adc_enable_unlocked(adc, engine, enabled);
202 mutex_unlock(&adc->lock);
203 }
204
205 static int ingenic_adc_capture(struct ingenic_adc *adc,
206 int engine)
207 {
208 u32 cfg;
209 u8 val;
210 int ret;
211
212 /*
213 * Disable CMD_SEL temporarily, because it causes wrong VBAT readings,
214 * probably due to the switch of VREF. We must keep the lock here to
215 * avoid races with the buffer enable/disable functions.
216 */
217 mutex_lock(&adc->lock);
218 cfg = readl(adc->base + JZ_ADC_REG_CFG);
219 writel(cfg & ~JZ_ADC_REG_CFG_CMD_SEL, adc->base + JZ_ADC_REG_CFG);
220
221 ingenic_adc_enable_unlocked(adc, engine, true);
222 ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
223 !(val & BIT(engine)), 250, 1000);
224 if (ret)
225 ingenic_adc_enable_unlocked(adc, engine, false);
226
227 writel(cfg, adc->base + JZ_ADC_REG_CFG);
228 mutex_unlock(&adc->lock);
229
230 return ret;
231 }
232
233 static int ingenic_adc_write_raw(struct iio_dev *iio_dev,
234 struct iio_chan_spec const *chan,
235 int val,
236 int val2,
237 long m)
238 {
239 struct ingenic_adc *adc = iio_priv(iio_dev);
240 struct device *dev = iio_dev->dev.parent;
241 int ret;
242
243 switch (m) {
244 case IIO_CHAN_INFO_SCALE:
245 switch (chan->channel) {
246 case INGENIC_ADC_BATTERY:
247 if (!adc->soc_data->battery_vref_mode)
248 return -EINVAL;
249
250 ret = clk_enable(adc->clk);
251 if (ret) {
252 dev_err(dev, "Failed to enable clock: %d\n",
253 ret);
254 return ret;
255 }
256
257 if (val > JZ_ADC_BATTERY_LOW_VREF) {
258 ingenic_adc_set_config(adc,
259 JZ_ADC_REG_CFG_BAT_MD,
260 0);
261 adc->low_vref_mode = false;
262 } else {
263 ingenic_adc_set_config(adc,
264 JZ_ADC_REG_CFG_BAT_MD,
265 JZ_ADC_REG_CFG_BAT_MD);
266 adc->low_vref_mode = true;
267 }
268
269 clk_disable(adc->clk);
270
271 return 0;
272 default:
273 return -EINVAL;
274 }
275 default:
276 return -EINVAL;
277 }
278 }
279
280 static const int jz4725b_adc_battery_raw_avail[] = {
281 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
282 };
283
284 static const int jz4725b_adc_battery_scale_avail[] = {
285 JZ4725B_ADC_BATTERY_HIGH_VREF, JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
286 JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
287 };
288
289 static const int jz4740_adc_battery_raw_avail[] = {
290 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
291 };
292
293 static const int jz4740_adc_battery_scale_avail[] = {
294 JZ4740_ADC_BATTERY_HIGH_VREF, JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
295 JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
296 };
297
298 static const int jz4770_adc_battery_raw_avail[] = {
299 0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1,
300 };
301
302 static const int jz4770_adc_battery_scale_avail[] = {
303 JZ4770_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS,
304 };
305
306 static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
307 {
308 struct clk *parent_clk;
309 unsigned long parent_rate, rate;
310 unsigned int div_main, div_10us;
311
312 parent_clk = clk_get_parent(adc->clk);
313 if (!parent_clk) {
314 dev_err(dev, "ADC clock has no parent\n");
315 return -ENODEV;
316 }
317 parent_rate = clk_get_rate(parent_clk);
318
319 /*
320 * The JZ4725B ADC works at 500 kHz to 8 MHz.
321 * We pick the highest rate possible.
322 * In practice we typically get 6 MHz, half of the 12 MHz EXT clock.
323 */
324 div_main = DIV_ROUND_UP(parent_rate, 8000000);
325 div_main = clamp(div_main, 1u, 64u);
326 rate = parent_rate / div_main;
327 if (rate < 500000 || rate > 8000000) {
328 dev_err(dev, "No valid divider for ADC main clock\n");
329 return -EINVAL;
330 }
331
332 /* We also need a divider that produces a 10us clock. */
333 div_10us = DIV_ROUND_UP(rate, 100000);
334
335 writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) |
336 (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
337 adc->base + JZ_ADC_REG_ADCLK);
338
339 return 0;
340 }
341
342 static int jz4770_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
343 {
344 struct clk *parent_clk;
345 unsigned long parent_rate, rate;
346 unsigned int div_main, div_ms, div_10us;
347
348 parent_clk = clk_get_parent(adc->clk);
349 if (!parent_clk) {
350 dev_err(dev, "ADC clock has no parent\n");
351 return -ENODEV;
352 }
353 parent_rate = clk_get_rate(parent_clk);
354
355 /*
356 * The JZ4770 ADC works at 20 kHz to 200 kHz.
357 * We pick the highest rate possible.
358 */
359 div_main = DIV_ROUND_UP(parent_rate, 200000);
360 div_main = clamp(div_main, 1u, 256u);
361 rate = parent_rate / div_main;
362 if (rate < 20000 || rate > 200000) {
363 dev_err(dev, "No valid divider for ADC main clock\n");
364 return -EINVAL;
365 }
366
367 /* We also need a divider that produces a 10us clock. */
368 div_10us = DIV_ROUND_UP(rate, 10000);
369 /* And another, which produces a 1ms clock. */
370 div_ms = DIV_ROUND_UP(rate, 1000);
371
372 writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) |
373 ((div_10us - 1) << JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB) |
374 (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
375 adc->base + JZ_ADC_REG_ADCLK);
376
377 return 0;
378 }
379
380 static const struct iio_chan_spec jz4740_channels[] = {
381 {
382 .extend_name = "aux",
383 .type = IIO_VOLTAGE,
384 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
385 BIT(IIO_CHAN_INFO_SCALE),
386 .indexed = 1,
387 .channel = INGENIC_ADC_AUX,
388 .scan_index = -1,
389 },
390 {
391 .extend_name = "battery",
392 .type = IIO_VOLTAGE,
393 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
394 BIT(IIO_CHAN_INFO_SCALE),
395 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
396 BIT(IIO_CHAN_INFO_SCALE),
397 .indexed = 1,
398 .channel = INGENIC_ADC_BATTERY,
399 .scan_index = -1,
400 },
401 };
402
403 static const struct iio_chan_spec jz4770_channels[] = {
404 {
405 .type = IIO_VOLTAGE,
406 .indexed = 1,
407 .channel = INGENIC_ADC_TOUCH_XP,
408 .scan_index = 0,
409 .scan_type = {
410 .sign = 'u',
411 .realbits = 12,
412 .storagebits = 16,
413 },
414 },
415 {
416 .type = IIO_VOLTAGE,
417 .indexed = 1,
418 .channel = INGENIC_ADC_TOUCH_YP,
419 .scan_index = 1,
420 .scan_type = {
421 .sign = 'u',
422 .realbits = 12,
423 .storagebits = 16,
424 },
425 },
426 {
427 .type = IIO_VOLTAGE,
428 .indexed = 1,
429 .channel = INGENIC_ADC_TOUCH_XN,
430 .scan_index = 2,
431 .scan_type = {
432 .sign = 'u',
433 .realbits = 12,
434 .storagebits = 16,
435 },
436 },
437 {
438 .type = IIO_VOLTAGE,
439 .indexed = 1,
440 .channel = INGENIC_ADC_TOUCH_YN,
441 .scan_index = 3,
442 .scan_type = {
443 .sign = 'u',
444 .realbits = 12,
445 .storagebits = 16,
446 },
447 },
448 {
449 .type = IIO_VOLTAGE,
450 .indexed = 1,
451 .channel = INGENIC_ADC_TOUCH_XD,
452 .scan_index = 4,
453 .scan_type = {
454 .sign = 'u',
455 .realbits = 12,
456 .storagebits = 16,
457 },
458 },
459 {
460 .type = IIO_VOLTAGE,
461 .indexed = 1,
462 .channel = INGENIC_ADC_TOUCH_YD,
463 .scan_index = 5,
464 .scan_type = {
465 .sign = 'u',
466 .realbits = 12,
467 .storagebits = 16,
468 },
469 },
470 {
471 .extend_name = "aux",
472 .type = IIO_VOLTAGE,
473 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
474 BIT(IIO_CHAN_INFO_SCALE),
475 .indexed = 1,
476 .channel = INGENIC_ADC_AUX,
477 .scan_index = -1,
478 },
479 {
480 .extend_name = "battery",
481 .type = IIO_VOLTAGE,
482 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
483 BIT(IIO_CHAN_INFO_SCALE),
484 .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
485 BIT(IIO_CHAN_INFO_SCALE),
486 .indexed = 1,
487 .channel = INGENIC_ADC_BATTERY,
488 .scan_index = -1,
489 },
490 {
491 .extend_name = "aux2",
492 .type = IIO_VOLTAGE,
493 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
494 BIT(IIO_CHAN_INFO_SCALE),
495 .indexed = 1,
496 .channel = INGENIC_ADC_AUX2,
497 .scan_index = -1,
498 },
499 };
500
501 static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
502 .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,
503 .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
504 .battery_raw_avail = jz4725b_adc_battery_raw_avail,
505 .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
506 .battery_scale_avail = jz4725b_adc_battery_scale_avail,
507 .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
508 .battery_vref_mode = true,
509 .has_aux2 = false,
510 .channels = jz4740_channels,
511 .num_channels = ARRAY_SIZE(jz4740_channels),
512 .init_clk_div = jz4725b_adc_init_clk_div,
513 };
514
515 static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
516 .battery_high_vref = JZ4740_ADC_BATTERY_HIGH_VREF,
517 .battery_high_vref_bits = JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
518 .battery_raw_avail = jz4740_adc_battery_raw_avail,
519 .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
520 .battery_scale_avail = jz4740_adc_battery_scale_avail,
521 .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
522 .battery_vref_mode = true,
523 .has_aux2 = false,
524 .channels = jz4740_channels,
525 .num_channels = ARRAY_SIZE(jz4740_channels),
526 .init_clk_div = NULL, /* no ADCLK register on JZ4740 */
527 };
528
529 static const struct ingenic_adc_soc_data jz4770_adc_soc_data = {
530 .battery_high_vref = JZ4770_ADC_BATTERY_VREF,
531 .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS,
532 .battery_raw_avail = jz4770_adc_battery_raw_avail,
533 .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail),
534 .battery_scale_avail = jz4770_adc_battery_scale_avail,
535 .battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail),
536 .battery_vref_mode = false,
537 .has_aux2 = true,
538 .channels = jz4770_channels,
539 .num_channels = ARRAY_SIZE(jz4770_channels),
540 .init_clk_div = jz4770_adc_init_clk_div,
541 };
542
543 static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
544 struct iio_chan_spec const *chan,
545 const int **vals,
546 int *type,
547 int *length,
548 long m)
549 {
550 struct ingenic_adc *adc = iio_priv(iio_dev);
551
552 switch (m) {
553 case IIO_CHAN_INFO_RAW:
554 *type = IIO_VAL_INT;
555 *length = adc->soc_data->battery_raw_avail_size;
556 *vals = adc->soc_data->battery_raw_avail;
557 return IIO_AVAIL_RANGE;
558 case IIO_CHAN_INFO_SCALE:
559 *type = IIO_VAL_FRACTIONAL_LOG2;
560 *length = adc->soc_data->battery_scale_avail_size;
561 *vals = adc->soc_data->battery_scale_avail;
562 return IIO_AVAIL_LIST;
563 default:
564 return -EINVAL;
565 }
566 }
567
568 static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev,
569 struct iio_chan_spec const *chan,
570 int *val)
571 {
572 int bit, ret, engine = (chan->channel == INGENIC_ADC_BATTERY);
573 struct ingenic_adc *adc = iio_priv(iio_dev);
574
575 ret = clk_enable(adc->clk);
576 if (ret) {
577 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
578 ret);
579 return ret;
580 }
581
582 /* We cannot sample AUX/AUX2 in parallel. */
583 mutex_lock(&adc->aux_lock);
584 if (adc->soc_data->has_aux2 && engine == 0) {
585 bit = BIT(chan->channel == INGENIC_ADC_AUX2);
586 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, bit);
587 }
588
589 ret = ingenic_adc_capture(adc, engine);
590 if (ret)
591 goto out;
592
593 switch (chan->channel) {
594 case INGENIC_ADC_AUX:
595 case INGENIC_ADC_AUX2:
596 *val = readw(adc->base + JZ_ADC_REG_ADSDAT);
597 break;
598 case INGENIC_ADC_BATTERY:
599 *val = readw(adc->base + JZ_ADC_REG_ADBDAT);
600 break;
601 }
602
603 ret = IIO_VAL_INT;
604 out:
605 mutex_unlock(&adc->aux_lock);
606 clk_disable(adc->clk);
607
608 return ret;
609 }
610
611 static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
612 struct iio_chan_spec const *chan,
613 int *val,
614 int *val2,
615 long m)
616 {
617 struct ingenic_adc *adc = iio_priv(iio_dev);
618
619 switch (m) {
620 case IIO_CHAN_INFO_RAW:
621 return ingenic_adc_read_chan_info_raw(iio_dev, chan, val);
622 case IIO_CHAN_INFO_SCALE:
623 switch (chan->channel) {
624 case INGENIC_ADC_AUX:
625 case INGENIC_ADC_AUX2:
626 *val = JZ_ADC_AUX_VREF;
627 *val2 = JZ_ADC_AUX_VREF_BITS;
628 break;
629 case INGENIC_ADC_BATTERY:
630 if (adc->low_vref_mode) {
631 *val = JZ_ADC_BATTERY_LOW_VREF;
632 *val2 = JZ_ADC_BATTERY_LOW_VREF_BITS;
633 } else {
634 *val = adc->soc_data->battery_high_vref;
635 *val2 = adc->soc_data->battery_high_vref_bits;
636 }
637 break;
638 }
639
640 return IIO_VAL_FRACTIONAL_LOG2;
641 default:
642 return -EINVAL;
643 }
644 }
645
646 static int ingenic_adc_of_xlate(struct iio_dev *iio_dev,
647 const struct of_phandle_args *iiospec)
648 {
649 int i;
650
651 if (!iiospec->args_count)
652 return -EINVAL;
653
654 for (i = 0; i < iio_dev->num_channels; ++i)
655 if (iio_dev->channels[i].channel == iiospec->args[0])
656 return i;
657
658 return -EINVAL;
659 }
660
661 static void ingenic_adc_clk_cleanup(void *data)
662 {
663 clk_unprepare(data);
664 }
665
666 static const struct iio_info ingenic_adc_info = {
667 .write_raw = ingenic_adc_write_raw,
668 .read_raw = ingenic_adc_read_raw,
669 .read_avail = ingenic_adc_read_avail,
670 .of_xlate = ingenic_adc_of_xlate,
671 };
672
673 static int ingenic_adc_buffer_enable(struct iio_dev *iio_dev)
674 {
675 struct ingenic_adc *adc = iio_priv(iio_dev);
676 int ret;
677
678 ret = clk_enable(adc->clk);
679 if (ret) {
680 dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
681 ret);
682 return ret;
683 }
684
685 /* It takes significant time for the touchscreen hw to stabilize. */
686 msleep(50);
687 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK,
688 JZ_ADC_REG_CFG_SAMPLE_NUM(4) |
689 JZ_ADC_REG_CFG_PULL_UP(4));
690
691 writew(80, adc->base + JZ_ADC_REG_ADWAIT);
692 writew(2, adc->base + JZ_ADC_REG_ADSAME);
693 writeb((u8)~JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_CTRL);
694 writel(0, adc->base + JZ_ADC_REG_ADTCH);
695
696 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL,
697 JZ_ADC_REG_CFG_CMD_SEL);
698 ingenic_adc_set_adcmd(iio_dev, iio_dev->active_scan_mask[0]);
699
700 ingenic_adc_enable(adc, 2, true);
701
702 return 0;
703 }
704
705 static int ingenic_adc_buffer_disable(struct iio_dev *iio_dev)
706 {
707 struct ingenic_adc *adc = iio_priv(iio_dev);
708
709 ingenic_adc_enable(adc, 2, false);
710
711 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL, 0);
712
713 writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
714 writeb(0xff, adc->base + JZ_ADC_REG_STATUS);
715 ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK, 0);
716 writew(0, adc->base + JZ_ADC_REG_ADSAME);
717 writew(0, adc->base + JZ_ADC_REG_ADWAIT);
718 clk_disable(adc->clk);
719
720 return 0;
721 }
722
723 static const struct iio_buffer_setup_ops ingenic_buffer_setup_ops = {
724 .postenable = &ingenic_adc_buffer_enable,
725 .predisable = &ingenic_adc_buffer_disable
726 };
727
728 static irqreturn_t ingenic_adc_irq(int irq, void *data)
729 {
730 struct iio_dev *iio_dev = data;
731 struct ingenic_adc *adc = iio_priv(iio_dev);
732 unsigned long mask = iio_dev->active_scan_mask[0];
733 unsigned int i;
734 u32 tdat[3];
735
736 for (i = 0; i < ARRAY_SIZE(tdat); mask >>= 2, i++) {
737 if (mask & 0x3)
738 tdat[i] = readl(adc->base + JZ_ADC_REG_ADTCH);
739 else
740 tdat[i] = 0;
741 }
742
743 iio_push_to_buffers(iio_dev, tdat);
744 writeb(JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_STATUS);
745
746 return IRQ_HANDLED;
747 }
748
749 static int ingenic_adc_probe(struct platform_device *pdev)
750 {
751 struct device *dev = &pdev->dev;
752 struct iio_dev *iio_dev;
753 struct ingenic_adc *adc;
754 const struct ingenic_adc_soc_data *soc_data;
755 int irq, ret;
756
757 soc_data = device_get_match_data(dev);
758 if (!soc_data)
759 return -EINVAL;
760
761 iio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
762 if (!iio_dev)
763 return -ENOMEM;
764
765 adc = iio_priv(iio_dev);
766 mutex_init(&adc->lock);
767 mutex_init(&adc->aux_lock);
768 adc->soc_data = soc_data;
769
770 irq = platform_get_irq(pdev, 0);
771 if (irq < 0)
772 return irq;
773
774 ret = devm_request_irq(dev, irq, ingenic_adc_irq, 0,
775 dev_name(dev), iio_dev);
776 if (ret < 0) {
777 dev_err(dev, "Failed to request irq: %d\n", ret);
778 return ret;
779 }
780
781 adc->base = devm_platform_ioremap_resource(pdev, 0);
782 if (IS_ERR(adc->base))
783 return PTR_ERR(adc->base);
784
785 adc->clk = devm_clk_get(dev, "adc");
786 if (IS_ERR(adc->clk)) {
787 dev_err(dev, "Unable to get clock\n");
788 return PTR_ERR(adc->clk);
789 }
790
791 ret = clk_prepare_enable(adc->clk);
792 if (ret) {
793 dev_err(dev, "Failed to enable clock\n");
794 return ret;
795 }
796
797 /* Set clock dividers. */
798 if (soc_data->init_clk_div) {
799 ret = soc_data->init_clk_div(dev, adc);
800 if (ret) {
801 clk_disable_unprepare(adc->clk);
802 return ret;
803 }
804 }
805
806 /* Put hardware in a known passive state. */
807 writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
808 writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
809 usleep_range(2000, 3000); /* Must wait at least 2ms. */
810 clk_disable(adc->clk);
811
812 ret = devm_add_action_or_reset(dev, ingenic_adc_clk_cleanup, adc->clk);
813 if (ret) {
814 dev_err(dev, "Unable to add action\n");
815 return ret;
816 }
817
818 iio_dev->name = "jz-adc";
819 iio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
820 iio_dev->setup_ops = &ingenic_buffer_setup_ops;
821 iio_dev->channels = soc_data->channels;
822 iio_dev->num_channels = soc_data->num_channels;
823 iio_dev->info = &ingenic_adc_info;
824
825 ret = devm_iio_device_register(dev, iio_dev);
826 if (ret)
827 dev_err(dev, "Unable to register IIO device\n");
828
829 return ret;
830 }
831
832 static const struct of_device_id ingenic_adc_of_match[] = {
833 { .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
834 { .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
835 { .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, },
836 { },
837 };
838 MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
839
840 static struct platform_driver ingenic_adc_driver = {
841 .driver = {
842 .name = "ingenic-adc",
843 .of_match_table = ingenic_adc_of_match,
844 },
845 .probe = ingenic_adc_probe,
846 };
847 module_platform_driver(ingenic_adc_driver);
848 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support