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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / iio / adc / stm32-adc.c
blobc067c994dae20a62f182b5a0d73e4d2c1d2efe9b
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/iio/iio.h>
14 #include <linux/iio/buffer.h>
15 #include <linux/iio/timer/stm32-lptim-trigger.h>
16 #include <linux/iio/timer/stm32-timer-trigger.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/trigger_consumer.h>
19 #include <linux/iio/triggered_buffer.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28
29 #include "stm32-adc-core.h"
30
31 /* Number of linear calibration shadow registers / LINCALRDYW control bits */
32 #define STM32H7_LINCALFACT_NUM 6
33
34 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
35 #define STM32H7_BOOST_CLKRATE 20000000UL
36
37 #define STM32_ADC_CH_MAX 20 /* max number of channels */
38 #define STM32_ADC_CH_SZ 10 /* max channel name size */
39 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
40 #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */
41 #define STM32_ADC_TIMEOUT_US 100000
42 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
43 #define STM32_ADC_HW_STOP_DELAY_MS 100
44
45 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE
46
47 /* External trigger enable */
48 enum stm32_adc_exten {
49 STM32_EXTEN_SWTRIG,
50 STM32_EXTEN_HWTRIG_RISING_EDGE,
51 STM32_EXTEN_HWTRIG_FALLING_EDGE,
52 STM32_EXTEN_HWTRIG_BOTH_EDGES,
53 };
54
55 /* extsel - trigger mux selection value */
56 enum stm32_adc_extsel {
57 STM32_EXT0,
58 STM32_EXT1,
59 STM32_EXT2,
60 STM32_EXT3,
61 STM32_EXT4,
62 STM32_EXT5,
63 STM32_EXT6,
64 STM32_EXT7,
65 STM32_EXT8,
66 STM32_EXT9,
67 STM32_EXT10,
68 STM32_EXT11,
69 STM32_EXT12,
70 STM32_EXT13,
71 STM32_EXT14,
72 STM32_EXT15,
73 STM32_EXT16,
74 STM32_EXT17,
75 STM32_EXT18,
76 STM32_EXT19,
77 STM32_EXT20,
78 };
79
80 /**
81 * struct stm32_adc_trig_info - ADC trigger info
82 * @name: name of the trigger, corresponding to its source
83 * @extsel: trigger selection
84 */
85 struct stm32_adc_trig_info {
86 const char *name;
87 enum stm32_adc_extsel extsel;
88 };
89
90 /**
91 * struct stm32_adc_calib - optional adc calibration data
92 * @calfact_s: Calibration offset for single ended channels
93 * @calfact_d: Calibration offset in differential
94 * @lincalfact: Linearity calibration factor
95 * @calibrated: Indicates calibration status
96 */
97 struct stm32_adc_calib {
98 u32 calfact_s;
99 u32 calfact_d;
100 u32 lincalfact[STM32H7_LINCALFACT_NUM];
101 bool calibrated;
102 };
103
104 /**
105 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
106 * @reg: register offset
107 * @mask: bitfield mask
108 * @shift: left shift
109 */
110 struct stm32_adc_regs {
111 int reg;
112 int mask;
113 int shift;
114 };
115
116 /**
117 * struct stm32_adc_regspec - stm32 registers definition
118 * @dr: data register offset
119 * @ier_eoc: interrupt enable register & eocie bitfield
120 * @ier_ovr: interrupt enable register & overrun bitfield
121 * @isr_eoc: interrupt status register & eoc bitfield
122 * @isr_ovr: interrupt status register & overrun bitfield
123 * @sqr: reference to sequence registers array
124 * @exten: trigger control register & bitfield
125 * @extsel: trigger selection register & bitfield
126 * @res: resolution selection register & bitfield
127 * @smpr: smpr1 & smpr2 registers offset array
128 * @smp_bits: smpr1 & smpr2 index and bitfields
129 */
130 struct stm32_adc_regspec {
131 const u32 dr;
132 const struct stm32_adc_regs ier_eoc;
133 const struct stm32_adc_regs ier_ovr;
134 const struct stm32_adc_regs isr_eoc;
135 const struct stm32_adc_regs isr_ovr;
136 const struct stm32_adc_regs *sqr;
137 const struct stm32_adc_regs exten;
138 const struct stm32_adc_regs extsel;
139 const struct stm32_adc_regs res;
140 const u32 smpr[2];
141 const struct stm32_adc_regs *smp_bits;
142 };
143
144 struct stm32_adc;
145
146 /**
147 * struct stm32_adc_cfg - stm32 compatible configuration data
148 * @regs: registers descriptions
149 * @adc_info: per instance input channels definitions
150 * @trigs: external trigger sources
151 * @clk_required: clock is required
152 * @has_vregready: vregready status flag presence
153 * @prepare: optional prepare routine (power-up, enable)
154 * @start_conv: routine to start conversions
155 * @stop_conv: routine to stop conversions
156 * @unprepare: optional unprepare routine (disable, power-down)
157 * @irq_clear: routine to clear irqs
158 * @smp_cycles: programmable sampling time (ADC clock cycles)
159 */
160 struct stm32_adc_cfg {
161 const struct stm32_adc_regspec *regs;
162 const struct stm32_adc_info *adc_info;
163 struct stm32_adc_trig_info *trigs;
164 bool clk_required;
165 bool has_vregready;
166 int (*prepare)(struct iio_dev *);
167 void (*start_conv)(struct iio_dev *, bool dma);
168 void (*stop_conv)(struct iio_dev *);
169 void (*unprepare)(struct iio_dev *);
170 void (*irq_clear)(struct iio_dev *indio_dev, u32 msk);
171 const unsigned int *smp_cycles;
172 };
173
174 /**
175 * struct stm32_adc - private data of each ADC IIO instance
176 * @common: reference to ADC block common data
177 * @offset: ADC instance register offset in ADC block
178 * @cfg: compatible configuration data
179 * @completion: end of single conversion completion
180 * @buffer: data buffer
181 * @clk: clock for this adc instance
182 * @irq: interrupt for this adc instance
183 * @lock: spinlock
184 * @bufi: data buffer index
185 * @num_conv: expected number of scan conversions
186 * @res: data resolution (e.g. RES bitfield value)
187 * @trigger_polarity: external trigger polarity (e.g. exten)
188 * @dma_chan: dma channel
189 * @rx_buf: dma rx buffer cpu address
190 * @rx_dma_buf: dma rx buffer bus address
191 * @rx_buf_sz: dma rx buffer size
192 * @difsel: bitmask to set single-ended/differential channel
193 * @pcsel: bitmask to preselect channels on some devices
194 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2)
195 * @cal: optional calibration data on some devices
196 * @chan_name: channel name array
197 */
198 struct stm32_adc {
199 struct stm32_adc_common *common;
200 u32 offset;
201 const struct stm32_adc_cfg *cfg;
202 struct completion completion;
203 u16 buffer[STM32_ADC_MAX_SQ];
204 struct clk *clk;
205 int irq;
206 spinlock_t lock; /* interrupt lock */
207 unsigned int bufi;
208 unsigned int num_conv;
209 u32 res;
210 u32 trigger_polarity;
211 struct dma_chan *dma_chan;
212 u8 *rx_buf;
213 dma_addr_t rx_dma_buf;
214 unsigned int rx_buf_sz;
215 u32 difsel;
216 u32 pcsel;
217 u32 smpr_val[2];
218 struct stm32_adc_calib cal;
219 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ];
220 };
221
222 struct stm32_adc_diff_channel {
223 u32 vinp;
224 u32 vinn;
225 };
226
227 /**
228 * struct stm32_adc_info - stm32 ADC, per instance config data
229 * @max_channels: Number of channels
230 * @resolutions: available resolutions
231 * @num_res: number of available resolutions
232 */
233 struct stm32_adc_info {
234 int max_channels;
235 const unsigned int *resolutions;
236 const unsigned int num_res;
237 };
238
239 static const unsigned int stm32f4_adc_resolutions[] = {
240 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */
241 12, 10, 8, 6,
242 };
243
244 /* stm32f4 can have up to 16 channels */
245 static const struct stm32_adc_info stm32f4_adc_info = {
246 .max_channels = 16,
247 .resolutions = stm32f4_adc_resolutions,
248 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions),
249 };
250
251 static const unsigned int stm32h7_adc_resolutions[] = {
252 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */
253 16, 14, 12, 10, 8,
254 };
255
256 /* stm32h7 can have up to 20 channels */
257 static const struct stm32_adc_info stm32h7_adc_info = {
258 .max_channels = STM32_ADC_CH_MAX,
259 .resolutions = stm32h7_adc_resolutions,
260 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions),
261 };
262
263 /*
264 * stm32f4_sq - describe regular sequence registers
265 * - L: sequence len (register & bit field)
266 * - SQ1..SQ16: sequence entries (register & bit field)
267 */
268 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = {
269 /* L: len bit field description to be kept as first element */
270 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 },
271 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
272 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 },
273 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 },
274 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 },
275 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 },
276 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 },
277 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 },
278 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 },
279 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 },
280 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 },
281 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 },
282 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 },
283 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 },
284 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 },
285 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 },
286 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 },
287 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 },
288 };
289
290 /* STM32F4 external trigger sources for all instances */
291 static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
292 { TIM1_CH1, STM32_EXT0 },
293 { TIM1_CH2, STM32_EXT1 },
294 { TIM1_CH3, STM32_EXT2 },
295 { TIM2_CH2, STM32_EXT3 },
296 { TIM2_CH3, STM32_EXT4 },
297 { TIM2_CH4, STM32_EXT5 },
298 { TIM2_TRGO, STM32_EXT6 },
299 { TIM3_CH1, STM32_EXT7 },
300 { TIM3_TRGO, STM32_EXT8 },
301 { TIM4_CH4, STM32_EXT9 },
302 { TIM5_CH1, STM32_EXT10 },
303 { TIM5_CH2, STM32_EXT11 },
304 { TIM5_CH3, STM32_EXT12 },
305 { TIM8_CH1, STM32_EXT13 },
306 { TIM8_TRGO, STM32_EXT14 },
307 {}, /* sentinel */
308 };
309
310 /*
311 * stm32f4_smp_bits[] - describe sampling time register index & bit fields
312 * Sorted so it can be indexed by channel number.
313 */
314 static const struct stm32_adc_regs stm32f4_smp_bits[] = {
315 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */
316 { 1, GENMASK(2, 0), 0 },
317 { 1, GENMASK(5, 3), 3 },
318 { 1, GENMASK(8, 6), 6 },
319 { 1, GENMASK(11, 9), 9 },
320 { 1, GENMASK(14, 12), 12 },
321 { 1, GENMASK(17, 15), 15 },
322 { 1, GENMASK(20, 18), 18 },
323 { 1, GENMASK(23, 21), 21 },
324 { 1, GENMASK(26, 24), 24 },
325 { 1, GENMASK(29, 27), 27 },
326 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */
327 { 0, GENMASK(2, 0), 0 },
328 { 0, GENMASK(5, 3), 3 },
329 { 0, GENMASK(8, 6), 6 },
330 { 0, GENMASK(11, 9), 9 },
331 { 0, GENMASK(14, 12), 12 },
332 { 0, GENMASK(17, 15), 15 },
333 { 0, GENMASK(20, 18), 18 },
334 { 0, GENMASK(23, 21), 21 },
335 { 0, GENMASK(26, 24), 24 },
336 };
337
338 /* STM32F4 programmable sampling time (ADC clock cycles) */
339 static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
340 3, 15, 28, 56, 84, 112, 144, 480,
341 };
342
343 static const struct stm32_adc_regspec stm32f4_adc_regspec = {
344 .dr = STM32F4_ADC_DR,
345 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE },
346 .ier_ovr = { STM32F4_ADC_CR1, STM32F4_OVRIE },
347 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC },
348 .isr_ovr = { STM32F4_ADC_SR, STM32F4_OVR },
349 .sqr = stm32f4_sq,
350 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT },
351 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK,
352 STM32F4_EXTSEL_SHIFT },
353 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
354 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 },
355 .smp_bits = stm32f4_smp_bits,
356 };
357
358 static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = {
359 /* L: len bit field description to be kept as first element */
360 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 },
361 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
362 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 },
363 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 },
364 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 },
365 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 },
366 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 },
367 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 },
368 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 },
369 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 },
370 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 },
371 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 },
372 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 },
373 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 },
374 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 },
375 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 },
376 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 },
377 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 },
378 };
379
380 /* STM32H7 external trigger sources for all instances */
381 static struct stm32_adc_trig_info stm32h7_adc_trigs[] = {
382 { TIM1_CH1, STM32_EXT0 },
383 { TIM1_CH2, STM32_EXT1 },
384 { TIM1_CH3, STM32_EXT2 },
385 { TIM2_CH2, STM32_EXT3 },
386 { TIM3_TRGO, STM32_EXT4 },
387 { TIM4_CH4, STM32_EXT5 },
388 { TIM8_TRGO, STM32_EXT7 },
389 { TIM8_TRGO2, STM32_EXT8 },
390 { TIM1_TRGO, STM32_EXT9 },
391 { TIM1_TRGO2, STM32_EXT10 },
392 { TIM2_TRGO, STM32_EXT11 },
393 { TIM4_TRGO, STM32_EXT12 },
394 { TIM6_TRGO, STM32_EXT13 },
395 { TIM15_TRGO, STM32_EXT14 },
396 { TIM3_CH4, STM32_EXT15 },
397 { LPTIM1_OUT, STM32_EXT18 },
398 { LPTIM2_OUT, STM32_EXT19 },
399 { LPTIM3_OUT, STM32_EXT20 },
400 {},
401 };
402
403 /*
404 * stm32h7_smp_bits - describe sampling time register index & bit fields
405 * Sorted so it can be indexed by channel number.
406 */
407 static const struct stm32_adc_regs stm32h7_smp_bits[] = {
408 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */
409 { 0, GENMASK(2, 0), 0 },
410 { 0, GENMASK(5, 3), 3 },
411 { 0, GENMASK(8, 6), 6 },
412 { 0, GENMASK(11, 9), 9 },
413 { 0, GENMASK(14, 12), 12 },
414 { 0, GENMASK(17, 15), 15 },
415 { 0, GENMASK(20, 18), 18 },
416 { 0, GENMASK(23, 21), 21 },
417 { 0, GENMASK(26, 24), 24 },
418 { 0, GENMASK(29, 27), 27 },
419 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */
420 { 1, GENMASK(2, 0), 0 },
421 { 1, GENMASK(5, 3), 3 },
422 { 1, GENMASK(8, 6), 6 },
423 { 1, GENMASK(11, 9), 9 },
424 { 1, GENMASK(14, 12), 12 },
425 { 1, GENMASK(17, 15), 15 },
426 { 1, GENMASK(20, 18), 18 },
427 { 1, GENMASK(23, 21), 21 },
428 { 1, GENMASK(26, 24), 24 },
429 { 1, GENMASK(29, 27), 27 },
430 };
431
432 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
433 static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
434 1, 2, 8, 16, 32, 64, 387, 810,
435 };
436
437 static const struct stm32_adc_regspec stm32h7_adc_regspec = {
438 .dr = STM32H7_ADC_DR,
439 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE },
440 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE },
441 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC },
442 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR },
443 .sqr = stm32h7_sq,
444 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT },
445 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK,
446 STM32H7_EXTSEL_SHIFT },
447 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
448 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
449 .smp_bits = stm32h7_smp_bits,
450 };
451
452 /**
453 * STM32 ADC registers access routines
454 * @adc: stm32 adc instance
455 * @reg: reg offset in adc instance
456 *
457 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
458 * for adc1, adc2 and adc3.
459 */
460 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
461 {
462 return readl_relaxed(adc->common->base + adc->offset + reg);
463 }
464
465 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
466
467 #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \
468 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \
469 cond, sleep_us, timeout_us)
470
471 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
472 {
473 return readw_relaxed(adc->common->base + adc->offset + reg);
474 }
475
476 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
477 {
478 writel_relaxed(val, adc->common->base + adc->offset + reg);
479 }
480
481 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
482 {
483 unsigned long flags;
484
485 spin_lock_irqsave(&adc->lock, flags);
486 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
487 spin_unlock_irqrestore(&adc->lock, flags);
488 }
489
490 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
491 {
492 unsigned long flags;
493
494 spin_lock_irqsave(&adc->lock, flags);
495 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
496 spin_unlock_irqrestore(&adc->lock, flags);
497 }
498
499 /**
500 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
501 * @adc: stm32 adc instance
502 */
503 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
504 {
505 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,
506 adc->cfg->regs->ier_eoc.mask);
507 };
508
509 /**
510 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
511 * @adc: stm32 adc instance
512 */
513 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
514 {
515 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,
516 adc->cfg->regs->ier_eoc.mask);
517 }
518
519 static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc)
520 {
521 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg,
522 adc->cfg->regs->ier_ovr.mask);
523 }
524
525 static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc)
526 {
527 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg,
528 adc->cfg->regs->ier_ovr.mask);
529 }
530
531 static void stm32_adc_set_res(struct stm32_adc *adc)
532 {
533 const struct stm32_adc_regs *res = &adc->cfg->regs->res;
534 u32 val;
535
536 val = stm32_adc_readl(adc, res->reg);
537 val = (val & ~res->mask) | (adc->res << res->shift);
538 stm32_adc_writel(adc, res->reg, val);
539 }
540
541 static int stm32_adc_hw_stop(struct device *dev)
542 {
543 struct iio_dev *indio_dev = dev_get_drvdata(dev);
544 struct stm32_adc *adc = iio_priv(indio_dev);
545
546 if (adc->cfg->unprepare)
547 adc->cfg->unprepare(indio_dev);
548
549 if (adc->clk)
550 clk_disable_unprepare(adc->clk);
551
552 return 0;
553 }
554
555 static int stm32_adc_hw_start(struct device *dev)
556 {
557 struct iio_dev *indio_dev = dev_get_drvdata(dev);
558 struct stm32_adc *adc = iio_priv(indio_dev);
559 int ret;
560
561 if (adc->clk) {
562 ret = clk_prepare_enable(adc->clk);
563 if (ret)
564 return ret;
565 }
566
567 stm32_adc_set_res(adc);
568
569 if (adc->cfg->prepare) {
570 ret = adc->cfg->prepare(indio_dev);
571 if (ret)
572 goto err_clk_dis;
573 }
574
575 return 0;
576
577 err_clk_dis:
578 if (adc->clk)
579 clk_disable_unprepare(adc->clk);
580
581 return ret;
582 }
583
584 /**
585 * stm32f4_adc_start_conv() - Start conversions for regular channels.
586 * @indio_dev: IIO device instance
587 * @dma: use dma to transfer conversion result
588 *
589 * Start conversions for regular channels.
590 * Also take care of normal or DMA mode. Circular DMA may be used for regular
591 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
592 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
593 */
594 static void stm32f4_adc_start_conv(struct iio_dev *indio_dev, bool dma)
595 {
596 struct stm32_adc *adc = iio_priv(indio_dev);
597
598 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
599
600 if (dma)
601 stm32_adc_set_bits(adc, STM32F4_ADC_CR2,
602 STM32F4_DMA | STM32F4_DDS);
603
604 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
605
606 /* Wait for Power-up time (tSTAB from datasheet) */
607 usleep_range(2, 3);
608
609 /* Software start ? (e.g. trigger detection disabled ?) */
610 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
611 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
612 }
613
614 static void stm32f4_adc_stop_conv(struct iio_dev *indio_dev)
615 {
616 struct stm32_adc *adc = iio_priv(indio_dev);
617
618 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
619 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
620
621 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
622 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2,
623 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
624 }
625
626 static void stm32f4_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
627 {
628 struct stm32_adc *adc = iio_priv(indio_dev);
629
630 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
631 }
632
633 static void stm32h7_adc_start_conv(struct iio_dev *indio_dev, bool dma)
634 {
635 struct stm32_adc *adc = iio_priv(indio_dev);
636 enum stm32h7_adc_dmngt dmngt;
637 unsigned long flags;
638 u32 val;
639
640 if (dma)
641 dmngt = STM32H7_DMNGT_DMA_CIRC;
642 else
643 dmngt = STM32H7_DMNGT_DR_ONLY;
644
645 spin_lock_irqsave(&adc->lock, flags);
646 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR);
647 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT);
648 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val);
649 spin_unlock_irqrestore(&adc->lock, flags);
650
651 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
652 }
653
654 static void stm32h7_adc_stop_conv(struct iio_dev *indio_dev)
655 {
656 struct stm32_adc *adc = iio_priv(indio_dev);
657 int ret;
658 u32 val;
659
660 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP);
661
662 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
663 !(val & (STM32H7_ADSTART)),
664 100, STM32_ADC_TIMEOUT_US);
665 if (ret)
666 dev_warn(&indio_dev->dev, "stop failed\n");
667
668 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
669 }
670
671 static void stm32h7_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
672 {
673 struct stm32_adc *adc = iio_priv(indio_dev);
674 /* On STM32H7 IRQs are cleared by writing 1 into ISR register */
675 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk);
676 }
677
678 static int stm32h7_adc_exit_pwr_down(struct iio_dev *indio_dev)
679 {
680 struct stm32_adc *adc = iio_priv(indio_dev);
681 int ret;
682 u32 val;
683
684 /* Exit deep power down, then enable ADC voltage regulator */
685 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
686 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
687
688 if (adc->common->rate > STM32H7_BOOST_CLKRATE)
689 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
690
691 /* Wait for startup time */
692 if (!adc->cfg->has_vregready) {
693 usleep_range(10, 20);
694 return 0;
695 }
696
697 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
698 val & STM32MP1_VREGREADY, 100,
699 STM32_ADC_TIMEOUT_US);
700 if (ret) {
701 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
702 dev_err(&indio_dev->dev, "Failed to exit power down\n");
703 }
704
705 return ret;
706 }
707
708 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
709 {
710 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
711
712 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
713 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
714 }
715
716 static int stm32h7_adc_enable(struct iio_dev *indio_dev)
717 {
718 struct stm32_adc *adc = iio_priv(indio_dev);
719 int ret;
720 u32 val;
721
722 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
723
724 /* Poll for ADRDY to be set (after adc startup time) */
725 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
726 val & STM32H7_ADRDY,
727 100, STM32_ADC_TIMEOUT_US);
728 if (ret) {
729 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
730 dev_err(&indio_dev->dev, "Failed to enable ADC\n");
731 } else {
732 /* Clear ADRDY by writing one */
733 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
734 }
735
736 return ret;
737 }
738
739 static void stm32h7_adc_disable(struct iio_dev *indio_dev)
740 {
741 struct stm32_adc *adc = iio_priv(indio_dev);
742 int ret;
743 u32 val;
744
745 /* Disable ADC and wait until it's effectively disabled */
746 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
747 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
748 !(val & STM32H7_ADEN), 100,
749 STM32_ADC_TIMEOUT_US);
750 if (ret)
751 dev_warn(&indio_dev->dev, "Failed to disable\n");
752 }
753
754 /**
755 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
756 * @indio_dev: IIO device instance
757 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable
758 */
759 static int stm32h7_adc_read_selfcalib(struct iio_dev *indio_dev)
760 {
761 struct stm32_adc *adc = iio_priv(indio_dev);
762 int i, ret;
763 u32 lincalrdyw_mask, val;
764
765 /* Read linearity calibration */
766 lincalrdyw_mask = STM32H7_LINCALRDYW6;
767 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
768 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */
769 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
770
771 /* Poll: wait calib data to be ready in CALFACT2 register */
772 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
773 !(val & lincalrdyw_mask),
774 100, STM32_ADC_TIMEOUT_US);
775 if (ret) {
776 dev_err(&indio_dev->dev, "Failed to read calfact\n");
777 return ret;
778 }
779
780 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
781 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);
782 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;
783
784 lincalrdyw_mask >>= 1;
785 }
786
787 /* Read offset calibration */
788 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT);
789 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK);
790 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;
791 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);
792 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;
793 adc->cal.calibrated = true;
794
795 return 0;
796 }
797
798 /**
799 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
800 * @indio_dev: IIO device instance
801 * Note: ADC must be enabled, with no on-going conversions.
802 */
803 static int stm32h7_adc_restore_selfcalib(struct iio_dev *indio_dev)
804 {
805 struct stm32_adc *adc = iio_priv(indio_dev);
806 int i, ret;
807 u32 lincalrdyw_mask, val;
808
809 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) |
810 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT);
811 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val);
812
813 lincalrdyw_mask = STM32H7_LINCALRDYW6;
814 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
815 /*
816 * Write saved calibration data to shadow registers:
817 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger
818 * data write. Then poll to wait for complete transfer.
819 */
820 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;
821 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val);
822 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
823 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
824 val & lincalrdyw_mask,
825 100, STM32_ADC_TIMEOUT_US);
826 if (ret) {
827 dev_err(&indio_dev->dev, "Failed to write calfact\n");
828 return ret;
829 }
830
831 /*
832 * Read back calibration data, has two effects:
833 * - It ensures bits LINCALRDYW[6..1] are kept cleared
834 * for next time calibration needs to be restored.
835 * - BTW, bit clear triggers a read, then check data has been
836 * correctly written.
837 */
838 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
839 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
840 !(val & lincalrdyw_mask),
841 100, STM32_ADC_TIMEOUT_US);
842 if (ret) {
843 dev_err(&indio_dev->dev, "Failed to read calfact\n");
844 return ret;
845 }
846 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
847 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {
848 dev_err(&indio_dev->dev, "calfact not consistent\n");
849 return -EIO;
850 }
851
852 lincalrdyw_mask >>= 1;
853 }
854
855 return 0;
856 }
857
858 /**
859 * Fixed timeout value for ADC calibration.
860 * worst cases:
861 * - low clock frequency
862 * - maximum prescalers
863 * Calibration requires:
864 * - 131,072 ADC clock cycle for the linear calibration
865 * - 20 ADC clock cycle for the offset calibration
866 *
867 * Set to 100ms for now
868 */
869 #define STM32H7_ADC_CALIB_TIMEOUT_US 100000
870
871 /**
872 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
873 * @indio_dev: IIO device instance
874 * Note: Must be called once ADC is out of power down.
875 */
876 static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev)
877 {
878 struct stm32_adc *adc = iio_priv(indio_dev);
879 int ret;
880 u32 val;
881
882 if (adc->cal.calibrated)
883 return true;
884
885 /*
886 * Select calibration mode:
887 * - Offset calibration for single ended inputs
888 * - No linearity calibration (do it later, before reading it)
889 */
890 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
891 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
892
893 /* Start calibration, then wait for completion */
894 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
895 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
896 !(val & STM32H7_ADCAL), 100,
897 STM32H7_ADC_CALIB_TIMEOUT_US);
898 if (ret) {
899 dev_err(&indio_dev->dev, "calibration failed\n");
900 goto out;
901 }
902
903 /*
904 * Select calibration mode, then start calibration:
905 * - Offset calibration for differential input
906 * - Linearity calibration (needs to be done only once for single/diff)
907 * will run simultaneously with offset calibration.
908 */
909 stm32_adc_set_bits(adc, STM32H7_ADC_CR,
910 STM32H7_ADCALDIF | STM32H7_ADCALLIN);
911 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
912 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
913 !(val & STM32H7_ADCAL), 100,
914 STM32H7_ADC_CALIB_TIMEOUT_US);
915 if (ret) {
916 dev_err(&indio_dev->dev, "calibration failed\n");
917 goto out;
918 }
919
920 out:
921 stm32_adc_clr_bits(adc, STM32H7_ADC_CR,
922 STM32H7_ADCALDIF | STM32H7_ADCALLIN);
923
924 return ret;
925 }
926
927 /**
928 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
929 * @indio_dev: IIO device instance
930 * Leave power down mode.
931 * Configure channels as single ended or differential before enabling ADC.
932 * Enable ADC.
933 * Restore calibration data.
934 * Pre-select channels that may be used in PCSEL (required by input MUX / IO):
935 * - Only one input is selected for single ended (e.g. 'vinp')
936 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn')
937 */
938 static int stm32h7_adc_prepare(struct iio_dev *indio_dev)
939 {
940 struct stm32_adc *adc = iio_priv(indio_dev);
941 int calib, ret;
942
943 ret = stm32h7_adc_exit_pwr_down(indio_dev);
944 if (ret)
945 return ret;
946
947 ret = stm32h7_adc_selfcalib(indio_dev);
948 if (ret < 0)
949 goto pwr_dwn;
950 calib = ret;
951
952 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel);
953
954 ret = stm32h7_adc_enable(indio_dev);
955 if (ret)
956 goto pwr_dwn;
957
958 /* Either restore or read calibration result for future reference */
959 if (calib)
960 ret = stm32h7_adc_restore_selfcalib(indio_dev);
961 else
962 ret = stm32h7_adc_read_selfcalib(indio_dev);
963 if (ret)
964 goto disable;
965
966 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);
967
968 return 0;
969
970 disable:
971 stm32h7_adc_disable(indio_dev);
972 pwr_dwn:
973 stm32h7_adc_enter_pwr_down(adc);
974
975 return ret;
976 }
977
978 static void stm32h7_adc_unprepare(struct iio_dev *indio_dev)
979 {
980 struct stm32_adc *adc = iio_priv(indio_dev);
981
982 stm32h7_adc_disable(indio_dev);
983 stm32h7_adc_enter_pwr_down(adc);
984 }
985
986 /**
987 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
988 * @indio_dev: IIO device
989 * @scan_mask: channels to be converted
990 *
991 * Conversion sequence :
992 * Apply sampling time settings for all channels.
993 * Configure ADC scan sequence based on selected channels in scan_mask.
994 * Add channels to SQR registers, from scan_mask LSB to MSB, then
995 * program sequence len.
996 */
997 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
998 const unsigned long *scan_mask)
999 {
1000 struct stm32_adc *adc = iio_priv(indio_dev);
1001 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;
1002 const struct iio_chan_spec *chan;
1003 u32 val, bit;
1004 int i = 0;
1005
1006 /* Apply sampling time settings */
1007 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
1008 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
1009
1010 for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
1011 chan = indio_dev->channels + bit;
1012 /*
1013 * Assign one channel per SQ entry in regular
1014 * sequence, starting with SQ1.
1015 */
1016 i++;
1017 if (i > STM32_ADC_MAX_SQ)
1018 return -EINVAL;
1019
1020 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",
1021 __func__, chan->channel, i);
1022
1023 val = stm32_adc_readl(adc, sqr[i].reg);
1024 val &= ~sqr[i].mask;
1025 val |= chan->channel << sqr[i].shift;
1026 stm32_adc_writel(adc, sqr[i].reg, val);
1027 }
1028
1029 if (!i)
1030 return -EINVAL;
1031
1032 /* Sequence len */
1033 val = stm32_adc_readl(adc, sqr[0].reg);
1034 val &= ~sqr[0].mask;
1035 val |= ((i - 1) << sqr[0].shift);
1036 stm32_adc_writel(adc, sqr[0].reg, val);
1037
1038 return 0;
1039 }
1040
1041 /**
1042 * stm32_adc_get_trig_extsel() - Get external trigger selection
1043 * @indio_dev: IIO device structure
1044 * @trig: trigger
1045 *
1046 * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
1047 */
1048 static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev,
1049 struct iio_trigger *trig)
1050 {
1051 struct stm32_adc *adc = iio_priv(indio_dev);
1052 int i;
1053
1054 /* lookup triggers registered by stm32 timer trigger driver */
1055 for (i = 0; adc->cfg->trigs[i].name; i++) {
1056 /**
1057 * Checking both stm32 timer trigger type and trig name
1058 * should be safe against arbitrary trigger names.
1059 */
1060 if ((is_stm32_timer_trigger(trig) ||
1061 is_stm32_lptim_trigger(trig)) &&
1062 !strcmp(adc->cfg->trigs[i].name, trig->name)) {
1063 return adc->cfg->trigs[i].extsel;
1064 }
1065 }
1066
1067 return -EINVAL;
1068 }
1069
1070 /**
1071 * stm32_adc_set_trig() - Set a regular trigger
1072 * @indio_dev: IIO device
1073 * @trig: IIO trigger
1074 *
1075 * Set trigger source/polarity (e.g. SW, or HW with polarity) :
1076 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
1077 * - if HW trigger enabled, set source & polarity
1078 */
1079 static int stm32_adc_set_trig(struct iio_dev *indio_dev,
1080 struct iio_trigger *trig)
1081 {
1082 struct stm32_adc *adc = iio_priv(indio_dev);
1083 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG;
1084 unsigned long flags;
1085 int ret;
1086
1087 if (trig) {
1088 ret = stm32_adc_get_trig_extsel(indio_dev, trig);
1089 if (ret < 0)
1090 return ret;
1091
1092 /* set trigger source and polarity (default to rising edge) */
1093 extsel = ret;
1094 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;
1095 }
1096
1097 spin_lock_irqsave(&adc->lock, flags);
1098 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);
1099 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);
1100 val |= exten << adc->cfg->regs->exten.shift;
1101 val |= extsel << adc->cfg->regs->extsel.shift;
1102 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val);
1103 spin_unlock_irqrestore(&adc->lock, flags);
1104
1105 return 0;
1106 }
1107
1108 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev,
1109 const struct iio_chan_spec *chan,
1110 unsigned int type)
1111 {
1112 struct stm32_adc *adc = iio_priv(indio_dev);
1113
1114 adc->trigger_polarity = type;
1115
1116 return 0;
1117 }
1118
1119 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev,
1120 const struct iio_chan_spec *chan)
1121 {
1122 struct stm32_adc *adc = iio_priv(indio_dev);
1123
1124 return adc->trigger_polarity;
1125 }
1126
1127 static const char * const stm32_trig_pol_items[] = {
1128 "rising-edge", "falling-edge", "both-edges",
1129 };
1130
1131 static const struct iio_enum stm32_adc_trig_pol = {
1132 .items = stm32_trig_pol_items,
1133 .num_items = ARRAY_SIZE(stm32_trig_pol_items),
1134 .get = stm32_adc_get_trig_pol,
1135 .set = stm32_adc_set_trig_pol,
1136 };
1137
1138 /**
1139 * stm32_adc_single_conv() - Performs a single conversion
1140 * @indio_dev: IIO device
1141 * @chan: IIO channel
1142 * @res: conversion result
1143 *
1144 * The function performs a single conversion on a given channel:
1145 * - Apply sampling time settings
1146 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1147 * - Use SW trigger
1148 * - Start conversion, then wait for interrupt completion.
1149 */
1150 static int stm32_adc_single_conv(struct iio_dev *indio_dev,
1151 const struct iio_chan_spec *chan,
1152 int *res)
1153 {
1154 struct stm32_adc *adc = iio_priv(indio_dev);
1155 struct device *dev = indio_dev->dev.parent;
1156 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1157 long timeout;
1158 u32 val;
1159 int ret;
1160
1161 reinit_completion(&adc->completion);
1162
1163 adc->bufi = 0;
1164
1165 ret = pm_runtime_get_sync(dev);
1166 if (ret < 0) {
1167 pm_runtime_put_noidle(dev);
1168 return ret;
1169 }
1170
1171 /* Apply sampling time settings */
1172 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
1173 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
1174
1175 /* Program chan number in regular sequence (SQ1) */
1176 val = stm32_adc_readl(adc, regs->sqr[1].reg);
1177 val &= ~regs->sqr[1].mask;
1178 val |= chan->channel << regs->sqr[1].shift;
1179 stm32_adc_writel(adc, regs->sqr[1].reg, val);
1180
1181 /* Set regular sequence len (0 for 1 conversion) */
1182 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);
1183
1184 /* Trigger detection disabled (conversion can be launched in SW) */
1185 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);
1186
1187 stm32_adc_conv_irq_enable(adc);
1188
1189 adc->cfg->start_conv(indio_dev, false);
1190
1191 timeout = wait_for_completion_interruptible_timeout(
1192 &adc->completion, STM32_ADC_TIMEOUT);
1193 if (timeout == 0) {
1194 ret = -ETIMEDOUT;
1195 } else if (timeout < 0) {
1196 ret = timeout;
1197 } else {
1198 *res = adc->buffer[0];
1199 ret = IIO_VAL_INT;
1200 }
1201
1202 adc->cfg->stop_conv(indio_dev);
1203
1204 stm32_adc_conv_irq_disable(adc);
1205
1206 pm_runtime_mark_last_busy(dev);
1207 pm_runtime_put_autosuspend(dev);
1208
1209 return ret;
1210 }
1211
1212 static int stm32_adc_read_raw(struct iio_dev *indio_dev,
1213 struct iio_chan_spec const *chan,
1214 int *val, int *val2, long mask)
1215 {
1216 struct stm32_adc *adc = iio_priv(indio_dev);
1217 int ret;
1218
1219 switch (mask) {
1220 case IIO_CHAN_INFO_RAW:
1221 ret = iio_device_claim_direct_mode(indio_dev);
1222 if (ret)
1223 return ret;
1224 if (chan->type == IIO_VOLTAGE)
1225 ret = stm32_adc_single_conv(indio_dev, chan, val);
1226 else
1227 ret = -EINVAL;
1228 iio_device_release_direct_mode(indio_dev);
1229 return ret;
1230
1231 case IIO_CHAN_INFO_SCALE:
1232 if (chan->differential) {
1233 *val = adc->common->vref_mv * 2;
1234 *val2 = chan->scan_type.realbits;
1235 } else {
1236 *val = adc->common->vref_mv;
1237 *val2 = chan->scan_type.realbits;
1238 }
1239 return IIO_VAL_FRACTIONAL_LOG2;
1240
1241 case IIO_CHAN_INFO_OFFSET:
1242 if (chan->differential)
1243 /* ADC_full_scale / 2 */
1244 *val = -((1 << chan->scan_type.realbits) / 2);
1245 else
1246 *val = 0;
1247 return IIO_VAL_INT;
1248
1249 default:
1250 return -EINVAL;
1251 }
1252 }
1253
1254 static void stm32_adc_irq_clear(struct iio_dev *indio_dev, u32 msk)
1255 {
1256 struct stm32_adc *adc = iio_priv(indio_dev);
1257
1258 adc->cfg->irq_clear(indio_dev, msk);
1259 }
1260
1261 static irqreturn_t stm32_adc_threaded_isr(int irq, void *data)
1262 {
1263 struct iio_dev *indio_dev = data;
1264 struct stm32_adc *adc = iio_priv(indio_dev);
1265 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1266 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1267 u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg);
1268
1269 /* Check ovr status right now, as ovr mask should be already disabled */
1270 if (status & regs->isr_ovr.mask) {
1271 /*
1272 * Clear ovr bit to avoid subsequent calls to IRQ handler.
1273 * This requires to stop ADC first. OVR bit state in ISR,
1274 * is propaged to CSR register by hardware.
1275 */
1276 adc->cfg->stop_conv(indio_dev);
1277 stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask);
1278 dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n");
1279 return IRQ_HANDLED;
1280 }
1281
1282 if (!(status & mask))
1283 dev_err_ratelimited(&indio_dev->dev,
1284 "Unexpected IRQ: IER=0x%08x, ISR=0x%08x\n",
1285 mask, status);
1286
1287 return IRQ_NONE;
1288 }
1289
1290 static irqreturn_t stm32_adc_isr(int irq, void *data)
1291 {
1292 struct iio_dev *indio_dev = data;
1293 struct stm32_adc *adc = iio_priv(indio_dev);
1294 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1295 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1296 u32 mask = stm32_adc_readl(adc, regs->ier_eoc.reg);
1297
1298 if (!(status & mask))
1299 return IRQ_WAKE_THREAD;
1300
1301 if (status & regs->isr_ovr.mask) {
1302 /*
1303 * Overrun occurred on regular conversions: data for wrong
1304 * channel may be read. Unconditionally disable interrupts
1305 * to stop processing data and print error message.
1306 * Restarting the capture can be done by disabling, then
1307 * re-enabling it (e.g. write 0, then 1 to buffer/enable).
1308 */
1309 stm32_adc_ovr_irq_disable(adc);
1310 stm32_adc_conv_irq_disable(adc);
1311 return IRQ_WAKE_THREAD;
1312 }
1313
1314 if (status & regs->isr_eoc.mask) {
1315 /* Reading DR also clears EOC status flag */
1316 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);
1317 if (iio_buffer_enabled(indio_dev)) {
1318 adc->bufi++;
1319 if (adc->bufi >= adc->num_conv) {
1320 stm32_adc_conv_irq_disable(adc);
1321 iio_trigger_poll(indio_dev->trig);
1322 }
1323 } else {
1324 complete(&adc->completion);
1325 }
1326 return IRQ_HANDLED;
1327 }
1328
1329 return IRQ_NONE;
1330 }
1331
1332 /**
1333 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1334 * @indio_dev: IIO device
1335 * @trig: new trigger
1336 *
1337 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1338 * driver, -EINVAL otherwise.
1339 */
1340 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
1341 struct iio_trigger *trig)
1342 {
1343 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1344 }
1345
1346 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1347 {
1348 struct stm32_adc *adc = iio_priv(indio_dev);
1349 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2;
1350 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE;
1351
1352 /*
1353 * dma cyclic transfers are used, buffer is split into two periods.
1354 * There should be :
1355 * - always one buffer (period) dma is working on
1356 * - one buffer (period) driver can push data.
1357 */
1358 watermark = min(watermark, val * (unsigned)(sizeof(u16)));
1359 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv);
1360
1361 return 0;
1362 }
1363
1364 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev,
1365 const unsigned long *scan_mask)
1366 {
1367 struct stm32_adc *adc = iio_priv(indio_dev);
1368 struct device *dev = indio_dev->dev.parent;
1369 int ret;
1370
1371 ret = pm_runtime_get_sync(dev);
1372 if (ret < 0) {
1373 pm_runtime_put_noidle(dev);
1374 return ret;
1375 }
1376
1377 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
1378
1379 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
1380 pm_runtime_mark_last_busy(dev);
1381 pm_runtime_put_autosuspend(dev);
1382
1383 return ret;
1384 }
1385
1386 static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
1387 const struct of_phandle_args *iiospec)
1388 {
1389 int i;
1390
1391 for (i = 0; i < indio_dev->num_channels; i++)
1392 if (indio_dev->channels[i].channel == iiospec->args[0])
1393 return i;
1394
1395 return -EINVAL;
1396 }
1397
1398 /**
1399 * stm32_adc_debugfs_reg_access - read or write register value
1400 * @indio_dev: IIO device structure
1401 * @reg: register offset
1402 * @writeval: value to write
1403 * @readval: value to read
1404 *
1405 * To read a value from an ADC register:
1406 * echo [ADC reg offset] > direct_reg_access
1407 * cat direct_reg_access
1408 *
1409 * To write a value in a ADC register:
1410 * echo [ADC_reg_offset] [value] > direct_reg_access
1411 */
1412 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
1413 unsigned reg, unsigned writeval,
1414 unsigned *readval)
1415 {
1416 struct stm32_adc *adc = iio_priv(indio_dev);
1417 struct device *dev = indio_dev->dev.parent;
1418 int ret;
1419
1420 ret = pm_runtime_get_sync(dev);
1421 if (ret < 0) {
1422 pm_runtime_put_noidle(dev);
1423 return ret;
1424 }
1425
1426 if (!readval)
1427 stm32_adc_writel(adc, reg, writeval);
1428 else
1429 *readval = stm32_adc_readl(adc, reg);
1430
1431 pm_runtime_mark_last_busy(dev);
1432 pm_runtime_put_autosuspend(dev);
1433
1434 return 0;
1435 }
1436
1437 static const struct iio_info stm32_adc_iio_info = {
1438 .read_raw = stm32_adc_read_raw,
1439 .validate_trigger = stm32_adc_validate_trigger,
1440 .hwfifo_set_watermark = stm32_adc_set_watermark,
1441 .update_scan_mode = stm32_adc_update_scan_mode,
1442 .debugfs_reg_access = stm32_adc_debugfs_reg_access,
1443 .of_xlate = stm32_adc_of_xlate,
1444 };
1445
1446 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
1447 {
1448 struct dma_tx_state state;
1449 enum dma_status status;
1450
1451 status = dmaengine_tx_status(adc->dma_chan,
1452 adc->dma_chan->cookie,
1453 &state);
1454 if (status == DMA_IN_PROGRESS) {
1455 /* Residue is size in bytes from end of buffer */
1456 unsigned int i = adc->rx_buf_sz - state.residue;
1457 unsigned int size;
1458
1459 /* Return available bytes */
1460 if (i >= adc->bufi)
1461 size = i - adc->bufi;
1462 else
1463 size = adc->rx_buf_sz + i - adc->bufi;
1464
1465 return size;
1466 }
1467
1468 return 0;
1469 }
1470
1471 static void stm32_adc_dma_buffer_done(void *data)
1472 {
1473 struct iio_dev *indio_dev = data;
1474 struct stm32_adc *adc = iio_priv(indio_dev);
1475 int residue = stm32_adc_dma_residue(adc);
1476
1477 /*
1478 * In DMA mode the trigger services of IIO are not used
1479 * (e.g. no call to iio_trigger_poll).
1480 * Calling irq handler associated to the hardware trigger is not
1481 * relevant as the conversions have already been done. Data
1482 * transfers are performed directly in DMA callback instead.
1483 * This implementation avoids to call trigger irq handler that
1484 * may sleep, in an atomic context (DMA irq handler context).
1485 */
1486 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1487
1488 while (residue >= indio_dev->scan_bytes) {
1489 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
1490
1491 iio_push_to_buffers(indio_dev, buffer);
1492
1493 residue -= indio_dev->scan_bytes;
1494 adc->bufi += indio_dev->scan_bytes;
1495 if (adc->bufi >= adc->rx_buf_sz)
1496 adc->bufi = 0;
1497 }
1498 }
1499
1500 static int stm32_adc_dma_start(struct iio_dev *indio_dev)
1501 {
1502 struct stm32_adc *adc = iio_priv(indio_dev);
1503 struct dma_async_tx_descriptor *desc;
1504 dma_cookie_t cookie;
1505 int ret;
1506
1507 if (!adc->dma_chan)
1508 return 0;
1509
1510 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
1511 adc->rx_buf_sz, adc->rx_buf_sz / 2);
1512
1513 /* Prepare a DMA cyclic transaction */
1514 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
1515 adc->rx_dma_buf,
1516 adc->rx_buf_sz, adc->rx_buf_sz / 2,
1517 DMA_DEV_TO_MEM,
1518 DMA_PREP_INTERRUPT);
1519 if (!desc)
1520 return -EBUSY;
1521
1522 desc->callback = stm32_adc_dma_buffer_done;
1523 desc->callback_param = indio_dev;
1524
1525 cookie = dmaengine_submit(desc);
1526 ret = dma_submit_error(cookie);
1527 if (ret) {
1528 dmaengine_terminate_sync(adc->dma_chan);
1529 return ret;
1530 }
1531
1532 /* Issue pending DMA requests */
1533 dma_async_issue_pending(adc->dma_chan);
1534
1535 return 0;
1536 }
1537
1538 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
1539 {
1540 struct stm32_adc *adc = iio_priv(indio_dev);
1541 struct device *dev = indio_dev->dev.parent;
1542 int ret;
1543
1544 ret = pm_runtime_get_sync(dev);
1545 if (ret < 0) {
1546 pm_runtime_put_noidle(dev);
1547 return ret;
1548 }
1549
1550 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
1551 if (ret) {
1552 dev_err(&indio_dev->dev, "Can't set trigger\n");
1553 goto err_pm_put;
1554 }
1555
1556 ret = stm32_adc_dma_start(indio_dev);
1557 if (ret) {
1558 dev_err(&indio_dev->dev, "Can't start dma\n");
1559 goto err_clr_trig;
1560 }
1561
1562 /* Reset adc buffer index */
1563 adc->bufi = 0;
1564
1565 stm32_adc_ovr_irq_enable(adc);
1566
1567 if (!adc->dma_chan)
1568 stm32_adc_conv_irq_enable(adc);
1569
1570 adc->cfg->start_conv(indio_dev, !!adc->dma_chan);
1571
1572 return 0;
1573
1574 err_clr_trig:
1575 stm32_adc_set_trig(indio_dev, NULL);
1576 err_pm_put:
1577 pm_runtime_mark_last_busy(dev);
1578 pm_runtime_put_autosuspend(dev);
1579
1580 return ret;
1581 }
1582
1583 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
1584 {
1585 struct stm32_adc *adc = iio_priv(indio_dev);
1586 struct device *dev = indio_dev->dev.parent;
1587
1588 adc->cfg->stop_conv(indio_dev);
1589 if (!adc->dma_chan)
1590 stm32_adc_conv_irq_disable(adc);
1591
1592 stm32_adc_ovr_irq_disable(adc);
1593
1594 if (adc->dma_chan)
1595 dmaengine_terminate_sync(adc->dma_chan);
1596
1597 if (stm32_adc_set_trig(indio_dev, NULL))
1598 dev_err(&indio_dev->dev, "Can't clear trigger\n");
1599
1600 pm_runtime_mark_last_busy(dev);
1601 pm_runtime_put_autosuspend(dev);
1602
1603 return 0;
1604 }
1605
1606 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = {
1607 .postenable = &stm32_adc_buffer_postenable,
1608 .predisable = &stm32_adc_buffer_predisable,
1609 };
1610
1611 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p)
1612 {
1613 struct iio_poll_func *pf = p;
1614 struct iio_dev *indio_dev = pf->indio_dev;
1615 struct stm32_adc *adc = iio_priv(indio_dev);
1616
1617 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1618
1619 /* reset buffer index */
1620 adc->bufi = 0;
1621 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
1622 pf->timestamp);
1623 iio_trigger_notify_done(indio_dev->trig);
1624
1625 /* re-enable eoc irq */
1626 stm32_adc_conv_irq_enable(adc);
1627
1628 return IRQ_HANDLED;
1629 }
1630
1631 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = {
1632 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol),
1633 {
1634 .name = "trigger_polarity_available",
1635 .shared = IIO_SHARED_BY_ALL,
1636 .read = iio_enum_available_read,
1637 .private = (uintptr_t)&stm32_adc_trig_pol,
1638 },
1639 {},
1640 };
1641
1642 static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
1643 {
1644 struct device_node *node = indio_dev->dev.of_node;
1645 struct stm32_adc *adc = iio_priv(indio_dev);
1646 unsigned int i;
1647 u32 res;
1648
1649 if (of_property_read_u32(node, "assigned-resolution-bits", &res))
1650 res = adc->cfg->adc_info->resolutions[0];
1651
1652 for (i = 0; i < adc->cfg->adc_info->num_res; i++)
1653 if (res == adc->cfg->adc_info->resolutions[i])
1654 break;
1655 if (i >= adc->cfg->adc_info->num_res) {
1656 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
1657 return -EINVAL;
1658 }
1659
1660 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res);
1661 adc->res = i;
1662
1663 return 0;
1664 }
1665
1666 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns)
1667 {
1668 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
1669 u32 period_ns, shift = smpr->shift, mask = smpr->mask;
1670 unsigned int smp, r = smpr->reg;
1671
1672 /* Determine sampling time (ADC clock cycles) */
1673 period_ns = NSEC_PER_SEC / adc->common->rate;
1674 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++)
1675 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns)
1676 break;
1677 if (smp > STM32_ADC_MAX_SMP)
1678 smp = STM32_ADC_MAX_SMP;
1679
1680 /* pre-build sampling time registers (e.g. smpr1, smpr2) */
1681 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift);
1682 }
1683
1684 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
1685 struct iio_chan_spec *chan, u32 vinp,
1686 u32 vinn, int scan_index, bool differential)
1687 {
1688 struct stm32_adc *adc = iio_priv(indio_dev);
1689 char *name = adc->chan_name[vinp];
1690
1691 chan->type = IIO_VOLTAGE;
1692 chan->channel = vinp;
1693 if (differential) {
1694 chan->differential = 1;
1695 chan->channel2 = vinn;
1696 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn);
1697 } else {
1698 snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp);
1699 }
1700 chan->datasheet_name = name;
1701 chan->scan_index = scan_index;
1702 chan->indexed = 1;
1703 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1704 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
1705 BIT(IIO_CHAN_INFO_OFFSET);
1706 chan->scan_type.sign = 'u';
1707 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
1708 chan->scan_type.storagebits = 16;
1709 chan->ext_info = stm32_adc_ext_info;
1710
1711 /* pre-build selected channels mask */
1712 adc->pcsel |= BIT(chan->channel);
1713 if (differential) {
1714 /* pre-build diff channels mask */
1715 adc->difsel |= BIT(chan->channel);
1716 /* Also add negative input to pre-selected channels */
1717 adc->pcsel |= BIT(chan->channel2);
1718 }
1719 }
1720
1721 static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
1722 {
1723 struct device_node *node = indio_dev->dev.of_node;
1724 struct stm32_adc *adc = iio_priv(indio_dev);
1725 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1726 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX];
1727 struct property *prop;
1728 const __be32 *cur;
1729 struct iio_chan_spec *channels;
1730 int scan_index = 0, num_channels = 0, num_diff = 0, ret, i;
1731 u32 val, smp = 0;
1732
1733 ret = of_property_count_u32_elems(node, "st,adc-channels");
1734 if (ret > adc_info->max_channels) {
1735 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
1736 return -EINVAL;
1737 } else if (ret > 0) {
1738 num_channels += ret;
1739 }
1740
1741 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels",
1742 sizeof(*diff));
1743 if (ret > adc_info->max_channels) {
1744 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n");
1745 return -EINVAL;
1746 } else if (ret > 0) {
1747 int size = ret * sizeof(*diff) / sizeof(u32);
1748
1749 num_diff = ret;
1750 num_channels += ret;
1751 ret = of_property_read_u32_array(node, "st,adc-diff-channels",
1752 (u32 *)diff, size);
1753 if (ret)
1754 return ret;
1755 }
1756
1757 if (!num_channels) {
1758 dev_err(&indio_dev->dev, "No channels configured\n");
1759 return -ENODATA;
1760 }
1761
1762 /* Optional sample time is provided either for each, or all channels */
1763 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs");
1764 if (ret > 1 && ret != num_channels) {
1765 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n");
1766 return -EINVAL;
1767 }
1768
1769 channels = devm_kcalloc(&indio_dev->dev, num_channels,
1770 sizeof(struct iio_chan_spec), GFP_KERNEL);
1771 if (!channels)
1772 return -ENOMEM;
1773
1774 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
1775 if (val >= adc_info->max_channels) {
1776 dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
1777 return -EINVAL;
1778 }
1779
1780 /* Channel can't be configured both as single-ended & diff */
1781 for (i = 0; i < num_diff; i++) {
1782 if (val == diff[i].vinp) {
1783 dev_err(&indio_dev->dev,
1784 "channel %d miss-configured\n", val);
1785 return -EINVAL;
1786 }
1787 }
1788 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val,
1789 0, scan_index, false);
1790 scan_index++;
1791 }
1792
1793 for (i = 0; i < num_diff; i++) {
1794 if (diff[i].vinp >= adc_info->max_channels ||
1795 diff[i].vinn >= adc_info->max_channels) {
1796 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n",
1797 diff[i].vinp, diff[i].vinn);
1798 return -EINVAL;
1799 }
1800 stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
1801 diff[i].vinp, diff[i].vinn, scan_index,
1802 true);
1803 scan_index++;
1804 }
1805
1806 for (i = 0; i < scan_index; i++) {
1807 /*
1808 * Using of_property_read_u32_index(), smp value will only be
1809 * modified if valid u32 value can be decoded. This allows to
1810 * get either no value, 1 shared value for all indexes, or one
1811 * value per channel.
1812 */
1813 of_property_read_u32_index(node, "st,min-sample-time-nsecs",
1814 i, &smp);
1815 /* Prepare sampling time settings */
1816 stm32_adc_smpr_init(adc, channels[i].channel, smp);
1817 }
1818
1819 indio_dev->num_channels = scan_index;
1820 indio_dev->channels = channels;
1821
1822 return 0;
1823 }
1824
1825 static int stm32_adc_dma_request(struct device *dev, struct iio_dev *indio_dev)
1826 {
1827 struct stm32_adc *adc = iio_priv(indio_dev);
1828 struct dma_slave_config config;
1829 int ret;
1830
1831 adc->dma_chan = dma_request_chan(dev, "rx");
1832 if (IS_ERR(adc->dma_chan)) {
1833 ret = PTR_ERR(adc->dma_chan);
1834 if (ret != -ENODEV)
1835 return dev_err_probe(dev, ret,
1836 "DMA channel request failed with\n");
1837
1838 /* DMA is optional: fall back to IRQ mode */
1839 adc->dma_chan = NULL;
1840 return 0;
1841 }
1842
1843 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1844 STM32_DMA_BUFFER_SIZE,
1845 &adc->rx_dma_buf, GFP_KERNEL);
1846 if (!adc->rx_buf) {
1847 ret = -ENOMEM;
1848 goto err_release;
1849 }
1850
1851 /* Configure DMA channel to read data register */
1852 memset(&config, 0, sizeof(config));
1853 config.src_addr = (dma_addr_t)adc->common->phys_base;
1854 config.src_addr += adc->offset + adc->cfg->regs->dr;
1855 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1856
1857 ret = dmaengine_slave_config(adc->dma_chan, &config);
1858 if (ret)
1859 goto err_free;
1860
1861 return 0;
1862
1863 err_free:
1864 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,
1865 adc->rx_buf, adc->rx_dma_buf);
1866 err_release:
1867 dma_release_channel(adc->dma_chan);
1868
1869 return ret;
1870 }
1871
1872 static int stm32_adc_probe(struct platform_device *pdev)
1873 {
1874 struct iio_dev *indio_dev;
1875 struct device *dev = &pdev->dev;
1876 irqreturn_t (*handler)(int irq, void *p) = NULL;
1877 struct stm32_adc *adc;
1878 int ret;
1879
1880 if (!pdev->dev.of_node)
1881 return -ENODEV;
1882
1883 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
1884 if (!indio_dev)
1885 return -ENOMEM;
1886
1887 adc = iio_priv(indio_dev);
1888 adc->common = dev_get_drvdata(pdev->dev.parent);
1889 spin_lock_init(&adc->lock);
1890 init_completion(&adc->completion);
1891 adc->cfg = (const struct stm32_adc_cfg *)
1892 of_match_device(dev->driver->of_match_table, dev)->data;
1893
1894 indio_dev->name = dev_name(&pdev->dev);
1895 indio_dev->dev.of_node = pdev->dev.of_node;
1896 indio_dev->info = &stm32_adc_iio_info;
1897 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;
1898
1899 platform_set_drvdata(pdev, indio_dev);
1900
1901 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
1902 if (ret != 0) {
1903 dev_err(&pdev->dev, "missing reg property\n");
1904 return -EINVAL;
1905 }
1906
1907 adc->irq = platform_get_irq(pdev, 0);
1908 if (adc->irq < 0)
1909 return adc->irq;
1910
1911 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr,
1912 stm32_adc_threaded_isr,
1913 0, pdev->name, indio_dev);
1914 if (ret) {
1915 dev_err(&pdev->dev, "failed to request IRQ\n");
1916 return ret;
1917 }
1918
1919 adc->clk = devm_clk_get(&pdev->dev, NULL);
1920 if (IS_ERR(adc->clk)) {
1921 ret = PTR_ERR(adc->clk);
1922 if (ret == -ENOENT && !adc->cfg->clk_required) {
1923 adc->clk = NULL;
1924 } else {
1925 dev_err(&pdev->dev, "Can't get clock\n");
1926 return ret;
1927 }
1928 }
1929
1930 ret = stm32_adc_of_get_resolution(indio_dev);
1931 if (ret < 0)
1932 return ret;
1933
1934 ret = stm32_adc_chan_of_init(indio_dev);
1935 if (ret < 0)
1936 return ret;
1937
1938 ret = stm32_adc_dma_request(dev, indio_dev);
1939 if (ret < 0)
1940 return ret;
1941
1942 if (!adc->dma_chan)
1943 handler = &stm32_adc_trigger_handler;
1944
1945 ret = iio_triggered_buffer_setup(indio_dev,
1946 &iio_pollfunc_store_time, handler,
1947 &stm32_adc_buffer_setup_ops);
1948 if (ret) {
1949 dev_err(&pdev->dev, "buffer setup failed\n");
1950 goto err_dma_disable;
1951 }
1952
1953 /* Get stm32-adc-core PM online */
1954 pm_runtime_get_noresume(dev);
1955 pm_runtime_set_active(dev);
1956 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_HW_STOP_DELAY_MS);
1957 pm_runtime_use_autosuspend(dev);
1958 pm_runtime_enable(dev);
1959
1960 ret = stm32_adc_hw_start(dev);
1961 if (ret)
1962 goto err_buffer_cleanup;
1963
1964 ret = iio_device_register(indio_dev);
1965 if (ret) {
1966 dev_err(&pdev->dev, "iio dev register failed\n");
1967 goto err_hw_stop;
1968 }
1969
1970 pm_runtime_mark_last_busy(dev);
1971 pm_runtime_put_autosuspend(dev);
1972
1973 return 0;
1974
1975 err_hw_stop:
1976 stm32_adc_hw_stop(dev);
1977
1978 err_buffer_cleanup:
1979 pm_runtime_disable(dev);
1980 pm_runtime_set_suspended(dev);
1981 pm_runtime_put_noidle(dev);
1982 iio_triggered_buffer_cleanup(indio_dev);
1983
1984 err_dma_disable:
1985 if (adc->dma_chan) {
1986 dma_free_coherent(adc->dma_chan->device->dev,
1987 STM32_DMA_BUFFER_SIZE,
1988 adc->rx_buf, adc->rx_dma_buf);
1989 dma_release_channel(adc->dma_chan);
1990 }
1991
1992 return ret;
1993 }
1994
1995 static int stm32_adc_remove(struct platform_device *pdev)
1996 {
1997 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1998 struct stm32_adc *adc = iio_priv(indio_dev);
1999
2000 pm_runtime_get_sync(&pdev->dev);
2001 iio_device_unregister(indio_dev);
2002 stm32_adc_hw_stop(&pdev->dev);
2003 pm_runtime_disable(&pdev->dev);
2004 pm_runtime_set_suspended(&pdev->dev);
2005 pm_runtime_put_noidle(&pdev->dev);
2006 iio_triggered_buffer_cleanup(indio_dev);
2007 if (adc->dma_chan) {
2008 dma_free_coherent(adc->dma_chan->device->dev,
2009 STM32_DMA_BUFFER_SIZE,
2010 adc->rx_buf, adc->rx_dma_buf);
2011 dma_release_channel(adc->dma_chan);
2012 }
2013
2014 return 0;
2015 }
2016
2017 #if defined(CONFIG_PM_SLEEP)
2018 static int stm32_adc_suspend(struct device *dev)
2019 {
2020 struct iio_dev *indio_dev = dev_get_drvdata(dev);
2021
2022 if (iio_buffer_enabled(indio_dev))
2023 stm32_adc_buffer_predisable(indio_dev);
2024
2025 return pm_runtime_force_suspend(dev);
2026 }
2027
2028 static int stm32_adc_resume(struct device *dev)
2029 {
2030 struct iio_dev *indio_dev = dev_get_drvdata(dev);
2031 int ret;
2032
2033 ret = pm_runtime_force_resume(dev);
2034 if (ret < 0)
2035 return ret;
2036
2037 if (!iio_buffer_enabled(indio_dev))
2038 return 0;
2039
2040 ret = stm32_adc_update_scan_mode(indio_dev,
2041 indio_dev->active_scan_mask);
2042 if (ret < 0)
2043 return ret;
2044
2045 return stm32_adc_buffer_postenable(indio_dev);
2046 }
2047 #endif
2048
2049 #if defined(CONFIG_PM)
2050 static int stm32_adc_runtime_suspend(struct device *dev)
2051 {
2052 return stm32_adc_hw_stop(dev);
2053 }
2054
2055 static int stm32_adc_runtime_resume(struct device *dev)
2056 {
2057 return stm32_adc_hw_start(dev);
2058 }
2059 #endif
2060
2061 static const struct dev_pm_ops stm32_adc_pm_ops = {
2062 SET_SYSTEM_SLEEP_PM_OPS(stm32_adc_suspend, stm32_adc_resume)
2063 SET_RUNTIME_PM_OPS(stm32_adc_runtime_suspend, stm32_adc_runtime_resume,
2064 NULL)
2065 };
2066
2067 static const struct stm32_adc_cfg stm32f4_adc_cfg = {
2068 .regs = &stm32f4_adc_regspec,
2069 .adc_info = &stm32f4_adc_info,
2070 .trigs = stm32f4_adc_trigs,
2071 .clk_required = true,
2072 .start_conv = stm32f4_adc_start_conv,
2073 .stop_conv = stm32f4_adc_stop_conv,
2074 .smp_cycles = stm32f4_adc_smp_cycles,
2075 .irq_clear = stm32f4_adc_irq_clear,
2076 };
2077
2078 static const struct stm32_adc_cfg stm32h7_adc_cfg = {
2079 .regs = &stm32h7_adc_regspec,
2080 .adc_info = &stm32h7_adc_info,
2081 .trigs = stm32h7_adc_trigs,
2082 .start_conv = stm32h7_adc_start_conv,
2083 .stop_conv = stm32h7_adc_stop_conv,
2084 .prepare = stm32h7_adc_prepare,
2085 .unprepare = stm32h7_adc_unprepare,
2086 .smp_cycles = stm32h7_adc_smp_cycles,
2087 .irq_clear = stm32h7_adc_irq_clear,
2088 };
2089
2090 static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
2091 .regs = &stm32h7_adc_regspec,
2092 .adc_info = &stm32h7_adc_info,
2093 .trigs = stm32h7_adc_trigs,
2094 .has_vregready = true,
2095 .start_conv = stm32h7_adc_start_conv,
2096 .stop_conv = stm32h7_adc_stop_conv,
2097 .prepare = stm32h7_adc_prepare,
2098 .unprepare = stm32h7_adc_unprepare,
2099 .smp_cycles = stm32h7_adc_smp_cycles,
2100 .irq_clear = stm32h7_adc_irq_clear,
2101 };
2102
2103 static const struct of_device_id stm32_adc_of_match[] = {
2104 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2105 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2106 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
2107 {},
2108 };
2109 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
2110
2111 static struct platform_driver stm32_adc_driver = {
2112 .probe = stm32_adc_probe,
2113 .remove = stm32_adc_remove,
2114 .driver = {
2115 .name = "stm32-adc",
2116 .of_match_table = stm32_adc_of_match,
2117 .pm = &stm32_adc_pm_ops,
2118 },
2119 };
2120 module_platform_driver(stm32_adc_driver);
2121
2122 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
2123 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
2124 MODULE_LICENSE("GPL v2");
2125 MODULE_ALIAS("platform:stm32-adc");
Linux with added FPC-III support