drivers/infiniband/hw/i40iw/i40iw_user.h

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   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
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   8 * COPYING in the main directory of this source tree, or the
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  33 *******************************************************************************/
  34
  35 #ifndef I40IW_USER_H
  36 #define I40IW_USER_H
  37
  38 enum i40iw_device_capabilities_const {
  39         I40IW_WQE_SIZE =                        4,
  40         I40IW_CQP_WQE_SIZE =                    8,
  41         I40IW_CQE_SIZE =                        4,
  42         I40IW_EXTENDED_CQE_SIZE =               8,
  43         I40IW_AEQE_SIZE =                       2,
  44         I40IW_CEQE_SIZE =                       1,
  45         I40IW_CQP_CTX_SIZE =                    8,
  46         I40IW_SHADOW_AREA_SIZE =                8,
  47         I40IW_CEQ_MAX_COUNT =                   256,
  48         I40IW_QUERY_FPM_BUF_SIZE =              128,
  49         I40IW_COMMIT_FPM_BUF_SIZE =             128,
  50         I40IW_MIN_IW_QP_ID =                    1,
  51         I40IW_MAX_IW_QP_ID =                    262143,
  52         I40IW_MIN_CEQID =                       0,
  53         I40IW_MAX_CEQID =                       256,
  54         I40IW_MIN_CQID =                        0,
  55         I40IW_MAX_CQID =                        131071,
  56         I40IW_MIN_AEQ_ENTRIES =                 1,
  57         I40IW_MAX_AEQ_ENTRIES =                 524287,
  58         I40IW_MIN_CEQ_ENTRIES =                 1,
  59         I40IW_MAX_CEQ_ENTRIES =                 131071,
  60         I40IW_MIN_CQ_SIZE =                     1,
  61         I40IW_MAX_CQ_SIZE =                     1048575,
  62         I40IW_DB_ID_ZERO =                      0,
  63         I40IW_MAX_WQ_FRAGMENT_COUNT =           3,
  64         I40IW_MAX_SGE_RD =                      1,
  65         I40IW_MAX_OUTBOUND_MESSAGE_SIZE =       2147483647,
  66         I40IW_MAX_INBOUND_MESSAGE_SIZE =        2147483647,
  67         I40IW_MAX_PE_ENABLED_VF_COUNT =         32,
  68         I40IW_MAX_VF_FPM_ID =                   47,
  69         I40IW_MAX_VF_PER_PF =                   127,
  70         I40IW_MAX_SQ_PAYLOAD_SIZE =             2145386496,
  71         I40IW_MAX_INLINE_DATA_SIZE =            48,
  72         I40IW_MAX_IRD_SIZE =                    64,
  73         I40IW_MAX_ORD_SIZE =                    127,
  74         I40IW_MAX_WQ_ENTRIES =                  2048,
  75         I40IW_Q2_BUFFER_SIZE =                  (248 + 100),
  76         I40IW_MAX_WQE_SIZE_RQ =                 128,
  77         I40IW_QP_CTX_SIZE =                     248,
  78         I40IW_MAX_PDS =                         32768
  79 };
  80
  81 #define i40iw_handle void *
  82 #define i40iw_adapter_handle i40iw_handle
  83 #define i40iw_qp_handle i40iw_handle
  84 #define i40iw_cq_handle i40iw_handle
  85 #define i40iw_srq_handle i40iw_handle
  86 #define i40iw_pd_id i40iw_handle
  87 #define i40iw_stag_handle i40iw_handle
  88 #define i40iw_stag_index u32
  89 #define i40iw_stag u32
  90 #define i40iw_stag_key u8
  91
  92 #define i40iw_tagged_offset u64
  93 #define i40iw_access_privileges u32
  94 #define i40iw_physical_fragment u64
  95 #define i40iw_address_list u64 *
  96
  97 #define I40IW_MAX_MR_SIZE       0x10000000000L
  98 #define I40IW_MAX_RQ_WQE_SHIFT  2
  99
 100 struct i40iw_qp_uk;
 101 struct i40iw_cq_uk;
 102 struct i40iw_srq_uk;
 103 struct i40iw_qp_uk_init_info;
 104 struct i40iw_cq_uk_init_info;
 105 struct i40iw_srq_uk_init_info;
 106
 107 struct i40iw_sge {
 108         i40iw_tagged_offset tag_off;
 109         u32 len;
 110         i40iw_stag stag;
 111 };
 112
 113 #define i40iw_sgl struct i40iw_sge *
 114
 115 struct i40iw_ring {
 116         u32 head;
 117         u32 tail;
 118         u32 size;
 119 };
 120
 121 struct i40iw_cqe {
 122         u64 buf[I40IW_CQE_SIZE];
 123 };
 124
 125 struct i40iw_extended_cqe {
 126         u64 buf[I40IW_EXTENDED_CQE_SIZE];
 127 };
 128
 129 struct i40iw_wqe {
 130         u64 buf[I40IW_WQE_SIZE];
 131 };
 132
 133 struct i40iw_qp_uk_ops;
 134
 135 enum i40iw_addressing_type {
 136         I40IW_ADDR_TYPE_ZERO_BASED = 0,
 137         I40IW_ADDR_TYPE_VA_BASED = 1,
 138 };
 139
 140 #define I40IW_ACCESS_FLAGS_LOCALREAD            0x01
 141 #define I40IW_ACCESS_FLAGS_LOCALWRITE           0x02
 142 #define I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY      0x04
 143 #define I40IW_ACCESS_FLAGS_REMOTEREAD           0x05
 144 #define I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY     0x08
 145 #define I40IW_ACCESS_FLAGS_REMOTEWRITE          0x0a
 146 #define I40IW_ACCESS_FLAGS_BIND_WINDOW          0x10
 147 #define I40IW_ACCESS_FLAGS_ALL                  0x1F
 148
 149 #define I40IW_OP_TYPE_RDMA_WRITE        0
 150 #define I40IW_OP_TYPE_RDMA_READ         1
 151 #define I40IW_OP_TYPE_SEND              3
 152 #define I40IW_OP_TYPE_SEND_INV          4
 153 #define I40IW_OP_TYPE_SEND_SOL          5
 154 #define I40IW_OP_TYPE_SEND_SOL_INV      6
 155 #define I40IW_OP_TYPE_REC               7
 156 #define I40IW_OP_TYPE_BIND_MW           8
 157 #define I40IW_OP_TYPE_FAST_REG_NSMR     9
 158 #define I40IW_OP_TYPE_INV_STAG          10
 159 #define I40IW_OP_TYPE_RDMA_READ_INV_STAG 11
 160 #define I40IW_OP_TYPE_NOP               12
 161
 162 enum i40iw_completion_status {
 163         I40IW_COMPL_STATUS_SUCCESS = 0,
 164         I40IW_COMPL_STATUS_FLUSHED,
 165         I40IW_COMPL_STATUS_INVALID_WQE,
 166         I40IW_COMPL_STATUS_QP_CATASTROPHIC,
 167         I40IW_COMPL_STATUS_REMOTE_TERMINATION,
 168         I40IW_COMPL_STATUS_INVALID_STAG,
 169         I40IW_COMPL_STATUS_BASE_BOUND_VIOLATION,
 170         I40IW_COMPL_STATUS_ACCESS_VIOLATION,
 171         I40IW_COMPL_STATUS_INVALID_PD_ID,
 172         I40IW_COMPL_STATUS_WRAP_ERROR,
 173         I40IW_COMPL_STATUS_STAG_INVALID_PDID,
 174         I40IW_COMPL_STATUS_RDMA_READ_ZERO_ORD,
 175         I40IW_COMPL_STATUS_QP_NOT_PRIVLEDGED,
 176         I40IW_COMPL_STATUS_STAG_NOT_INVALID,
 177         I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_SIZE,
 178         I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_ENTRY,
 179         I40IW_COMPL_STATUS_INVALID_FBO,
 180         I40IW_COMPL_STATUS_INVALID_LENGTH,
 181         I40IW_COMPL_STATUS_INVALID_ACCESS,
 182         I40IW_COMPL_STATUS_PHYS_BUFFER_LIST_TOO_LONG,
 183         I40IW_COMPL_STATUS_INVALID_VIRT_ADDRESS,
 184         I40IW_COMPL_STATUS_INVALID_REGION,
 185         I40IW_COMPL_STATUS_INVALID_WINDOW,
 186         I40IW_COMPL_STATUS_INVALID_TOTAL_LENGTH
 187 };
 188
 189 enum i40iw_completion_notify {
 190         IW_CQ_COMPL_EVENT = 0,
 191         IW_CQ_COMPL_SOLICITED = 1
 192 };
 193
 194 struct i40iw_post_send {
 195         i40iw_sgl sg_list;
 196         u32 num_sges;
 197 };
 198
 199 struct i40iw_post_inline_send {
 200         void *data;
 201         u32 len;
 202 };
 203
 204 struct i40iw_rdma_write {
 205         i40iw_sgl lo_sg_list;
 206         u32 num_lo_sges;
 207         struct i40iw_sge rem_addr;
 208 };
 209
 210 struct i40iw_inline_rdma_write {
 211         void *data;
 212         u32 len;
 213         struct i40iw_sge rem_addr;
 214 };
 215
 216 struct i40iw_rdma_read {
 217         struct i40iw_sge lo_addr;
 218         struct i40iw_sge rem_addr;
 219 };
 220
 221 struct i40iw_bind_window {
 222         i40iw_stag mr_stag;
 223         u64 bind_length;
 224         void *va;
 225         enum i40iw_addressing_type addressing_type;
 226         bool enable_reads;
 227         bool enable_writes;
 228         i40iw_stag mw_stag;
 229 };
 230
 231 struct i40iw_inv_local_stag {
 232         i40iw_stag target_stag;
 233 };
 234
 235 struct i40iw_post_sq_info {
 236         u64 wr_id;
 237         u8 op_type;
 238         bool signaled;
 239         bool read_fence;
 240         bool local_fence;
 241         bool inline_data;
 242         bool defer_flag;
 243         union {
 244                 struct i40iw_post_send send;
 245                 struct i40iw_rdma_write rdma_write;
 246                 struct i40iw_rdma_read rdma_read;
 247                 struct i40iw_rdma_read rdma_read_inv;
 248                 struct i40iw_bind_window bind_window;
 249                 struct i40iw_inv_local_stag inv_local_stag;
 250                 struct i40iw_inline_rdma_write inline_rdma_write;
 251                 struct i40iw_post_inline_send inline_send;
 252         } op;
 253 };
 254
 255 struct i40iw_post_rq_info {
 256         u64 wr_id;
 257         i40iw_sgl sg_list;
 258         u32 num_sges;
 259 };
 260
 261 struct i40iw_cq_poll_info {
 262         u64 wr_id;
 263         i40iw_qp_handle qp_handle;
 264         u32 bytes_xfered;
 265         u32 tcp_seq_num;
 266         u32 qp_id;
 267         i40iw_stag inv_stag;
 268         enum i40iw_completion_status comp_status;
 269         u16 major_err;
 270         u16 minor_err;
 271         u8 op_type;
 272         bool stag_invalid_set;
 273         bool error;
 274         bool is_srq;
 275         bool solicited_event;
 276 };
 277
 278 struct i40iw_qp_uk_ops {
 279         void (*iw_qp_post_wr)(struct i40iw_qp_uk *);
 280         enum i40iw_status_code (*iw_rdma_write)(struct i40iw_qp_uk *,
 281                                                 struct i40iw_post_sq_info *, bool);
 282         enum i40iw_status_code (*iw_rdma_read)(struct i40iw_qp_uk *,
 283                                                struct i40iw_post_sq_info *, bool, bool);
 284         enum i40iw_status_code (*iw_send)(struct i40iw_qp_uk *,
 285                                           struct i40iw_post_sq_info *, u32, bool);
 286         enum i40iw_status_code (*iw_inline_rdma_write)(struct i40iw_qp_uk *,
 287                                                        struct i40iw_post_sq_info *, bool);
 288         enum i40iw_status_code (*iw_inline_send)(struct i40iw_qp_uk *,
 289                                                  struct i40iw_post_sq_info *, u32, bool);
 290         enum i40iw_status_code (*iw_stag_local_invalidate)(struct i40iw_qp_uk *,
 291                                                            struct i40iw_post_sq_info *, bool);
 292         enum i40iw_status_code (*iw_mw_bind)(struct i40iw_qp_uk *,
 293                                              struct i40iw_post_sq_info *, bool);
 294         enum i40iw_status_code (*iw_post_receive)(struct i40iw_qp_uk *,
 295                                                   struct i40iw_post_rq_info *);
 296         enum i40iw_status_code (*iw_post_nop)(struct i40iw_qp_uk *, u64, bool, bool);
 297 };
 298
 299 struct i40iw_cq_ops {
 300         void (*iw_cq_request_notification)(struct i40iw_cq_uk *,
 301                                            enum i40iw_completion_notify);
 302         enum i40iw_status_code (*iw_cq_poll_completion)(struct i40iw_cq_uk *,
 303                                                         struct i40iw_cq_poll_info *);
 304         enum i40iw_status_code (*iw_cq_post_entries)(struct i40iw_cq_uk *, u8 count);
 305         void (*iw_cq_clean)(void *, struct i40iw_cq_uk *);
 306 };
 307
 308 struct i40iw_dev_uk;
 309
 310 struct i40iw_device_uk_ops {
 311         enum i40iw_status_code (*iwarp_cq_uk_init)(struct i40iw_cq_uk *,
 312                                                    struct i40iw_cq_uk_init_info *);
 313         enum i40iw_status_code (*iwarp_qp_uk_init)(struct i40iw_qp_uk *,
 314                                                    struct i40iw_qp_uk_init_info *);
 315 };
 316
 317 struct i40iw_dev_uk {
 318         struct i40iw_device_uk_ops ops_uk;
 319 };
 320
 321 struct i40iw_sq_uk_wr_trk_info {
 322         u64 wrid;
 323         u32 wr_len;
 324         u8 wqe_size;
 325         u8 reserved[3];
 326 };
 327
 328 struct i40iw_qp_quanta {
 329         u64 elem[I40IW_WQE_SIZE];
 330 };
 331
 332 struct i40iw_qp_uk {
 333         struct i40iw_qp_quanta *sq_base;
 334         struct i40iw_qp_quanta *rq_base;
 335         u32 __iomem *wqe_alloc_reg;
 336         struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
 337         u64 *rq_wrid_array;
 338         u64 *shadow_area;
 339         struct i40iw_ring sq_ring;
 340         struct i40iw_ring rq_ring;
 341         struct i40iw_ring initial_ring;
 342         u32 qp_id;
 343         u32 sq_size;
 344         u32 rq_size;
 345         u32 max_sq_frag_cnt;
 346         u32 max_rq_frag_cnt;
 347         struct i40iw_qp_uk_ops ops;
 348         bool use_srq;
 349         u8 swqe_polarity;
 350         u8 swqe_polarity_deferred;
 351         u8 rwqe_polarity;
 352         u8 rq_wqe_size;
 353         u8 rq_wqe_size_multiplier;
 354         bool first_sq_wq;
 355         bool deferred_flag;
 356 };
 357
 358 struct i40iw_cq_uk {
 359         struct i40iw_cqe *cq_base;
 360         u32 __iomem *cqe_alloc_reg;
 361         u64 *shadow_area;
 362         u32 cq_id;
 363         u32 cq_size;
 364         struct i40iw_ring cq_ring;
 365         u8 polarity;
 366         bool avoid_mem_cflct;
 367
 368         struct i40iw_cq_ops ops;
 369 };
 370
 371 struct i40iw_qp_uk_init_info {
 372         struct i40iw_qp_quanta *sq;
 373         struct i40iw_qp_quanta *rq;
 374         u32 __iomem *wqe_alloc_reg;
 375         u64 *shadow_area;
 376         struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
 377         u64 *rq_wrid_array;
 378         u32 qp_id;
 379         u32 sq_size;
 380         u32 rq_size;
 381         u32 max_sq_frag_cnt;
 382         u32 max_rq_frag_cnt;
 383         u32 max_inline_data;
 384         int abi_ver;
 385 };
 386
 387 struct i40iw_cq_uk_init_info {
 388         u32 __iomem *cqe_alloc_reg;
 389         struct i40iw_cqe *cq_base;
 390         u64 *shadow_area;
 391         u32 cq_size;
 392         u32 cq_id;
 393         bool avoid_mem_cflct;
 394 };
 395
 396 void i40iw_device_init_uk(struct i40iw_dev_uk *dev);
 397
 398 void i40iw_qp_post_wr(struct i40iw_qp_uk *qp);
 399 u64 *i40iw_qp_get_next_send_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx,
 400                                 u8 wqe_size,
 401                                 u32 total_size,
 402                                 u64 wr_id
 403                                 );
 404 u64 *i40iw_qp_get_next_recv_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx);
 405 u64 *i40iw_qp_get_next_srq_wqe(struct i40iw_srq_uk *srq, u32 *wqe_idx);
 406
 407 enum i40iw_status_code i40iw_cq_uk_init(struct i40iw_cq_uk *cq,
 408                                         struct i40iw_cq_uk_init_info *info);
 409 enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
 410                                         struct i40iw_qp_uk_init_info *info);
 411
 412 void i40iw_clean_cq(void *queue, struct i40iw_cq_uk *cq);
 413 enum i40iw_status_code i40iw_nop(struct i40iw_qp_uk *qp, u64 wr_id,
 414                                  bool signaled, bool post_sq);
 415 enum i40iw_status_code i40iw_fragcnt_to_wqesize_sq(u32 frag_cnt, u8 *wqe_size);
 416 enum i40iw_status_code i40iw_fragcnt_to_wqesize_rq(u32 frag_cnt, u8 *wqe_size);
 417 enum i40iw_status_code i40iw_inline_data_size_to_wqesize(u32 data_size,
 418                                                          u8 *wqe_size);
 419 void i40iw_get_wqe_shift(u32 sge, u32 inline_data, u8 *shift);
 420 enum i40iw_status_code i40iw_get_sqdepth(u32 sq_size, u8 shift, u32 *sqdepth);
 421 enum i40iw_status_code i40iw_get_rqdepth(u32 rq_size, u8 shift, u32 *rqdepth);
 422 #endif