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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / infiniband / hw / i40iw / i40iw_verbs.c
blob65aedfe57e77667b6ef987e8acebbf37cfa53d6e
1 /*******************************************************************************
2 *
3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenFabrics.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 *******************************************************************************/
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/random.h>
38 #include <linux/highmem.h>
39 #include <linux/time.h>
40 #include <linux/hugetlb.h>
41 #include <linux/irq.h>
42 #include <asm/byteorder.h>
43 #include <net/ip.h>
44 #include <rdma/ib_verbs.h>
45 #include <rdma/iw_cm.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/ib_umem.h>
48 #include <rdma/uverbs_ioctl.h>
49 #include "i40iw.h"
50
51 /**
52 * i40iw_query_device - get device attributes
53 * @ibdev: device pointer from stack
54 * @props: returning device attributes
55 * @udata: user data
56 */
57 static int i40iw_query_device(struct ib_device *ibdev,
58 struct ib_device_attr *props,
59 struct ib_udata *udata)
60 {
61 struct i40iw_device *iwdev = to_iwdev(ibdev);
62
63 if (udata->inlen || udata->outlen)
64 return -EINVAL;
65 memset(props, 0, sizeof(*props));
66 ether_addr_copy((u8 *)&props->sys_image_guid, iwdev->netdev->dev_addr);
67 props->fw_ver = i40iw_fw_major_ver(&iwdev->sc_dev) << 32 |
68 i40iw_fw_minor_ver(&iwdev->sc_dev);
69 props->device_cap_flags = iwdev->device_cap_flags;
70 props->vendor_id = iwdev->ldev->pcidev->vendor;
71 props->vendor_part_id = iwdev->ldev->pcidev->device;
72 props->hw_ver = (u32)iwdev->sc_dev.hw_rev;
73 props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
74 props->max_qp = iwdev->max_qp - iwdev->used_qps;
75 props->max_qp_wr = I40IW_MAX_QP_WRS;
76 props->max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
77 props->max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
78 props->max_cq = iwdev->max_cq - iwdev->used_cqs;
79 props->max_cqe = iwdev->max_cqe;
80 props->max_mr = iwdev->max_mr - iwdev->used_mrs;
81 props->max_pd = iwdev->max_pd - iwdev->used_pds;
82 props->max_sge_rd = I40IW_MAX_SGE_RD;
83 props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE;
84 props->max_qp_init_rd_atom = props->max_qp_rd_atom;
85 props->atomic_cap = IB_ATOMIC_NONE;
86 props->max_fast_reg_page_list_len = I40IW_MAX_PAGES_PER_FMR;
87 return 0;
88 }
89
90 /**
91 * i40iw_query_port - get port attrubutes
92 * @ibdev: device pointer from stack
93 * @port: port number for query
94 * @props: returning device attributes
95 */
96 static int i40iw_query_port(struct ib_device *ibdev,
97 u8 port,
98 struct ib_port_attr *props)
99 {
100 props->lid = 1;
101 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
102 IB_PORT_VENDOR_CLASS_SUP | IB_PORT_BOOT_MGMT_SUP;
103 props->gid_tbl_len = 1;
104 props->active_width = IB_WIDTH_4X;
105 props->active_speed = 1;
106 props->max_msg_sz = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
107 return 0;
108 }
109
110 /**
111 * i40iw_alloc_ucontext - Allocate the user context data structure
112 * @uctx: Uverbs context pointer from stack
113 * @udata: user data
114 *
115 * This keeps track of all objects associated with a particular
116 * user-mode client.
117 */
118 static int i40iw_alloc_ucontext(struct ib_ucontext *uctx,
119 struct ib_udata *udata)
120 {
121 struct ib_device *ibdev = uctx->device;
122 struct i40iw_device *iwdev = to_iwdev(ibdev);
123 struct i40iw_alloc_ucontext_req req;
124 struct i40iw_alloc_ucontext_resp uresp = {};
125 struct i40iw_ucontext *ucontext = to_ucontext(uctx);
126
127 if (ib_copy_from_udata(&req, udata, sizeof(req)))
128 return -EINVAL;
129
130 if (req.userspace_ver < 4 || req.userspace_ver > I40IW_ABI_VER) {
131 i40iw_pr_err("Unsupported provider library version %u.\n", req.userspace_ver);
132 return -EINVAL;
133 }
134
135 uresp.max_qps = iwdev->max_qp;
136 uresp.max_pds = iwdev->max_pd;
137 uresp.wq_size = iwdev->max_qp_wr * 2;
138 uresp.kernel_ver = req.userspace_ver;
139
140 ucontext->iwdev = iwdev;
141 ucontext->abi_ver = req.userspace_ver;
142
143 if (ib_copy_to_udata(udata, &uresp, sizeof(uresp)))
144 return -EFAULT;
145
146 INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
147 spin_lock_init(&ucontext->cq_reg_mem_list_lock);
148 INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
149 spin_lock_init(&ucontext->qp_reg_mem_list_lock);
150
151 return 0;
152 }
153
154 /**
155 * i40iw_dealloc_ucontext - deallocate the user context data structure
156 * @context: user context created during alloc
157 */
158 static void i40iw_dealloc_ucontext(struct ib_ucontext *context)
159 {
160 return;
161 }
162
163 /**
164 * i40iw_mmap - user memory map
165 * @context: context created during alloc
166 * @vma: kernel info for user memory map
167 */
168 static int i40iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
169 {
170 struct i40iw_ucontext *ucontext = to_ucontext(context);
171 u64 dbaddr;
172
173 if (vma->vm_pgoff || vma->vm_end - vma->vm_start != PAGE_SIZE)
174 return -EINVAL;
175
176 dbaddr = I40IW_DB_ADDR_OFFSET + pci_resource_start(ucontext->iwdev->ldev->pcidev, 0);
177
178 return rdma_user_mmap_io(context, vma, dbaddr >> PAGE_SHIFT, PAGE_SIZE,
179 pgprot_noncached(vma->vm_page_prot), NULL);
180 }
181
182 /**
183 * i40iw_alloc_pd - allocate protection domain
184 * @pd: PD pointer
185 * @udata: user data
186 */
187 static int i40iw_alloc_pd(struct ib_pd *pd, struct ib_udata *udata)
188 {
189 struct i40iw_pd *iwpd = to_iwpd(pd);
190 struct i40iw_device *iwdev = to_iwdev(pd->device);
191 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
192 struct i40iw_alloc_pd_resp uresp;
193 struct i40iw_sc_pd *sc_pd;
194 u32 pd_id = 0;
195 int err;
196
197 if (iwdev->closing)
198 return -ENODEV;
199
200 err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds,
201 iwdev->max_pd, &pd_id, &iwdev->next_pd);
202 if (err) {
203 i40iw_pr_err("alloc resource failed\n");
204 return err;
205 }
206
207 sc_pd = &iwpd->sc_pd;
208
209 if (udata) {
210 struct i40iw_ucontext *ucontext = rdma_udata_to_drv_context(
211 udata, struct i40iw_ucontext, ibucontext);
212 dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, ucontext->abi_ver);
213 memset(&uresp, 0, sizeof(uresp));
214 uresp.pd_id = pd_id;
215 if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
216 err = -EFAULT;
217 goto error;
218 }
219 } else {
220 dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, -1);
221 }
222
223 i40iw_add_pdusecount(iwpd);
224 return 0;
225
226 error:
227 i40iw_free_resource(iwdev, iwdev->allocated_pds, pd_id);
228 return err;
229 }
230
231 /**
232 * i40iw_dealloc_pd - deallocate pd
233 * @ibpd: ptr of pd to be deallocated
234 * @udata: user data or null for kernel object
235 */
236 static int i40iw_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
237 {
238 struct i40iw_pd *iwpd = to_iwpd(ibpd);
239 struct i40iw_device *iwdev = to_iwdev(ibpd->device);
240
241 i40iw_rem_pdusecount(iwpd, iwdev);
242 return 0;
243 }
244
245 /**
246 * i40iw_get_pbl - Retrieve pbl from a list given a virtual
247 * address
248 * @va: user virtual address
249 * @pbl_list: pbl list to search in (QP's or CQ's)
250 */
251 static struct i40iw_pbl *i40iw_get_pbl(unsigned long va,
252 struct list_head *pbl_list)
253 {
254 struct i40iw_pbl *iwpbl;
255
256 list_for_each_entry(iwpbl, pbl_list, list) {
257 if (iwpbl->user_base == va) {
258 iwpbl->on_list = false;
259 list_del(&iwpbl->list);
260 return iwpbl;
261 }
262 }
263 return NULL;
264 }
265
266 /**
267 * i40iw_free_qp_resources - free up memory resources for qp
268 * @iwdev: iwarp device
269 * @iwqp: qp ptr (user or kernel)
270 * @qp_num: qp number assigned
271 */
272 void i40iw_free_qp_resources(struct i40iw_qp *iwqp)
273 {
274 struct i40iw_pbl *iwpbl = &iwqp->iwpbl;
275 struct i40iw_device *iwdev = iwqp->iwdev;
276 u32 qp_num = iwqp->ibqp.qp_num;
277
278 i40iw_ieq_cleanup_qp(iwdev->vsi.ieq, &iwqp->sc_qp);
279 if (qp_num)
280 i40iw_free_resource(iwdev, iwdev->allocated_qps, qp_num);
281 if (iwpbl->pbl_allocated)
282 i40iw_free_pble(iwdev->pble_rsrc, &iwpbl->pble_alloc);
283 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->q2_ctx_mem);
284 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->kqp.dma_mem);
285 kfree(iwqp->kqp.wrid_mem);
286 iwqp->kqp.wrid_mem = NULL;
287 kfree(iwqp);
288 }
289
290 /**
291 * i40iw_clean_cqes - clean cq entries for qp
292 * @iwqp: qp ptr (user or kernel)
293 * @iwcq: cq ptr
294 */
295 static void i40iw_clean_cqes(struct i40iw_qp *iwqp, struct i40iw_cq *iwcq)
296 {
297 struct i40iw_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
298
299 ukcq->ops.iw_cq_clean(&iwqp->sc_qp.qp_uk, ukcq);
300 }
301
302 /**
303 * i40iw_destroy_qp - destroy qp
304 * @ibqp: qp's ib pointer also to get to device's qp address
305 */
306 static int i40iw_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
307 {
308 struct i40iw_qp *iwqp = to_iwqp(ibqp);
309 struct ib_qp_attr attr;
310 struct i40iw_device *iwdev = iwqp->iwdev;
311
312 memset(&attr, 0, sizeof(attr));
313
314 iwqp->destroyed = 1;
315
316 if (iwqp->ibqp_state >= IB_QPS_INIT && iwqp->ibqp_state < IB_QPS_RTS)
317 i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 0, 0, 0);
318
319 if (!iwqp->user_mode) {
320 if (iwqp->iwscq) {
321 i40iw_clean_cqes(iwqp, iwqp->iwscq);
322 if (iwqp->iwrcq != iwqp->iwscq)
323 i40iw_clean_cqes(iwqp, iwqp->iwrcq);
324 }
325 }
326
327 attr.qp_state = IB_QPS_ERR;
328 i40iw_modify_qp(&iwqp->ibqp, &attr, IB_QP_STATE, NULL);
329 i40iw_qp_rem_ref(&iwqp->ibqp);
330 wait_for_completion(&iwqp->free_qp);
331 i40iw_cqp_qp_destroy_cmd(&iwdev->sc_dev, &iwqp->sc_qp);
332 i40iw_rem_pdusecount(iwqp->iwpd, iwdev);
333 i40iw_free_qp_resources(iwqp);
334 i40iw_rem_devusecount(iwdev);
335
336 return 0;
337 }
338
339 /**
340 * i40iw_setup_virt_qp - setup for allocation of virtual qp
341 * @dev: iwarp device
342 * @qp: qp ptr
343 * @init_info: initialize info to return
344 */
345 static int i40iw_setup_virt_qp(struct i40iw_device *iwdev,
346 struct i40iw_qp *iwqp,
347 struct i40iw_qp_init_info *init_info)
348 {
349 struct i40iw_pbl *iwpbl = &iwqp->iwpbl;
350 struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
351
352 iwqp->page = qpmr->sq_page;
353 init_info->shadow_area_pa = cpu_to_le64(qpmr->shadow);
354 if (iwpbl->pbl_allocated) {
355 init_info->virtual_map = true;
356 init_info->sq_pa = qpmr->sq_pbl.idx;
357 init_info->rq_pa = qpmr->rq_pbl.idx;
358 } else {
359 init_info->sq_pa = qpmr->sq_pbl.addr;
360 init_info->rq_pa = qpmr->rq_pbl.addr;
361 }
362 return 0;
363 }
364
365 /**
366 * i40iw_setup_kmode_qp - setup initialization for kernel mode qp
367 * @iwdev: iwarp device
368 * @iwqp: qp ptr (user or kernel)
369 * @info: initialize info to return
370 */
371 static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev,
372 struct i40iw_qp *iwqp,
373 struct i40iw_qp_init_info *info)
374 {
375 struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem;
376 u32 sqdepth, rqdepth;
377 u8 sqshift;
378 u32 size;
379 enum i40iw_status_code status;
380 struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
381
382 i40iw_get_wqe_shift(ukinfo->max_sq_frag_cnt, ukinfo->max_inline_data, &sqshift);
383 status = i40iw_get_sqdepth(ukinfo->sq_size, sqshift, &sqdepth);
384 if (status)
385 return -ENOMEM;
386
387 status = i40iw_get_rqdepth(ukinfo->rq_size, I40IW_MAX_RQ_WQE_SHIFT, &rqdepth);
388 if (status)
389 return -ENOMEM;
390
391 size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3);
392 iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL);
393
394 ukinfo->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)iwqp->kqp.wrid_mem;
395 if (!ukinfo->sq_wrtrk_array)
396 return -ENOMEM;
397
398 ukinfo->rq_wrid_array = (u64 *)&ukinfo->sq_wrtrk_array[sqdepth];
399
400 size = (sqdepth + rqdepth) * I40IW_QP_WQE_MIN_SIZE;
401 size += (I40IW_SHADOW_AREA_SIZE << 3);
402
403 status = i40iw_allocate_dma_mem(iwdev->sc_dev.hw, mem, size, 256);
404 if (status) {
405 kfree(ukinfo->sq_wrtrk_array);
406 ukinfo->sq_wrtrk_array = NULL;
407 return -ENOMEM;
408 }
409
410 ukinfo->sq = mem->va;
411 info->sq_pa = mem->pa;
412
413 ukinfo->rq = &ukinfo->sq[sqdepth];
414 info->rq_pa = info->sq_pa + (sqdepth * I40IW_QP_WQE_MIN_SIZE);
415
416 ukinfo->shadow_area = ukinfo->rq[rqdepth].elem;
417 info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE);
418
419 ukinfo->sq_size = sqdepth >> sqshift;
420 ukinfo->rq_size = rqdepth >> I40IW_MAX_RQ_WQE_SHIFT;
421 ukinfo->qp_id = iwqp->ibqp.qp_num;
422 return 0;
423 }
424
425 /**
426 * i40iw_create_qp - create qp
427 * @ibpd: ptr of pd
428 * @init_attr: attributes for qp
429 * @udata: user data for create qp
430 */
431 static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
432 struct ib_qp_init_attr *init_attr,
433 struct ib_udata *udata)
434 {
435 struct i40iw_pd *iwpd = to_iwpd(ibpd);
436 struct i40iw_device *iwdev = to_iwdev(ibpd->device);
437 struct i40iw_cqp *iwcqp = &iwdev->cqp;
438 struct i40iw_qp *iwqp;
439 struct i40iw_ucontext *ucontext = rdma_udata_to_drv_context(
440 udata, struct i40iw_ucontext, ibucontext);
441 struct i40iw_create_qp_req req;
442 struct i40iw_create_qp_resp uresp;
443 u32 qp_num = 0;
444 enum i40iw_status_code ret;
445 int err_code;
446 int sq_size;
447 int rq_size;
448 struct i40iw_sc_qp *qp;
449 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
450 struct i40iw_qp_init_info init_info;
451 struct i40iw_create_qp_info *qp_info;
452 struct i40iw_cqp_request *cqp_request;
453 struct cqp_commands_info *cqp_info;
454
455 struct i40iw_qp_host_ctx_info *ctx_info;
456 struct i40iwarp_offload_info *iwarp_info;
457 unsigned long flags;
458
459 if (iwdev->closing)
460 return ERR_PTR(-ENODEV);
461
462 if (init_attr->create_flags)
463 return ERR_PTR(-EOPNOTSUPP);
464 if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE)
465 init_attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
466
467 if (init_attr->cap.max_send_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
468 init_attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
469
470 if (init_attr->cap.max_recv_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
471 init_attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
472
473 memset(&init_info, 0, sizeof(init_info));
474
475 sq_size = init_attr->cap.max_send_wr;
476 rq_size = init_attr->cap.max_recv_wr;
477
478 init_info.vsi = &iwdev->vsi;
479 init_info.qp_uk_init_info.sq_size = sq_size;
480 init_info.qp_uk_init_info.rq_size = rq_size;
481 init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
482 init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
483 init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data;
484
485 iwqp = kzalloc(sizeof(*iwqp), GFP_KERNEL);
486 if (!iwqp)
487 return ERR_PTR(-ENOMEM);
488
489 qp = &iwqp->sc_qp;
490 qp->back_qp = (void *)iwqp;
491 iwqp->iwdev = iwdev;
492 iwqp->ctx_info.iwarp_info = &iwqp->iwarp_info;
493
494 if (i40iw_allocate_dma_mem(dev->hw,
495 &iwqp->q2_ctx_mem,
496 I40IW_Q2_BUFFER_SIZE + I40IW_QP_CTX_SIZE,
497 256)) {
498 i40iw_pr_err("dma_mem failed\n");
499 err_code = -ENOMEM;
500 goto error;
501 }
502
503 init_info.q2 = iwqp->q2_ctx_mem.va;
504 init_info.q2_pa = iwqp->q2_ctx_mem.pa;
505
506 init_info.host_ctx = (void *)init_info.q2 + I40IW_Q2_BUFFER_SIZE;
507 init_info.host_ctx_pa = init_info.q2_pa + I40IW_Q2_BUFFER_SIZE;
508
509 err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_qps, iwdev->max_qp,
510 &qp_num, &iwdev->next_qp);
511 if (err_code) {
512 i40iw_pr_err("qp resource\n");
513 goto error;
514 }
515
516 iwqp->iwpd = iwpd;
517 iwqp->ibqp.qp_num = qp_num;
518 qp = &iwqp->sc_qp;
519 iwqp->iwscq = to_iwcq(init_attr->send_cq);
520 iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
521
522 iwqp->host_ctx.va = init_info.host_ctx;
523 iwqp->host_ctx.pa = init_info.host_ctx_pa;
524 iwqp->host_ctx.size = I40IW_QP_CTX_SIZE;
525
526 init_info.pd = &iwpd->sc_pd;
527 init_info.qp_uk_init_info.qp_id = iwqp->ibqp.qp_num;
528 iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
529
530 if (init_attr->qp_type != IB_QPT_RC) {
531 err_code = -EOPNOTSUPP;
532 goto error;
533 }
534 if (udata) {
535 err_code = ib_copy_from_udata(&req, udata, sizeof(req));
536 if (err_code) {
537 i40iw_pr_err("ib_copy_from_data\n");
538 goto error;
539 }
540 iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
541 iwqp->user_mode = 1;
542
543 if (req.user_wqe_buffers) {
544 struct i40iw_pbl *iwpbl;
545
546 spin_lock_irqsave(
547 &ucontext->qp_reg_mem_list_lock, flags);
548 iwpbl = i40iw_get_pbl(
549 (unsigned long)req.user_wqe_buffers,
550 &ucontext->qp_reg_mem_list);
551 spin_unlock_irqrestore(
552 &ucontext->qp_reg_mem_list_lock, flags);
553
554 if (!iwpbl) {
555 err_code = -ENODATA;
556 i40iw_pr_err("no pbl info\n");
557 goto error;
558 }
559 memcpy(&iwqp->iwpbl, iwpbl, sizeof(iwqp->iwpbl));
560 }
561 err_code = i40iw_setup_virt_qp(iwdev, iwqp, &init_info);
562 } else {
563 err_code = i40iw_setup_kmode_qp(iwdev, iwqp, &init_info);
564 }
565
566 if (err_code) {
567 i40iw_pr_err("setup qp failed\n");
568 goto error;
569 }
570
571 init_info.type = I40IW_QP_TYPE_IWARP;
572 ret = dev->iw_priv_qp_ops->qp_init(qp, &init_info);
573 if (ret) {
574 err_code = -EPROTO;
575 i40iw_pr_err("qp_init fail\n");
576 goto error;
577 }
578 ctx_info = &iwqp->ctx_info;
579 iwarp_info = &iwqp->iwarp_info;
580 iwarp_info->rd_enable = true;
581 iwarp_info->wr_rdresp_en = true;
582 if (!iwqp->user_mode) {
583 iwarp_info->fast_reg_en = true;
584 iwarp_info->priv_mode_en = true;
585 }
586 iwarp_info->ddp_ver = 1;
587 iwarp_info->rdmap_ver = 1;
588
589 ctx_info->iwarp_info_valid = true;
590 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
591 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
592 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
593 (u64 *)iwqp->host_ctx.va,
594 ctx_info);
595 ctx_info->iwarp_info_valid = false;
596 cqp_request = i40iw_get_cqp_request(iwcqp, true);
597 if (!cqp_request) {
598 err_code = -ENOMEM;
599 goto error;
600 }
601 cqp_info = &cqp_request->info;
602 qp_info = &cqp_request->info.in.u.qp_create.info;
603
604 memset(qp_info, 0, sizeof(*qp_info));
605
606 qp_info->cq_num_valid = true;
607 qp_info->next_iwarp_state = I40IW_QP_STATE_IDLE;
608
609 cqp_info->cqp_cmd = OP_QP_CREATE;
610 cqp_info->post_sq = 1;
611 cqp_info->in.u.qp_create.qp = qp;
612 cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
613 ret = i40iw_handle_cqp_op(iwdev, cqp_request);
614 if (ret) {
615 i40iw_pr_err("CQP-OP QP create fail");
616 err_code = -EACCES;
617 goto error;
618 }
619
620 refcount_set(&iwqp->refcount, 1);
621 spin_lock_init(&iwqp->lock);
622 iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
623 iwdev->qp_table[qp_num] = iwqp;
624 i40iw_add_pdusecount(iwqp->iwpd);
625 i40iw_add_devusecount(iwdev);
626 if (udata) {
627 memset(&uresp, 0, sizeof(uresp));
628 uresp.actual_sq_size = sq_size;
629 uresp.actual_rq_size = rq_size;
630 uresp.qp_id = qp_num;
631 uresp.push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
632 err_code = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
633 if (err_code) {
634 i40iw_pr_err("copy_to_udata failed\n");
635 i40iw_destroy_qp(&iwqp->ibqp, udata);
636 /* let the completion of the qp destroy free the qp */
637 return ERR_PTR(err_code);
638 }
639 }
640 init_completion(&iwqp->sq_drained);
641 init_completion(&iwqp->rq_drained);
642 init_completion(&iwqp->free_qp);
643
644 return &iwqp->ibqp;
645 error:
646 i40iw_free_qp_resources(iwqp);
647 return ERR_PTR(err_code);
648 }
649
650 /**
651 * i40iw_query - query qp attributes
652 * @ibqp: qp pointer
653 * @attr: attributes pointer
654 * @attr_mask: Not used
655 * @init_attr: qp attributes to return
656 */
657 static int i40iw_query_qp(struct ib_qp *ibqp,
658 struct ib_qp_attr *attr,
659 int attr_mask,
660 struct ib_qp_init_attr *init_attr)
661 {
662 struct i40iw_qp *iwqp = to_iwqp(ibqp);
663 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
664
665 attr->qp_state = iwqp->ibqp_state;
666 attr->cur_qp_state = attr->qp_state;
667 attr->qp_access_flags = 0;
668 attr->cap.max_send_wr = qp->qp_uk.sq_size;
669 attr->cap.max_recv_wr = qp->qp_uk.rq_size;
670 attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
671 attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
672 attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
673 attr->port_num = 1;
674 init_attr->event_handler = iwqp->ibqp.event_handler;
675 init_attr->qp_context = iwqp->ibqp.qp_context;
676 init_attr->send_cq = iwqp->ibqp.send_cq;
677 init_attr->recv_cq = iwqp->ibqp.recv_cq;
678 init_attr->srq = iwqp->ibqp.srq;
679 init_attr->cap = attr->cap;
680 init_attr->port_num = 1;
681 return 0;
682 }
683
684 /**
685 * i40iw_hw_modify_qp - setup cqp for modify qp
686 * @iwdev: iwarp device
687 * @iwqp: qp ptr (user or kernel)
688 * @info: info for modify qp
689 * @wait: flag to wait or not for modify qp completion
690 */
691 void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp,
692 struct i40iw_modify_qp_info *info, bool wait)
693 {
694 struct i40iw_cqp_request *cqp_request;
695 struct cqp_commands_info *cqp_info;
696 struct i40iw_modify_qp_info *m_info;
697 struct i40iw_gen_ae_info ae_info;
698
699 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
700 if (!cqp_request)
701 return;
702
703 cqp_info = &cqp_request->info;
704 m_info = &cqp_info->in.u.qp_modify.info;
705 memcpy(m_info, info, sizeof(*m_info));
706 cqp_info->cqp_cmd = OP_QP_MODIFY;
707 cqp_info->post_sq = 1;
708 cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
709 cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
710 if (!i40iw_handle_cqp_op(iwdev, cqp_request))
711 return;
712
713 switch (m_info->next_iwarp_state) {
714 case I40IW_QP_STATE_RTS:
715 if (iwqp->iwarp_state == I40IW_QP_STATE_IDLE)
716 i40iw_send_reset(iwqp->cm_node);
717 fallthrough;
718 case I40IW_QP_STATE_IDLE:
719 case I40IW_QP_STATE_TERMINATE:
720 case I40IW_QP_STATE_CLOSING:
721 ae_info.ae_code = I40IW_AE_BAD_CLOSE;
722 ae_info.ae_source = 0;
723 i40iw_gen_ae(iwdev, &iwqp->sc_qp, &ae_info, false);
724 break;
725 case I40IW_QP_STATE_ERROR:
726 default:
727 break;
728 }
729 }
730
731 /**
732 * i40iw_modify_qp - modify qp request
733 * @ibqp: qp's pointer for modify
734 * @attr: access attributes
735 * @attr_mask: state mask
736 * @udata: user data
737 */
738 int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
739 int attr_mask, struct ib_udata *udata)
740 {
741 struct i40iw_qp *iwqp = to_iwqp(ibqp);
742 struct i40iw_device *iwdev = iwqp->iwdev;
743 struct i40iw_qp_host_ctx_info *ctx_info;
744 struct i40iwarp_offload_info *iwarp_info;
745 struct i40iw_modify_qp_info info;
746 u8 issue_modify_qp = 0;
747 u8 dont_wait = 0;
748 u32 err;
749 unsigned long flags;
750
751 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
752 return -EOPNOTSUPP;
753
754 memset(&info, 0, sizeof(info));
755 ctx_info = &iwqp->ctx_info;
756 iwarp_info = &iwqp->iwarp_info;
757
758 spin_lock_irqsave(&iwqp->lock, flags);
759
760 if (attr_mask & IB_QP_STATE) {
761 if (iwdev->closing && attr->qp_state != IB_QPS_ERR) {
762 err = -EINVAL;
763 goto exit;
764 }
765
766 switch (attr->qp_state) {
767 case IB_QPS_INIT:
768 case IB_QPS_RTR:
769 if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_IDLE) {
770 err = -EINVAL;
771 goto exit;
772 }
773 if (iwqp->iwarp_state == I40IW_QP_STATE_INVALID) {
774 info.next_iwarp_state = I40IW_QP_STATE_IDLE;
775 issue_modify_qp = 1;
776 }
777 break;
778 case IB_QPS_RTS:
779 if ((iwqp->iwarp_state > (u32)I40IW_QP_STATE_RTS) ||
780 (!iwqp->cm_id)) {
781 err = -EINVAL;
782 goto exit;
783 }
784
785 issue_modify_qp = 1;
786 iwqp->hw_tcp_state = I40IW_TCP_STATE_ESTABLISHED;
787 iwqp->hte_added = 1;
788 info.next_iwarp_state = I40IW_QP_STATE_RTS;
789 info.tcp_ctx_valid = true;
790 info.ord_valid = true;
791 info.arp_cache_idx_valid = true;
792 info.cq_num_valid = true;
793 break;
794 case IB_QPS_SQD:
795 if (iwqp->hw_iwarp_state > (u32)I40IW_QP_STATE_RTS) {
796 err = 0;
797 goto exit;
798 }
799 if ((iwqp->iwarp_state == (u32)I40IW_QP_STATE_CLOSING) ||
800 (iwqp->iwarp_state < (u32)I40IW_QP_STATE_RTS)) {
801 err = 0;
802 goto exit;
803 }
804 if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_CLOSING) {
805 err = -EINVAL;
806 goto exit;
807 }
808 info.next_iwarp_state = I40IW_QP_STATE_CLOSING;
809 issue_modify_qp = 1;
810 break;
811 case IB_QPS_SQE:
812 if (iwqp->iwarp_state >= (u32)I40IW_QP_STATE_TERMINATE) {
813 err = -EINVAL;
814 goto exit;
815 }
816 info.next_iwarp_state = I40IW_QP_STATE_TERMINATE;
817 issue_modify_qp = 1;
818 break;
819 case IB_QPS_ERR:
820 case IB_QPS_RESET:
821 if (iwqp->iwarp_state == (u32)I40IW_QP_STATE_ERROR) {
822 err = -EINVAL;
823 goto exit;
824 }
825 if (iwqp->sc_qp.term_flags)
826 i40iw_terminate_del_timer(&iwqp->sc_qp);
827 info.next_iwarp_state = I40IW_QP_STATE_ERROR;
828 if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) &&
829 iwdev->iw_status &&
830 (iwqp->hw_tcp_state != I40IW_TCP_STATE_TIME_WAIT))
831 info.reset_tcp_conn = true;
832 else
833 dont_wait = 1;
834 issue_modify_qp = 1;
835 info.next_iwarp_state = I40IW_QP_STATE_ERROR;
836 break;
837 default:
838 err = -EINVAL;
839 goto exit;
840 }
841
842 iwqp->ibqp_state = attr->qp_state;
843
844 }
845 if (attr_mask & IB_QP_ACCESS_FLAGS) {
846 ctx_info->iwarp_info_valid = true;
847 if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
848 iwarp_info->wr_rdresp_en = true;
849 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
850 iwarp_info->wr_rdresp_en = true;
851 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
852 iwarp_info->rd_enable = true;
853 if (attr->qp_access_flags & IB_ACCESS_MW_BIND)
854 iwarp_info->bind_en = true;
855
856 if (iwqp->user_mode) {
857 iwarp_info->rd_enable = true;
858 iwarp_info->wr_rdresp_en = true;
859 iwarp_info->priv_mode_en = false;
860 }
861 }
862
863 if (ctx_info->iwarp_info_valid) {
864 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
865 int ret;
866
867 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
868 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
869 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
870 (u64 *)iwqp->host_ctx.va,
871 ctx_info);
872 if (ret) {
873 i40iw_pr_err("setting QP context\n");
874 err = -EINVAL;
875 goto exit;
876 }
877 }
878
879 spin_unlock_irqrestore(&iwqp->lock, flags);
880
881 if (issue_modify_qp) {
882 i40iw_hw_modify_qp(iwdev, iwqp, &info, true);
883
884 spin_lock_irqsave(&iwqp->lock, flags);
885 iwqp->iwarp_state = info.next_iwarp_state;
886 spin_unlock_irqrestore(&iwqp->lock, flags);
887 }
888
889 if (issue_modify_qp && (iwqp->ibqp_state > IB_QPS_RTS)) {
890 if (dont_wait) {
891 if (iwqp->cm_id && iwqp->hw_tcp_state) {
892 spin_lock_irqsave(&iwqp->lock, flags);
893 iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSED;
894 iwqp->last_aeq = I40IW_AE_RESET_SENT;
895 spin_unlock_irqrestore(&iwqp->lock, flags);
896 i40iw_cm_disconn(iwqp);
897 }
898 } else {
899 spin_lock_irqsave(&iwqp->lock, flags);
900 if (iwqp->cm_id) {
901 if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
902 iwqp->cm_id->add_ref(iwqp->cm_id);
903 i40iw_schedule_cm_timer(iwqp->cm_node,
904 (struct i40iw_puda_buf *)iwqp,
905 I40IW_TIMER_TYPE_CLOSE, 1, 0);
906 }
907 }
908 spin_unlock_irqrestore(&iwqp->lock, flags);
909 }
910 }
911 return 0;
912 exit:
913 spin_unlock_irqrestore(&iwqp->lock, flags);
914 return err;
915 }
916
917 /**
918 * cq_free_resources - free up recources for cq
919 * @iwdev: iwarp device
920 * @iwcq: cq ptr
921 */
922 static void cq_free_resources(struct i40iw_device *iwdev, struct i40iw_cq *iwcq)
923 {
924 struct i40iw_sc_cq *cq = &iwcq->sc_cq;
925
926 if (!iwcq->user_mode)
927 i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwcq->kmem);
928 i40iw_free_resource(iwdev, iwdev->allocated_cqs, cq->cq_uk.cq_id);
929 }
930
931 /**
932 * i40iw_cq_wq_destroy - send cq destroy cqp
933 * @iwdev: iwarp device
934 * @cq: hardware control cq
935 */
936 void i40iw_cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq)
937 {
938 enum i40iw_status_code status;
939 struct i40iw_cqp_request *cqp_request;
940 struct cqp_commands_info *cqp_info;
941
942 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
943 if (!cqp_request)
944 return;
945
946 cqp_info = &cqp_request->info;
947
948 cqp_info->cqp_cmd = OP_CQ_DESTROY;
949 cqp_info->post_sq = 1;
950 cqp_info->in.u.cq_destroy.cq = cq;
951 cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;
952 status = i40iw_handle_cqp_op(iwdev, cqp_request);
953 if (status)
954 i40iw_pr_err("CQP-OP Destroy QP fail");
955 }
956
957 /**
958 * i40iw_destroy_cq - destroy cq
959 * @ib_cq: cq pointer
960 * @udata: user data or NULL for kernel object
961 */
962 static int i40iw_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
963 {
964 struct i40iw_cq *iwcq;
965 struct i40iw_device *iwdev;
966 struct i40iw_sc_cq *cq;
967
968 iwcq = to_iwcq(ib_cq);
969 iwdev = to_iwdev(ib_cq->device);
970 cq = &iwcq->sc_cq;
971 i40iw_cq_wq_destroy(iwdev, cq);
972 cq_free_resources(iwdev, iwcq);
973 i40iw_rem_devusecount(iwdev);
974 return 0;
975 }
976
977 /**
978 * i40iw_create_cq - create cq
979 * @ibcq: CQ allocated
980 * @attr: attributes for cq
981 * @udata: user data
982 */
983 static int i40iw_create_cq(struct ib_cq *ibcq,
984 const struct ib_cq_init_attr *attr,
985 struct ib_udata *udata)
986 {
987 struct ib_device *ibdev = ibcq->device;
988 struct i40iw_device *iwdev = to_iwdev(ibdev);
989 struct i40iw_cq *iwcq = to_iwcq(ibcq);
990 struct i40iw_pbl *iwpbl;
991 u32 cq_num = 0;
992 struct i40iw_sc_cq *cq;
993 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
994 struct i40iw_cq_init_info info = {};
995 enum i40iw_status_code status;
996 struct i40iw_cqp_request *cqp_request;
997 struct cqp_commands_info *cqp_info;
998 struct i40iw_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
999 unsigned long flags;
1000 int err_code;
1001 int entries = attr->cqe;
1002
1003 if (attr->flags)
1004 return -EOPNOTSUPP;
1005
1006 if (iwdev->closing)
1007 return -ENODEV;
1008
1009 if (entries > iwdev->max_cqe)
1010 return -EINVAL;
1011
1012 err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_cqs,
1013 iwdev->max_cq, &cq_num,
1014 &iwdev->next_cq);
1015 if (err_code)
1016 return err_code;
1017
1018 cq = &iwcq->sc_cq;
1019 cq->back_cq = (void *)iwcq;
1020 spin_lock_init(&iwcq->lock);
1021
1022 info.dev = dev;
1023 ukinfo->cq_size = max(entries, 4);
1024 ukinfo->cq_id = cq_num;
1025 iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
1026 info.ceqe_mask = 0;
1027 if (attr->comp_vector < iwdev->ceqs_count)
1028 info.ceq_id = attr->comp_vector;
1029 info.ceq_id_valid = true;
1030 info.ceqe_mask = 1;
1031 info.type = I40IW_CQ_TYPE_IWARP;
1032 if (udata) {
1033 struct i40iw_ucontext *ucontext = rdma_udata_to_drv_context(
1034 udata, struct i40iw_ucontext, ibucontext);
1035 struct i40iw_create_cq_req req;
1036 struct i40iw_cq_mr *cqmr;
1037
1038 memset(&req, 0, sizeof(req));
1039 iwcq->user_mode = true;
1040 if (ib_copy_from_udata(&req, udata, sizeof(struct i40iw_create_cq_req))) {
1041 err_code = -EFAULT;
1042 goto cq_free_resources;
1043 }
1044
1045 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
1046 iwpbl = i40iw_get_pbl((unsigned long)req.user_cq_buffer,
1047 &ucontext->cq_reg_mem_list);
1048 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1049 if (!iwpbl) {
1050 err_code = -EPROTO;
1051 goto cq_free_resources;
1052 }
1053
1054 iwcq->iwpbl = iwpbl;
1055 iwcq->cq_mem_size = 0;
1056 cqmr = &iwpbl->cq_mr;
1057 info.shadow_area_pa = cpu_to_le64(cqmr->shadow);
1058 if (iwpbl->pbl_allocated) {
1059 info.virtual_map = true;
1060 info.pbl_chunk_size = 1;
1061 info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
1062 } else {
1063 info.cq_base_pa = cqmr->cq_pbl.addr;
1064 }
1065 } else {
1066 /* Kmode allocations */
1067 int rsize;
1068 int shadow;
1069
1070 rsize = info.cq_uk_init_info.cq_size * sizeof(struct i40iw_cqe);
1071 rsize = round_up(rsize, 256);
1072 shadow = I40IW_SHADOW_AREA_SIZE << 3;
1073 status = i40iw_allocate_dma_mem(dev->hw, &iwcq->kmem,
1074 rsize + shadow, 256);
1075 if (status) {
1076 err_code = -ENOMEM;
1077 goto cq_free_resources;
1078 }
1079 ukinfo->cq_base = iwcq->kmem.va;
1080 info.cq_base_pa = iwcq->kmem.pa;
1081 info.shadow_area_pa = info.cq_base_pa + rsize;
1082 ukinfo->shadow_area = iwcq->kmem.va + rsize;
1083 }
1084
1085 if (dev->iw_priv_cq_ops->cq_init(cq, &info)) {
1086 i40iw_pr_err("init cq fail\n");
1087 err_code = -EPROTO;
1088 goto cq_free_resources;
1089 }
1090
1091 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1092 if (!cqp_request) {
1093 err_code = -ENOMEM;
1094 goto cq_free_resources;
1095 }
1096
1097 cqp_info = &cqp_request->info;
1098 cqp_info->cqp_cmd = OP_CQ_CREATE;
1099 cqp_info->post_sq = 1;
1100 cqp_info->in.u.cq_create.cq = cq;
1101 cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
1102 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1103 if (status) {
1104 i40iw_pr_err("CQP-OP Create QP fail");
1105 err_code = -EPROTO;
1106 goto cq_free_resources;
1107 }
1108
1109 if (udata) {
1110 struct i40iw_create_cq_resp resp;
1111
1112 memset(&resp, 0, sizeof(resp));
1113 resp.cq_id = info.cq_uk_init_info.cq_id;
1114 resp.cq_size = info.cq_uk_init_info.cq_size;
1115 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1116 i40iw_pr_err("copy to user data\n");
1117 err_code = -EPROTO;
1118 goto cq_destroy;
1119 }
1120 }
1121
1122 i40iw_add_devusecount(iwdev);
1123 return 0;
1124
1125 cq_destroy:
1126 i40iw_cq_wq_destroy(iwdev, cq);
1127 cq_free_resources:
1128 cq_free_resources(iwdev, iwcq);
1129 return err_code;
1130 }
1131
1132 /**
1133 * i40iw_get_user_access - get hw access from IB access
1134 * @acc: IB access to return hw access
1135 */
1136 static inline u16 i40iw_get_user_access(int acc)
1137 {
1138 u16 access = 0;
1139
1140 access |= (acc & IB_ACCESS_LOCAL_WRITE) ? I40IW_ACCESS_FLAGS_LOCALWRITE : 0;
1141 access |= (acc & IB_ACCESS_REMOTE_WRITE) ? I40IW_ACCESS_FLAGS_REMOTEWRITE : 0;
1142 access |= (acc & IB_ACCESS_REMOTE_READ) ? I40IW_ACCESS_FLAGS_REMOTEREAD : 0;
1143 access |= (acc & IB_ACCESS_MW_BIND) ? I40IW_ACCESS_FLAGS_BIND_WINDOW : 0;
1144 return access;
1145 }
1146
1147 /**
1148 * i40iw_free_stag - free stag resource
1149 * @iwdev: iwarp device
1150 * @stag: stag to free
1151 */
1152 static void i40iw_free_stag(struct i40iw_device *iwdev, u32 stag)
1153 {
1154 u32 stag_idx;
1155
1156 stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1157 i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx);
1158 i40iw_rem_devusecount(iwdev);
1159 }
1160
1161 /**
1162 * i40iw_create_stag - create random stag
1163 * @iwdev: iwarp device
1164 */
1165 static u32 i40iw_create_stag(struct i40iw_device *iwdev)
1166 {
1167 u32 stag = 0;
1168 u32 stag_index = 0;
1169 u32 next_stag_index;
1170 u32 driver_key;
1171 u32 random;
1172 u8 consumer_key;
1173 int ret;
1174
1175 get_random_bytes(&random, sizeof(random));
1176 consumer_key = (u8)random;
1177
1178 driver_key = random & ~iwdev->mr_stagmask;
1179 next_stag_index = (random & iwdev->mr_stagmask) >> 8;
1180 next_stag_index %= iwdev->max_mr;
1181
1182 ret = i40iw_alloc_resource(iwdev,
1183 iwdev->allocated_mrs, iwdev->max_mr,
1184 &stag_index, &next_stag_index);
1185 if (!ret) {
1186 stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT;
1187 stag |= driver_key;
1188 stag += (u32)consumer_key;
1189 i40iw_add_devusecount(iwdev);
1190 }
1191 return stag;
1192 }
1193
1194 /**
1195 * i40iw_next_pbl_addr - Get next pbl address
1196 * @pbl: pointer to a pble
1197 * @pinfo: info pointer
1198 * @idx: index
1199 */
1200 static inline u64 *i40iw_next_pbl_addr(u64 *pbl,
1201 struct i40iw_pble_info **pinfo,
1202 u32 *idx)
1203 {
1204 *idx += 1;
1205 if ((!(*pinfo)) || (*idx != (*pinfo)->cnt))
1206 return ++pbl;
1207 *idx = 0;
1208 (*pinfo)++;
1209 return (u64 *)(*pinfo)->addr;
1210 }
1211
1212 /**
1213 * i40iw_copy_user_pgaddrs - copy user page address to pble's os locally
1214 * @iwmr: iwmr for IB's user page addresses
1215 * @pbl: ple pointer to save 1 level or 0 level pble
1216 * @level: indicated level 0, 1 or 2
1217 */
1218 static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
1219 u64 *pbl,
1220 enum i40iw_pble_level level)
1221 {
1222 struct ib_umem *region = iwmr->region;
1223 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1224 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1225 struct i40iw_pble_info *pinfo;
1226 struct ib_block_iter biter;
1227 u32 idx = 0;
1228
1229 pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf;
1230
1231 if (iwmr->type == IW_MEMREG_TYPE_QP)
1232 iwpbl->qp_mr.sq_page = sg_page(region->sg_head.sgl);
1233
1234 rdma_umem_for_each_dma_block(region, &biter, iwmr->page_size) {
1235 *pbl = rdma_block_iter_dma_address(&biter);
1236 pbl = i40iw_next_pbl_addr(pbl, &pinfo, &idx);
1237 }
1238 }
1239
1240 /**
1241 * i40iw_check_mem_contiguous - check if pbls stored in arr are contiguous
1242 * @arr: lvl1 pbl array
1243 * @npages: page count
1244 * pg_size: page size
1245 *
1246 */
1247 static bool i40iw_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
1248 {
1249 u32 pg_idx;
1250
1251 for (pg_idx = 0; pg_idx < npages; pg_idx++) {
1252 if ((*arr + (pg_size * pg_idx)) != arr[pg_idx])
1253 return false;
1254 }
1255 return true;
1256 }
1257
1258 /**
1259 * i40iw_check_mr_contiguous - check if MR is physically contiguous
1260 * @palloc: pbl allocation struct
1261 * pg_size: page size
1262 */
1263 static bool i40iw_check_mr_contiguous(struct i40iw_pble_alloc *palloc, u32 pg_size)
1264 {
1265 struct i40iw_pble_level2 *lvl2 = &palloc->level2;
1266 struct i40iw_pble_info *leaf = lvl2->leaf;
1267 u64 *arr = NULL;
1268 u64 *start_addr = NULL;
1269 int i;
1270 bool ret;
1271
1272 if (palloc->level == I40IW_LEVEL_1) {
1273 arr = (u64 *)palloc->level1.addr;
1274 ret = i40iw_check_mem_contiguous(arr, palloc->total_cnt, pg_size);
1275 return ret;
1276 }
1277
1278 start_addr = (u64 *)leaf->addr;
1279
1280 for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
1281 arr = (u64 *)leaf->addr;
1282 if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr)
1283 return false;
1284 ret = i40iw_check_mem_contiguous(arr, leaf->cnt, pg_size);
1285 if (!ret)
1286 return false;
1287 }
1288
1289 return true;
1290 }
1291
1292 /**
1293 * i40iw_setup_pbles - copy user pg address to pble's
1294 * @iwdev: iwarp device
1295 * @iwmr: mr pointer for this memory registration
1296 * @use_pbles: flag if to use pble's
1297 */
1298 static int i40iw_setup_pbles(struct i40iw_device *iwdev,
1299 struct i40iw_mr *iwmr,
1300 bool use_pbles)
1301 {
1302 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1303 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1304 struct i40iw_pble_info *pinfo;
1305 u64 *pbl;
1306 enum i40iw_status_code status;
1307 enum i40iw_pble_level level = I40IW_LEVEL_1;
1308
1309 if (use_pbles) {
1310 mutex_lock(&iwdev->pbl_mutex);
1311 status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
1312 mutex_unlock(&iwdev->pbl_mutex);
1313 if (status)
1314 return -ENOMEM;
1315
1316 iwpbl->pbl_allocated = true;
1317 level = palloc->level;
1318 pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf;
1319 pbl = (u64 *)pinfo->addr;
1320 } else {
1321 pbl = iwmr->pgaddrmem;
1322 }
1323
1324 i40iw_copy_user_pgaddrs(iwmr, pbl, level);
1325
1326 if (use_pbles)
1327 iwmr->pgaddrmem[0] = *pbl;
1328
1329 return 0;
1330 }
1331
1332 /**
1333 * i40iw_handle_q_mem - handle memory for qp and cq
1334 * @iwdev: iwarp device
1335 * @req: information for q memory management
1336 * @iwpbl: pble struct
1337 * @use_pbles: flag to use pble
1338 */
1339 static int i40iw_handle_q_mem(struct i40iw_device *iwdev,
1340 struct i40iw_mem_reg_req *req,
1341 struct i40iw_pbl *iwpbl,
1342 bool use_pbles)
1343 {
1344 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1345 struct i40iw_mr *iwmr = iwpbl->iwmr;
1346 struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
1347 struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr;
1348 struct i40iw_hmc_pble *hmc_p;
1349 u64 *arr = iwmr->pgaddrmem;
1350 u32 pg_size;
1351 int err;
1352 int total;
1353 bool ret = true;
1354
1355 total = req->sq_pages + req->rq_pages + req->cq_pages;
1356 pg_size = iwmr->page_size;
1357
1358 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
1359 if (err)
1360 return err;
1361
1362 if (use_pbles && (palloc->level != I40IW_LEVEL_1)) {
1363 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1364 iwpbl->pbl_allocated = false;
1365 return -ENOMEM;
1366 }
1367
1368 if (use_pbles)
1369 arr = (u64 *)palloc->level1.addr;
1370
1371 if (iwmr->type == IW_MEMREG_TYPE_QP) {
1372 hmc_p = &qpmr->sq_pbl;
1373 qpmr->shadow = (dma_addr_t)arr[total];
1374
1375 if (use_pbles) {
1376 ret = i40iw_check_mem_contiguous(arr, req->sq_pages, pg_size);
1377 if (ret)
1378 ret = i40iw_check_mem_contiguous(&arr[req->sq_pages], req->rq_pages, pg_size);
1379 }
1380
1381 if (!ret) {
1382 hmc_p->idx = palloc->level1.idx;
1383 hmc_p = &qpmr->rq_pbl;
1384 hmc_p->idx = palloc->level1.idx + req->sq_pages;
1385 } else {
1386 hmc_p->addr = arr[0];
1387 hmc_p = &qpmr->rq_pbl;
1388 hmc_p->addr = arr[req->sq_pages];
1389 }
1390 } else { /* CQ */
1391 hmc_p = &cqmr->cq_pbl;
1392 cqmr->shadow = (dma_addr_t)arr[total];
1393
1394 if (use_pbles)
1395 ret = i40iw_check_mem_contiguous(arr, req->cq_pages, pg_size);
1396
1397 if (!ret)
1398 hmc_p->idx = palloc->level1.idx;
1399 else
1400 hmc_p->addr = arr[0];
1401 }
1402
1403 if (use_pbles && ret) {
1404 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1405 iwpbl->pbl_allocated = false;
1406 }
1407
1408 return err;
1409 }
1410
1411 /**
1412 * i40iw_hw_alloc_stag - cqp command to allocate stag
1413 * @iwdev: iwarp device
1414 * @iwmr: iwarp mr pointer
1415 */
1416 static int i40iw_hw_alloc_stag(struct i40iw_device *iwdev, struct i40iw_mr *iwmr)
1417 {
1418 struct i40iw_allocate_stag_info *info;
1419 struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
1420 enum i40iw_status_code status;
1421 int err = 0;
1422 struct i40iw_cqp_request *cqp_request;
1423 struct cqp_commands_info *cqp_info;
1424
1425 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1426 if (!cqp_request)
1427 return -ENOMEM;
1428
1429 cqp_info = &cqp_request->info;
1430 info = &cqp_info->in.u.alloc_stag.info;
1431 memset(info, 0, sizeof(*info));
1432 info->page_size = PAGE_SIZE;
1433 info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1434 info->pd_id = iwpd->sc_pd.pd_id;
1435 info->total_len = iwmr->length;
1436 info->remote_access = true;
1437 cqp_info->cqp_cmd = OP_ALLOC_STAG;
1438 cqp_info->post_sq = 1;
1439 cqp_info->in.u.alloc_stag.dev = &iwdev->sc_dev;
1440 cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
1441
1442 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1443 if (status) {
1444 err = -ENOMEM;
1445 i40iw_pr_err("CQP-OP MR Reg fail");
1446 }
1447 return err;
1448 }
1449
1450 /**
1451 * i40iw_alloc_mr - register stag for fast memory registration
1452 * @pd: ibpd pointer
1453 * @mr_type: memory for stag registrion
1454 * @max_num_sg: man number of pages
1455 */
1456 static struct ib_mr *i40iw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1457 u32 max_num_sg)
1458 {
1459 struct i40iw_pd *iwpd = to_iwpd(pd);
1460 struct i40iw_device *iwdev = to_iwdev(pd->device);
1461 struct i40iw_pble_alloc *palloc;
1462 struct i40iw_pbl *iwpbl;
1463 struct i40iw_mr *iwmr;
1464 enum i40iw_status_code status;
1465 u32 stag;
1466 int err_code = -ENOMEM;
1467
1468 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1469 if (!iwmr)
1470 return ERR_PTR(-ENOMEM);
1471
1472 stag = i40iw_create_stag(iwdev);
1473 if (!stag) {
1474 err_code = -EOVERFLOW;
1475 goto err;
1476 }
1477 stag &= ~I40IW_CQPSQ_STAG_KEY_MASK;
1478 iwmr->stag = stag;
1479 iwmr->ibmr.rkey = stag;
1480 iwmr->ibmr.lkey = stag;
1481 iwmr->ibmr.pd = pd;
1482 iwmr->ibmr.device = pd->device;
1483 iwpbl = &iwmr->iwpbl;
1484 iwpbl->iwmr = iwmr;
1485 iwmr->type = IW_MEMREG_TYPE_MEM;
1486 palloc = &iwpbl->pble_alloc;
1487 iwmr->page_cnt = max_num_sg;
1488 mutex_lock(&iwdev->pbl_mutex);
1489 status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
1490 mutex_unlock(&iwdev->pbl_mutex);
1491 if (status)
1492 goto err1;
1493
1494 if (palloc->level != I40IW_LEVEL_1)
1495 goto err2;
1496 err_code = i40iw_hw_alloc_stag(iwdev, iwmr);
1497 if (err_code)
1498 goto err2;
1499 iwpbl->pbl_allocated = true;
1500 i40iw_add_pdusecount(iwpd);
1501 return &iwmr->ibmr;
1502 err2:
1503 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1504 err1:
1505 i40iw_free_stag(iwdev, stag);
1506 err:
1507 kfree(iwmr);
1508 return ERR_PTR(err_code);
1509 }
1510
1511 /**
1512 * i40iw_set_page - populate pbl list for fmr
1513 * @ibmr: ib mem to access iwarp mr pointer
1514 * @addr: page dma address fro pbl list
1515 */
1516 static int i40iw_set_page(struct ib_mr *ibmr, u64 addr)
1517 {
1518 struct i40iw_mr *iwmr = to_iwmr(ibmr);
1519 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1520 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1521 u64 *pbl;
1522
1523 if (unlikely(iwmr->npages == iwmr->page_cnt))
1524 return -ENOMEM;
1525
1526 pbl = (u64 *)palloc->level1.addr;
1527 pbl[iwmr->npages++] = cpu_to_le64(addr);
1528 return 0;
1529 }
1530
1531 /**
1532 * i40iw_map_mr_sg - map of sg list for fmr
1533 * @ibmr: ib mem to access iwarp mr pointer
1534 * @sg: scatter gather list for fmr
1535 * @sg_nents: number of sg pages
1536 */
1537 static int i40iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
1538 int sg_nents, unsigned int *sg_offset)
1539 {
1540 struct i40iw_mr *iwmr = to_iwmr(ibmr);
1541
1542 iwmr->npages = 0;
1543 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, i40iw_set_page);
1544 }
1545
1546 /**
1547 * i40iw_drain_sq - drain the send queue
1548 * @ibqp: ib qp pointer
1549 */
1550 static void i40iw_drain_sq(struct ib_qp *ibqp)
1551 {
1552 struct i40iw_qp *iwqp = to_iwqp(ibqp);
1553 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
1554
1555 if (I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
1556 wait_for_completion(&iwqp->sq_drained);
1557 }
1558
1559 /**
1560 * i40iw_drain_rq - drain the receive queue
1561 * @ibqp: ib qp pointer
1562 */
1563 static void i40iw_drain_rq(struct ib_qp *ibqp)
1564 {
1565 struct i40iw_qp *iwqp = to_iwqp(ibqp);
1566 struct i40iw_sc_qp *qp = &iwqp->sc_qp;
1567
1568 if (I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
1569 wait_for_completion(&iwqp->rq_drained);
1570 }
1571
1572 /**
1573 * i40iw_hwreg_mr - send cqp command for memory registration
1574 * @iwdev: iwarp device
1575 * @iwmr: iwarp mr pointer
1576 * @access: access for MR
1577 */
1578 static int i40iw_hwreg_mr(struct i40iw_device *iwdev,
1579 struct i40iw_mr *iwmr,
1580 u16 access)
1581 {
1582 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1583 struct i40iw_reg_ns_stag_info *stag_info;
1584 struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
1585 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1586 enum i40iw_status_code status;
1587 int err = 0;
1588 struct i40iw_cqp_request *cqp_request;
1589 struct cqp_commands_info *cqp_info;
1590
1591 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1592 if (!cqp_request)
1593 return -ENOMEM;
1594
1595 cqp_info = &cqp_request->info;
1596 stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
1597 memset(stag_info, 0, sizeof(*stag_info));
1598 stag_info->va = (void *)(unsigned long)iwpbl->user_base;
1599 stag_info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1600 stag_info->stag_key = (u8)iwmr->stag;
1601 stag_info->total_len = iwmr->length;
1602 stag_info->access_rights = access;
1603 stag_info->pd_id = iwpd->sc_pd.pd_id;
1604 stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED;
1605 stag_info->page_size = iwmr->page_size;
1606
1607 if (iwpbl->pbl_allocated) {
1608 if (palloc->level == I40IW_LEVEL_1) {
1609 stag_info->first_pm_pbl_index = palloc->level1.idx;
1610 stag_info->chunk_size = 1;
1611 } else {
1612 stag_info->first_pm_pbl_index = palloc->level2.root.idx;
1613 stag_info->chunk_size = 3;
1614 }
1615 } else {
1616 stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
1617 }
1618
1619 cqp_info->cqp_cmd = OP_MR_REG_NON_SHARED;
1620 cqp_info->post_sq = 1;
1621 cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->sc_dev;
1622 cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
1623
1624 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1625 if (status) {
1626 err = -ENOMEM;
1627 i40iw_pr_err("CQP-OP MR Reg fail");
1628 }
1629 return err;
1630 }
1631
1632 /**
1633 * i40iw_reg_user_mr - Register a user memory region
1634 * @pd: ptr of pd
1635 * @start: virtual start address
1636 * @length: length of mr
1637 * @virt: virtual address
1638 * @acc: access of mr
1639 * @udata: user data
1640 */
1641 static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
1642 u64 start,
1643 u64 length,
1644 u64 virt,
1645 int acc,
1646 struct ib_udata *udata)
1647 {
1648 struct i40iw_pd *iwpd = to_iwpd(pd);
1649 struct i40iw_device *iwdev = to_iwdev(pd->device);
1650 struct i40iw_ucontext *ucontext = rdma_udata_to_drv_context(
1651 udata, struct i40iw_ucontext, ibucontext);
1652 struct i40iw_pble_alloc *palloc;
1653 struct i40iw_pbl *iwpbl;
1654 struct i40iw_mr *iwmr;
1655 struct ib_umem *region;
1656 struct i40iw_mem_reg_req req;
1657 u32 stag = 0;
1658 u16 access;
1659 bool use_pbles = false;
1660 unsigned long flags;
1661 int err = -ENOSYS;
1662 int ret;
1663
1664 if (!udata)
1665 return ERR_PTR(-EOPNOTSUPP);
1666
1667 if (iwdev->closing)
1668 return ERR_PTR(-ENODEV);
1669
1670 if (length > I40IW_MAX_MR_SIZE)
1671 return ERR_PTR(-EINVAL);
1672 region = ib_umem_get(pd->device, start, length, acc);
1673 if (IS_ERR(region))
1674 return (struct ib_mr *)region;
1675
1676 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
1677 ib_umem_release(region);
1678 return ERR_PTR(-EFAULT);
1679 }
1680
1681 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1682 if (!iwmr) {
1683 ib_umem_release(region);
1684 return ERR_PTR(-ENOMEM);
1685 }
1686
1687 iwpbl = &iwmr->iwpbl;
1688 iwpbl->iwmr = iwmr;
1689 iwmr->region = region;
1690 iwmr->ibmr.pd = pd;
1691 iwmr->ibmr.device = pd->device;
1692
1693 iwmr->page_size = PAGE_SIZE;
1694 if (req.reg_type == IW_MEMREG_TYPE_MEM)
1695 iwmr->page_size = ib_umem_find_best_pgsz(region, SZ_4K | SZ_2M,
1696 virt);
1697 iwmr->length = region->length;
1698
1699 iwpbl->user_base = virt;
1700 palloc = &iwpbl->pble_alloc;
1701
1702 iwmr->type = req.reg_type;
1703 iwmr->page_cnt = ib_umem_num_dma_blocks(region, iwmr->page_size);
1704
1705 switch (req.reg_type) {
1706 case IW_MEMREG_TYPE_QP:
1707 use_pbles = ((req.sq_pages + req.rq_pages) > 2);
1708 err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
1709 if (err)
1710 goto error;
1711 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
1712 list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
1713 iwpbl->on_list = true;
1714 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
1715 break;
1716 case IW_MEMREG_TYPE_CQ:
1717 use_pbles = (req.cq_pages > 1);
1718 err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
1719 if (err)
1720 goto error;
1721
1722 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
1723 list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
1724 iwpbl->on_list = true;
1725 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1726 break;
1727 case IW_MEMREG_TYPE_MEM:
1728 use_pbles = (iwmr->page_cnt != 1);
1729 access = I40IW_ACCESS_FLAGS_LOCALREAD;
1730
1731 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
1732 if (err)
1733 goto error;
1734
1735 if (use_pbles) {
1736 ret = i40iw_check_mr_contiguous(palloc, iwmr->page_size);
1737 if (ret) {
1738 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1739 iwpbl->pbl_allocated = false;
1740 }
1741 }
1742
1743 access |= i40iw_get_user_access(acc);
1744 stag = i40iw_create_stag(iwdev);
1745 if (!stag) {
1746 err = -ENOMEM;
1747 goto error;
1748 }
1749
1750 iwmr->stag = stag;
1751 iwmr->ibmr.rkey = stag;
1752 iwmr->ibmr.lkey = stag;
1753
1754 err = i40iw_hwreg_mr(iwdev, iwmr, access);
1755 if (err) {
1756 i40iw_free_stag(iwdev, stag);
1757 goto error;
1758 }
1759
1760 break;
1761 default:
1762 goto error;
1763 }
1764
1765 iwmr->type = req.reg_type;
1766 if (req.reg_type == IW_MEMREG_TYPE_MEM)
1767 i40iw_add_pdusecount(iwpd);
1768 return &iwmr->ibmr;
1769
1770 error:
1771 if (palloc->level != I40IW_LEVEL_0 && iwpbl->pbl_allocated)
1772 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1773 ib_umem_release(region);
1774 kfree(iwmr);
1775 return ERR_PTR(err);
1776 }
1777
1778 /**
1779 * i40iw_reg_phys_mr - register kernel physical memory
1780 * @pd: ibpd pointer
1781 * @addr: physical address of memory to register
1782 * @size: size of memory to register
1783 * @acc: Access rights
1784 * @iova_start: start of virtual address for physical buffers
1785 */
1786 struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *pd,
1787 u64 addr,
1788 u64 size,
1789 int acc,
1790 u64 *iova_start)
1791 {
1792 struct i40iw_pd *iwpd = to_iwpd(pd);
1793 struct i40iw_device *iwdev = to_iwdev(pd->device);
1794 struct i40iw_pbl *iwpbl;
1795 struct i40iw_mr *iwmr;
1796 enum i40iw_status_code status;
1797 u32 stag;
1798 u16 access = I40IW_ACCESS_FLAGS_LOCALREAD;
1799 int ret;
1800
1801 iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
1802 if (!iwmr)
1803 return ERR_PTR(-ENOMEM);
1804 iwmr->ibmr.pd = pd;
1805 iwmr->ibmr.device = pd->device;
1806 iwpbl = &iwmr->iwpbl;
1807 iwpbl->iwmr = iwmr;
1808 iwmr->type = IW_MEMREG_TYPE_MEM;
1809 iwpbl->user_base = *iova_start;
1810 stag = i40iw_create_stag(iwdev);
1811 if (!stag) {
1812 ret = -EOVERFLOW;
1813 goto err;
1814 }
1815 access |= i40iw_get_user_access(acc);
1816 iwmr->stag = stag;
1817 iwmr->ibmr.rkey = stag;
1818 iwmr->ibmr.lkey = stag;
1819 iwmr->page_cnt = 1;
1820 iwmr->pgaddrmem[0] = addr;
1821 iwmr->length = size;
1822 status = i40iw_hwreg_mr(iwdev, iwmr, access);
1823 if (status) {
1824 i40iw_free_stag(iwdev, stag);
1825 ret = -ENOMEM;
1826 goto err;
1827 }
1828
1829 i40iw_add_pdusecount(iwpd);
1830 return &iwmr->ibmr;
1831 err:
1832 kfree(iwmr);
1833 return ERR_PTR(ret);
1834 }
1835
1836 /**
1837 * i40iw_get_dma_mr - register physical mem
1838 * @pd: ptr of pd
1839 * @acc: access for memory
1840 */
1841 static struct ib_mr *i40iw_get_dma_mr(struct ib_pd *pd, int acc)
1842 {
1843 u64 kva = 0;
1844
1845 return i40iw_reg_phys_mr(pd, 0, 0, acc, &kva);
1846 }
1847
1848 /**
1849 * i40iw_del_mem_list - Deleting pbl list entries for CQ/QP
1850 * @iwmr: iwmr for IB's user page addresses
1851 * @ucontext: ptr to user context
1852 */
1853 static void i40iw_del_memlist(struct i40iw_mr *iwmr,
1854 struct i40iw_ucontext *ucontext)
1855 {
1856 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1857 unsigned long flags;
1858
1859 switch (iwmr->type) {
1860 case IW_MEMREG_TYPE_CQ:
1861 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
1862 if (iwpbl->on_list) {
1863 iwpbl->on_list = false;
1864 list_del(&iwpbl->list);
1865 }
1866 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1867 break;
1868 case IW_MEMREG_TYPE_QP:
1869 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
1870 if (iwpbl->on_list) {
1871 iwpbl->on_list = false;
1872 list_del(&iwpbl->list);
1873 }
1874 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
1875 break;
1876 default:
1877 break;
1878 }
1879 }
1880
1881 /**
1882 * i40iw_dereg_mr - deregister mr
1883 * @ib_mr: mr ptr for dereg
1884 */
1885 static int i40iw_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
1886 {
1887 struct ib_pd *ibpd = ib_mr->pd;
1888 struct i40iw_pd *iwpd = to_iwpd(ibpd);
1889 struct i40iw_mr *iwmr = to_iwmr(ib_mr);
1890 struct i40iw_device *iwdev = to_iwdev(ib_mr->device);
1891 enum i40iw_status_code status;
1892 struct i40iw_dealloc_stag_info *info;
1893 struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
1894 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1895 struct i40iw_cqp_request *cqp_request;
1896 struct cqp_commands_info *cqp_info;
1897 u32 stag_idx;
1898
1899 ib_umem_release(iwmr->region);
1900
1901 if (iwmr->type != IW_MEMREG_TYPE_MEM) {
1902 /* region is released. only test for userness. */
1903 if (iwmr->region) {
1904 struct i40iw_ucontext *ucontext =
1905 rdma_udata_to_drv_context(
1906 udata,
1907 struct i40iw_ucontext,
1908 ibucontext);
1909
1910 i40iw_del_memlist(iwmr, ucontext);
1911 }
1912 if (iwpbl->pbl_allocated && iwmr->type != IW_MEMREG_TYPE_QP)
1913 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1914 kfree(iwmr);
1915 return 0;
1916 }
1917
1918 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
1919 if (!cqp_request)
1920 return -ENOMEM;
1921
1922 cqp_info = &cqp_request->info;
1923 info = &cqp_info->in.u.dealloc_stag.info;
1924 memset(info, 0, sizeof(*info));
1925
1926 info->pd_id = cpu_to_le32(iwpd->sc_pd.pd_id & 0x00007fff);
1927 info->stag_idx = RS_64_1(ib_mr->rkey, I40IW_CQPSQ_STAG_IDX_SHIFT);
1928 stag_idx = info->stag_idx;
1929 info->mr = true;
1930 if (iwpbl->pbl_allocated)
1931 info->dealloc_pbl = true;
1932
1933 cqp_info->cqp_cmd = OP_DEALLOC_STAG;
1934 cqp_info->post_sq = 1;
1935 cqp_info->in.u.dealloc_stag.dev = &iwdev->sc_dev;
1936 cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
1937 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1938 if (status)
1939 i40iw_pr_err("CQP-OP dealloc failed for stag_idx = 0x%x\n", stag_idx);
1940 i40iw_rem_pdusecount(iwpd, iwdev);
1941 i40iw_free_stag(iwdev, iwmr->stag);
1942 if (iwpbl->pbl_allocated)
1943 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1944 kfree(iwmr);
1945 return 0;
1946 }
1947
1948 /**
1949 * hw_rev_show
1950 */
1951 static ssize_t hw_rev_show(struct device *dev,
1952 struct device_attribute *attr, char *buf)
1953 {
1954 struct i40iw_ib_device *iwibdev =
1955 rdma_device_to_drv_device(dev, struct i40iw_ib_device, ibdev);
1956 u32 hw_rev = iwibdev->iwdev->sc_dev.hw_rev;
1957
1958 return sysfs_emit(buf, "%x\n", hw_rev);
1959 }
1960 static DEVICE_ATTR_RO(hw_rev);
1961
1962 /**
1963 * hca_type_show
1964 */
1965 static ssize_t hca_type_show(struct device *dev,
1966 struct device_attribute *attr, char *buf)
1967 {
1968 return sysfs_emit(buf, "I40IW\n");
1969 }
1970 static DEVICE_ATTR_RO(hca_type);
1971
1972 /**
1973 * board_id_show
1974 */
1975 static ssize_t board_id_show(struct device *dev,
1976 struct device_attribute *attr, char *buf)
1977 {
1978 return sysfs_emit(buf, "%.*s\n", 32, "I40IW Board ID");
1979 }
1980 static DEVICE_ATTR_RO(board_id);
1981
1982 static struct attribute *i40iw_dev_attributes[] = {
1983 &dev_attr_hw_rev.attr,
1984 &dev_attr_hca_type.attr,
1985 &dev_attr_board_id.attr,
1986 NULL
1987 };
1988
1989 static const struct attribute_group i40iw_attr_group = {
1990 .attrs = i40iw_dev_attributes,
1991 };
1992
1993 /**
1994 * i40iw_copy_sg_list - copy sg list for qp
1995 * @sg_list: copied into sg_list
1996 * @sgl: copy from sgl
1997 * @num_sges: count of sg entries
1998 */
1999 static void i40iw_copy_sg_list(struct i40iw_sge *sg_list, struct ib_sge *sgl, int num_sges)
2000 {
2001 unsigned int i;
2002
2003 for (i = 0; (i < num_sges) && (i < I40IW_MAX_WQ_FRAGMENT_COUNT); i++) {
2004 sg_list[i].tag_off = sgl[i].addr;
2005 sg_list[i].len = sgl[i].length;
2006 sg_list[i].stag = sgl[i].lkey;
2007 }
2008 }
2009
2010 /**
2011 * i40iw_post_send - kernel application wr
2012 * @ibqp: qp ptr for wr
2013 * @ib_wr: work request ptr
2014 * @bad_wr: return of bad wr if err
2015 */
2016 static int i40iw_post_send(struct ib_qp *ibqp,
2017 const struct ib_send_wr *ib_wr,
2018 const struct ib_send_wr **bad_wr)
2019 {
2020 struct i40iw_qp *iwqp;
2021 struct i40iw_qp_uk *ukqp;
2022 struct i40iw_post_sq_info info;
2023 enum i40iw_status_code ret;
2024 int err = 0;
2025 unsigned long flags;
2026 bool inv_stag;
2027
2028 iwqp = (struct i40iw_qp *)ibqp;
2029 ukqp = &iwqp->sc_qp.qp_uk;
2030
2031 spin_lock_irqsave(&iwqp->lock, flags);
2032
2033 if (iwqp->flush_issued) {
2034 err = -EINVAL;
2035 goto out;
2036 }
2037
2038 while (ib_wr) {
2039 inv_stag = false;
2040 memset(&info, 0, sizeof(info));
2041 info.wr_id = (u64)(ib_wr->wr_id);
2042 if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
2043 info.signaled = true;
2044 if (ib_wr->send_flags & IB_SEND_FENCE)
2045 info.read_fence = true;
2046
2047 switch (ib_wr->opcode) {
2048 case IB_WR_SEND:
2049 case IB_WR_SEND_WITH_INV:
2050 if (ib_wr->opcode == IB_WR_SEND) {
2051 if (ib_wr->send_flags & IB_SEND_SOLICITED)
2052 info.op_type = I40IW_OP_TYPE_SEND_SOL;
2053 else
2054 info.op_type = I40IW_OP_TYPE_SEND;
2055 } else {
2056 if (ib_wr->send_flags & IB_SEND_SOLICITED)
2057 info.op_type = I40IW_OP_TYPE_SEND_SOL_INV;
2058 else
2059 info.op_type = I40IW_OP_TYPE_SEND_INV;
2060 }
2061
2062 if (ib_wr->send_flags & IB_SEND_INLINE) {
2063 info.op.inline_send.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
2064 info.op.inline_send.len = ib_wr->sg_list[0].length;
2065 ret = ukqp->ops.iw_inline_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
2066 } else {
2067 info.op.send.num_sges = ib_wr->num_sge;
2068 info.op.send.sg_list = (struct i40iw_sge *)ib_wr->sg_list;
2069 ret = ukqp->ops.iw_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
2070 }
2071
2072 if (ret) {
2073 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2074 err = -ENOMEM;
2075 else
2076 err = -EINVAL;
2077 }
2078 break;
2079 case IB_WR_RDMA_WRITE:
2080 info.op_type = I40IW_OP_TYPE_RDMA_WRITE;
2081
2082 if (ib_wr->send_flags & IB_SEND_INLINE) {
2083 info.op.inline_rdma_write.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
2084 info.op.inline_rdma_write.len = ib_wr->sg_list[0].length;
2085 info.op.inline_rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2086 info.op.inline_rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2087 ret = ukqp->ops.iw_inline_rdma_write(ukqp, &info, false);
2088 } else {
2089 info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;
2090 info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
2091 info.op.rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2092 info.op.rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2093 ret = ukqp->ops.iw_rdma_write(ukqp, &info, false);
2094 }
2095
2096 if (ret) {
2097 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2098 err = -ENOMEM;
2099 else
2100 err = -EINVAL;
2101 }
2102 break;
2103 case IB_WR_RDMA_READ_WITH_INV:
2104 inv_stag = true;
2105 fallthrough;
2106 case IB_WR_RDMA_READ:
2107 if (ib_wr->num_sge > I40IW_MAX_SGE_RD) {
2108 err = -EINVAL;
2109 break;
2110 }
2111 info.op_type = I40IW_OP_TYPE_RDMA_READ;
2112 info.op.rdma_read.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
2113 info.op.rdma_read.rem_addr.stag = rdma_wr(ib_wr)->rkey;
2114 info.op.rdma_read.lo_addr.tag_off = ib_wr->sg_list->addr;
2115 info.op.rdma_read.lo_addr.stag = ib_wr->sg_list->lkey;
2116 info.op.rdma_read.lo_addr.len = ib_wr->sg_list->length;
2117 ret = ukqp->ops.iw_rdma_read(ukqp, &info, inv_stag, false);
2118 if (ret) {
2119 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2120 err = -ENOMEM;
2121 else
2122 err = -EINVAL;
2123 }
2124 break;
2125 case IB_WR_LOCAL_INV:
2126 info.op_type = I40IW_OP_TYPE_INV_STAG;
2127 info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
2128 ret = ukqp->ops.iw_stag_local_invalidate(ukqp, &info, true);
2129 if (ret)
2130 err = -ENOMEM;
2131 break;
2132 case IB_WR_REG_MR:
2133 {
2134 struct i40iw_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
2135 int flags = reg_wr(ib_wr)->access;
2136 struct i40iw_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
2137 struct i40iw_sc_dev *dev = &iwqp->iwdev->sc_dev;
2138 struct i40iw_fast_reg_stag_info info;
2139
2140 memset(&info, 0, sizeof(info));
2141 info.access_rights = I40IW_ACCESS_FLAGS_LOCALREAD;
2142 info.access_rights |= i40iw_get_user_access(flags);
2143 info.stag_key = reg_wr(ib_wr)->key & 0xff;
2144 info.stag_idx = reg_wr(ib_wr)->key >> 8;
2145 info.page_size = reg_wr(ib_wr)->mr->page_size;
2146 info.wr_id = ib_wr->wr_id;
2147
2148 info.addr_type = I40IW_ADDR_TYPE_VA_BASED;
2149 info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
2150 info.total_len = iwmr->ibmr.length;
2151 info.reg_addr_pa = *(u64 *)palloc->level1.addr;
2152 info.first_pm_pbl_index = palloc->level1.idx;
2153 info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
2154 info.signaled = ib_wr->send_flags & IB_SEND_SIGNALED;
2155
2156 if (iwmr->npages > I40IW_MIN_PAGES_PER_FMR)
2157 info.chunk_size = 1;
2158
2159 ret = dev->iw_priv_qp_ops->iw_mr_fast_register(&iwqp->sc_qp, &info, true);
2160 if (ret)
2161 err = -ENOMEM;
2162 break;
2163 }
2164 default:
2165 err = -EINVAL;
2166 i40iw_pr_err(" upost_send bad opcode = 0x%x\n",
2167 ib_wr->opcode);
2168 break;
2169 }
2170
2171 if (err)
2172 break;
2173 ib_wr = ib_wr->next;
2174 }
2175
2176 out:
2177 if (err)
2178 *bad_wr = ib_wr;
2179 else
2180 ukqp->ops.iw_qp_post_wr(ukqp);
2181 spin_unlock_irqrestore(&iwqp->lock, flags);
2182
2183 return err;
2184 }
2185
2186 /**
2187 * i40iw_post_recv - post receive wr for kernel application
2188 * @ibqp: ib qp pointer
2189 * @ib_wr: work request for receive
2190 * @bad_wr: bad wr caused an error
2191 */
2192 static int i40iw_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *ib_wr,
2193 const struct ib_recv_wr **bad_wr)
2194 {
2195 struct i40iw_qp *iwqp;
2196 struct i40iw_qp_uk *ukqp;
2197 struct i40iw_post_rq_info post_recv;
2198 struct i40iw_sge sg_list[I40IW_MAX_WQ_FRAGMENT_COUNT];
2199 enum i40iw_status_code ret = 0;
2200 unsigned long flags;
2201 int err = 0;
2202
2203 iwqp = (struct i40iw_qp *)ibqp;
2204 ukqp = &iwqp->sc_qp.qp_uk;
2205
2206 memset(&post_recv, 0, sizeof(post_recv));
2207 spin_lock_irqsave(&iwqp->lock, flags);
2208
2209 if (iwqp->flush_issued) {
2210 err = -EINVAL;
2211 goto out;
2212 }
2213
2214 while (ib_wr) {
2215 post_recv.num_sges = ib_wr->num_sge;
2216 post_recv.wr_id = ib_wr->wr_id;
2217 i40iw_copy_sg_list(sg_list, ib_wr->sg_list, ib_wr->num_sge);
2218 post_recv.sg_list = sg_list;
2219 ret = ukqp->ops.iw_post_receive(ukqp, &post_recv);
2220 if (ret) {
2221 i40iw_pr_err(" post_recv err %d\n", ret);
2222 if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
2223 err = -ENOMEM;
2224 else
2225 err = -EINVAL;
2226 *bad_wr = ib_wr;
2227 goto out;
2228 }
2229 ib_wr = ib_wr->next;
2230 }
2231 out:
2232 spin_unlock_irqrestore(&iwqp->lock, flags);
2233 return err;
2234 }
2235
2236 /**
2237 * i40iw_poll_cq - poll cq for completion (kernel apps)
2238 * @ibcq: cq to poll
2239 * @num_entries: number of entries to poll
2240 * @entry: wr of entry completed
2241 */
2242 static int i40iw_poll_cq(struct ib_cq *ibcq,
2243 int num_entries,
2244 struct ib_wc *entry)
2245 {
2246 struct i40iw_cq *iwcq;
2247 int cqe_count = 0;
2248 struct i40iw_cq_poll_info cq_poll_info;
2249 enum i40iw_status_code ret;
2250 struct i40iw_cq_uk *ukcq;
2251 struct i40iw_sc_qp *qp;
2252 struct i40iw_qp *iwqp;
2253 unsigned long flags;
2254
2255 iwcq = (struct i40iw_cq *)ibcq;
2256 ukcq = &iwcq->sc_cq.cq_uk;
2257
2258 spin_lock_irqsave(&iwcq->lock, flags);
2259 while (cqe_count < num_entries) {
2260 ret = ukcq->ops.iw_cq_poll_completion(ukcq, &cq_poll_info);
2261 if (ret == I40IW_ERR_QUEUE_EMPTY) {
2262 break;
2263 } else if (ret == I40IW_ERR_QUEUE_DESTROYED) {
2264 continue;
2265 } else if (ret) {
2266 if (!cqe_count)
2267 cqe_count = -1;
2268 break;
2269 }
2270 entry->wc_flags = 0;
2271 entry->wr_id = cq_poll_info.wr_id;
2272 if (cq_poll_info.error) {
2273 entry->status = IB_WC_WR_FLUSH_ERR;
2274 entry->vendor_err = cq_poll_info.major_err << 16 | cq_poll_info.minor_err;
2275 } else {
2276 entry->status = IB_WC_SUCCESS;
2277 }
2278
2279 switch (cq_poll_info.op_type) {
2280 case I40IW_OP_TYPE_RDMA_WRITE:
2281 entry->opcode = IB_WC_RDMA_WRITE;
2282 break;
2283 case I40IW_OP_TYPE_RDMA_READ_INV_STAG:
2284 case I40IW_OP_TYPE_RDMA_READ:
2285 entry->opcode = IB_WC_RDMA_READ;
2286 break;
2287 case I40IW_OP_TYPE_SEND_SOL:
2288 case I40IW_OP_TYPE_SEND_SOL_INV:
2289 case I40IW_OP_TYPE_SEND_INV:
2290 case I40IW_OP_TYPE_SEND:
2291 entry->opcode = IB_WC_SEND;
2292 break;
2293 case I40IW_OP_TYPE_REC:
2294 entry->opcode = IB_WC_RECV;
2295 break;
2296 default:
2297 entry->opcode = IB_WC_RECV;
2298 break;
2299 }
2300
2301 entry->ex.imm_data = 0;
2302 qp = (struct i40iw_sc_qp *)cq_poll_info.qp_handle;
2303 entry->qp = (struct ib_qp *)qp->back_qp;
2304 entry->src_qp = cq_poll_info.qp_id;
2305 iwqp = (struct i40iw_qp *)qp->back_qp;
2306 if (iwqp->iwarp_state > I40IW_QP_STATE_RTS) {
2307 if (!I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
2308 complete(&iwqp->sq_drained);
2309 if (!I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
2310 complete(&iwqp->rq_drained);
2311 }
2312 entry->byte_len = cq_poll_info.bytes_xfered;
2313 entry++;
2314 cqe_count++;
2315 }
2316 spin_unlock_irqrestore(&iwcq->lock, flags);
2317 return cqe_count;
2318 }
2319
2320 /**
2321 * i40iw_req_notify_cq - arm cq kernel application
2322 * @ibcq: cq to arm
2323 * @notify_flags: notofication flags
2324 */
2325 static int i40iw_req_notify_cq(struct ib_cq *ibcq,
2326 enum ib_cq_notify_flags notify_flags)
2327 {
2328 struct i40iw_cq *iwcq;
2329 struct i40iw_cq_uk *ukcq;
2330 unsigned long flags;
2331 enum i40iw_completion_notify cq_notify = IW_CQ_COMPL_EVENT;
2332
2333 iwcq = (struct i40iw_cq *)ibcq;
2334 ukcq = &iwcq->sc_cq.cq_uk;
2335 if (notify_flags == IB_CQ_SOLICITED)
2336 cq_notify = IW_CQ_COMPL_SOLICITED;
2337 spin_lock_irqsave(&iwcq->lock, flags);
2338 ukcq->ops.iw_cq_request_notification(ukcq, cq_notify);
2339 spin_unlock_irqrestore(&iwcq->lock, flags);
2340 return 0;
2341 }
2342
2343 /**
2344 * i40iw_port_immutable - return port's immutable data
2345 * @ibdev: ib dev struct
2346 * @port_num: port number
2347 * @immutable: immutable data for the port return
2348 */
2349 static int i40iw_port_immutable(struct ib_device *ibdev, u8 port_num,
2350 struct ib_port_immutable *immutable)
2351 {
2352 struct ib_port_attr attr;
2353 int err;
2354
2355 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
2356
2357 err = ib_query_port(ibdev, port_num, &attr);
2358
2359 if (err)
2360 return err;
2361
2362 immutable->gid_tbl_len = attr.gid_tbl_len;
2363
2364 return 0;
2365 }
2366
2367 static const char * const i40iw_hw_stat_names[] = {
2368 // 32bit names
2369 [I40IW_HW_STAT_INDEX_IP4RXDISCARD] = "ip4InDiscards",
2370 [I40IW_HW_STAT_INDEX_IP4RXTRUNC] = "ip4InTruncatedPkts",
2371 [I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = "ip4OutNoRoutes",
2372 [I40IW_HW_STAT_INDEX_IP6RXDISCARD] = "ip6InDiscards",
2373 [I40IW_HW_STAT_INDEX_IP6RXTRUNC] = "ip6InTruncatedPkts",
2374 [I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = "ip6OutNoRoutes",
2375 [I40IW_HW_STAT_INDEX_TCPRTXSEG] = "tcpRetransSegs",
2376 [I40IW_HW_STAT_INDEX_TCPRXOPTERR] = "tcpInOptErrors",
2377 [I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = "tcpInProtoErrors",
2378 // 64bit names
2379 [I40IW_HW_STAT_INDEX_IP4RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2380 "ip4InOctets",
2381 [I40IW_HW_STAT_INDEX_IP4RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2382 "ip4InPkts",
2383 [I40IW_HW_STAT_INDEX_IP4RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2384 "ip4InReasmRqd",
2385 [I40IW_HW_STAT_INDEX_IP4RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2386 "ip4InMcastPkts",
2387 [I40IW_HW_STAT_INDEX_IP4TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2388 "ip4OutOctets",
2389 [I40IW_HW_STAT_INDEX_IP4TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2390 "ip4OutPkts",
2391 [I40IW_HW_STAT_INDEX_IP4TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2392 "ip4OutSegRqd",
2393 [I40IW_HW_STAT_INDEX_IP4TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2394 "ip4OutMcastPkts",
2395 [I40IW_HW_STAT_INDEX_IP6RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2396 "ip6InOctets",
2397 [I40IW_HW_STAT_INDEX_IP6RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2398 "ip6InPkts",
2399 [I40IW_HW_STAT_INDEX_IP6RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2400 "ip6InReasmRqd",
2401 [I40IW_HW_STAT_INDEX_IP6RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2402 "ip6InMcastPkts",
2403 [I40IW_HW_STAT_INDEX_IP6TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
2404 "ip6OutOctets",
2405 [I40IW_HW_STAT_INDEX_IP6TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2406 "ip6OutPkts",
2407 [I40IW_HW_STAT_INDEX_IP6TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
2408 "ip6OutSegRqd",
2409 [I40IW_HW_STAT_INDEX_IP6TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
2410 "ip6OutMcastPkts",
2411 [I40IW_HW_STAT_INDEX_TCPRXSEGS + I40IW_HW_STAT_INDEX_MAX_32] =
2412 "tcpInSegs",
2413 [I40IW_HW_STAT_INDEX_TCPTXSEG + I40IW_HW_STAT_INDEX_MAX_32] =
2414 "tcpOutSegs",
2415 [I40IW_HW_STAT_INDEX_RDMARXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
2416 "iwInRdmaReads",
2417 [I40IW_HW_STAT_INDEX_RDMARXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
2418 "iwInRdmaSends",
2419 [I40IW_HW_STAT_INDEX_RDMARXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
2420 "iwInRdmaWrites",
2421 [I40IW_HW_STAT_INDEX_RDMATXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
2422 "iwOutRdmaReads",
2423 [I40IW_HW_STAT_INDEX_RDMATXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
2424 "iwOutRdmaSends",
2425 [I40IW_HW_STAT_INDEX_RDMATXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
2426 "iwOutRdmaWrites",
2427 [I40IW_HW_STAT_INDEX_RDMAVBND + I40IW_HW_STAT_INDEX_MAX_32] =
2428 "iwRdmaBnd",
2429 [I40IW_HW_STAT_INDEX_RDMAVINV + I40IW_HW_STAT_INDEX_MAX_32] =
2430 "iwRdmaInv"
2431 };
2432
2433 static void i40iw_get_dev_fw_str(struct ib_device *dev, char *str)
2434 {
2435 struct i40iw_device *iwdev = to_iwdev(dev);
2436
2437 snprintf(str, IB_FW_VERSION_NAME_MAX, "%llu.%llu",
2438 i40iw_fw_major_ver(&iwdev->sc_dev),
2439 i40iw_fw_minor_ver(&iwdev->sc_dev));
2440 }
2441
2442 /**
2443 * i40iw_alloc_hw_stats - Allocate a hw stats structure
2444 * @ibdev: device pointer from stack
2445 * @port_num: port number
2446 */
2447 static struct rdma_hw_stats *i40iw_alloc_hw_stats(struct ib_device *ibdev,
2448 u8 port_num)
2449 {
2450 struct i40iw_device *iwdev = to_iwdev(ibdev);
2451 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
2452 int num_counters = I40IW_HW_STAT_INDEX_MAX_32 +
2453 I40IW_HW_STAT_INDEX_MAX_64;
2454 unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN;
2455
2456 BUILD_BUG_ON(ARRAY_SIZE(i40iw_hw_stat_names) !=
2457 (I40IW_HW_STAT_INDEX_MAX_32 +
2458 I40IW_HW_STAT_INDEX_MAX_64));
2459
2460 /*
2461 * PFs get the default update lifespan, but VFs only update once
2462 * per second
2463 */
2464 if (!dev->is_pf)
2465 lifespan = 1000;
2466 return rdma_alloc_hw_stats_struct(i40iw_hw_stat_names, num_counters,
2467 lifespan);
2468 }
2469
2470 /**
2471 * i40iw_get_hw_stats - Populates the rdma_hw_stats structure
2472 * @ibdev: device pointer from stack
2473 * @stats: stats pointer from stack
2474 * @port_num: port number
2475 * @index: which hw counter the stack is requesting we update
2476 */
2477 static int i40iw_get_hw_stats(struct ib_device *ibdev,
2478 struct rdma_hw_stats *stats,
2479 u8 port_num, int index)
2480 {
2481 struct i40iw_device *iwdev = to_iwdev(ibdev);
2482 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
2483 struct i40iw_vsi_pestat *devstat = iwdev->vsi.pestat;
2484 struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats;
2485
2486 if (dev->is_pf) {
2487 i40iw_hw_stats_read_all(devstat, &devstat->hw_stats);
2488 } else {
2489 if (i40iw_vchnl_vf_get_pe_stats(dev, &devstat->hw_stats))
2490 return -ENOSYS;
2491 }
2492
2493 memcpy(&stats->value[0], hw_stats, sizeof(*hw_stats));
2494
2495 return stats->num_counters;
2496 }
2497
2498 /**
2499 * i40iw_query_gid - Query port GID
2500 * @ibdev: device pointer from stack
2501 * @port: port number
2502 * @index: Entry index
2503 * @gid: Global ID
2504 */
2505 static int i40iw_query_gid(struct ib_device *ibdev,
2506 u8 port,
2507 int index,
2508 union ib_gid *gid)
2509 {
2510 struct i40iw_device *iwdev = to_iwdev(ibdev);
2511
2512 memset(gid->raw, 0, sizeof(gid->raw));
2513 ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
2514 return 0;
2515 }
2516
2517 static const struct ib_device_ops i40iw_dev_ops = {
2518 .owner = THIS_MODULE,
2519 .driver_id = RDMA_DRIVER_I40IW,
2520 /* NOTE: Older kernels wrongly use 0 for the uverbs_abi_ver */
2521 .uverbs_abi_ver = I40IW_ABI_VER,
2522
2523 .alloc_hw_stats = i40iw_alloc_hw_stats,
2524 .alloc_mr = i40iw_alloc_mr,
2525 .alloc_pd = i40iw_alloc_pd,
2526 .alloc_ucontext = i40iw_alloc_ucontext,
2527 .create_cq = i40iw_create_cq,
2528 .create_qp = i40iw_create_qp,
2529 .dealloc_pd = i40iw_dealloc_pd,
2530 .dealloc_ucontext = i40iw_dealloc_ucontext,
2531 .dereg_mr = i40iw_dereg_mr,
2532 .destroy_cq = i40iw_destroy_cq,
2533 .destroy_qp = i40iw_destroy_qp,
2534 .drain_rq = i40iw_drain_rq,
2535 .drain_sq = i40iw_drain_sq,
2536 .get_dev_fw_str = i40iw_get_dev_fw_str,
2537 .get_dma_mr = i40iw_get_dma_mr,
2538 .get_hw_stats = i40iw_get_hw_stats,
2539 .get_port_immutable = i40iw_port_immutable,
2540 .iw_accept = i40iw_accept,
2541 .iw_add_ref = i40iw_qp_add_ref,
2542 .iw_connect = i40iw_connect,
2543 .iw_create_listen = i40iw_create_listen,
2544 .iw_destroy_listen = i40iw_destroy_listen,
2545 .iw_get_qp = i40iw_get_qp,
2546 .iw_reject = i40iw_reject,
2547 .iw_rem_ref = i40iw_qp_rem_ref,
2548 .map_mr_sg = i40iw_map_mr_sg,
2549 .mmap = i40iw_mmap,
2550 .modify_qp = i40iw_modify_qp,
2551 .poll_cq = i40iw_poll_cq,
2552 .post_recv = i40iw_post_recv,
2553 .post_send = i40iw_post_send,
2554 .query_device = i40iw_query_device,
2555 .query_gid = i40iw_query_gid,
2556 .query_port = i40iw_query_port,
2557 .query_qp = i40iw_query_qp,
2558 .reg_user_mr = i40iw_reg_user_mr,
2559 .req_notify_cq = i40iw_req_notify_cq,
2560 INIT_RDMA_OBJ_SIZE(ib_pd, i40iw_pd, ibpd),
2561 INIT_RDMA_OBJ_SIZE(ib_cq, i40iw_cq, ibcq),
2562 INIT_RDMA_OBJ_SIZE(ib_ucontext, i40iw_ucontext, ibucontext),
2563 };
2564
2565 /**
2566 * i40iw_init_rdma_device - initialization of iwarp device
2567 * @iwdev: iwarp device
2568 */
2569 static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev)
2570 {
2571 struct i40iw_ib_device *iwibdev;
2572 struct net_device *netdev = iwdev->netdev;
2573 struct pci_dev *pcidev = iwdev->hw.pcidev;
2574
2575 iwibdev = ib_alloc_device(i40iw_ib_device, ibdev);
2576 if (!iwibdev) {
2577 i40iw_pr_err("iwdev == NULL\n");
2578 return NULL;
2579 }
2580 iwdev->iwibdev = iwibdev;
2581 iwibdev->iwdev = iwdev;
2582
2583 iwibdev->ibdev.node_type = RDMA_NODE_RNIC;
2584 ether_addr_copy((u8 *)&iwibdev->ibdev.node_guid, netdev->dev_addr);
2585
2586 iwibdev->ibdev.phys_port_cnt = 1;
2587 iwibdev->ibdev.num_comp_vectors = iwdev->ceqs_count;
2588 iwibdev->ibdev.dev.parent = &pcidev->dev;
2589 memcpy(iwibdev->ibdev.iw_ifname, netdev->name,
2590 sizeof(iwibdev->ibdev.iw_ifname));
2591 ib_set_device_ops(&iwibdev->ibdev, &i40iw_dev_ops);
2592
2593 return iwibdev;
2594 }
2595
2596 /**
2597 * i40iw_port_ibevent - indicate port event
2598 * @iwdev: iwarp device
2599 */
2600 void i40iw_port_ibevent(struct i40iw_device *iwdev)
2601 {
2602 struct i40iw_ib_device *iwibdev = iwdev->iwibdev;
2603 struct ib_event event;
2604
2605 event.device = &iwibdev->ibdev;
2606 event.element.port_num = 1;
2607 event.event = iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2608 ib_dispatch_event(&event);
2609 }
2610
2611 /**
2612 * i40iw_destroy_rdma_device - destroy rdma device and free resources
2613 * @iwibdev: IB device ptr
2614 */
2615 void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev)
2616 {
2617 ib_unregister_device(&iwibdev->ibdev);
2618 wait_event_timeout(iwibdev->iwdev->close_wq,
2619 !atomic64_read(&iwibdev->iwdev->use_count),
2620 I40IW_EVENT_TIMEOUT);
2621 ib_dealloc_device(&iwibdev->ibdev);
2622 }
2623
2624 /**
2625 * i40iw_register_rdma_device - register iwarp device to IB
2626 * @iwdev: iwarp device
2627 */
2628 int i40iw_register_rdma_device(struct i40iw_device *iwdev)
2629 {
2630 int ret;
2631 struct i40iw_ib_device *iwibdev;
2632
2633 iwdev->iwibdev = i40iw_init_rdma_device(iwdev);
2634 if (!iwdev->iwibdev)
2635 return -ENOMEM;
2636 iwibdev = iwdev->iwibdev;
2637 rdma_set_device_sysfs_group(&iwibdev->ibdev, &i40iw_attr_group);
2638 ret = ib_device_set_netdev(&iwibdev->ibdev, iwdev->netdev, 1);
2639 if (ret)
2640 goto error;
2641
2642 dma_set_max_seg_size(&iwdev->hw.pcidev->dev, UINT_MAX);
2643 ret = ib_register_device(&iwibdev->ibdev, "i40iw%d", &iwdev->hw.pcidev->dev);
2644 if (ret)
2645 goto error;
2646
2647 return 0;
2648 error:
2649 ib_dealloc_device(&iwdev->iwibdev->ibdev);
2650 return ret;
2651 }
Linux with added FPC-III support