| blob | c2e0d0fa44be4a466434010f10682148a680fd72 |
1 /* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
5 * www.emulex.com
6 *
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * Contact Information:
36 * linux-drivers@emulex.com
37 *
38 * Emulex
39 * 3333 Susan Street
40 * Costa Mesa, CA 92626
41 */
43 #ifndef __OCRDMA_SLI_H__
44 #define __OCRDMA_SLI_H__
49 };
55 };
57 #define OCRDMA_SUBSYS_ROCE 10
96 OCRDMA_CMD_MAX
97 };
99 #define OCRDMA_SUBSYS_COMMON 1
114 };
120 };
122 #define OCRDMA_MAX_SGID 16
124 #define OCRDMA_MAX_QP 2048
125 #define OCRDMA_MAX_CQ 2048
126 #define OCRDMA_MAX_STAG 16384
141 };
147 };
151 /* qid #2 msbits at 12-11 */
152 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1
154 /* Rearm bit */
156 /* solicited bit */
163 /* Clear the interrupt for this eq */
165 /* Must be 1 */
167 /* Number of event entries processed */
169 /* Rearm bit */
173 /* Number of entries posted */
176 #define OCRDMA_MIN_HPAGE_SIZE 4096
178 #define OCRDMA_MIN_Q_PAGE_SIZE 4096
179 #define OCRDMA_MAX_Q_PAGES 8
181 #define OCRDMA_SLI_ASIC_ID_OFFSET 0x9C
182 #define OCRDMA_SLI_ASIC_REV_MASK 0x000000FF
183 #define OCRDMA_SLI_ASIC_GEN_NUM_MASK 0x0000FF00
184 #define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT 0x08
185 /*
186 # 0: 4K Bytes
187 # 1: 8K Bytes
188 # 2: 16K Bytes
189 # 3: 32K Bytes
190 # 4: 64K Bytes
191 # 5: 128K Bytes
192 # 6: 256K Bytes
193 # 7: 512K Bytes
194 */
195 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT 8
196 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
198 #define MAX_OCRDMA_QP_PAGES 8
199 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
201 #define OCRDMA_CREATE_CQ_MAX_PAGES 4
202 #define OCRDMA_DPP_CQE_SIZE 4
204 #define OCRDMA_GEN2_MAX_CQE 1024
205 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
206 #define OCRDMA_GEN2_WQE_SIZE 256
207 #define OCRDMA_MAX_CQE 4095
208 #define OCRDMA_CQ_PAGE_SIZE 16384
209 #define OCRDMA_WQE_SIZE 128
210 #define OCRDMA_WQE_STRIDE 8
211 #define OCRDMA_WQE_ALIGN_BYTES 16
213 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
220 };
222 /* mailbox cmd header */
224 u32 subsys_op;
226 u32 cmd_len;
227 u32 rsvd_version;
228 };
240 };
242 /* mailbox cmd response */
244 u32 subsys_op;
245 u32 status;
246 u32 rsp_len;
247 u32 add_rsp_len;
248 };
253 };
256 u32 pa_lo;
257 u32 pa_hi;
258 u32 len;
259 };
268 };
271 u32 spcl_sge_cnt_emb;
272 u32 pyld_len;
273 u32 tag_lo;
274 u32 tag_hi;
275 u32 rsvd3;
276 };
281 };
293 };
295 #define OCRDMA_EQ_LEN 4096
296 #define OCRDMA_MQ_CQ_LEN 256
297 #define OCRDMA_MQ_LEN 128
299 #define PAGE_SHIFT_4K 12
300 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
302 /* Returns number of pages spanned by the data starting at the given addr */
303 #define PAGES_4K_SPANNED(_address, size) \
304 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
305 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
309 u32 id;
310 };
313 u32 lo;
314 u32 hi;
315 };
317 #define MAX_OCRDMA_EQ_PAGES 8
320 u32 num_pages;
321 u32 valid;
322 u32 cnt;
323 u32 delay;
324 u32 rsvd;
326 };
332 };
336 u32 vector_eqid;
337 };
339 #define OCRDMA_EQ_MINOR_OTHER 0x1
342 u32 eq_id;
343 u32 phase;
344 u32 delay_multiplier;
345 };
349 u32 num_eq;
356 };
361 u32 rsvd0;
377 };
380 u32 status;
381 u32 tag_lo;
382 u32 tag_hi;
383 u32 valid_ae_cmpl_cons;
384 };
395 OCRDMA_AE_MCQE_EVENT_TYPE_MASK =
398 OCRDMA_AE_MCQE_EVENT_CODE_MASK =
400 };
402 u32 qpvalid_qpid;
403 u32 cqvalid_cqid;
404 u32 evt_tag;
405 u32 valid_ae_event;
406 };
413 };
416 u32 tag_enabled;
417 u32 event_tag;
418 u32 rsvd1;
419 u32 rsvd2;
420 };
425 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
429 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
432 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
437 };
440 u32 req_id;
441 u32 w1;
442 u32 w2;
443 u32 valid_ae_event;
444 };
451 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
455 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
458 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
463 };
466 u32 qp_id_state;
467 u32 w1;
468 u32 w2;
469 u32 valid_ae_event;
470 };
476 };
482 };
496 OCRDMA_MAX_ASYNC_ERRORS
497 };
500 u32 speed_state_ptn;
501 u32 qos_reason_falut;
502 u32 evt_tag;
503 u32 valid_ae_event;
504 };
510 OCRDMA_AE_LSC_PT_SHIFT),
513 OCRDMA_AE_LSC_LS_SHIFT),
516 OCRDMA_AE_LSC_LD_SHIFT),
519 OCRDMA_AE_LSC_PPS_SHIFT),
523 OCRDMA_AE_LSC_ER_SHIFT),
526 OCRDMA_AE_LSC_QOS_SHIFT)
527 };
535 };
537 /* mailbox command request and responses */
545 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
549 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
552 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
559 OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_SHIFT,
565 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
569 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
572 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
575 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
579 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
582 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
586 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
589 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
593 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
597 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
600 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,
604 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
607 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
611 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
614 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
617 };
622 u32 qp_srq_cq_ird_ord;
623 u32 max_pd_ca_ack_delay;
624 u32 max_recv_send_sge;
625 u32 max_ird_ord_per_qp;
626 u32 max_shared_ird_ord;
627 u32 max_mr;
628 u32 max_mr_size_hi;
629 u32 max_mr_size_lo;
630 u32 max_num_mr_pbl;
631 u32 max_mw;
632 u32 max_fmr;
633 u32 max_pages_per_frmr;
634 u32 max_mcast_group;
635 u32 max_mcast_qp_attach;
636 u32 max_total_mcast_qp_attach;
637 u32 wqe_rqe_stride_max_dpp_cqs;
638 u32 max_srq_rpir_qps;
639 u32 max_dpp_pds_credits;
640 u32 max_dpp_credits_pds_per_pd;
641 u32 max_wqes_rqes_per_q;
642 u32 max_cq_cqes_per_cq;
643 u32 max_srq_rqe_sge;
644 u32 max_wr_rd_sge;
645 u32 ird_pgsz_num_pages;
646 };
653 };
659 u32 config_num;
660 u32 asic_revision;
661 u32 phy_port;
662 u32 fn_mode;
664 u32 mode;
665 u32 nic_wqid_base;
666 u32 nic_wq_tot;
667 u32 prot_wqid_base;
668 u32 prot_wq_tot;
669 u32 prot_rqid_base;
670 u32 prot_rqid_tot;
673 u32 fn_capabilities;
674 u32 rsvd1;
675 u32 rsvd2;
676 u32 base_eqid;
677 u32 max_eq;
679 };
683 };
695 };
701 u32 ityp_ptyp;
702 u32 misc_params;
703 u32 ftrdtl_exphydtl;
704 u32 fspeed_aspeed;
706 };
715 };
736 };
742 u32 pflt_pps_ld_pnum;
743 u32 qos_lsp;
744 u32 res_lnk_st;
745 };
757 };
774 };
786 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
787 OCRDMA_CREATE_CQ_FLAGS_NODELAY
788 };
792 u32 pgsz_pgcnt;
793 u32 ev_cnt_flags;
794 u32 eqn;
795 u32 pdid_cqecnt;
796 u32 rsvd6;
798 };
803 };
807 };
811 };
815 u32 cq_id;
816 };
821 };
829 };
833 u32 cqid_pages;
834 u32 async_event_bitmap;
835 u32 async_cqid_ringsize;
836 u32 valid;
837 u32 async_cqid_valid;
838 u32 rsvd;
840 };
844 u32 id;
845 };
852 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
853 };
859 u32 bypass_flush_qid;
860 };
865 };
871 };
885 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
891 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
913 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
919 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
925 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
931 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
937 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
943 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
944 };
949 };
951 #define MAX_OCRDMA_IRD_PAGES 4
959 };
970 };
976 u32 type_pgsz_pdn;
977 u32 max_wqe_rqe;
978 u32 max_sge_send_write;
979 u32 max_sge_recv_flags;
980 u32 max_ord_ird;
981 u32 num_wq_rq_pages;
982 u32 wqe_rqe_size;
983 u32 wq_rq_cqid;
986 u32 dpp_credits_cqid;
987 u32 rpir_lkey;
989 };
999 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
1005 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
1009 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
1015 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
1021 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
1026 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
1029 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
1030 };
1036 u32 qp_id;
1037 u32 max_wqe_rqe;
1038 u32 max_sge_send_write;
1039 u32 max_sge_recv;
1040 u32 max_ord_ird;
1041 u32 sq_rq_id;
1042 u32 dpp_response;
1043 };
1048 u32 qp_id;
1049 };
1054 };
1092 };
1102 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
1108 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
1123 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
1129 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
1135 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
1141 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
1147 OCRDMA_QP_PARAMS_TCLASS_SHIFT,
1153 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
1156 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
1162 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
1168 OCRDMA_QP_PARAMS_SL_SHIFT,
1171 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
1174 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
1180 OCRDMA_QP_PARAMS_VLAN_SHIFT
1181 };
1184 u32 id;
1185 u32 max_wqe_rqe;
1186 u32 max_sge_send_write;
1187 u32 max_sge_recv_flags;
1188 u32 max_ord_ird;
1189 u32 wq_rq_cqid;
1190 u32 hop_lmt_rq_psn;
1191 u32 tclass_sq_psn;
1192 u32 ack_to_rnr_rtc_dest_qpn;
1193 u32 path_mtu_pkey_indx;
1194 u32 rnt_rc_sl_fl;
1197 u32 dmac_b0_to_b3;
1198 u32 vlan_dmac_b4_to_b5;
1199 u32 qkey;
1200 };
1208 u32 flags;
1209 u32 rdma_flags;
1210 u32 num_outstanding_atomic_rd;
1211 };
1218 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1224 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1225 };
1231 u32 max_wqe_rqe;
1232 u32 max_ord_ird;
1233 };
1239 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0
1240 #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF
1241 u32 qp_id;
1242 };
1248 u32 dpp_credits_cqid;
1249 u32 rbq_id;
1250 };
1257 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1262 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1268 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1269 };
1275 u32 pgsz_pdid;
1276 u32 max_sge_rqe;
1277 u32 pages_rqe_sz;
1279 };
1289 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1290 };
1296 u32 id;
1297 u32 max_sge_rqe_allocated;
1298 };
1308 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1309 };
1315 u32 id;
1316 u32 limit_max_rqe;
1317 };
1322 };
1328 u32 id;
1329 };
1336 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1342 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1343 };
1349 u32 max_rqe_pdid;
1350 u32 srq_lmt_max_sge;
1351 };
1356 };
1362 u32 id;
1363 };
1368 };
1373 u32 enable_dpp_rsvd;
1374 };
1380 };
1385 u32 dpp_page_pdid;
1386 };
1391 u32 id;
1392 };
1397 };
1402 u32 enable_dpp_rsvd;
1403 u32 pd_count;
1404 };
1409 u32 dpp_page_pdid;
1410 u32 pd_count;
1411 };
1415 };
1420 u32 start_pd_id;
1421 u32 pd_count;
1422 };
1427 u32 rsvd;
1428 };
1433 };
1455 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1456 };
1462 u32 pdid;
1463 u32 pbl_sz_flags;
1464 };
1470 u32 lrkey;
1471 u32 num_pbl_rsvd;
1472 };
1478 u32 lkey;
1479 u32 rsvd_frmr;
1480 };
1485 };
1487 #define MAX_OCRDMA_NSMR_PBL (u32)22
1488 #define MAX_OCRDMA_PBL_SIZE 65536
1489 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1496 OCRDMA_REG_NSMR_LRKEY_SHIFT,
1502 OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1508 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1525 };
1531 u32 fr_mr;
1532 u32 num_pbl_pdid;
1533 u32 flags_hpage_pbe_sz;
1534 u32 totlen_low;
1535 u32 totlen_high;
1536 u32 fbo_low;
1537 u32 fbo_high;
1538 u32 va_loaddr;
1539 u32 va_hiaddr;
1541 };
1548 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1552 };
1558 u32 lrkey;
1559 u32 num_pbl_offset;
1560 u32 last;
1563 };
1566 u32 pa_hi;
1567 u32 pa_lo;
1568 };
1573 };
1578 u32 lrkey;
1579 u32 num_pbl;
1580 };
1587 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1591 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1592 };
1598 u32 lrkey_key_index;
1599 u32 num_pbl;
1600 };
1605 };
1611 u32 pdid;
1612 };
1617 };
1623 u32 lrkey_index;
1624 };
1629 u32 qp_id;
1631 u32 mac_b0_to_b3;
1632 u32 vlan_mac_b4_to_b5;
1633 };
1638 };
1643 u32 qp_id;
1645 u32 mac_b0_to_b3;
1646 u32 vlan_mac_b4_to_b5;
1647 };
1652 };
1657 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1661 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1665 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1666 };
1668 #define OCRDMA_AH_TBL_PAGES 8
1674 u32 ah_conf;
1676 };
1681 u32 ahid;
1682 };
1687 u32 ahid;
1688 };
1693 };
1703 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1704 };
1709 };
1712 u32 id_valid;
1713 };
1717 OCRDMA_CQE_LOC_LEN_ERR,
1718 OCRDMA_CQE_LOC_QP_OP_ERR,
1719 OCRDMA_CQE_LOC_EEC_OP_ERR,
1720 OCRDMA_CQE_LOC_PROT_ERR,
1721 OCRDMA_CQE_WR_FLUSH_ERR,
1722 OCRDMA_CQE_MW_BIND_ERR,
1723 OCRDMA_CQE_BAD_RESP_ERR,
1724 OCRDMA_CQE_LOC_ACCESS_ERR,
1725 OCRDMA_CQE_REM_INV_REQ_ERR,
1726 OCRDMA_CQE_REM_ACCESS_ERR,
1727 OCRDMA_CQE_REM_OP_ERR,
1728 OCRDMA_CQE_RETRY_EXC_ERR,
1729 OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1730 OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1731 OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1732 OCRDMA_CQE_REM_ABORT_ERR,
1733 OCRDMA_CQE_INV_EECN_ERR,
1734 OCRDMA_CQE_INV_EEC_STATE_ERR,
1735 OCRDMA_CQE_FATAL_ERR,
1736 OCRDMA_CQE_RESP_TIMEOUT_ERR,
1737 OCRDMA_CQE_GENERAL_ERR,
1739 OCRDMA_MAX_CQE_ERR
1740 };
1743 /* w0 */
1747 /* w1 */
1755 /* w2 */
1762 /* w3 */
1775 };
1779 /* w0 to w2 */
1781 u32 wqeidx;
1782 u32 bytes_xfered;
1783 u32 qpn;
1786 u32 lkey_immdt;
1787 u32 rxlen;
1788 u32 buftag_qpn;
1791 u32 lkey_immdt;
1792 u32 rxlen_pkey;
1793 u32 buftag_qpn;
1796 u32 word_0;
1797 u32 word_1;
1798 u32 qpn;
1800 };
1802 };
1805 u32 addr_hi;
1806 u32 addr_lo;
1807 u32 lrkey;
1808 u32 len;
1809 };
1820 /* Stag flags */
1825 };
1839 };
1844 };
1858 };
1860 /* header WQE for all the SQ and RQ operations */
1862 u32 cw;
1864 u32 rsvd_tag;
1865 u32 rsvd_lkey_flags;
1866 };
1868 u32 immdt;
1869 u32 lkey;
1870 };
1871 u32 total_len;
1872 };
1875 u32 rsvd_dest_qpn;
1876 u32 qkey;
1877 u32 rsvd_ahid;
1878 u32 hdr_type;
1879 };
1881 /* extended wqe followed by hdr_wqe for Fast Memory register */
1883 u32 va_hi;
1884 u32 va_lo;
1885 u32 fbo_hi;
1886 u32 fbo_lo;
1887 u32 size_sge;
1888 u32 num_sges;
1889 u32 rsvd;
1890 u32 rsvd2;
1891 };
1896 __be16 eth_type;
1902 __be16 eth_type;
1903 __be16 vlan_tag;
1904 __be16 roce_eth_type;
1908 __be32 tclass_flow;
1909 __be32 pdid_hoplimit;
1912 u16 rsvd;
1915 #define OCRDMA_AV_VALID BIT(7)
1916 #define OCRDMA_AV_VLAN_VALID BIT(1)
1921 u32 valid;
1925 u32 dpp_pds;
1926 u32 non_dpp_pds;
1927 u32 rc_dpp_qps;
1928 u32 uc_dpp_qps;
1929 u32 ud_dpp_qps;
1930 u32 rc_non_dpp_qps;
1931 u32 rsvd;
1932 u32 uc_non_dpp_qps;
1933 u32 ud_non_dpp_qps;
1934 u32 rsvd1;
1935 u32 srqs;
1936 u32 rbqs;
1937 u32 r64K_nsmr;
1938 u32 r64K_to_2M_nsmr;
1939 u32 r2M_to_44M_nsmr;
1940 u32 r44M_to_1G_nsmr;
1941 u32 r1G_to_4G_nsmr;
1942 u32 nsmr_count_4G_to_32G;
1943 u32 r32G_to_64G_nsmr;
1944 u32 r64G_to_128G_nsmr;
1945 u32 r128G_to_higher_nsmr;
1946 u32 embedded_nsmr;
1947 u32 frmr;
1948 u32 prefetch_qps;
1949 u32 ondemand_qps;
1950 u32 phy_mr;
1951 u32 mw;
1953 };
1956 u32 sq_doorbell_errors;
1957 u32 cq_doorbell_errors;
1958 u32 rq_srq_doorbell_errors;
1959 u32 cq_overflow_errors;
1961 };
1964 u32 large_send_rc_wqes_lo;
1965 u32 large_send_rc_wqes_hi;
1966 u32 large_write_rc_wqes_lo;
1967 u32 large_write_rc_wqes_hi;
1969 u32 read_wqes_lo;
1970 u32 read_wqes_hi;
1971 u32 frmr_wqes_lo;
1972 u32 frmr_wqes_hi;
1973 u32 mw_bind_wqes_lo;
1974 u32 mw_bind_wqes_hi;
1975 u32 invalidate_wqes_lo;
1976 u32 invalidate_wqes_hi;
1978 u32 dpp_wqe_drops;
1980 };
1983 u32 send_pkts_lo;
1984 u32 send_pkts_hi;
1985 u32 write_pkts_lo;
1986 u32 write_pkts_hi;
1987 u32 read_pkts_lo;
1988 u32 read_pkts_hi;
1989 u32 read_rsp_pkts_lo;
1990 u32 read_rsp_pkts_hi;
1991 u32 ack_pkts_lo;
1992 u32 ack_pkts_hi;
1993 u32 send_bytes_lo;
1994 u32 send_bytes_hi;
1995 u32 write_bytes_lo;
1996 u32 write_bytes_hi;
1997 u32 read_req_bytes_lo;
1998 u32 read_req_bytes_hi;
1999 u32 read_rsp_bytes_lo;
2000 u32 read_rsp_bytes_hi;
2001 u32 ack_timeouts;
2003 };
2007 u32 local_length_errors;
2008 u32 local_protection_errors;
2009 u32 local_qp_operation_errors;
2010 u32 retry_count_exceeded_errors;
2011 u32 rnr_retry_count_exceeded_errors;
2013 };
2016 u32 roce_frame_bytes_lo;
2017 u32 roce_frame_bytes_hi;
2018 u32 roce_frame_icrc_drops;
2019 u32 roce_frame_payload_len_drops;
2020 u32 ud_drops;
2021 u32 qp1_drops;
2022 u32 psn_error_request_packets;
2023 u32 psn_error_resp_packets;
2024 u32 rnr_nak_timeouts;
2025 u32 rnr_nak_receives;
2026 u32 roce_frame_rxmt_drops;
2027 u32 nak_count_psn_sequence_errors;
2028 u32 rc_drop_count_lookup_errors;
2029 u32 rq_rnr_naks;
2030 u32 srq_rnr_naks;
2031 u32 roce_frames_lo;
2032 u32 roce_frames_hi;
2033 u32 rsvd;
2034 };
2037 u32 nak_invalid_request_errors;
2038 u32 nak_remote_operation_errors;
2039 u32 nak_count_remote_access_errors;
2040 u32 local_length_errors;
2041 u32 local_protection_errors;
2042 u32 local_qp_operation_errors;
2044 };
2048 };
2052 };
2056 u8 reset_stats;
2121 };
2126 u32 supported_modes;
2127 u32 rsvd_eprom_verhi_verlo;
2128 u32 mbx_ds_ver;
2129 u32 epfw_ds_ver;
2131 u32 default_extended_timeout;
2141 u32 functionalities_supported;
2142 u32 guid0_asicrev_cdblen;
2144 u32 portcnt_guid15;
2145 u32 mfuncdev_iscsi_ldtout;
2146 u32 ptpnum_maxdoms_hbast_cv;
2147 u32 firmware_post_status;
2149 u32 res_asicgen_iscsi_feaures;
2151 };
2155 u32 pci_did_vid;
2156 u32 pci_ssid_svid;
2157 u32 ityp_fnum_devnum_bnum;
2158 u32 uid_hi;
2159 u32 uid_lo;
2160 u32 res_nnetfil;
2162 };
2167 };
2169 #define OCRDMA_SUBSYS_DCBX 0x10
2173 };
2179 };
2184 };
2192 };
2201 };
2209 };
2212 u32 valid_proto_app;
2213 u32 oui;
2215 };
2218 u32 tcv_aev_opv_st;
2219 u32 tc_state;
2220 u32 pfc_state;
2221 u32 qcn_state;
2222 u32 appl_state;
2223 u32 ll_state;
2228 };
2232 u32 param_type;