?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / iommu / intel / irq_remapping.c
blob685200a5cff0f30578d847e3915aa5179fb66e7d
1 // SPDX-License-Identifier: GPL-2.0
2
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
4
5 #include <linux/interrupt.h>
6 #include <linux/dmar.h>
7 #include <linux/spinlock.h>
8 #include <linux/slab.h>
9 #include <linux/jiffies.h>
10 #include <linux/hpet.h>
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/intel-iommu.h>
14 #include <linux/acpi.h>
15 #include <linux/irqdomain.h>
16 #include <linux/crash_dump.h>
17 #include <asm/io_apic.h>
18 #include <asm/apic.h>
19 #include <asm/smp.h>
20 #include <asm/cpu.h>
21 #include <asm/irq_remapping.h>
22 #include <asm/pci-direct.h>
23
24 #include "../irq_remapping.h"
25
26 enum irq_mode {
27 IRQ_REMAPPING,
28 IRQ_POSTING,
29 };
30
31 struct ioapic_scope {
32 struct intel_iommu *iommu;
33 unsigned int id;
34 unsigned int bus; /* PCI bus number */
35 unsigned int devfn; /* PCI devfn number */
36 };
37
38 struct hpet_scope {
39 struct intel_iommu *iommu;
40 u8 id;
41 unsigned int bus;
42 unsigned int devfn;
43 };
44
45 struct irq_2_iommu {
46 struct intel_iommu *iommu;
47 u16 irte_index;
48 u16 sub_handle;
49 u8 irte_mask;
50 enum irq_mode mode;
51 };
52
53 struct intel_ir_data {
54 struct irq_2_iommu irq_2_iommu;
55 struct irte irte_entry;
56 union {
57 struct msi_msg msi_entry;
58 };
59 };
60
61 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
62 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
63
64 static int __read_mostly eim_mode;
65 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
66 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
67
68 /*
69 * Lock ordering:
70 * ->dmar_global_lock
71 * ->irq_2_ir_lock
72 * ->qi->q_lock
73 * ->iommu->register_lock
74 * Note:
75 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
76 * in single-threaded environment with interrupt disabled, so no need to tabke
77 * the dmar_global_lock.
78 */
79 DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
80 static const struct irq_domain_ops intel_ir_domain_ops;
81
82 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
83 static int __init parse_ioapics_under_ir(void);
84
85 static bool ir_pre_enabled(struct intel_iommu *iommu)
86 {
87 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
88 }
89
90 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
91 {
92 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
93 }
94
95 static void init_ir_status(struct intel_iommu *iommu)
96 {
97 u32 gsts;
98
99 gsts = readl(iommu->reg + DMAR_GSTS_REG);
100 if (gsts & DMA_GSTS_IRES)
101 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
102 }
103
104 static int alloc_irte(struct intel_iommu *iommu,
105 struct irq_2_iommu *irq_iommu, u16 count)
106 {
107 struct ir_table *table = iommu->ir_table;
108 unsigned int mask = 0;
109 unsigned long flags;
110 int index;
111
112 if (!count || !irq_iommu)
113 return -1;
114
115 if (count > 1) {
116 count = __roundup_pow_of_two(count);
117 mask = ilog2(count);
118 }
119
120 if (mask > ecap_max_handle_mask(iommu->ecap)) {
121 pr_err("Requested mask %x exceeds the max invalidation handle"
122 " mask value %Lx\n", mask,
123 ecap_max_handle_mask(iommu->ecap));
124 return -1;
125 }
126
127 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
128 index = bitmap_find_free_region(table->bitmap,
129 INTR_REMAP_TABLE_ENTRIES, mask);
130 if (index < 0) {
131 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
132 } else {
133 irq_iommu->iommu = iommu;
134 irq_iommu->irte_index = index;
135 irq_iommu->sub_handle = 0;
136 irq_iommu->irte_mask = mask;
137 irq_iommu->mode = IRQ_REMAPPING;
138 }
139 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
140
141 return index;
142 }
143
144 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
145 {
146 struct qi_desc desc;
147
148 desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
149 | QI_IEC_SELECTIVE;
150 desc.qw1 = 0;
151 desc.qw2 = 0;
152 desc.qw3 = 0;
153
154 return qi_submit_sync(iommu, &desc, 1, 0);
155 }
156
157 static int modify_irte(struct irq_2_iommu *irq_iommu,
158 struct irte *irte_modified)
159 {
160 struct intel_iommu *iommu;
161 unsigned long flags;
162 struct irte *irte;
163 int rc, index;
164
165 if (!irq_iommu)
166 return -1;
167
168 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
169
170 iommu = irq_iommu->iommu;
171
172 index = irq_iommu->irte_index + irq_iommu->sub_handle;
173 irte = &iommu->ir_table->base[index];
174
175 #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
176 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
177 bool ret;
178
179 ret = cmpxchg_double(&irte->low, &irte->high,
180 irte->low, irte->high,
181 irte_modified->low, irte_modified->high);
182 /*
183 * We use cmpxchg16 to atomically update the 128-bit IRTE,
184 * and it cannot be updated by the hardware or other processors
185 * behind us, so the return value of cmpxchg16 should be the
186 * same as the old value.
187 */
188 WARN_ON(!ret);
189 } else
190 #endif
191 {
192 set_64bit(&irte->low, irte_modified->low);
193 set_64bit(&irte->high, irte_modified->high);
194 }
195 __iommu_flush_cache(iommu, irte, sizeof(*irte));
196
197 rc = qi_flush_iec(iommu, index, 0);
198
199 /* Update iommu mode according to the IRTE mode */
200 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
201 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
202
203 return rc;
204 }
205
206 static struct intel_iommu *map_hpet_to_iommu(u8 hpet_id)
207 {
208 int i;
209
210 for (i = 0; i < MAX_HPET_TBS; i++) {
211 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
212 return ir_hpet[i].iommu;
213 }
214 return NULL;
215 }
216
217 static struct intel_iommu *map_ioapic_to_iommu(int apic)
218 {
219 int i;
220
221 for (i = 0; i < MAX_IO_APICS; i++) {
222 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
223 return ir_ioapic[i].iommu;
224 }
225 return NULL;
226 }
227
228 static struct irq_domain *map_dev_to_ir(struct pci_dev *dev)
229 {
230 struct dmar_drhd_unit *drhd = dmar_find_matched_drhd_unit(dev);
231
232 return drhd ? drhd->iommu->ir_msi_domain : NULL;
233 }
234
235 static int clear_entries(struct irq_2_iommu *irq_iommu)
236 {
237 struct irte *start, *entry, *end;
238 struct intel_iommu *iommu;
239 int index;
240
241 if (irq_iommu->sub_handle)
242 return 0;
243
244 iommu = irq_iommu->iommu;
245 index = irq_iommu->irte_index;
246
247 start = iommu->ir_table->base + index;
248 end = start + (1 << irq_iommu->irte_mask);
249
250 for (entry = start; entry < end; entry++) {
251 set_64bit(&entry->low, 0);
252 set_64bit(&entry->high, 0);
253 }
254 bitmap_release_region(iommu->ir_table->bitmap, index,
255 irq_iommu->irte_mask);
256
257 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
258 }
259
260 /*
261 * source validation type
262 */
263 #define SVT_NO_VERIFY 0x0 /* no verification is required */
264 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
265 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
266
267 /*
268 * source-id qualifier
269 */
270 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
271 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
272 * the third least significant bit
273 */
274 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
275 * the second and third least significant bits
276 */
277 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
278 * the least three significant bits
279 */
280
281 /*
282 * set SVT, SQ and SID fields of irte to verify
283 * source ids of interrupt requests
284 */
285 static void set_irte_sid(struct irte *irte, unsigned int svt,
286 unsigned int sq, unsigned int sid)
287 {
288 if (disable_sourceid_checking)
289 svt = SVT_NO_VERIFY;
290 irte->svt = svt;
291 irte->sq = sq;
292 irte->sid = sid;
293 }
294
295 /*
296 * Set an IRTE to match only the bus number. Interrupt requests that reference
297 * this IRTE must have a requester-id whose bus number is between or equal
298 * to the start_bus and end_bus arguments.
299 */
300 static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus,
301 unsigned int end_bus)
302 {
303 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
304 (start_bus << 8) | end_bus);
305 }
306
307 static int set_ioapic_sid(struct irte *irte, int apic)
308 {
309 int i;
310 u16 sid = 0;
311
312 if (!irte)
313 return -1;
314
315 down_read(&dmar_global_lock);
316 for (i = 0; i < MAX_IO_APICS; i++) {
317 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
318 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
319 break;
320 }
321 }
322 up_read(&dmar_global_lock);
323
324 if (sid == 0) {
325 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
326 return -1;
327 }
328
329 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
330
331 return 0;
332 }
333
334 static int set_hpet_sid(struct irte *irte, u8 id)
335 {
336 int i;
337 u16 sid = 0;
338
339 if (!irte)
340 return -1;
341
342 down_read(&dmar_global_lock);
343 for (i = 0; i < MAX_HPET_TBS; i++) {
344 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
345 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
346 break;
347 }
348 }
349 up_read(&dmar_global_lock);
350
351 if (sid == 0) {
352 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
353 return -1;
354 }
355
356 /*
357 * Should really use SQ_ALL_16. Some platforms are broken.
358 * While we figure out the right quirks for these broken platforms, use
359 * SQ_13_IGNORE_3 for now.
360 */
361 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
362
363 return 0;
364 }
365
366 struct set_msi_sid_data {
367 struct pci_dev *pdev;
368 u16 alias;
369 int count;
370 int busmatch_count;
371 };
372
373 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
374 {
375 struct set_msi_sid_data *data = opaque;
376
377 if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias))
378 data->busmatch_count++;
379
380 data->pdev = pdev;
381 data->alias = alias;
382 data->count++;
383
384 return 0;
385 }
386
387 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
388 {
389 struct set_msi_sid_data data;
390
391 if (!irte || !dev)
392 return -1;
393
394 data.count = 0;
395 data.busmatch_count = 0;
396 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
397
398 /*
399 * DMA alias provides us with a PCI device and alias. The only case
400 * where the it will return an alias on a different bus than the
401 * device is the case of a PCIe-to-PCI bridge, where the alias is for
402 * the subordinate bus. In this case we can only verify the bus.
403 *
404 * If there are multiple aliases, all with the same bus number,
405 * then all we can do is verify the bus. This is typical in NTB
406 * hardware which use proxy IDs where the device will generate traffic
407 * from multiple devfn numbers on the same bus.
408 *
409 * If the alias device is on a different bus than our source device
410 * then we have a topology based alias, use it.
411 *
412 * Otherwise, the alias is for a device DMA quirk and we cannot
413 * assume that MSI uses the same requester ID. Therefore use the
414 * original device.
415 */
416 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
417 set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias),
418 dev->bus->number);
419 else if (data.count >= 2 && data.busmatch_count == data.count)
420 set_irte_verify_bus(irte, dev->bus->number, dev->bus->number);
421 else if (data.pdev->bus->number != dev->bus->number)
422 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
423 else
424 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
425 pci_dev_id(dev));
426
427 return 0;
428 }
429
430 static int iommu_load_old_irte(struct intel_iommu *iommu)
431 {
432 struct irte *old_ir_table;
433 phys_addr_t irt_phys;
434 unsigned int i;
435 size_t size;
436 u64 irta;
437
438 /* Check whether the old ir-table has the same size as ours */
439 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
440 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
441 != INTR_REMAP_TABLE_REG_SIZE)
442 return -EINVAL;
443
444 irt_phys = irta & VTD_PAGE_MASK;
445 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
446
447 /* Map the old IR table */
448 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
449 if (!old_ir_table)
450 return -ENOMEM;
451
452 /* Copy data over */
453 memcpy(iommu->ir_table->base, old_ir_table, size);
454
455 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
456
457 /*
458 * Now check the table for used entries and mark those as
459 * allocated in the bitmap
460 */
461 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
462 if (iommu->ir_table->base[i].present)
463 bitmap_set(iommu->ir_table->bitmap, i, 1);
464 }
465
466 memunmap(old_ir_table);
467
468 return 0;
469 }
470
471
472 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
473 {
474 unsigned long flags;
475 u64 addr;
476 u32 sts;
477
478 addr = virt_to_phys((void *)iommu->ir_table->base);
479
480 raw_spin_lock_irqsave(&iommu->register_lock, flags);
481
482 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
483 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
484
485 /* Set interrupt-remapping table pointer */
486 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
487
488 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
489 readl, (sts & DMA_GSTS_IRTPS), sts);
490 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
491
492 /*
493 * Global invalidation of interrupt entry cache to make sure the
494 * hardware uses the new irq remapping table.
495 */
496 qi_global_iec(iommu);
497 }
498
499 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
500 {
501 unsigned long flags;
502 u32 sts;
503
504 raw_spin_lock_irqsave(&iommu->register_lock, flags);
505
506 /* Enable interrupt-remapping */
507 iommu->gcmd |= DMA_GCMD_IRE;
508 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
509 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
510 readl, (sts & DMA_GSTS_IRES), sts);
511
512 /* Block compatibility-format MSIs */
513 if (sts & DMA_GSTS_CFIS) {
514 iommu->gcmd &= ~DMA_GCMD_CFI;
515 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
516 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
517 readl, !(sts & DMA_GSTS_CFIS), sts);
518 }
519
520 /*
521 * With CFI clear in the Global Command register, we should be
522 * protected from dangerous (i.e. compatibility) interrupts
523 * regardless of x2apic status. Check just to be sure.
524 */
525 if (sts & DMA_GSTS_CFIS)
526 WARN(1, KERN_WARNING
527 "Compatibility-format IRQs enabled despite intr remapping;\n"
528 "you are vulnerable to IRQ injection.\n");
529
530 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
531 }
532
533 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
534 {
535 struct ir_table *ir_table;
536 struct fwnode_handle *fn;
537 unsigned long *bitmap;
538 struct page *pages;
539
540 if (iommu->ir_table)
541 return 0;
542
543 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
544 if (!ir_table)
545 return -ENOMEM;
546
547 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
548 INTR_REMAP_PAGE_ORDER);
549 if (!pages) {
550 pr_err("IR%d: failed to allocate pages of order %d\n",
551 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
552 goto out_free_table;
553 }
554
555 bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_ATOMIC);
556 if (bitmap == NULL) {
557 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
558 goto out_free_pages;
559 }
560
561 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
562 if (!fn)
563 goto out_free_bitmap;
564
565 iommu->ir_domain =
566 irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
567 0, INTR_REMAP_TABLE_ENTRIES,
568 fn, &intel_ir_domain_ops,
569 iommu);
570 if (!iommu->ir_domain) {
571 irq_domain_free_fwnode(fn);
572 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
573 goto out_free_bitmap;
574 }
575 iommu->ir_msi_domain =
576 arch_create_remap_msi_irq_domain(iommu->ir_domain,
577 "INTEL-IR-MSI",
578 iommu->seq_id);
579
580 ir_table->base = page_address(pages);
581 ir_table->bitmap = bitmap;
582 iommu->ir_table = ir_table;
583
584 /*
585 * If the queued invalidation is already initialized,
586 * shouldn't disable it.
587 */
588 if (!iommu->qi) {
589 /*
590 * Clear previous faults.
591 */
592 dmar_fault(-1, iommu);
593 dmar_disable_qi(iommu);
594
595 if (dmar_enable_qi(iommu)) {
596 pr_err("Failed to enable queued invalidation\n");
597 goto out_free_bitmap;
598 }
599 }
600
601 init_ir_status(iommu);
602
603 if (ir_pre_enabled(iommu)) {
604 if (!is_kdump_kernel()) {
605 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
606 iommu->name);
607 clear_ir_pre_enabled(iommu);
608 iommu_disable_irq_remapping(iommu);
609 } else if (iommu_load_old_irte(iommu))
610 pr_err("Failed to copy IR table for %s from previous kernel\n",
611 iommu->name);
612 else
613 pr_info("Copied IR table for %s from previous kernel\n",
614 iommu->name);
615 }
616
617 iommu_set_irq_remapping(iommu, eim_mode);
618
619 return 0;
620
621 out_free_bitmap:
622 bitmap_free(bitmap);
623 out_free_pages:
624 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
625 out_free_table:
626 kfree(ir_table);
627
628 iommu->ir_table = NULL;
629
630 return -ENOMEM;
631 }
632
633 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
634 {
635 struct fwnode_handle *fn;
636
637 if (iommu && iommu->ir_table) {
638 if (iommu->ir_msi_domain) {
639 fn = iommu->ir_msi_domain->fwnode;
640
641 irq_domain_remove(iommu->ir_msi_domain);
642 irq_domain_free_fwnode(fn);
643 iommu->ir_msi_domain = NULL;
644 }
645 if (iommu->ir_domain) {
646 fn = iommu->ir_domain->fwnode;
647
648 irq_domain_remove(iommu->ir_domain);
649 irq_domain_free_fwnode(fn);
650 iommu->ir_domain = NULL;
651 }
652 free_pages((unsigned long)iommu->ir_table->base,
653 INTR_REMAP_PAGE_ORDER);
654 bitmap_free(iommu->ir_table->bitmap);
655 kfree(iommu->ir_table);
656 iommu->ir_table = NULL;
657 }
658 }
659
660 /*
661 * Disable Interrupt Remapping.
662 */
663 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
664 {
665 unsigned long flags;
666 u32 sts;
667
668 if (!ecap_ir_support(iommu->ecap))
669 return;
670
671 /*
672 * global invalidation of interrupt entry cache before disabling
673 * interrupt-remapping.
674 */
675 qi_global_iec(iommu);
676
677 raw_spin_lock_irqsave(&iommu->register_lock, flags);
678
679 sts = readl(iommu->reg + DMAR_GSTS_REG);
680 if (!(sts & DMA_GSTS_IRES))
681 goto end;
682
683 iommu->gcmd &= ~DMA_GCMD_IRE;
684 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
685
686 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
687 readl, !(sts & DMA_GSTS_IRES), sts);
688
689 end:
690 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
691 }
692
693 static int __init dmar_x2apic_optout(void)
694 {
695 struct acpi_table_dmar *dmar;
696 dmar = (struct acpi_table_dmar *)dmar_tbl;
697 if (!dmar || no_x2apic_optout)
698 return 0;
699 return dmar->flags & DMAR_X2APIC_OPT_OUT;
700 }
701
702 static void __init intel_cleanup_irq_remapping(void)
703 {
704 struct dmar_drhd_unit *drhd;
705 struct intel_iommu *iommu;
706
707 for_each_iommu(iommu, drhd) {
708 if (ecap_ir_support(iommu->ecap)) {
709 iommu_disable_irq_remapping(iommu);
710 intel_teardown_irq_remapping(iommu);
711 }
712 }
713
714 if (x2apic_supported())
715 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
716 }
717
718 static int __init intel_prepare_irq_remapping(void)
719 {
720 struct dmar_drhd_unit *drhd;
721 struct intel_iommu *iommu;
722 int eim = 0;
723
724 if (irq_remap_broken) {
725 pr_warn("This system BIOS has enabled interrupt remapping\n"
726 "on a chipset that contains an erratum making that\n"
727 "feature unstable. To maintain system stability\n"
728 "interrupt remapping is being disabled. Please\n"
729 "contact your BIOS vendor for an update\n");
730 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
731 return -ENODEV;
732 }
733
734 if (dmar_table_init() < 0)
735 return -ENODEV;
736
737 if (!dmar_ir_support())
738 return -ENODEV;
739
740 if (parse_ioapics_under_ir()) {
741 pr_info("Not enabling interrupt remapping\n");
742 goto error;
743 }
744
745 /* First make sure all IOMMUs support IRQ remapping */
746 for_each_iommu(iommu, drhd)
747 if (!ecap_ir_support(iommu->ecap))
748 goto error;
749
750 /* Detect remapping mode: lapic or x2apic */
751 if (x2apic_supported()) {
752 eim = !dmar_x2apic_optout();
753 if (!eim) {
754 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
755 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
756 }
757 }
758
759 for_each_iommu(iommu, drhd) {
760 if (eim && !ecap_eim_support(iommu->ecap)) {
761 pr_info("%s does not support EIM\n", iommu->name);
762 eim = 0;
763 }
764 }
765
766 eim_mode = eim;
767 if (eim)
768 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
769
770 /* Do the initializations early */
771 for_each_iommu(iommu, drhd) {
772 if (intel_setup_irq_remapping(iommu)) {
773 pr_err("Failed to setup irq remapping for %s\n",
774 iommu->name);
775 goto error;
776 }
777 }
778
779 return 0;
780
781 error:
782 intel_cleanup_irq_remapping();
783 return -ENODEV;
784 }
785
786 /*
787 * Set Posted-Interrupts capability.
788 */
789 static inline void set_irq_posting_cap(void)
790 {
791 struct dmar_drhd_unit *drhd;
792 struct intel_iommu *iommu;
793
794 if (!disable_irq_post) {
795 /*
796 * If IRTE is in posted format, the 'pda' field goes across the
797 * 64-bit boundary, we need use cmpxchg16b to atomically update
798 * it. We only expose posted-interrupt when X86_FEATURE_CX16
799 * is supported. Actually, hardware platforms supporting PI
800 * should have X86_FEATURE_CX16 support, this has been confirmed
801 * with Intel hardware guys.
802 */
803 if (boot_cpu_has(X86_FEATURE_CX16))
804 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
805
806 for_each_iommu(iommu, drhd)
807 if (!cap_pi_support(iommu->cap)) {
808 intel_irq_remap_ops.capability &=
809 ~(1 << IRQ_POSTING_CAP);
810 break;
811 }
812 }
813 }
814
815 static int __init intel_enable_irq_remapping(void)
816 {
817 struct dmar_drhd_unit *drhd;
818 struct intel_iommu *iommu;
819 bool setup = false;
820
821 /*
822 * Setup Interrupt-remapping for all the DRHD's now.
823 */
824 for_each_iommu(iommu, drhd) {
825 if (!ir_pre_enabled(iommu))
826 iommu_enable_irq_remapping(iommu);
827 setup = true;
828 }
829
830 if (!setup)
831 goto error;
832
833 irq_remapping_enabled = 1;
834
835 set_irq_posting_cap();
836
837 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
838
839 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
840
841 error:
842 intel_cleanup_irq_remapping();
843 return -1;
844 }
845
846 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
847 struct intel_iommu *iommu,
848 struct acpi_dmar_hardware_unit *drhd)
849 {
850 struct acpi_dmar_pci_path *path;
851 u8 bus;
852 int count, free = -1;
853
854 bus = scope->bus;
855 path = (struct acpi_dmar_pci_path *)(scope + 1);
856 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
857 / sizeof(struct acpi_dmar_pci_path);
858
859 while (--count > 0) {
860 /*
861 * Access PCI directly due to the PCI
862 * subsystem isn't initialized yet.
863 */
864 bus = read_pci_config_byte(bus, path->device, path->function,
865 PCI_SECONDARY_BUS);
866 path++;
867 }
868
869 for (count = 0; count < MAX_HPET_TBS; count++) {
870 if (ir_hpet[count].iommu == iommu &&
871 ir_hpet[count].id == scope->enumeration_id)
872 return 0;
873 else if (ir_hpet[count].iommu == NULL && free == -1)
874 free = count;
875 }
876 if (free == -1) {
877 pr_warn("Exceeded Max HPET blocks\n");
878 return -ENOSPC;
879 }
880
881 ir_hpet[free].iommu = iommu;
882 ir_hpet[free].id = scope->enumeration_id;
883 ir_hpet[free].bus = bus;
884 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
885 pr_info("HPET id %d under DRHD base 0x%Lx\n",
886 scope->enumeration_id, drhd->address);
887
888 return 0;
889 }
890
891 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
892 struct intel_iommu *iommu,
893 struct acpi_dmar_hardware_unit *drhd)
894 {
895 struct acpi_dmar_pci_path *path;
896 u8 bus;
897 int count, free = -1;
898
899 bus = scope->bus;
900 path = (struct acpi_dmar_pci_path *)(scope + 1);
901 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
902 / sizeof(struct acpi_dmar_pci_path);
903
904 while (--count > 0) {
905 /*
906 * Access PCI directly due to the PCI
907 * subsystem isn't initialized yet.
908 */
909 bus = read_pci_config_byte(bus, path->device, path->function,
910 PCI_SECONDARY_BUS);
911 path++;
912 }
913
914 for (count = 0; count < MAX_IO_APICS; count++) {
915 if (ir_ioapic[count].iommu == iommu &&
916 ir_ioapic[count].id == scope->enumeration_id)
917 return 0;
918 else if (ir_ioapic[count].iommu == NULL && free == -1)
919 free = count;
920 }
921 if (free == -1) {
922 pr_warn("Exceeded Max IO APICS\n");
923 return -ENOSPC;
924 }
925
926 ir_ioapic[free].bus = bus;
927 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
928 ir_ioapic[free].iommu = iommu;
929 ir_ioapic[free].id = scope->enumeration_id;
930 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
931 scope->enumeration_id, drhd->address, iommu->seq_id);
932
933 return 0;
934 }
935
936 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
937 struct intel_iommu *iommu)
938 {
939 int ret = 0;
940 struct acpi_dmar_hardware_unit *drhd;
941 struct acpi_dmar_device_scope *scope;
942 void *start, *end;
943
944 drhd = (struct acpi_dmar_hardware_unit *)header;
945 start = (void *)(drhd + 1);
946 end = ((void *)drhd) + header->length;
947
948 while (start < end && ret == 0) {
949 scope = start;
950 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
951 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
952 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
953 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
954 start += scope->length;
955 }
956
957 return ret;
958 }
959
960 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
961 {
962 int i;
963
964 for (i = 0; i < MAX_HPET_TBS; i++)
965 if (ir_hpet[i].iommu == iommu)
966 ir_hpet[i].iommu = NULL;
967
968 for (i = 0; i < MAX_IO_APICS; i++)
969 if (ir_ioapic[i].iommu == iommu)
970 ir_ioapic[i].iommu = NULL;
971 }
972
973 /*
974 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
975 * hardware unit.
976 */
977 static int __init parse_ioapics_under_ir(void)
978 {
979 struct dmar_drhd_unit *drhd;
980 struct intel_iommu *iommu;
981 bool ir_supported = false;
982 int ioapic_idx;
983
984 for_each_iommu(iommu, drhd) {
985 int ret;
986
987 if (!ecap_ir_support(iommu->ecap))
988 continue;
989
990 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
991 if (ret)
992 return ret;
993
994 ir_supported = true;
995 }
996
997 if (!ir_supported)
998 return -ENODEV;
999
1000 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1001 int ioapic_id = mpc_ioapic_id(ioapic_idx);
1002 if (!map_ioapic_to_iommu(ioapic_id)) {
1003 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
1004 "interrupt remapping will be disabled\n",
1005 ioapic_id);
1006 return -1;
1007 }
1008 }
1009
1010 return 0;
1011 }
1012
1013 static int __init ir_dev_scope_init(void)
1014 {
1015 int ret;
1016
1017 if (!irq_remapping_enabled)
1018 return 0;
1019
1020 down_write(&dmar_global_lock);
1021 ret = dmar_dev_scope_init();
1022 up_write(&dmar_global_lock);
1023
1024 return ret;
1025 }
1026 rootfs_initcall(ir_dev_scope_init);
1027
1028 static void disable_irq_remapping(void)
1029 {
1030 struct dmar_drhd_unit *drhd;
1031 struct intel_iommu *iommu = NULL;
1032
1033 /*
1034 * Disable Interrupt-remapping for all the DRHD's now.
1035 */
1036 for_each_iommu(iommu, drhd) {
1037 if (!ecap_ir_support(iommu->ecap))
1038 continue;
1039
1040 iommu_disable_irq_remapping(iommu);
1041 }
1042
1043 /*
1044 * Clear Posted-Interrupts capability.
1045 */
1046 if (!disable_irq_post)
1047 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1048 }
1049
1050 static int reenable_irq_remapping(int eim)
1051 {
1052 struct dmar_drhd_unit *drhd;
1053 bool setup = false;
1054 struct intel_iommu *iommu = NULL;
1055
1056 for_each_iommu(iommu, drhd)
1057 if (iommu->qi)
1058 dmar_reenable_qi(iommu);
1059
1060 /*
1061 * Setup Interrupt-remapping for all the DRHD's now.
1062 */
1063 for_each_iommu(iommu, drhd) {
1064 if (!ecap_ir_support(iommu->ecap))
1065 continue;
1066
1067 /* Set up interrupt remapping for iommu.*/
1068 iommu_set_irq_remapping(iommu, eim);
1069 iommu_enable_irq_remapping(iommu);
1070 setup = true;
1071 }
1072
1073 if (!setup)
1074 goto error;
1075
1076 set_irq_posting_cap();
1077
1078 return 0;
1079
1080 error:
1081 /*
1082 * handle error condition gracefully here!
1083 */
1084 return -1;
1085 }
1086
1087 /*
1088 * Store the MSI remapping domain pointer in the device if enabled.
1089 *
1090 * This is called from dmar_pci_bus_add_dev() so it works even when DMA
1091 * remapping is disabled. Only update the pointer if the device is not
1092 * already handled by a non default PCI/MSI interrupt domain. This protects
1093 * e.g. VMD devices.
1094 */
1095 void intel_irq_remap_add_device(struct dmar_pci_notify_info *info)
1096 {
1097 if (!irq_remapping_enabled || pci_dev_has_special_msi_domain(info->dev))
1098 return;
1099
1100 dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev));
1101 }
1102
1103 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1104 {
1105 memset(irte, 0, sizeof(*irte));
1106
1107 irte->present = 1;
1108 irte->dst_mode = apic->dest_mode_logical;
1109 /*
1110 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1111 * actual level or edge trigger will be setup in the IO-APIC
1112 * RTE. This will help simplify level triggered irq migration.
1113 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1114 * irq migration in the presence of interrupt-remapping.
1115 */
1116 irte->trigger_mode = 0;
1117 irte->dlvry_mode = apic->delivery_mode;
1118 irte->vector = vector;
1119 irte->dest_id = IRTE_DEST(dest);
1120 irte->redir_hint = 1;
1121 }
1122
1123 struct irq_remap_ops intel_irq_remap_ops = {
1124 .prepare = intel_prepare_irq_remapping,
1125 .enable = intel_enable_irq_remapping,
1126 .disable = disable_irq_remapping,
1127 .reenable = reenable_irq_remapping,
1128 .enable_faulting = enable_drhd_fault_handling,
1129 };
1130
1131 static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force)
1132 {
1133 struct intel_ir_data *ir_data = irqd->chip_data;
1134 struct irte *irte = &ir_data->irte_entry;
1135 struct irq_cfg *cfg = irqd_cfg(irqd);
1136
1137 /*
1138 * Atomically updates the IRTE with the new destination, vector
1139 * and flushes the interrupt entry cache.
1140 */
1141 irte->vector = cfg->vector;
1142 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1143
1144 /* Update the hardware only if the interrupt is in remapped mode. */
1145 if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1146 modify_irte(&ir_data->irq_2_iommu, irte);
1147 }
1148
1149 /*
1150 * Migrate the IO-APIC irq in the presence of intr-remapping.
1151 *
1152 * For both level and edge triggered, irq migration is a simple atomic
1153 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1154 *
1155 * For level triggered, we eliminate the io-apic RTE modification (with the
1156 * updated vector information), by using a virtual vector (io-apic pin number).
1157 * Real vector that is used for interrupting cpu will be coming from
1158 * the interrupt-remapping table entry.
1159 *
1160 * As the migration is a simple atomic update of IRTE, the same mechanism
1161 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1162 */
1163 static int
1164 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1165 bool force)
1166 {
1167 struct irq_data *parent = data->parent_data;
1168 struct irq_cfg *cfg = irqd_cfg(data);
1169 int ret;
1170
1171 ret = parent->chip->irq_set_affinity(parent, mask, force);
1172 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1173 return ret;
1174
1175 intel_ir_reconfigure_irte(data, false);
1176 /*
1177 * After this point, all the interrupts will start arriving
1178 * at the new destination. So, time to cleanup the previous
1179 * vector allocation.
1180 */
1181 send_cleanup_vector(cfg);
1182
1183 return IRQ_SET_MASK_OK_DONE;
1184 }
1185
1186 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1187 struct msi_msg *msg)
1188 {
1189 struct intel_ir_data *ir_data = irq_data->chip_data;
1190
1191 *msg = ir_data->msi_entry;
1192 }
1193
1194 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1195 {
1196 struct intel_ir_data *ir_data = data->chip_data;
1197 struct vcpu_data *vcpu_pi_info = info;
1198
1199 /* stop posting interrupts, back to remapping mode */
1200 if (!vcpu_pi_info) {
1201 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1202 } else {
1203 struct irte irte_pi;
1204
1205 /*
1206 * We are not caching the posted interrupt entry. We
1207 * copy the data from the remapped entry and modify
1208 * the fields which are relevant for posted mode. The
1209 * cached remapped entry is used for switching back to
1210 * remapped mode.
1211 */
1212 memset(&irte_pi, 0, sizeof(irte_pi));
1213 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1214
1215 /* Update the posted mode fields */
1216 irte_pi.p_pst = 1;
1217 irte_pi.p_urgent = 0;
1218 irte_pi.p_vector = vcpu_pi_info->vector;
1219 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1220 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1221 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1222 ~(-1UL << PDA_HIGH_BIT);
1223
1224 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1225 }
1226
1227 return 0;
1228 }
1229
1230 static struct irq_chip intel_ir_chip = {
1231 .name = "INTEL-IR",
1232 .irq_ack = apic_ack_irq,
1233 .irq_set_affinity = intel_ir_set_affinity,
1234 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1235 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1236 };
1237
1238 static void fill_msi_msg(struct msi_msg *msg, u32 index, u32 subhandle)
1239 {
1240 memset(msg, 0, sizeof(*msg));
1241
1242 msg->arch_addr_lo.dmar_base_address = X86_MSI_BASE_ADDRESS_LOW;
1243 msg->arch_addr_lo.dmar_subhandle_valid = true;
1244 msg->arch_addr_lo.dmar_format = true;
1245 msg->arch_addr_lo.dmar_index_0_14 = index & 0x7FFF;
1246 msg->arch_addr_lo.dmar_index_15 = !!(index & 0x8000);
1247
1248 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
1249
1250 msg->arch_data.dmar_subhandle = subhandle;
1251 }
1252
1253 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1254 struct irq_cfg *irq_cfg,
1255 struct irq_alloc_info *info,
1256 int index, int sub_handle)
1257 {
1258 struct irte *irte = &data->irte_entry;
1259
1260 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1261
1262 switch (info->type) {
1263 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1264 /* Set source-id of interrupt request */
1265 set_ioapic_sid(irte, info->devid);
1266 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1267 info->devid, irte->present, irte->fpd,
1268 irte->dst_mode, irte->redir_hint,
1269 irte->trigger_mode, irte->dlvry_mode,
1270 irte->avail, irte->vector, irte->dest_id,
1271 irte->sid, irte->sq, irte->svt);
1272 sub_handle = info->ioapic.pin;
1273 break;
1274 case X86_IRQ_ALLOC_TYPE_HPET:
1275 set_hpet_sid(irte, info->devid);
1276 break;
1277 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
1278 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
1279 set_msi_sid(irte, msi_desc_to_pci_dev(info->desc));
1280 break;
1281 default:
1282 BUG_ON(1);
1283 break;
1284 }
1285 fill_msi_msg(&data->msi_entry, index, sub_handle);
1286 }
1287
1288 static void intel_free_irq_resources(struct irq_domain *domain,
1289 unsigned int virq, unsigned int nr_irqs)
1290 {
1291 struct irq_data *irq_data;
1292 struct intel_ir_data *data;
1293 struct irq_2_iommu *irq_iommu;
1294 unsigned long flags;
1295 int i;
1296 for (i = 0; i < nr_irqs; i++) {
1297 irq_data = irq_domain_get_irq_data(domain, virq + i);
1298 if (irq_data && irq_data->chip_data) {
1299 data = irq_data->chip_data;
1300 irq_iommu = &data->irq_2_iommu;
1301 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1302 clear_entries(irq_iommu);
1303 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1304 irq_domain_reset_irq_data(irq_data);
1305 kfree(data);
1306 }
1307 }
1308 }
1309
1310 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1311 unsigned int virq, unsigned int nr_irqs,
1312 void *arg)
1313 {
1314 struct intel_iommu *iommu = domain->host_data;
1315 struct irq_alloc_info *info = arg;
1316 struct intel_ir_data *data, *ird;
1317 struct irq_data *irq_data;
1318 struct irq_cfg *irq_cfg;
1319 int i, ret, index;
1320
1321 if (!info || !iommu)
1322 return -EINVAL;
1323 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
1324 info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
1325 return -EINVAL;
1326
1327 /*
1328 * With IRQ remapping enabled, don't need contiguous CPU vectors
1329 * to support multiple MSI interrupts.
1330 */
1331 if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
1332 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1333
1334 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1335 if (ret < 0)
1336 return ret;
1337
1338 ret = -ENOMEM;
1339 data = kzalloc(sizeof(*data), GFP_KERNEL);
1340 if (!data)
1341 goto out_free_parent;
1342
1343 down_read(&dmar_global_lock);
1344 index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs);
1345 up_read(&dmar_global_lock);
1346 if (index < 0) {
1347 pr_warn("Failed to allocate IRTE\n");
1348 kfree(data);
1349 goto out_free_parent;
1350 }
1351
1352 for (i = 0; i < nr_irqs; i++) {
1353 irq_data = irq_domain_get_irq_data(domain, virq + i);
1354 irq_cfg = irqd_cfg(irq_data);
1355 if (!irq_data || !irq_cfg) {
1356 if (!i)
1357 kfree(data);
1358 ret = -EINVAL;
1359 goto out_free_data;
1360 }
1361
1362 if (i > 0) {
1363 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1364 if (!ird)
1365 goto out_free_data;
1366 /* Initialize the common data */
1367 ird->irq_2_iommu = data->irq_2_iommu;
1368 ird->irq_2_iommu.sub_handle = i;
1369 } else {
1370 ird = data;
1371 }
1372
1373 irq_data->hwirq = (index << 16) + i;
1374 irq_data->chip_data = ird;
1375 irq_data->chip = &intel_ir_chip;
1376 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1377 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1378 }
1379 return 0;
1380
1381 out_free_data:
1382 intel_free_irq_resources(domain, virq, i);
1383 out_free_parent:
1384 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1385 return ret;
1386 }
1387
1388 static void intel_irq_remapping_free(struct irq_domain *domain,
1389 unsigned int virq, unsigned int nr_irqs)
1390 {
1391 intel_free_irq_resources(domain, virq, nr_irqs);
1392 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1393 }
1394
1395 static int intel_irq_remapping_activate(struct irq_domain *domain,
1396 struct irq_data *irq_data, bool reserve)
1397 {
1398 intel_ir_reconfigure_irte(irq_data, true);
1399 return 0;
1400 }
1401
1402 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1403 struct irq_data *irq_data)
1404 {
1405 struct intel_ir_data *data = irq_data->chip_data;
1406 struct irte entry;
1407
1408 memset(&entry, 0, sizeof(entry));
1409 modify_irte(&data->irq_2_iommu, &entry);
1410 }
1411
1412 static int intel_irq_remapping_select(struct irq_domain *d,
1413 struct irq_fwspec *fwspec,
1414 enum irq_domain_bus_token bus_token)
1415 {
1416 struct intel_iommu *iommu = NULL;
1417
1418 if (x86_fwspec_is_ioapic(fwspec))
1419 iommu = map_ioapic_to_iommu(fwspec->param[0]);
1420 else if (x86_fwspec_is_hpet(fwspec))
1421 iommu = map_hpet_to_iommu(fwspec->param[0]);
1422
1423 return iommu && d == iommu->ir_domain;
1424 }
1425
1426 static const struct irq_domain_ops intel_ir_domain_ops = {
1427 .select = intel_irq_remapping_select,
1428 .alloc = intel_irq_remapping_alloc,
1429 .free = intel_irq_remapping_free,
1430 .activate = intel_irq_remapping_activate,
1431 .deactivate = intel_irq_remapping_deactivate,
1432 };
1433
1434 /*
1435 * Support of Interrupt Remapping Unit Hotplug
1436 */
1437 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1438 {
1439 int ret;
1440 int eim = x2apic_enabled();
1441
1442 if (eim && !ecap_eim_support(iommu->ecap)) {
1443 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1444 iommu->reg_phys, iommu->ecap);
1445 return -ENODEV;
1446 }
1447
1448 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1449 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1450 iommu->reg_phys);
1451 return -ENODEV;
1452 }
1453
1454 /* TODO: check all IOAPICs are covered by IOMMU */
1455
1456 /* Setup Interrupt-remapping now. */
1457 ret = intel_setup_irq_remapping(iommu);
1458 if (ret) {
1459 pr_err("Failed to setup irq remapping for %s\n",
1460 iommu->name);
1461 intel_teardown_irq_remapping(iommu);
1462 ir_remove_ioapic_hpet_scope(iommu);
1463 } else {
1464 iommu_enable_irq_remapping(iommu);
1465 }
1466
1467 return ret;
1468 }
1469
1470 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1471 {
1472 int ret = 0;
1473 struct intel_iommu *iommu = dmaru->iommu;
1474
1475 if (!irq_remapping_enabled)
1476 return 0;
1477 if (iommu == NULL)
1478 return -EINVAL;
1479 if (!ecap_ir_support(iommu->ecap))
1480 return 0;
1481 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1482 !cap_pi_support(iommu->cap))
1483 return -EBUSY;
1484
1485 if (insert) {
1486 if (!iommu->ir_table)
1487 ret = dmar_ir_add(dmaru, iommu);
1488 } else {
1489 if (iommu->ir_table) {
1490 if (!bitmap_empty(iommu->ir_table->bitmap,
1491 INTR_REMAP_TABLE_ENTRIES)) {
1492 ret = -EBUSY;
1493 } else {
1494 iommu_disable_irq_remapping(iommu);
1495 intel_teardown_irq_remapping(iommu);
1496 ir_remove_ioapic_hpet_scope(iommu);
1497 }
1498 }
1499 }
1500
1501 return ret;
1502 }
Linux with added FPC-III support