drivers/irqchip/irq-loongson-liointc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
   4  *  Loongson Local IO Interrupt Controller support
   5  */
   6
   7 #include <linux/errno.h>
   8 #include <linux/init.h>
   9 #include <linux/types.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/ioport.h>
  12 #include <linux/irqchip.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/io.h>
  16 #include <linux/smp.h>
  17 #include <linux/irqchip/chained_irq.h>
  18
  19 #include <boot_param.h>
  20
  21 #define LIOINTC_CHIP_IRQ        32
  22 #define LIOINTC_NUM_PARENT 4
  23
  24 #define LIOINTC_INTC_CHIP_START 0x20
  25
  26 #define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
  27 #define LIOINTC_REG_INTC_EN_STATUS      (LIOINTC_INTC_CHIP_START + 0x04)
  28 #define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
  29 #define LIOINTC_REG_INTC_DISABLE        (LIOINTC_INTC_CHIP_START + 0x0c)
  30 #define LIOINTC_REG_INTC_POL    (LIOINTC_INTC_CHIP_START + 0x10)
  31 #define LIOINTC_REG_INTC_EDGE   (LIOINTC_INTC_CHIP_START + 0x14)
  32
  33 #define LIOINTC_SHIFT_INTx      4
  34
  35 #define LIOINTC_ERRATA_IRQ      10
  36
  37 struct liointc_handler_data {
  38         struct liointc_priv     *priv;
  39         u32                     parent_int_map;
  40 };
  41
  42 struct liointc_priv {
  43         struct irq_chip_generic         *gc;
  44         struct liointc_handler_data     handler[LIOINTC_NUM_PARENT];
  45         u8                              map_cache[LIOINTC_CHIP_IRQ];
  46         bool                            has_lpc_irq_errata;
  47 };
  48
  49 static void liointc_chained_handle_irq(struct irq_desc *desc)
  50 {
  51         struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
  52         struct irq_chip *chip = irq_desc_get_chip(desc);
  53         struct irq_chip_generic *gc = handler->priv->gc;
  54         u32 pending;
  55
  56         chained_irq_enter(chip, desc);
  57
  58         pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
  59
  60         if (!pending) {
  61                 /* Always blame LPC IRQ if we have that bug */
  62                 if (handler->priv->has_lpc_irq_errata &&
  63                         (handler->parent_int_map & gc->mask_cache &
  64                         BIT(LIOINTC_ERRATA_IRQ)))
  65                         pending = BIT(LIOINTC_ERRATA_IRQ);
  66                 else
  67                         spurious_interrupt();
  68         }
  69
  70         while (pending) {
  71                 int bit = __ffs(pending);
  72
  73                 generic_handle_irq(irq_find_mapping(gc->domain, bit));
  74                 pending &= ~BIT(bit);
  75         }
  76
  77         chained_irq_exit(chip, desc);
  78 }
  79
  80 static void liointc_set_bit(struct irq_chip_generic *gc,
  81                                 unsigned int offset,
  82                                 u32 mask, bool set)
  83 {
  84         if (set)
  85                 writel(readl(gc->reg_base + offset) | mask,
  86                                 gc->reg_base + offset);
  87         else
  88                 writel(readl(gc->reg_base + offset) & ~mask,
  89                                 gc->reg_base + offset);
  90 }
  91
  92 static int liointc_set_type(struct irq_data *data, unsigned int type)
  93 {
  94         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
  95         u32 mask = data->mask;
  96         unsigned long flags;
  97
  98         irq_gc_lock_irqsave(gc, flags);
  99         switch (type) {
 100         case IRQ_TYPE_LEVEL_HIGH:
 101                 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
 102                 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
 103                 break;
 104         case IRQ_TYPE_LEVEL_LOW:
 105                 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
 106                 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
 107                 break;
 108         case IRQ_TYPE_EDGE_RISING:
 109                 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
 110                 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
 111                 break;
 112         case IRQ_TYPE_EDGE_FALLING:
 113                 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
 114                 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
 115                 break;
 116         default:
 117                 irq_gc_unlock_irqrestore(gc, flags);
 118                 return -EINVAL;
 119         }
 120         irq_gc_unlock_irqrestore(gc, flags);
 121
 122         irqd_set_trigger_type(data, type);
 123         return 0;
 124 }
 125
 126 static void liointc_resume(struct irq_chip_generic *gc)
 127 {
 128         struct liointc_priv *priv = gc->private;
 129         unsigned long flags;
 130         int i;
 131
 132         irq_gc_lock_irqsave(gc, flags);
 133         /* Disable all at first */
 134         writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
 135         /* Restore map cache */
 136         for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
 137                 writeb(priv->map_cache[i], gc->reg_base + i);
 138         /* Restore mask cache */
 139         writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
 140         irq_gc_unlock_irqrestore(gc, flags);
 141 }
 142
 143 static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
 144
 145 int __init liointc_of_init(struct device_node *node,
 146                                 struct device_node *parent)
 147 {
 148         struct irq_chip_generic *gc;
 149         struct irq_domain *domain;
 150         struct irq_chip_type *ct;
 151         struct liointc_priv *priv;
 152         void __iomem *base;
 153         u32 of_parent_int_map[LIOINTC_NUM_PARENT];
 154         int parent_irq[LIOINTC_NUM_PARENT];
 155         bool have_parent = FALSE;
 156         int sz, i, err = 0;
 157
 158         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 159         if (!priv)
 160                 return -ENOMEM;
 161
 162         base = of_iomap(node, 0);
 163         if (!base) {
 164                 err = -ENODEV;
 165                 goto out_free_priv;
 166         }
 167
 168         for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
 169                 parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
 170                 if (parent_irq[i] > 0)
 171                         have_parent = TRUE;
 172         }
 173         if (!have_parent) {
 174                 err = -ENODEV;
 175                 goto out_iounmap;
 176         }
 177
 178         sz = of_property_read_variable_u32_array(node,
 179                                                 "loongson,parent_int_map",
 180                                                 &of_parent_int_map[0],
 181                                                 LIOINTC_NUM_PARENT,
 182                                                 LIOINTC_NUM_PARENT);
 183         if (sz < 4) {
 184                 pr_err("loongson-liointc: No parent_int_map\n");
 185                 err = -ENODEV;
 186                 goto out_iounmap;
 187         }
 188
 189         for (i = 0; i < LIOINTC_NUM_PARENT; i++)
 190                 priv->handler[i].parent_int_map = of_parent_int_map[i];
 191
 192         /* Setup IRQ domain */
 193         domain = irq_domain_add_linear(node, 32,
 194                                         &irq_generic_chip_ops, priv);
 195         if (!domain) {
 196                 pr_err("loongson-liointc: cannot add IRQ domain\n");
 197                 err = -EINVAL;
 198                 goto out_iounmap;
 199         }
 200
 201         err = irq_alloc_domain_generic_chips(domain, 32, 1,
 202                                         node->full_name, handle_level_irq,
 203                                         IRQ_NOPROBE, 0, 0);
 204         if (err) {
 205                 pr_err("loongson-liointc: unable to register IRQ domain\n");
 206                 goto out_free_domain;
 207         }
 208
 209
 210         /* Disable all IRQs */
 211         writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
 212         /* Set to level triggered */
 213         writel(0x0, base + LIOINTC_REG_INTC_EDGE);
 214
 215         /* Generate parent INT part of map cache */
 216         for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
 217                 u32 pending = priv->handler[i].parent_int_map;
 218
 219                 while (pending) {
 220                         int bit = __ffs(pending);
 221
 222                         priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
 223                         pending &= ~BIT(bit);
 224                 }
 225         }
 226
 227         for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
 228                 /* Generate core part of map cache */
 229                 priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
 230                 writeb(priv->map_cache[i], base + i);
 231         }
 232
 233         gc = irq_get_domain_generic_chip(domain, 0);
 234         gc->private = priv;
 235         gc->reg_base = base;
 236         gc->domain = domain;
 237         gc->resume = liointc_resume;
 238
 239         ct = gc->chip_types;
 240         ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
 241         ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
 242         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 243         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 244         ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
 245         ct->chip.irq_set_type = liointc_set_type;
 246
 247         gc->mask_cache = 0;
 248         priv->gc = gc;
 249
 250         for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
 251                 if (parent_irq[i] <= 0)
 252                         continue;
 253
 254                 priv->handler[i].priv = priv;
 255                 irq_set_chained_handler_and_data(parent_irq[i],
 256                                 liointc_chained_handle_irq, &priv->handler[i]);
 257         }
 258
 259         return 0;
 260
 261 out_free_domain:
 262         irq_domain_remove(domain);
 263 out_iounmap:
 264         iounmap(base);
 265 out_free_priv:
 266         kfree(priv);
 267
 268         return err;
 269 }
 270
 271 IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
 272 IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);