drivers/irqchip/irq-stm32-exti.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics 2017
   5  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/delay.h>
  10 #include <linux/hwspinlock.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/irq.h>
  14 #include <linux/irqchip.h>
  15 #include <linux/irqchip/chained_irq.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/module.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/syscore_ops.h>
  22
  23 #include <dt-bindings/interrupt-controller/arm-gic.h>
  24
  25 #define IRQS_PER_BANK 32
  26
  27 #define HWSPNLCK_TIMEOUT        1000 /* usec */
  28
  29 struct stm32_exti_bank {
  30         u32 imr_ofst;
  31         u32 emr_ofst;
  32         u32 rtsr_ofst;
  33         u32 ftsr_ofst;
  34         u32 swier_ofst;
  35         u32 rpr_ofst;
  36         u32 fpr_ofst;
  37 };
  38
  39 #define UNDEF_REG ~0
  40
  41 struct stm32_desc_irq {
  42         u32 exti;
  43         u32 irq_parent;
  44         struct irq_chip *chip;
  45 };
  46
  47 struct stm32_exti_drv_data {
  48         const struct stm32_exti_bank **exti_banks;
  49         const struct stm32_desc_irq *desc_irqs;
  50         u32 bank_nr;
  51         u32 irq_nr;
  52 };
  53
  54 struct stm32_exti_chip_data {
  55         struct stm32_exti_host_data *host_data;
  56         const struct stm32_exti_bank *reg_bank;
  57         struct raw_spinlock rlock;
  58         u32 wake_active;
  59         u32 mask_cache;
  60         u32 rtsr_cache;
  61         u32 ftsr_cache;
  62 };
  63
  64 struct stm32_exti_host_data {
  65         void __iomem *base;
  66         struct stm32_exti_chip_data *chips_data;
  67         const struct stm32_exti_drv_data *drv_data;
  68         struct hwspinlock *hwlock;
  69 };
  70
  71 static struct stm32_exti_host_data *stm32_host_data;
  72
  73 static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
  74         .imr_ofst       = 0x00,
  75         .emr_ofst       = 0x04,
  76         .rtsr_ofst      = 0x08,
  77         .ftsr_ofst      = 0x0C,
  78         .swier_ofst     = 0x10,
  79         .rpr_ofst       = 0x14,
  80         .fpr_ofst       = UNDEF_REG,
  81 };
  82
  83 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
  84         &stm32f4xx_exti_b1,
  85 };
  86
  87 static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
  88         .exti_banks = stm32f4xx_exti_banks,
  89         .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
  90 };
  91
  92 static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
  93         .imr_ofst       = 0x80,
  94         .emr_ofst       = 0x84,
  95         .rtsr_ofst      = 0x00,
  96         .ftsr_ofst      = 0x04,
  97         .swier_ofst     = 0x08,
  98         .rpr_ofst       = 0x88,
  99         .fpr_ofst       = UNDEF_REG,
 100 };
 101
 102 static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
 103         .imr_ofst       = 0x90,
 104         .emr_ofst       = 0x94,
 105         .rtsr_ofst      = 0x20,
 106         .ftsr_ofst      = 0x24,
 107         .swier_ofst     = 0x28,
 108         .rpr_ofst       = 0x98,
 109         .fpr_ofst       = UNDEF_REG,
 110 };
 111
 112 static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
 113         .imr_ofst       = 0xA0,
 114         .emr_ofst       = 0xA4,
 115         .rtsr_ofst      = 0x40,
 116         .ftsr_ofst      = 0x44,
 117         .swier_ofst     = 0x48,
 118         .rpr_ofst       = 0xA8,
 119         .fpr_ofst       = UNDEF_REG,
 120 };
 121
 122 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
 123         &stm32h7xx_exti_b1,
 124         &stm32h7xx_exti_b2,
 125         &stm32h7xx_exti_b3,
 126 };
 127
 128 static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
 129         .exti_banks = stm32h7xx_exti_banks,
 130         .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
 131 };
 132
 133 static const struct stm32_exti_bank stm32mp1_exti_b1 = {
 134         .imr_ofst       = 0x80,
 135         .emr_ofst       = 0x84,
 136         .rtsr_ofst      = 0x00,
 137         .ftsr_ofst      = 0x04,
 138         .swier_ofst     = 0x08,
 139         .rpr_ofst       = 0x0C,
 140         .fpr_ofst       = 0x10,
 141 };
 142
 143 static const struct stm32_exti_bank stm32mp1_exti_b2 = {
 144         .imr_ofst       = 0x90,
 145         .emr_ofst       = 0x94,
 146         .rtsr_ofst      = 0x20,
 147         .ftsr_ofst      = 0x24,
 148         .swier_ofst     = 0x28,
 149         .rpr_ofst       = 0x2C,
 150         .fpr_ofst       = 0x30,
 151 };
 152
 153 static const struct stm32_exti_bank stm32mp1_exti_b3 = {
 154         .imr_ofst       = 0xA0,
 155         .emr_ofst       = 0xA4,
 156         .rtsr_ofst      = 0x40,
 157         .ftsr_ofst      = 0x44,
 158         .swier_ofst     = 0x48,
 159         .rpr_ofst       = 0x4C,
 160         .fpr_ofst       = 0x50,
 161 };
 162
 163 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
 164         &stm32mp1_exti_b1,
 165         &stm32mp1_exti_b2,
 166         &stm32mp1_exti_b3,
 167 };
 168
 169 static struct irq_chip stm32_exti_h_chip;
 170 static struct irq_chip stm32_exti_h_chip_direct;
 171
 172 static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
 173         { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
 174         { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
 175         { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
 176         { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
 177         { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
 178         { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
 179         { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
 180         { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
 181         { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
 182         { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
 183         { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
 184         { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
 185         { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
 186         { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
 187         { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
 188         { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
 189         { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
 190         { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
 191         { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
 192         { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
 193         { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
 194         { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
 195         { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
 196         { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
 197         { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
 198         { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
 199         { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
 200         { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
 201         { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
 202         { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
 203         { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
 204         { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
 205         { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
 206         { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
 207         { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
 208 };
 209
 210 static const struct stm32_exti_drv_data stm32mp1_drv_data = {
 211         .exti_banks = stm32mp1_exti_banks,
 212         .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
 213         .desc_irqs = stm32mp1_desc_irq,
 214         .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
 215 };
 216
 217 static const struct
 218 stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
 219                                     irq_hw_number_t hwirq)
 220 {
 221         const struct stm32_desc_irq *desc = NULL;
 222         int i;
 223
 224         if (!drv_data->desc_irqs)
 225                 return NULL;
 226
 227         for (i = 0; i < drv_data->irq_nr; i++) {
 228                 desc = &drv_data->desc_irqs[i];
 229                 if (desc->exti == hwirq)
 230                         break;
 231         }
 232
 233         return desc;
 234 }
 235
 236 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
 237 {
 238         struct stm32_exti_chip_data *chip_data = gc->private;
 239         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 240         unsigned long pending;
 241
 242         pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
 243         if (stm32_bank->fpr_ofst != UNDEF_REG)
 244                 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
 245
 246         return pending;
 247 }
 248
 249 static void stm32_irq_handler(struct irq_desc *desc)
 250 {
 251         struct irq_domain *domain = irq_desc_get_handler_data(desc);
 252         struct irq_chip *chip = irq_desc_get_chip(desc);
 253         unsigned int virq, nbanks = domain->gc->num_chips;
 254         struct irq_chip_generic *gc;
 255         unsigned long pending;
 256         int n, i, irq_base = 0;
 257
 258         chained_irq_enter(chip, desc);
 259
 260         for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
 261                 gc = irq_get_domain_generic_chip(domain, irq_base);
 262
 263                 while ((pending = stm32_exti_pending(gc))) {
 264                         for_each_set_bit(n, &pending, IRQS_PER_BANK) {
 265                                 virq = irq_find_mapping(domain, irq_base + n);
 266                                 generic_handle_irq(virq);
 267                         }
 268                 }
 269         }
 270
 271         chained_irq_exit(chip, desc);
 272 }
 273
 274 static int stm32_exti_set_type(struct irq_data *d,
 275                                unsigned int type, u32 *rtsr, u32 *ftsr)
 276 {
 277         u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
 278
 279         switch (type) {
 280         case IRQ_TYPE_EDGE_RISING:
 281                 *rtsr |= mask;
 282                 *ftsr &= ~mask;
 283                 break;
 284         case IRQ_TYPE_EDGE_FALLING:
 285                 *rtsr &= ~mask;
 286                 *ftsr |= mask;
 287                 break;
 288         case IRQ_TYPE_EDGE_BOTH:
 289                 *rtsr |= mask;
 290                 *ftsr |= mask;
 291                 break;
 292         default:
 293                 return -EINVAL;
 294         }
 295
 296         return 0;
 297 }
 298
 299 static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
 300 {
 301         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 302         struct stm32_exti_chip_data *chip_data = gc->private;
 303         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 304         struct hwspinlock *hwlock = chip_data->host_data->hwlock;
 305         u32 rtsr, ftsr;
 306         int err;
 307
 308         irq_gc_lock(gc);
 309
 310         if (hwlock) {
 311                 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
 312                 if (err) {
 313                         pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
 314                         goto unlock;
 315                 }
 316         }
 317
 318         rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
 319         ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
 320
 321         err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
 322         if (err)
 323                 goto unspinlock;
 324
 325         irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
 326         irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
 327
 328 unspinlock:
 329         if (hwlock)
 330                 hwspin_unlock_in_atomic(hwlock);
 331 unlock:
 332         irq_gc_unlock(gc);
 333
 334         return err;
 335 }
 336
 337 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
 338                                u32 wake_active)
 339 {
 340         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 341         void __iomem *base = chip_data->host_data->base;
 342
 343         /* save rtsr, ftsr registers */
 344         chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
 345         chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
 346
 347         writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
 348 }
 349
 350 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
 351                               u32 mask_cache)
 352 {
 353         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 354         void __iomem *base = chip_data->host_data->base;
 355
 356         /* restore rtsr, ftsr, registers */
 357         writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
 358         writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
 359
 360         writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
 361 }
 362
 363 static void stm32_irq_suspend(struct irq_chip_generic *gc)
 364 {
 365         struct stm32_exti_chip_data *chip_data = gc->private;
 366
 367         irq_gc_lock(gc);
 368         stm32_chip_suspend(chip_data, gc->wake_active);
 369         irq_gc_unlock(gc);
 370 }
 371
 372 static void stm32_irq_resume(struct irq_chip_generic *gc)
 373 {
 374         struct stm32_exti_chip_data *chip_data = gc->private;
 375
 376         irq_gc_lock(gc);
 377         stm32_chip_resume(chip_data, gc->mask_cache);
 378         irq_gc_unlock(gc);
 379 }
 380
 381 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
 382                             unsigned int nr_irqs, void *data)
 383 {
 384         struct irq_fwspec *fwspec = data;
 385         irq_hw_number_t hwirq;
 386
 387         hwirq = fwspec->param[0];
 388
 389         irq_map_generic_chip(d, virq, hwirq);
 390
 391         return 0;
 392 }
 393
 394 static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
 395                             unsigned int nr_irqs)
 396 {
 397         struct irq_data *data = irq_domain_get_irq_data(d, virq);
 398
 399         irq_domain_reset_irq_data(data);
 400 }
 401
 402 static const struct irq_domain_ops irq_exti_domain_ops = {
 403         .map    = irq_map_generic_chip,
 404         .alloc  = stm32_exti_alloc,
 405         .free   = stm32_exti_free,
 406 };
 407
 408 static void stm32_irq_ack(struct irq_data *d)
 409 {
 410         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 411         struct stm32_exti_chip_data *chip_data = gc->private;
 412         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 413
 414         irq_gc_lock(gc);
 415
 416         irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
 417         if (stm32_bank->fpr_ofst != UNDEF_REG)
 418                 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
 419
 420         irq_gc_unlock(gc);
 421 }
 422
 423 /* directly set the target bit without reading first. */
 424 static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
 425 {
 426         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 427         void __iomem *base = chip_data->host_data->base;
 428         u32 val = BIT(d->hwirq % IRQS_PER_BANK);
 429
 430         writel_relaxed(val, base + reg);
 431 }
 432
 433 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
 434 {
 435         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 436         void __iomem *base = chip_data->host_data->base;
 437         u32 val;
 438
 439         val = readl_relaxed(base + reg);
 440         val |= BIT(d->hwirq % IRQS_PER_BANK);
 441         writel_relaxed(val, base + reg);
 442
 443         return val;
 444 }
 445
 446 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
 447 {
 448         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 449         void __iomem *base = chip_data->host_data->base;
 450         u32 val;
 451
 452         val = readl_relaxed(base + reg);
 453         val &= ~BIT(d->hwirq % IRQS_PER_BANK);
 454         writel_relaxed(val, base + reg);
 455
 456         return val;
 457 }
 458
 459 static void stm32_exti_h_eoi(struct irq_data *d)
 460 {
 461         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 462         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 463
 464         raw_spin_lock(&chip_data->rlock);
 465
 466         stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
 467         if (stm32_bank->fpr_ofst != UNDEF_REG)
 468                 stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
 469
 470         raw_spin_unlock(&chip_data->rlock);
 471
 472         if (d->parent_data->chip)
 473                 irq_chip_eoi_parent(d);
 474 }
 475
 476 static void stm32_exti_h_mask(struct irq_data *d)
 477 {
 478         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 479         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 480
 481         raw_spin_lock(&chip_data->rlock);
 482         chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
 483         raw_spin_unlock(&chip_data->rlock);
 484
 485         if (d->parent_data->chip)
 486                 irq_chip_mask_parent(d);
 487 }
 488
 489 static void stm32_exti_h_unmask(struct irq_data *d)
 490 {
 491         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 492         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 493
 494         raw_spin_lock(&chip_data->rlock);
 495         chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
 496         raw_spin_unlock(&chip_data->rlock);
 497
 498         if (d->parent_data->chip)
 499                 irq_chip_unmask_parent(d);
 500 }
 501
 502 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
 503 {
 504         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 505         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 506         struct hwspinlock *hwlock = chip_data->host_data->hwlock;
 507         void __iomem *base = chip_data->host_data->base;
 508         u32 rtsr, ftsr;
 509         int err;
 510
 511         raw_spin_lock(&chip_data->rlock);
 512
 513         if (hwlock) {
 514                 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
 515                 if (err) {
 516                         pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
 517                         goto unlock;
 518                 }
 519         }
 520
 521         rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
 522         ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
 523
 524         err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
 525         if (err)
 526                 goto unspinlock;
 527
 528         writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
 529         writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
 530
 531 unspinlock:
 532         if (hwlock)
 533                 hwspin_unlock_in_atomic(hwlock);
 534 unlock:
 535         raw_spin_unlock(&chip_data->rlock);
 536
 537         return err;
 538 }
 539
 540 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
 541 {
 542         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 543         u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
 544
 545         raw_spin_lock(&chip_data->rlock);
 546
 547         if (on)
 548                 chip_data->wake_active |= mask;
 549         else
 550                 chip_data->wake_active &= ~mask;
 551
 552         raw_spin_unlock(&chip_data->rlock);
 553
 554         return 0;
 555 }
 556
 557 static int stm32_exti_h_set_affinity(struct irq_data *d,
 558                                      const struct cpumask *dest, bool force)
 559 {
 560         if (d->parent_data->chip)
 561                 return irq_chip_set_affinity_parent(d, dest, force);
 562
 563         return -EINVAL;
 564 }
 565
 566 static int __maybe_unused stm32_exti_h_suspend(void)
 567 {
 568         struct stm32_exti_chip_data *chip_data;
 569         int i;
 570
 571         for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
 572                 chip_data = &stm32_host_data->chips_data[i];
 573                 raw_spin_lock(&chip_data->rlock);
 574                 stm32_chip_suspend(chip_data, chip_data->wake_active);
 575                 raw_spin_unlock(&chip_data->rlock);
 576         }
 577
 578         return 0;
 579 }
 580
 581 static void __maybe_unused stm32_exti_h_resume(void)
 582 {
 583         struct stm32_exti_chip_data *chip_data;
 584         int i;
 585
 586         for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
 587                 chip_data = &stm32_host_data->chips_data[i];
 588                 raw_spin_lock(&chip_data->rlock);
 589                 stm32_chip_resume(chip_data, chip_data->mask_cache);
 590                 raw_spin_unlock(&chip_data->rlock);
 591         }
 592 }
 593
 594 static struct syscore_ops stm32_exti_h_syscore_ops = {
 595 #ifdef CONFIG_PM_SLEEP
 596         .suspend        = stm32_exti_h_suspend,
 597         .resume         = stm32_exti_h_resume,
 598 #endif
 599 };
 600
 601 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
 602 {
 603         stm32_host_data = host_data;
 604         register_syscore_ops(&stm32_exti_h_syscore_ops);
 605 }
 606
 607 static void stm32_exti_h_syscore_deinit(void)
 608 {
 609         unregister_syscore_ops(&stm32_exti_h_syscore_ops);
 610 }
 611
 612 static int stm32_exti_h_retrigger(struct irq_data *d)
 613 {
 614         struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
 615         const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 616         void __iomem *base = chip_data->host_data->base;
 617         u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
 618
 619         writel_relaxed(mask, base + stm32_bank->swier_ofst);
 620
 621         return 0;
 622 }
 623
 624 static struct irq_chip stm32_exti_h_chip = {
 625         .name                   = "stm32-exti-h",
 626         .irq_eoi                = stm32_exti_h_eoi,
 627         .irq_mask               = stm32_exti_h_mask,
 628         .irq_unmask             = stm32_exti_h_unmask,
 629         .irq_retrigger          = stm32_exti_h_retrigger,
 630         .irq_set_type           = stm32_exti_h_set_type,
 631         .irq_set_wake           = stm32_exti_h_set_wake,
 632         .flags                  = IRQCHIP_MASK_ON_SUSPEND,
 633         .irq_set_affinity       = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
 634 };
 635
 636 static struct irq_chip stm32_exti_h_chip_direct = {
 637         .name                   = "stm32-exti-h-direct",
 638         .irq_eoi                = irq_chip_eoi_parent,
 639         .irq_ack                = irq_chip_ack_parent,
 640         .irq_mask               = irq_chip_mask_parent,
 641         .irq_unmask             = irq_chip_unmask_parent,
 642         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 643         .irq_set_type           = irq_chip_set_type_parent,
 644         .irq_set_wake           = stm32_exti_h_set_wake,
 645         .flags                  = IRQCHIP_MASK_ON_SUSPEND,
 646         .irq_set_affinity       = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
 647 };
 648
 649 static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
 650                                      unsigned int virq,
 651                                      unsigned int nr_irqs, void *data)
 652 {
 653         struct stm32_exti_host_data *host_data = dm->host_data;
 654         struct stm32_exti_chip_data *chip_data;
 655         const struct stm32_desc_irq *desc;
 656         struct irq_fwspec *fwspec = data;
 657         struct irq_fwspec p_fwspec;
 658         irq_hw_number_t hwirq;
 659         int bank;
 660
 661         hwirq = fwspec->param[0];
 662         bank  = hwirq / IRQS_PER_BANK;
 663         chip_data = &host_data->chips_data[bank];
 664
 665
 666         desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
 667         if (!desc)
 668                 return -EINVAL;
 669
 670         irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
 671                                       chip_data);
 672         if (desc->irq_parent) {
 673                 p_fwspec.fwnode = dm->parent->fwnode;
 674                 p_fwspec.param_count = 3;
 675                 p_fwspec.param[0] = GIC_SPI;
 676                 p_fwspec.param[1] = desc->irq_parent;
 677                 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
 678
 679                 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
 680         }
 681
 682         return 0;
 683 }
 684
 685 static struct
 686 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
 687                                            struct device_node *node)
 688 {
 689         struct stm32_exti_host_data *host_data;
 690
 691         host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
 692         if (!host_data)
 693                 return NULL;
 694
 695         host_data->drv_data = dd;
 696         host_data->chips_data = kcalloc(dd->bank_nr,
 697                                         sizeof(struct stm32_exti_chip_data),
 698                                         GFP_KERNEL);
 699         if (!host_data->chips_data)
 700                 goto free_host_data;
 701
 702         host_data->base = of_iomap(node, 0);
 703         if (!host_data->base) {
 704                 pr_err("%pOF: Unable to map registers\n", node);
 705                 goto free_chips_data;
 706         }
 707
 708         stm32_host_data = host_data;
 709
 710         return host_data;
 711
 712 free_chips_data:
 713         kfree(host_data->chips_data);
 714 free_host_data:
 715         kfree(host_data);
 716
 717         return NULL;
 718 }
 719
 720 static struct
 721 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
 722                                            u32 bank_idx,
 723                                            struct device_node *node)
 724 {
 725         const struct stm32_exti_bank *stm32_bank;
 726         struct stm32_exti_chip_data *chip_data;
 727         void __iomem *base = h_data->base;
 728
 729         stm32_bank = h_data->drv_data->exti_banks[bank_idx];
 730         chip_data = &h_data->chips_data[bank_idx];
 731         chip_data->host_data = h_data;
 732         chip_data->reg_bank = stm32_bank;
 733
 734         raw_spin_lock_init(&chip_data->rlock);
 735
 736         /*
 737          * This IP has no reset, so after hot reboot we should
 738          * clear registers to avoid residue
 739          */
 740         writel_relaxed(0, base + stm32_bank->imr_ofst);
 741         writel_relaxed(0, base + stm32_bank->emr_ofst);
 742
 743         pr_info("%pOF: bank%d\n", node, bank_idx);
 744
 745         return chip_data;
 746 }
 747
 748 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
 749                                   struct device_node *node)
 750 {
 751         struct stm32_exti_host_data *host_data;
 752         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 753         int nr_irqs, ret, i;
 754         struct irq_chip_generic *gc;
 755         struct irq_domain *domain;
 756
 757         host_data = stm32_exti_host_init(drv_data, node);
 758         if (!host_data)
 759                 return -ENOMEM;
 760
 761         domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
 762                                        &irq_exti_domain_ops, NULL);
 763         if (!domain) {
 764                 pr_err("%pOFn: Could not register interrupt domain.\n",
 765                        node);
 766                 ret = -ENOMEM;
 767                 goto out_unmap;
 768         }
 769
 770         ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
 771                                              handle_edge_irq, clr, 0, 0);
 772         if (ret) {
 773                 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
 774                        node);
 775                 goto out_free_domain;
 776         }
 777
 778         for (i = 0; i < drv_data->bank_nr; i++) {
 779                 const struct stm32_exti_bank *stm32_bank;
 780                 struct stm32_exti_chip_data *chip_data;
 781
 782                 stm32_bank = drv_data->exti_banks[i];
 783                 chip_data = stm32_exti_chip_init(host_data, i, node);
 784
 785                 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
 786
 787                 gc->reg_base = host_data->base;
 788                 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
 789                 gc->chip_types->chip.irq_ack = stm32_irq_ack;
 790                 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
 791                 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
 792                 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
 793                 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
 794                 gc->suspend = stm32_irq_suspend;
 795                 gc->resume = stm32_irq_resume;
 796                 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
 797
 798                 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
 799                 gc->private = (void *)chip_data;
 800         }
 801
 802         nr_irqs = of_irq_count(node);
 803         for (i = 0; i < nr_irqs; i++) {
 804                 unsigned int irq = irq_of_parse_and_map(node, i);
 805
 806                 irq_set_handler_data(irq, domain);
 807                 irq_set_chained_handler(irq, stm32_irq_handler);
 808         }
 809
 810         return 0;
 811
 812 out_free_domain:
 813         irq_domain_remove(domain);
 814 out_unmap:
 815         iounmap(host_data->base);
 816         kfree(host_data->chips_data);
 817         kfree(host_data);
 818         return ret;
 819 }
 820
 821 static const struct irq_domain_ops stm32_exti_h_domain_ops = {
 822         .alloc  = stm32_exti_h_domain_alloc,
 823         .free   = irq_domain_free_irqs_common,
 824         .xlate = irq_domain_xlate_twocell,
 825 };
 826
 827 static void stm32_exti_remove_irq(void *data)
 828 {
 829         struct irq_domain *domain = data;
 830
 831         irq_domain_remove(domain);
 832 }
 833
 834 static int stm32_exti_remove(struct platform_device *pdev)
 835 {
 836         stm32_exti_h_syscore_deinit();
 837         return 0;
 838 }
 839
 840 static int stm32_exti_probe(struct platform_device *pdev)
 841 {
 842         int ret, i;
 843         struct device *dev = &pdev->dev;
 844         struct device_node *np = dev->of_node;
 845         struct irq_domain *parent_domain, *domain;
 846         struct stm32_exti_host_data *host_data;
 847         const struct stm32_exti_drv_data *drv_data;
 848         struct resource *res;
 849
 850         host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
 851         if (!host_data)
 852                 return -ENOMEM;
 853
 854         /* check for optional hwspinlock which may be not available yet */
 855         ret = of_hwspin_lock_get_id(np, 0);
 856         if (ret == -EPROBE_DEFER)
 857                 /* hwspinlock framework not yet ready */
 858                 return ret;
 859
 860         if (ret >= 0) {
 861                 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
 862                 if (!host_data->hwlock) {
 863                         dev_err(dev, "Failed to request hwspinlock\n");
 864                         return -EINVAL;
 865                 }
 866         } else if (ret != -ENOENT) {
 867                 /* note: ENOENT is a valid case (means 'no hwspinlock') */
 868                 dev_err(dev, "Failed to get hwspinlock\n");
 869                 return ret;
 870         }
 871
 872         /* initialize host_data */
 873         drv_data = of_device_get_match_data(dev);
 874         if (!drv_data) {
 875                 dev_err(dev, "no of match data\n");
 876                 return -ENODEV;
 877         }
 878         host_data->drv_data = drv_data;
 879
 880         host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
 881                                              sizeof(*host_data->chips_data),
 882                                              GFP_KERNEL);
 883         if (!host_data->chips_data)
 884                 return -ENOMEM;
 885
 886         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 887         host_data->base = devm_ioremap_resource(dev, res);
 888         if (IS_ERR(host_data->base)) {
 889                 dev_err(dev, "Unable to map registers\n");
 890                 return PTR_ERR(host_data->base);
 891         }
 892
 893         for (i = 0; i < drv_data->bank_nr; i++)
 894                 stm32_exti_chip_init(host_data, i, np);
 895
 896         parent_domain = irq_find_host(of_irq_find_parent(np));
 897         if (!parent_domain) {
 898                 dev_err(dev, "GIC interrupt-parent not found\n");
 899                 return -EINVAL;
 900         }
 901
 902         domain = irq_domain_add_hierarchy(parent_domain, 0,
 903                                           drv_data->bank_nr * IRQS_PER_BANK,
 904                                           np, &stm32_exti_h_domain_ops,
 905                                           host_data);
 906
 907         if (!domain) {
 908                 dev_err(dev, "Could not register exti domain\n");
 909                 return -ENOMEM;
 910         }
 911
 912         ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
 913         if (ret)
 914                 return ret;
 915
 916         stm32_exti_h_syscore_init(host_data);
 917
 918         return 0;
 919 }
 920
 921 /* platform driver only for MP1 */
 922 static const struct of_device_id stm32_exti_ids[] = {
 923         { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
 924         {},
 925 };
 926 MODULE_DEVICE_TABLE(of, stm32_exti_ids);
 927
 928 static struct platform_driver stm32_exti_driver = {
 929         .probe          = stm32_exti_probe,
 930         .remove         = stm32_exti_remove,
 931         .driver         = {
 932                 .name   = "stm32_exti",
 933                 .of_match_table = stm32_exti_ids,
 934         },
 935 };
 936
 937 static int __init stm32_exti_arch_init(void)
 938 {
 939         return platform_driver_register(&stm32_exti_driver);
 940 }
 941
 942 static void __exit stm32_exti_arch_exit(void)
 943 {
 944         return platform_driver_unregister(&stm32_exti_driver);
 945 }
 946
 947 arch_initcall(stm32_exti_arch_init);
 948 module_exit(stm32_exti_arch_exit);
 949
 950 /* no platform driver for F4 and H7 */
 951 static int __init stm32f4_exti_of_init(struct device_node *np,
 952                                        struct device_node *parent)
 953 {
 954         return stm32_exti_init(&stm32f4xx_drv_data, np);
 955 }
 956
 957 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
 958
 959 static int __init stm32h7_exti_of_init(struct device_node *np,
 960                                        struct device_node *parent)
 961 {
 962         return stm32_exti_init(&stm32h7xx_drv_data, np);
 963 }
 964
 965 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);