drivers/media/dvb-frontends/atbm8830_priv.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *    Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
   4  *    ATBM8830, ATBM8831
   5  *
   6  *    Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
   7  */
   8
   9 #ifndef __ATBM8830_PRIV_H
  10 #define __ATBM8830_PRIV_H
  11
  12 struct atbm_state {
  13         struct i2c_adapter *i2c;
  14         /* configuration settings */
  15         const struct atbm8830_config *config;
  16         struct dvb_frontend frontend;
  17 };
  18
  19 #define REG_CHIP_ID     0x0000
  20 #define REG_TUNER_BASEBAND      0x0001
  21 #define REG_DEMOD_RUN   0x0004
  22 #define REG_DSP_RESET   0x0005
  23 #define REG_RAM_RESET   0x0006
  24 #define REG_ADC_RESET   0x0007
  25 #define REG_TSPORT_RESET        0x0008
  26 #define REG_BLKERR_POL  0x000C
  27 #define REG_I2C_GATE    0x0103
  28 #define REG_TS_SAMPLE_EDGE      0x0301
  29 #define REG_TS_PKT_LEN_204      0x0302
  30 #define REG_TS_PKT_LEN_AUTO     0x0303
  31 #define REG_TS_SERIAL   0x0305
  32 #define REG_TS_CLK_FREERUN      0x0306
  33 #define REG_TS_VALID_MODE       0x0307
  34 #define REG_TS_CLK_MODE 0x030B /* 1 for serial, 0 for parallel */
  35
  36 #define REG_TS_ERRBIT_USE       0x030C
  37 #define REG_LOCK_STATUS 0x030D
  38 #define REG_ADC_CONFIG  0x0602
  39 #define REG_CARRIER_OFFSET      0x0827 /* 0x0827-0x0829 little endian */
  40 #define REG_DETECTED_PN_MODE    0x082D
  41 #define REG_READ_LATCH  0x084D
  42 #define REG_IF_FREQ     0x0A00 /* 0x0A00-0x0A02 little endian */
  43 #define REG_OSC_CLK     0x0A03 /* 0x0A03-0x0A05 little endian */
  44 #define REG_BYPASS_CCI  0x0A06
  45 #define REG_ANALOG_LUMA_DETECTED        0x0A25
  46 #define REG_ANALOG_AUDIO_DETECTED       0x0A26
  47 #define REG_ANALOG_CHROMA_DETECTED      0x0A39
  48 #define REG_FRAME_ERR_CNT       0x0B04
  49 #define REG_USE_EXT_ADC 0x0C00
  50 #define REG_SWAP_I_Q    0x0C01
  51 #define REG_TPS_MANUAL  0x0D01
  52 #define REG_TPS_CONFIG  0x0D02
  53 #define REG_BYPASS_DEINTERLEAVER        0x0E00
  54 #define REG_AGC_TARGET  0x1003 /* 0x1003-0x1005 little endian */
  55 #define REG_AGC_MIN     0x1020
  56 #define REG_AGC_MAX     0x1023
  57 #define REG_AGC_LOCK    0x1027
  58 #define REG_AGC_PWM_VAL 0x1028 /* 0x1028-0x1029 little endian */
  59 #define REG_AGC_HOLD_LOOP       0x1031
  60
  61 #endif
  62