1 // SPDX-License-Identifier: GPL-2.0-only
3 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
5 * Copyright (C) 2003-2007 Micronas
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
14 #include <linux/i2c.h>
15 #include <asm/div64.h>
17 #include <media/dvb_frontend.h>
19 #include "drxd_firm.h"
21 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
22 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
26 #define DRX_I2C_RMW 0x10
27 #define DRX_I2C_BROADCAST 0x20
28 #define DRX_I2C_CLEARCRC 0x80
29 #define DRX_I2C_SINGLE_MASTER 0xC0
30 #define DRX_I2C_MODEFLAGS 0xC0
31 #define DRX_I2C_FLAGS 0xF0
33 #define DEFAULT_LOCK_TIMEOUT 1100
35 #define DRX_CHANNEL_AUTO 0
36 #define DRX_CHANNEL_HIGH 1
37 #define DRX_CHANNEL_LOW 2
39 #define DRX_LOCK_MPEG 1
40 #define DRX_LOCK_FEC 2
41 #define DRX_LOCK_DEMOD 4
43 /****************************************************************************/
52 DRXD_UNINITIALIZED
= 0,
65 OM_DVBT_Diversity_Front
,
70 enum AGC_CTRL_MODE ctrlMode
;
71 u16 outputLevel
; /* range [0, ... , 1023], 1/n of fullscale range */
72 u16 settleLevel
; /* range [0, ... , 1023], 1/n of fullscale range */
73 u16 minOutputLevel
; /* range [0, ... , 1023], 1/n of fullscale range */
74 u16 maxOutputLevel
; /* range [0, ... , 1023], 1/n of fullscale range */
75 u16 speed
; /* range [0, ... , 1023], 1/n of fullscale range */
101 struct dvb_frontend frontend
;
102 struct dvb_frontend_ops ops
;
103 struct dtv_frontend_properties props
;
105 const struct firmware
*fw
;
108 struct i2c_adapter
*i2c
;
110 struct drxd_config config
;
117 u16 hi_cfg_timing_div
;
118 u16 hi_cfg_bridge_delay
;
119 u16 hi_cfg_wakeup_key
;
122 u16 intermediate_freq
;
125 enum CSCDState cscd_state
;
126 enum CDrxdState drxd_state
;
129 s16 osc_clock_deviation
;
130 u16 expected_sys_clock_freq
;
137 struct SCfgAgc if_agc_cfg
;
138 struct SCfgAgc rf_agc_cfg
;
140 struct SNoiseCal noise_cal
;
143 u32 org_fe_fs_add_incr
;
144 u16 current_fe_if_incr
;
147 u16 m_FeAgRegAgAgcSio
;
149 u16 m_EcOcRegOcModeLop
;
150 u16 m_EcOcRegSncSncLvl
;
151 u8
*m_InitAtomicRead
;
163 u8
*m_InitDiversityFront
;
164 u8
*m_InitDiversityEnd
;
165 u8
*m_DisableDiversity
;
166 u8
*m_StartDiversityFront
;
167 u8
*m_StartDiversityEnd
;
169 u8
*m_DiversityDelay8MHZ
;
170 u8
*m_DiversityDelay6MHZ
;
173 u32 microcode_length
;
180 enum app_env app_env_default
;
181 enum app_env app_env_diversity
;
185 /****************************************************************************/
186 /* I2C **********************************************************************/
187 /****************************************************************************/
189 static int i2c_write(struct i2c_adapter
*adap
, u8 adr
, u8
* data
, int len
)
191 struct i2c_msg msg
= {.addr
= adr
, .flags
= 0, .buf
= data
, .len
= len
};
193 if (i2c_transfer(adap
, &msg
, 1) != 1)
198 static int i2c_read(struct i2c_adapter
*adap
,
199 u8 adr
, u8
*msg
, int len
, u8
*answ
, int alen
)
201 struct i2c_msg msgs
[2] = {
203 .addr
= adr
, .flags
= 0,
204 .buf
= msg
, .len
= len
206 .addr
= adr
, .flags
= I2C_M_RD
,
207 .buf
= answ
, .len
= alen
210 if (i2c_transfer(adap
, msgs
, 2) != 2)
215 static inline u32
MulDiv32(u32 a
, u32 b
, u32 c
)
219 tmp64
= (u64
)a
* (u64
)b
;
225 static int Read16(struct drxd_state
*state
, u32 reg
, u16
*data
, u8 flags
)
227 u8 adr
= state
->config
.demod_address
;
228 u8 mm1
[4] = { reg
& 0xff, (reg
>> 16) & 0xff,
229 flags
| ((reg
>> 24) & 0xff), (reg
>> 8) & 0xff
232 if (i2c_read(state
->i2c
, adr
, mm1
, 4, mm2
, 2) < 0)
235 *data
= mm2
[0] | (mm2
[1] << 8);
236 return mm2
[0] | (mm2
[1] << 8);
239 static int Read32(struct drxd_state
*state
, u32 reg
, u32
*data
, u8 flags
)
241 u8 adr
= state
->config
.demod_address
;
242 u8 mm1
[4] = { reg
& 0xff, (reg
>> 16) & 0xff,
243 flags
| ((reg
>> 24) & 0xff), (reg
>> 8) & 0xff
247 if (i2c_read(state
->i2c
, adr
, mm1
, 4, mm2
, 4) < 0)
251 mm2
[0] | (mm2
[1] << 8) | (mm2
[2] << 16) | (mm2
[3] << 24);
255 static int Write16(struct drxd_state
*state
, u32 reg
, u16 data
, u8 flags
)
257 u8 adr
= state
->config
.demod_address
;
258 u8 mm
[6] = { reg
& 0xff, (reg
>> 16) & 0xff,
259 flags
| ((reg
>> 24) & 0xff), (reg
>> 8) & 0xff,
260 data
& 0xff, (data
>> 8) & 0xff
263 if (i2c_write(state
->i2c
, adr
, mm
, 6) < 0)
268 static int Write32(struct drxd_state
*state
, u32 reg
, u32 data
, u8 flags
)
270 u8 adr
= state
->config
.demod_address
;
271 u8 mm
[8] = { reg
& 0xff, (reg
>> 16) & 0xff,
272 flags
| ((reg
>> 24) & 0xff), (reg
>> 8) & 0xff,
273 data
& 0xff, (data
>> 8) & 0xff,
274 (data
>> 16) & 0xff, (data
>> 24) & 0xff
277 if (i2c_write(state
->i2c
, adr
, mm
, 8) < 0)
282 static int write_chunk(struct drxd_state
*state
,
283 u32 reg
, u8
*data
, u32 len
, u8 flags
)
285 u8 adr
= state
->config
.demod_address
;
286 u8 mm
[CHUNK_SIZE
+ 4] = { reg
& 0xff, (reg
>> 16) & 0xff,
287 flags
| ((reg
>> 24) & 0xff), (reg
>> 8) & 0xff
291 for (i
= 0; i
< len
; i
++)
293 if (i2c_write(state
->i2c
, adr
, mm
, 4 + len
) < 0) {
294 printk(KERN_ERR
"error in write_chunk\n");
300 static int WriteBlock(struct drxd_state
*state
,
301 u32 Address
, u16 BlockSize
, u8
*pBlock
, u8 Flags
)
303 while (BlockSize
> 0) {
304 u16 Chunk
= BlockSize
> CHUNK_SIZE
? CHUNK_SIZE
: BlockSize
;
306 if (write_chunk(state
, Address
, pBlock
, Chunk
, Flags
) < 0)
309 Address
+= (Chunk
>> 1);
315 static int WriteTable(struct drxd_state
*state
, u8
* pTable
)
324 u32 Address
= pTable
[0] | (pTable
[1] << 8) |
325 (pTable
[2] << 16) | (pTable
[3] << 24);
327 if (Address
== 0xFFFFFFFF)
329 pTable
+= sizeof(u32
);
331 Length
= pTable
[0] | (pTable
[1] << 8);
332 pTable
+= sizeof(u16
);
335 status
= WriteBlock(state
, Address
, Length
* 2, pTable
, 0);
336 pTable
+= (Length
* 2);
341 /****************************************************************************/
342 /****************************************************************************/
343 /****************************************************************************/
345 static int ResetCEFR(struct drxd_state
*state
)
347 return WriteTable(state
, state
->m_ResetCEFR
);
350 static int InitCP(struct drxd_state
*state
)
352 return WriteTable(state
, state
->m_InitCP
);
355 static int InitCE(struct drxd_state
*state
)
358 enum app_env AppEnv
= state
->app_env_default
;
361 status
= WriteTable(state
, state
->m_InitCE
);
365 if (state
->operation_mode
== OM_DVBT_Diversity_Front
||
366 state
->operation_mode
== OM_DVBT_Diversity_End
) {
367 AppEnv
= state
->app_env_diversity
;
369 if (AppEnv
== APPENV_STATIC
) {
370 status
= Write16(state
, CE_REG_TAPSET__A
, 0x0000, 0);
373 } else if (AppEnv
== APPENV_PORTABLE
) {
374 status
= Write16(state
, CE_REG_TAPSET__A
, 0x0001, 0);
377 } else if (AppEnv
== APPENV_MOBILE
&& state
->type_A
) {
378 status
= Write16(state
, CE_REG_TAPSET__A
, 0x0002, 0);
381 } else if (AppEnv
== APPENV_MOBILE
&& !state
->type_A
) {
382 status
= Write16(state
, CE_REG_TAPSET__A
, 0x0006, 0);
388 status
= Write16(state
, B_CE_REG_COMM_EXEC__A
, 0x0001, 0);
395 static int StopOC(struct drxd_state
*state
)
399 u16 ocModeLop
= state
->m_EcOcRegOcModeLop
;
404 /* Store output configuration */
405 status
= Read16(state
, EC_OC_REG_SNC_ISC_LVL__A
, &ocSyncLvl
, 0);
408 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
409 state
->m_EcOcRegSncSncLvl
= ocSyncLvl
;
410 /* m_EcOcRegOcModeLop = ocModeLop; */
412 /* Flush FIFO (byte-boundary) at fixed rate */
413 status
= Read16(state
, EC_OC_REG_RCN_MAP_LOP__A
, &dtoIncLop
, 0);
416 status
= Read16(state
, EC_OC_REG_RCN_MAP_HIP__A
, &dtoIncHip
, 0);
419 status
= Write16(state
, EC_OC_REG_DTO_INC_LOP__A
, dtoIncLop
, 0);
422 status
= Write16(state
, EC_OC_REG_DTO_INC_HIP__A
, dtoIncHip
, 0);
425 ocModeLop
&= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M
);
426 ocModeLop
|= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC
;
427 status
= Write16(state
, EC_OC_REG_OC_MODE_LOP__A
, ocModeLop
, 0);
430 status
= Write16(state
, EC_OC_REG_COMM_EXEC__A
, EC_OC_REG_COMM_EXEC_CTL_HOLD
, 0);
435 /* Output pins to '0' */
436 status
= Write16(state
, EC_OC_REG_OCR_MPG_UOS__A
, EC_OC_REG_OCR_MPG_UOS__M
, 0);
440 /* Force the OC out of sync */
441 ocSyncLvl
&= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M
);
442 status
= Write16(state
, EC_OC_REG_SNC_ISC_LVL__A
, ocSyncLvl
, 0);
445 ocModeLop
&= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M
);
446 ocModeLop
|= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE
;
447 ocModeLop
|= 0x2; /* Magically-out-of-sync */
448 status
= Write16(state
, EC_OC_REG_OC_MODE_LOP__A
, ocModeLop
, 0);
451 status
= Write16(state
, EC_OC_REG_COMM_INT_STA__A
, 0x0, 0);
454 status
= Write16(state
, EC_OC_REG_COMM_EXEC__A
, EC_OC_REG_COMM_EXEC_CTL_ACTIVE
, 0);
462 static int StartOC(struct drxd_state
*state
)
468 status
= Write16(state
, EC_OC_REG_COMM_EXEC__A
, EC_OC_REG_COMM_EXEC_CTL_HOLD
, 0);
472 /* Restore output configuration */
473 status
= Write16(state
, EC_OC_REG_SNC_ISC_LVL__A
, state
->m_EcOcRegSncSncLvl
, 0);
476 status
= Write16(state
, EC_OC_REG_OC_MODE_LOP__A
, state
->m_EcOcRegOcModeLop
, 0);
480 /* Output pins active again */
481 status
= Write16(state
, EC_OC_REG_OCR_MPG_UOS__A
, EC_OC_REG_OCR_MPG_UOS_INIT
, 0);
486 status
= Write16(state
, EC_OC_REG_COMM_EXEC__A
, EC_OC_REG_COMM_EXEC_CTL_ACTIVE
, 0);
493 static int InitEQ(struct drxd_state
*state
)
495 return WriteTable(state
, state
->m_InitEQ
);
498 static int InitEC(struct drxd_state
*state
)
500 return WriteTable(state
, state
->m_InitEC
);
503 static int InitSC(struct drxd_state
*state
)
505 return WriteTable(state
, state
->m_InitSC
);
508 static int InitAtomicRead(struct drxd_state
*state
)
510 return WriteTable(state
, state
->m_InitAtomicRead
);
513 static int CorrectSysClockDeviation(struct drxd_state
*state
);
515 static int DRX_GetLockStatus(struct drxd_state
*state
, u32
* pLockStatus
)
518 const u16 mpeg_lock_mask
= (SC_RA_RAM_LOCK_MPEG__M
|
519 SC_RA_RAM_LOCK_FEC__M
|
520 SC_RA_RAM_LOCK_DEMOD__M
);
521 const u16 fec_lock_mask
= (SC_RA_RAM_LOCK_FEC__M
|
522 SC_RA_RAM_LOCK_DEMOD__M
);
523 const u16 demod_lock_mask
= SC_RA_RAM_LOCK_DEMOD__M
;
529 status
= Read16(state
, SC_RA_RAM_LOCK__A
, &ScRaRamLock
, 0x0000);
531 printk(KERN_ERR
"Can't read SC_RA_RAM_LOCK__A status = %08x\n", status
);
535 if (state
->drxd_state
!= DRXD_STARTED
)
538 if ((ScRaRamLock
& mpeg_lock_mask
) == mpeg_lock_mask
) {
539 *pLockStatus
|= DRX_LOCK_MPEG
;
540 CorrectSysClockDeviation(state
);
543 if ((ScRaRamLock
& fec_lock_mask
) == fec_lock_mask
)
544 *pLockStatus
|= DRX_LOCK_FEC
;
546 if ((ScRaRamLock
& demod_lock_mask
) == demod_lock_mask
)
547 *pLockStatus
|= DRX_LOCK_DEMOD
;
551 /****************************************************************************/
553 static int SetCfgIfAgc(struct drxd_state
*state
, struct SCfgAgc
*cfg
)
557 if (cfg
->outputLevel
> DRXD_FE_CTRL_MAX
)
560 if (cfg
->ctrlMode
== AGC_CTRL_USER
) {
562 u16 FeAgRegPm1AgcWri
;
563 u16 FeAgRegAgModeLop
;
565 status
= Read16(state
, FE_AG_REG_AG_MODE_LOP__A
, &FeAgRegAgModeLop
, 0);
568 FeAgRegAgModeLop
&= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M
);
569 FeAgRegAgModeLop
|= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC
;
570 status
= Write16(state
, FE_AG_REG_AG_MODE_LOP__A
, FeAgRegAgModeLop
, 0);
574 FeAgRegPm1AgcWri
= (u16
) (cfg
->outputLevel
&
575 FE_AG_REG_PM1_AGC_WRI__M
);
576 status
= Write16(state
, FE_AG_REG_PM1_AGC_WRI__A
, FeAgRegPm1AgcWri
, 0);
580 } else if (cfg
->ctrlMode
== AGC_CTRL_AUTO
) {
581 if (((cfg
->maxOutputLevel
) < (cfg
->minOutputLevel
)) ||
582 ((cfg
->maxOutputLevel
) > DRXD_FE_CTRL_MAX
) ||
583 ((cfg
->speed
) > DRXD_FE_CTRL_MAX
) ||
584 ((cfg
->settleLevel
) > DRXD_FE_CTRL_MAX
)
588 u16 FeAgRegAgModeLop
;
589 u16 FeAgRegEgcSetLvl
;
594 status
= Read16(state
, FE_AG_REG_AG_MODE_LOP__A
, &FeAgRegAgModeLop
, 0);
597 FeAgRegAgModeLop
&= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M
);
599 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC
;
600 status
= Write16(state
, FE_AG_REG_AG_MODE_LOP__A
, FeAgRegAgModeLop
, 0);
604 /* == Settle level == */
606 FeAgRegEgcSetLvl
= (u16
) ((cfg
->settleLevel
>> 1) &
607 FE_AG_REG_EGC_SET_LVL__M
);
608 status
= Write16(state
, FE_AG_REG_EGC_SET_LVL__A
, FeAgRegEgcSetLvl
, 0);
614 slope
= (u16
) ((cfg
->maxOutputLevel
-
615 cfg
->minOutputLevel
) / 2);
616 offset
= (u16
) ((cfg
->maxOutputLevel
+
617 cfg
->minOutputLevel
) / 2 - 511);
619 status
= Write16(state
, FE_AG_REG_GC1_AGC_RIC__A
, slope
, 0);
622 status
= Write16(state
, FE_AG_REG_GC1_AGC_OFF__A
, offset
, 0);
628 const u16 maxRur
= 8;
629 static const u16 slowIncrDecLUT
[] = {
631 static const u16 fastIncrDecLUT
[] = {
639 u16 fineSteps
= (DRXD_FE_CTRL_MAX
+ 1) /
641 u16 fineSpeed
= (u16
) (cfg
->speed
-
645 u16 invRurCount
= (u16
) (cfg
->speed
/
648 if (invRurCount
> maxRur
) {
650 fineSpeed
+= fineSteps
;
652 rurCount
= maxRur
- invRurCount
;
657 (2^(fineSpeed/fineSteps))
658 => range[default...2*default>
660 (2^(fineSpeed/fineSteps))
664 fastIncrDecLUT
[fineSpeed
/
668 slowIncrDecLUT
[fineSpeed
/
672 status
= Write16(state
, FE_AG_REG_EGC_RUR_CNT__A
, rurCount
, 0);
675 status
= Write16(state
, FE_AG_REG_EGC_FAS_INC__A
, fastIncrDec
, 0);
678 status
= Write16(state
, FE_AG_REG_EGC_FAS_DEC__A
, fastIncrDec
, 0);
681 status
= Write16(state
, FE_AG_REG_EGC_SLO_INC__A
, slowIncrDec
, 0);
684 status
= Write16(state
, FE_AG_REG_EGC_SLO_DEC__A
, slowIncrDec
, 0);
692 /* No OFF mode for IF control */
698 static int SetCfgRfAgc(struct drxd_state
*state
, struct SCfgAgc
*cfg
)
702 if (cfg
->outputLevel
> DRXD_FE_CTRL_MAX
)
705 if (cfg
->ctrlMode
== AGC_CTRL_USER
) {
708 u16 level
= (cfg
->outputLevel
);
710 if (level
== DRXD_FE_CTRL_MAX
)
713 status
= Write16(state
, FE_AG_REG_PM2_AGC_WRI__A
, level
, 0x0000);
719 /* Powerdown PD2, WRI source */
720 state
->m_FeAgRegAgPwd
&= ~(FE_AG_REG_AG_PWD_PWD_PD2__M
);
721 state
->m_FeAgRegAgPwd
|=
722 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE
;
723 status
= Write16(state
, FE_AG_REG_AG_PWD__A
, state
->m_FeAgRegAgPwd
, 0x0000);
727 status
= Read16(state
, FE_AG_REG_AG_MODE_LOP__A
, &AgModeLop
, 0x0000);
730 AgModeLop
&= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M
|
731 FE_AG_REG_AG_MODE_LOP_MODE_E__M
));
732 AgModeLop
|= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC
|
733 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC
);
734 status
= Write16(state
, FE_AG_REG_AG_MODE_LOP__A
, AgModeLop
, 0x0000);
738 /* enable AGC2 pin */
740 u16 FeAgRegAgAgcSio
= 0;
741 status
= Read16(state
, FE_AG_REG_AG_AGC_SIO__A
, &FeAgRegAgAgcSio
, 0x0000);
745 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M
);
747 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT
;
748 status
= Write16(state
, FE_AG_REG_AG_AGC_SIO__A
, FeAgRegAgAgcSio
, 0x0000);
754 } else if (cfg
->ctrlMode
== AGC_CTRL_AUTO
) {
759 /* Automatic control */
760 /* Powerup PD2, AGC2 as output, TGC source */
761 (state
->m_FeAgRegAgPwd
) &=
762 ~(FE_AG_REG_AG_PWD_PWD_PD2__M
);
763 (state
->m_FeAgRegAgPwd
) |=
764 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE
;
765 status
= Write16(state
, FE_AG_REG_AG_PWD__A
, (state
->m_FeAgRegAgPwd
), 0x0000);
769 status
= Read16(state
, FE_AG_REG_AG_MODE_LOP__A
, &AgModeLop
, 0x0000);
772 AgModeLop
&= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M
|
773 FE_AG_REG_AG_MODE_LOP_MODE_E__M
));
774 AgModeLop
|= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC
|
775 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC
);
776 status
= Write16(state
, FE_AG_REG_AG_MODE_LOP__A
, AgModeLop
, 0x0000);
780 level
= (((cfg
->settleLevel
) >> 4) &
781 FE_AG_REG_TGC_SET_LVL__M
);
782 status
= Write16(state
, FE_AG_REG_TGC_SET_LVL__A
, level
, 0x0000);
786 /* Min/max: don't care */
790 /* enable AGC2 pin */
792 u16 FeAgRegAgAgcSio
= 0;
793 status
= Read16(state
, FE_AG_REG_AG_AGC_SIO__A
, &FeAgRegAgAgcSio
, 0x0000);
797 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M
);
799 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT
;
800 status
= Write16(state
, FE_AG_REG_AG_AGC_SIO__A
, FeAgRegAgAgcSio
, 0x0000);
810 /* No RF AGC control */
811 /* Powerdown PD2, AGC2 as output, WRI source */
812 (state
->m_FeAgRegAgPwd
) &=
813 ~(FE_AG_REG_AG_PWD_PWD_PD2__M
);
814 (state
->m_FeAgRegAgPwd
) |=
815 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE
;
816 status
= Write16(state
, FE_AG_REG_AG_PWD__A
, (state
->m_FeAgRegAgPwd
), 0x0000);
820 status
= Read16(state
, FE_AG_REG_AG_MODE_LOP__A
, &AgModeLop
, 0x0000);
823 AgModeLop
&= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M
|
824 FE_AG_REG_AG_MODE_LOP_MODE_E__M
));
825 AgModeLop
|= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC
|
826 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC
);
827 status
= Write16(state
, FE_AG_REG_AG_MODE_LOP__A
, AgModeLop
, 0x0000);
831 /* set FeAgRegAgAgcSio AGC2 (RF) as input */
833 u16 FeAgRegAgAgcSio
= 0;
834 status
= Read16(state
, FE_AG_REG_AG_AGC_SIO__A
, &FeAgRegAgAgcSio
, 0x0000);
838 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M
);
840 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT
;
841 status
= Write16(state
, FE_AG_REG_AG_AGC_SIO__A
, FeAgRegAgAgcSio
, 0x0000);
850 static int ReadIFAgc(struct drxd_state
*state
, u32
* pValue
)
855 if (state
->if_agc_cfg
.ctrlMode
!= AGC_CTRL_OFF
) {
857 status
= Read16(state
, FE_AG_REG_GC1_AGC_DAT__A
, &Value
, 0);
858 Value
&= FE_AG_REG_GC1_AGC_DAT__M
;
870 u32 R1
= state
->if_agc_cfg
.R1
;
871 u32 R2
= state
->if_agc_cfg
.R2
;
872 u32 R3
= state
->if_agc_cfg
.R3
;
874 u32 Vmax
, Rpar
, Vmin
, Vout
;
876 if (R2
== 0 && (R1
== 0 || R3
== 0))
879 Vmax
= (3300 * R2
) / (R1
+ R2
);
880 Rpar
= (R2
* R3
) / (R3
+ R2
);
881 Vmin
= (3300 * Rpar
) / (R1
+ Rpar
);
882 Vout
= Vmin
+ ((Vmax
- Vmin
) * Value
) / 1024;
890 static int load_firmware(struct drxd_state
*state
, const char *fw_name
)
892 const struct firmware
*fw
;
894 if (request_firmware(&fw
, fw_name
, state
->dev
) < 0) {
895 printk(KERN_ERR
"drxd: firmware load failure [%s]\n", fw_name
);
899 state
->microcode
= kmemdup(fw
->data
, fw
->size
, GFP_KERNEL
);
900 if (!state
->microcode
) {
901 release_firmware(fw
);
905 state
->microcode_length
= fw
->size
;
906 release_firmware(fw
);
910 static int DownloadMicrocode(struct drxd_state
*state
,
911 const u8
*pMCImage
, u32 Length
)
920 pSrc
= (u8
*) pMCImage
;
921 /* We're not using Flags */
922 /* Flags = (pSrc[0] << 8) | pSrc[1]; */
924 offset
+= sizeof(u16
);
925 nBlocks
= (pSrc
[0] << 8) | pSrc
[1];
927 offset
+= sizeof(u16
);
929 for (i
= 0; i
< nBlocks
; i
++) {
930 Address
= (pSrc
[0] << 24) | (pSrc
[1] << 16) |
931 (pSrc
[2] << 8) | pSrc
[3];
933 offset
+= sizeof(u32
);
935 BlockSize
= ((pSrc
[0] << 8) | pSrc
[1]) * sizeof(u16
);
937 offset
+= sizeof(u16
);
939 /* We're not using Flags */
940 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
942 offset
+= sizeof(u16
);
944 /* We're not using BlockCRC */
945 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
947 offset
+= sizeof(u16
);
949 status
= WriteBlock(state
, Address
, BlockSize
,
950 pSrc
, DRX_I2C_CLEARCRC
);
960 static int HI_Command(struct drxd_state
*state
, u16 cmd
, u16
* pResult
)
965 status
= Write16(state
, HI_RA_RAM_SRV_CMD__A
, cmd
, 0);
971 if (nrRetries
> DRXD_MAX_RETRIES
) {
975 status
= Read16(state
, HI_RA_RAM_SRV_CMD__A
, NULL
, 0);
976 } while (status
!= 0);
979 status
= Read16(state
, HI_RA_RAM_SRV_RES__A
, pResult
, 0);
983 static int HI_CfgCommand(struct drxd_state
*state
)
987 mutex_lock(&state
->mutex
);
988 Write16(state
, HI_RA_RAM_SRV_CFG_KEY__A
, HI_RA_RAM_SRV_RST_KEY_ACT
, 0);
989 Write16(state
, HI_RA_RAM_SRV_CFG_DIV__A
, state
->hi_cfg_timing_div
, 0);
990 Write16(state
, HI_RA_RAM_SRV_CFG_BDL__A
, state
->hi_cfg_bridge_delay
, 0);
991 Write16(state
, HI_RA_RAM_SRV_CFG_WUP__A
, state
->hi_cfg_wakeup_key
, 0);
992 Write16(state
, HI_RA_RAM_SRV_CFG_ACT__A
, state
->hi_cfg_ctrl
, 0);
994 Write16(state
, HI_RA_RAM_SRV_CFG_KEY__A
, HI_RA_RAM_SRV_RST_KEY_ACT
, 0);
996 if ((state
->hi_cfg_ctrl
& HI_RA_RAM_SRV_CFG_ACT_PWD_EXE
) ==
997 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE
)
998 status
= Write16(state
, HI_RA_RAM_SRV_CMD__A
,
999 HI_RA_RAM_SRV_CMD_CONFIG
, 0);
1001 status
= HI_Command(state
, HI_RA_RAM_SRV_CMD_CONFIG
, NULL
);
1002 mutex_unlock(&state
->mutex
);
1006 static int InitHI(struct drxd_state
*state
)
1008 state
->hi_cfg_wakeup_key
= (state
->chip_adr
);
1009 /* port/bridge/power down ctrl */
1010 state
->hi_cfg_ctrl
= HI_RA_RAM_SRV_CFG_ACT_SLV0_ON
;
1011 return HI_CfgCommand(state
);
1014 static int HI_ResetCommand(struct drxd_state
*state
)
1018 mutex_lock(&state
->mutex
);
1019 status
= Write16(state
, HI_RA_RAM_SRV_RST_KEY__A
,
1020 HI_RA_RAM_SRV_RST_KEY_ACT
, 0);
1022 status
= HI_Command(state
, HI_RA_RAM_SRV_CMD_RESET
, NULL
);
1023 mutex_unlock(&state
->mutex
);
1028 static int DRX_ConfigureI2CBridge(struct drxd_state
*state
, int bEnableBridge
)
1030 state
->hi_cfg_ctrl
&= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M
);
1032 state
->hi_cfg_ctrl
|= HI_RA_RAM_SRV_CFG_ACT_BRD_ON
;
1034 state
->hi_cfg_ctrl
|= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF
;
1036 return HI_CfgCommand(state
);
1039 #define HI_TR_WRITE 0x9
1040 #define HI_TR_READ 0xA
1041 #define HI_TR_READ_WRITE 0xB
1042 #define HI_TR_BROADCAST 0x4
1045 static int AtomicReadBlock(struct drxd_state
*state
,
1046 u32 Addr
, u16 DataSize
, u8
*pData
, u8 Flags
)
1051 /* Parameter check */
1052 if ((!pData
) || ((DataSize
& 1) != 0))
1055 mutex_lock(&state
->mutex
);
1058 /* Instruct HI to read n bytes */
1059 /* TODO use proper names forthese egisters */
1060 status
= Write16(state
, HI_RA_RAM_SRV_CFG_KEY__A
, (HI_TR_FUNC_ADDR
& 0xFFFF), 0);
1063 status
= Write16(state
, HI_RA_RAM_SRV_CFG_DIV__A
, (u16
) (Addr
>> 16), 0);
1066 status
= Write16(state
, HI_RA_RAM_SRV_CFG_BDL__A
, (u16
) (Addr
& 0xFFFF), 0);
1069 status
= Write16(state
, HI_RA_RAM_SRV_CFG_WUP__A
, (u16
) ((DataSize
/ 2) - 1), 0);
1072 status
= Write16(state
, HI_RA_RAM_SRV_CFG_ACT__A
, HI_TR_READ
, 0);
1076 status
= HI_Command(state
, HI_RA_RAM_SRV_CMD_EXECUTE
, 0);
1083 for (i
= 0; i
< (DataSize
/ 2); i
+= 1) {
1086 status
= Read16(state
, (HI_RA_RAM_USR_BEGIN__A
+ i
),
1090 pData
[2 * i
] = (u8
) (word
& 0xFF);
1091 pData
[(2 * i
) + 1] = (u8
) (word
>> 8);
1094 mutex_unlock(&state
->mutex
);
1098 static int AtomicReadReg32(struct drxd_state
*state
,
1099 u32 Addr
, u32
*pData
, u8 Flags
)
1101 u8 buf
[sizeof(u32
)];
1106 status
= AtomicReadBlock(state
, Addr
, sizeof(u32
), buf
, Flags
);
1107 *pData
= (((u32
) buf
[0]) << 0) +
1108 (((u32
) buf
[1]) << 8) +
1109 (((u32
) buf
[2]) << 16) + (((u32
) buf
[3]) << 24);
1114 static int StopAllProcessors(struct drxd_state
*state
)
1116 return Write16(state
, HI_COMM_EXEC__A
,
1117 SC_COMM_EXEC_CTL_STOP
, DRX_I2C_BROADCAST
);
1120 static int EnableAndResetMB(struct drxd_state
*state
)
1122 if (state
->type_A
) {
1123 /* disable? monitor bus observe @ EC_OC */
1124 Write16(state
, EC_OC_REG_OC_MON_SIO__A
, 0x0000, 0x0000);
1127 /* do inverse broadcast, followed by explicit write to HI */
1128 Write16(state
, HI_COMM_MB__A
, 0x0000, DRX_I2C_BROADCAST
);
1129 Write16(state
, HI_COMM_MB__A
, 0x0000, 0x0000);
1133 static int InitCC(struct drxd_state
*state
)
1137 if (state
->osc_clock_freq
== 0 ||
1138 state
->osc_clock_freq
> 20000 ||
1139 (state
->osc_clock_freq
% 4000) != 0) {
1140 printk(KERN_ERR
"invalid osc frequency %d\n", state
->osc_clock_freq
);
1144 status
|= Write16(state
, CC_REG_OSC_MODE__A
, CC_REG_OSC_MODE_M20
, 0);
1145 status
|= Write16(state
, CC_REG_PLL_MODE__A
,
1146 CC_REG_PLL_MODE_BYPASS_PLL
|
1147 CC_REG_PLL_MODE_PUMP_CUR_12
, 0);
1148 status
|= Write16(state
, CC_REG_REF_DIVIDE__A
,
1149 state
->osc_clock_freq
/ 4000, 0);
1150 status
|= Write16(state
, CC_REG_PWD_MODE__A
, CC_REG_PWD_MODE_DOWN_PLL
,
1152 status
|= Write16(state
, CC_REG_UPDATE__A
, CC_REG_UPDATE_KEY
, 0);
1157 static int ResetECOD(struct drxd_state
*state
)
1162 status
= Write16(state
, EC_OD_REG_SYNC__A
, 0x0664, 0);
1164 status
= Write16(state
, B_EC_OD_REG_SYNC__A
, 0x0664, 0);
1167 status
= WriteTable(state
, state
->m_ResetECRAM
);
1169 status
= Write16(state
, EC_OD_REG_COMM_EXEC__A
, 0x0001, 0);
1173 /* Configure PGA switch */
1175 static int SetCfgPga(struct drxd_state
*state
, int pgaSwitch
)
1184 status
= Read16(state
, B_FE_AG_REG_AG_MODE_LOP__A
, &AgModeLop
, 0x0000);
1187 AgModeLop
&= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M
));
1188 AgModeLop
|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC
;
1189 status
= Write16(state
, B_FE_AG_REG_AG_MODE_LOP__A
, AgModeLop
, 0x0000);
1194 status
= Read16(state
, B_FE_AG_REG_AG_MODE_HIP__A
, &AgModeHip
, 0x0000);
1197 AgModeHip
&= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M
));
1198 AgModeHip
|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC
;
1199 status
= Write16(state
, B_FE_AG_REG_AG_MODE_HIP__A
, AgModeHip
, 0x0000);
1203 /* enable fine and coarse gain, enable AAF,
1205 status
= Write16(state
, B_FE_AG_REG_AG_PGA_MODE__A
, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN
, 0x0000);
1209 /* PGA off, bypass */
1212 status
= Read16(state
, B_FE_AG_REG_AG_MODE_LOP__A
, &AgModeLop
, 0x0000);
1215 AgModeLop
&= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M
));
1216 AgModeLop
|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC
;
1217 status
= Write16(state
, B_FE_AG_REG_AG_MODE_LOP__A
, AgModeLop
, 0x0000);
1222 status
= Read16(state
, B_FE_AG_REG_AG_MODE_HIP__A
, &AgModeHip
, 0x0000);
1225 AgModeHip
&= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M
));
1226 AgModeHip
|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC
;
1227 status
= Write16(state
, B_FE_AG_REG_AG_MODE_HIP__A
, AgModeHip
, 0x0000);
1231 /* disable fine and coarse gain, enable AAF,
1233 status
= Write16(state
, B_FE_AG_REG_AG_PGA_MODE__A
, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN
, 0x0000);
1241 static int InitFE(struct drxd_state
*state
)
1246 status
= WriteTable(state
, state
->m_InitFE_1
);
1250 if (state
->type_A
) {
1251 status
= Write16(state
, FE_AG_REG_AG_PGA_MODE__A
,
1252 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN
,
1256 status
= SetCfgPga(state
, 0);
1259 Write16(state
, B_FE_AG_REG_AG_PGA_MODE__A
,
1260 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN
,
1266 status
= Write16(state
, FE_AG_REG_AG_AGC_SIO__A
, state
->m_FeAgRegAgAgcSio
, 0x0000);
1269 status
= Write16(state
, FE_AG_REG_AG_PWD__A
, state
->m_FeAgRegAgPwd
, 0x0000);
1273 status
= WriteTable(state
, state
->m_InitFE_2
);
1282 static int InitFT(struct drxd_state
*state
)
1285 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1288 return Write16(state
, FT_REG_COMM_EXEC__A
, 0x0001, 0x0000);
1291 static int SC_WaitForReady(struct drxd_state
*state
)
1295 for (i
= 0; i
< DRXD_MAX_RETRIES
; i
+= 1) {
1296 int status
= Read16(state
, SC_RA_RAM_CMD__A
, NULL
, 0);
1303 static int SC_SendCommand(struct drxd_state
*state
, u16 cmd
)
1305 int status
= 0, ret
;
1308 status
= Write16(state
, SC_RA_RAM_CMD__A
, cmd
, 0);
1312 SC_WaitForReady(state
);
1314 ret
= Read16(state
, SC_RA_RAM_CMD_ADDR__A
, &errCode
, 0);
1316 if (ret
< 0 || errCode
== 0xFFFF) {
1317 printk(KERN_ERR
"Command Error\n");
1324 static int SC_ProcStartCommand(struct drxd_state
*state
,
1325 u16 subCmd
, u16 param0
, u16 param1
)
1327 int ret
, status
= 0;
1330 mutex_lock(&state
->mutex
);
1332 ret
= Read16(state
, SC_COMM_EXEC__A
, &scExec
, 0);
1333 if (ret
< 0 || scExec
!= 1) {
1337 SC_WaitForReady(state
);
1338 status
|= Write16(state
, SC_RA_RAM_CMD_ADDR__A
, subCmd
, 0);
1339 status
|= Write16(state
, SC_RA_RAM_PARAM1__A
, param1
, 0);
1340 status
|= Write16(state
, SC_RA_RAM_PARAM0__A
, param0
, 0);
1342 SC_SendCommand(state
, SC_RA_RAM_CMD_PROC_START
);
1344 mutex_unlock(&state
->mutex
);
1348 static int SC_SetPrefParamCommand(struct drxd_state
*state
,
1349 u16 subCmd
, u16 param0
, u16 param1
)
1353 mutex_lock(&state
->mutex
);
1355 status
= SC_WaitForReady(state
);
1358 status
= Write16(state
, SC_RA_RAM_CMD_ADDR__A
, subCmd
, 0);
1361 status
= Write16(state
, SC_RA_RAM_PARAM1__A
, param1
, 0);
1364 status
= Write16(state
, SC_RA_RAM_PARAM0__A
, param0
, 0);
1368 status
= SC_SendCommand(state
, SC_RA_RAM_CMD_SET_PREF_PARAM
);
1372 mutex_unlock(&state
->mutex
);
1377 static int SC_GetOpParamCommand(struct drxd_state
*state
, u16
* result
)
1381 mutex_lock(&state
->mutex
);
1383 status
= SC_WaitForReady(state
);
1386 status
= SC_SendCommand(state
, SC_RA_RAM_CMD_GET_OP_PARAM
);
1389 status
= Read16(state
, SC_RA_RAM_PARAM0__A
, result
, 0);
1393 mutex_unlock(&state
->mutex
);
1398 static int ConfigureMPEGOutput(struct drxd_state
*state
, int bEnableOutput
)
1403 u16 EcOcRegIprInvMpg
= 0;
1404 u16 EcOcRegOcModeLop
= 0;
1405 u16 EcOcRegOcModeHip
= 0;
1406 u16 EcOcRegOcMpgSio
= 0;
1408 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1410 if (state
->operation_mode
== OM_DVBT_Diversity_Front
) {
1411 if (bEnableOutput
) {
1413 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR
;
1415 EcOcRegOcMpgSio
|= EC_OC_REG_OC_MPG_SIO__M
;
1417 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE
;
1419 EcOcRegOcModeLop
= state
->m_EcOcRegOcModeLop
;
1422 EcOcRegOcMpgSio
&= (~(EC_OC_REG_OC_MPG_SIO__M
));
1424 EcOcRegOcMpgSio
|= EC_OC_REG_OC_MPG_SIO__M
;
1426 /* Don't Insert RS Byte */
1427 if (state
->insert_rs_byte
) {
1429 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M
));
1431 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M
);
1433 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE
;
1436 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE
;
1438 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M
);
1440 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE
;
1443 /* Mode = Parallel */
1444 if (state
->enable_parallel
)
1446 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M
));
1449 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL
;
1452 /* EcOcRegIprInvMpg |= 0x00FF; */
1453 EcOcRegIprInvMpg
&= (~(0x00FF));
1455 /* Invert Error ( we don't use the pin ) */
1456 /* EcOcRegIprInvMpg |= 0x0100; */
1457 EcOcRegIprInvMpg
&= (~(0x0100));
1459 /* Invert Start ( we don't use the pin ) */
1460 /* EcOcRegIprInvMpg |= 0x0200; */
1461 EcOcRegIprInvMpg
&= (~(0x0200));
1463 /* Invert Valid ( we don't use the pin ) */
1464 /* EcOcRegIprInvMpg |= 0x0400; */
1465 EcOcRegIprInvMpg
&= (~(0x0400));
1468 /* EcOcRegIprInvMpg |= 0x0800; */
1469 EcOcRegIprInvMpg
&= (~(0x0800));
1471 /* EcOcRegOcModeLop =0x05; */
1472 status
= Write16(state
, EC_OC_REG_IPR_INV_MPG__A
, EcOcRegIprInvMpg
, 0);
1475 status
= Write16(state
, EC_OC_REG_OC_MODE_LOP__A
, EcOcRegOcModeLop
, 0);
1478 status
= Write16(state
, EC_OC_REG_OC_MODE_HIP__A
, EcOcRegOcModeHip
, 0x0000);
1481 status
= Write16(state
, EC_OC_REG_OC_MPG_SIO__A
, EcOcRegOcMpgSio
, 0);
1488 static int SetDeviceTypeId(struct drxd_state
*state
)
1494 status
= Read16(state
, CC_REG_JTAGID_L__A
, &deviceId
, 0);
1497 /* TODO: why twice? */
1498 status
= Read16(state
, CC_REG_JTAGID_L__A
, &deviceId
, 0);
1501 printk(KERN_INFO
"drxd: deviceId = %04x\n", deviceId
);
1505 state
->diversity
= 0;
1506 if (deviceId
== 0) { /* on A2 only 3975 available */
1508 printk(KERN_INFO
"DRX3975D-A2\n");
1511 printk(KERN_INFO
"DRX397%dD-B1\n", deviceId
);
1514 state
->diversity
= 1;
1521 state
->diversity
= 1;
1536 /* Init Table selection */
1537 state
->m_InitAtomicRead
= DRXD_InitAtomicRead
;
1538 state
->m_InitSC
= DRXD_InitSC
;
1539 state
->m_ResetECRAM
= DRXD_ResetECRAM
;
1540 if (state
->type_A
) {
1541 state
->m_ResetCEFR
= DRXD_ResetCEFR
;
1542 state
->m_InitFE_1
= DRXD_InitFEA2_1
;
1543 state
->m_InitFE_2
= DRXD_InitFEA2_2
;
1544 state
->m_InitCP
= DRXD_InitCPA2
;
1545 state
->m_InitCE
= DRXD_InitCEA2
;
1546 state
->m_InitEQ
= DRXD_InitEQA2
;
1547 state
->m_InitEC
= DRXD_InitECA2
;
1548 if (load_firmware(state
, DRX_FW_FILENAME_A2
))
1551 state
->m_ResetCEFR
= NULL
;
1552 state
->m_InitFE_1
= DRXD_InitFEB1_1
;
1553 state
->m_InitFE_2
= DRXD_InitFEB1_2
;
1554 state
->m_InitCP
= DRXD_InitCPB1
;
1555 state
->m_InitCE
= DRXD_InitCEB1
;
1556 state
->m_InitEQ
= DRXD_InitEQB1
;
1557 state
->m_InitEC
= DRXD_InitECB1
;
1558 if (load_firmware(state
, DRX_FW_FILENAME_B1
))
1561 if (state
->diversity
) {
1562 state
->m_InitDiversityFront
= DRXD_InitDiversityFront
;
1563 state
->m_InitDiversityEnd
= DRXD_InitDiversityEnd
;
1564 state
->m_DisableDiversity
= DRXD_DisableDiversity
;
1565 state
->m_StartDiversityFront
= DRXD_StartDiversityFront
;
1566 state
->m_StartDiversityEnd
= DRXD_StartDiversityEnd
;
1567 state
->m_DiversityDelay8MHZ
= DRXD_DiversityDelay8MHZ
;
1568 state
->m_DiversityDelay6MHZ
= DRXD_DiversityDelay6MHZ
;
1570 state
->m_InitDiversityFront
= NULL
;
1571 state
->m_InitDiversityEnd
= NULL
;
1572 state
->m_DisableDiversity
= NULL
;
1573 state
->m_StartDiversityFront
= NULL
;
1574 state
->m_StartDiversityEnd
= NULL
;
1575 state
->m_DiversityDelay8MHZ
= NULL
;
1576 state
->m_DiversityDelay6MHZ
= NULL
;
1582 static int CorrectSysClockDeviation(struct drxd_state
*state
)
1588 u32 sysClockInHz
= 0;
1589 u32 sysClockFreq
= 0; /* in kHz */
1590 s16 oscClockDeviation
;
1594 /* Retrieve bandwidth and incr, sanity check */
1596 /* These accesses should be AtomicReadReg32, but that
1597 causes trouble (at least for diversity */
1598 status
= Read32(state
, LC_RA_RAM_IFINCR_NOM_L__A
, ((u32
*) &nomincr
), 0);
1601 status
= Read32(state
, FE_IF_REG_INCR0__A
, (u32
*) &incr
, 0);
1605 if (state
->type_A
) {
1606 if ((nomincr
- incr
< -500) || (nomincr
- incr
> 500))
1609 if ((nomincr
- incr
< -2000) || (nomincr
- incr
> 2000))
1613 switch (state
->props
.bandwidth_hz
) {
1615 bandwidth
= DRXD_BANDWIDTH_8MHZ_IN_HZ
;
1618 bandwidth
= DRXD_BANDWIDTH_7MHZ_IN_HZ
;
1621 bandwidth
= DRXD_BANDWIDTH_6MHZ_IN_HZ
;
1627 /* Compute new sysclock value
1628 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1630 sysClockInHz
= MulDiv32(incr
, bandwidth
, 1 << 21);
1631 sysClockFreq
= (u32
) (sysClockInHz
/ 1000);
1633 if ((sysClockInHz
% 1000) > 500)
1636 /* Compute clock deviation in ppm */
1637 oscClockDeviation
= (u16
) ((((s32
) (sysClockFreq
) -
1639 (state
->expected_sys_clock_freq
)) *
1642 (state
->expected_sys_clock_freq
));
1644 Diff
= oscClockDeviation
- state
->osc_clock_deviation
;
1645 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1646 if (Diff
>= -200 && Diff
<= 200) {
1647 state
->sys_clock_freq
= (u16
) sysClockFreq
;
1648 if (oscClockDeviation
!= state
->osc_clock_deviation
) {
1649 if (state
->config
.osc_deviation
) {
1650 state
->config
.osc_deviation(state
->priv
,
1653 state
->osc_clock_deviation
=
1657 /* switch OFF SRMM scan in SC */
1658 status
= Write16(state
, SC_RA_RAM_SAMPLE_RATE_COUNT__A
, DRXD_OSCDEV_DONT_SCAN
, 0);
1661 /* overrule FE_IF internal value for
1662 proper re-locking */
1663 status
= Write16(state
, SC_RA_RAM_IF_SAVE__AX
, state
->current_fe_if_incr
, 0);
1666 state
->cscd_state
= CSCD_SAVED
;
1673 static int DRX_Stop(struct drxd_state
*state
)
1677 if (state
->drxd_state
!= DRXD_STARTED
)
1681 if (state
->cscd_state
!= CSCD_SAVED
) {
1683 status
= DRX_GetLockStatus(state
, &lock
);
1688 status
= StopOC(state
);
1692 state
->drxd_state
= DRXD_STOPPED
;
1694 status
= ConfigureMPEGOutput(state
, 0);
1698 if (state
->type_A
) {
1699 /* Stop relevant processors off the device */
1700 status
= Write16(state
, EC_OD_REG_COMM_EXEC__A
, 0x0000, 0x0000);
1704 status
= Write16(state
, SC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1707 status
= Write16(state
, LC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1711 /* Stop all processors except HI & CC & FE */
1712 status
= Write16(state
, B_SC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1715 status
= Write16(state
, B_LC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1718 status
= Write16(state
, B_FT_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1721 status
= Write16(state
, B_CP_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1724 status
= Write16(state
, B_CE_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1727 status
= Write16(state
, B_EQ_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
1730 status
= Write16(state
, EC_OD_REG_COMM_EXEC__A
, 0x0000, 0);
1739 #if 0 /* Currently unused */
1740 static int SetOperationMode(struct drxd_state
*state
, int oMode
)
1745 if (state
->drxd_state
!= DRXD_STOPPED
) {
1750 if (oMode
== state
->operation_mode
) {
1755 if (oMode
!= OM_Default
&& !state
->diversity
) {
1761 case OM_DVBT_Diversity_Front
:
1762 status
= WriteTable(state
, state
->m_InitDiversityFront
);
1764 case OM_DVBT_Diversity_End
:
1765 status
= WriteTable(state
, state
->m_InitDiversityEnd
);
1768 /* We need to check how to
1769 get DRXD out of diversity */
1771 status
= WriteTable(state
, state
->m_DisableDiversity
);
1777 state
->operation_mode
= oMode
;
1782 static int StartDiversity(struct drxd_state
*state
)
1788 if (state
->operation_mode
== OM_DVBT_Diversity_Front
) {
1789 status
= WriteTable(state
, state
->m_StartDiversityFront
);
1792 } else if (state
->operation_mode
== OM_DVBT_Diversity_End
) {
1793 status
= WriteTable(state
, state
->m_StartDiversityEnd
);
1796 if (state
->props
.bandwidth_hz
== 8000000) {
1797 status
= WriteTable(state
, state
->m_DiversityDelay8MHZ
);
1801 status
= WriteTable(state
, state
->m_DiversityDelay6MHZ
);
1806 status
= Read16(state
, B_EQ_REG_RC_SEL_CAR__A
, &rcControl
, 0);
1809 rcControl
&= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M
);
1810 rcControl
|= B_EQ_REG_RC_SEL_CAR_DIV_ON
|
1811 /* combining enabled */
1812 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC
|
1813 B_EQ_REG_RC_SEL_CAR_PASS_A_CC
|
1814 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC
;
1815 status
= Write16(state
, B_EQ_REG_RC_SEL_CAR__A
, rcControl
, 0);
1823 static int SetFrequencyShift(struct drxd_state
*state
,
1824 u32 offsetFreq
, int channelMirrored
)
1826 int negativeShift
= (state
->tuner_mirrors
== channelMirrored
);
1828 /* Handle all mirroring
1830 * Note: ADC mirroring (aliasing) is implictly handled by limiting
1831 * feFsRegAddInc to 28 bits below
1832 * (if the result before masking is more than 28 bits, this means
1833 * that the ADC is mirroring.
1834 * The masking is in fact the aliasing of the ADC)
1838 /* Compute register value, unsigned computation */
1839 state
->fe_fs_add_incr
= MulDiv32(state
->intermediate_freq
+
1841 1 << 28, state
->sys_clock_freq
);
1842 /* Remove integer part */
1843 state
->fe_fs_add_incr
&= 0x0FFFFFFFL
;
1845 state
->fe_fs_add_incr
= ((1 << 28) - state
->fe_fs_add_incr
);
1847 /* Save the frequency shift without tunerOffset compensation
1848 for CtrlGetChannel. */
1849 state
->org_fe_fs_add_incr
= MulDiv32(state
->intermediate_freq
,
1850 1 << 28, state
->sys_clock_freq
);
1851 /* Remove integer part */
1852 state
->org_fe_fs_add_incr
&= 0x0FFFFFFFL
;
1854 state
->org_fe_fs_add_incr
= ((1L << 28) -
1855 state
->org_fe_fs_add_incr
);
1857 return Write32(state
, FE_FS_REG_ADD_INC_LOP__A
,
1858 state
->fe_fs_add_incr
, 0);
1861 static int SetCfgNoiseCalibration(struct drxd_state
*state
,
1862 struct SNoiseCal
*noiseCal
)
1868 status
= Read16(state
, SC_RA_RAM_BE_OPT_ENA__A
, &beOptEna
, 0);
1871 if (noiseCal
->cpOpt
) {
1872 beOptEna
|= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT
);
1874 beOptEna
&= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT
);
1875 status
= Write16(state
, CP_REG_AC_NEXP_OFFS__A
, noiseCal
->cpNexpOfs
, 0);
1879 status
= Write16(state
, SC_RA_RAM_BE_OPT_ENA__A
, beOptEna
, 0);
1883 if (!state
->type_A
) {
1884 status
= Write16(state
, B_SC_RA_RAM_CO_TD_CAL_2K__A
, noiseCal
->tdCal2k
, 0);
1887 status
= Write16(state
, B_SC_RA_RAM_CO_TD_CAL_8K__A
, noiseCal
->tdCal8k
, 0);
1896 static int DRX_Start(struct drxd_state
*state
, s32 off
)
1898 struct dtv_frontend_properties
*p
= &state
->props
;
1901 u16 transmissionParams
= 0;
1902 u16 operationMode
= 0;
1903 u16 qpskTdTpsPwr
= 0;
1904 u16 qam16TdTpsPwr
= 0;
1905 u16 qam64TdTpsPwr
= 0;
1908 int mirrorFreqSpect
;
1910 u16 qpskSnCeGain
= 0;
1911 u16 qam16SnCeGain
= 0;
1912 u16 qam64SnCeGain
= 0;
1913 u16 qpskIsGainMan
= 0;
1914 u16 qam16IsGainMan
= 0;
1915 u16 qam64IsGainMan
= 0;
1916 u16 qpskIsGainExp
= 0;
1917 u16 qam16IsGainExp
= 0;
1918 u16 qam64IsGainExp
= 0;
1919 u16 bandwidthParam
= 0;
1922 off
= (off
- 500) / 1000;
1924 off
= (off
+ 500) / 1000;
1927 if (state
->drxd_state
!= DRXD_STOPPED
)
1929 status
= ResetECOD(state
);
1932 if (state
->type_A
) {
1933 status
= InitSC(state
);
1937 status
= InitFT(state
);
1940 status
= InitCP(state
);
1943 status
= InitCE(state
);
1946 status
= InitEQ(state
);
1949 status
= InitSC(state
);
1954 /* Restore current IF & RF AGC settings */
1956 status
= SetCfgIfAgc(state
, &state
->if_agc_cfg
);
1959 status
= SetCfgRfAgc(state
, &state
->rf_agc_cfg
);
1963 mirrorFreqSpect
= (state
->props
.inversion
== INVERSION_ON
);
1965 switch (p
->transmission_mode
) {
1966 default: /* Not set, detect it automatically */
1967 operationMode
|= SC_RA_RAM_OP_AUTO_MODE__M
;
1968 fallthrough
; /* try first guess DRX_FFTMODE_8K */
1969 case TRANSMISSION_MODE_8K
:
1970 transmissionParams
|= SC_RA_RAM_OP_PARAM_MODE_8K
;
1971 if (state
->type_A
) {
1972 status
= Write16(state
, EC_SB_REG_TR_MODE__A
, EC_SB_REG_TR_MODE_8K
, 0x0000);
1980 case TRANSMISSION_MODE_2K
:
1981 transmissionParams
|= SC_RA_RAM_OP_PARAM_MODE_2K
;
1982 if (state
->type_A
) {
1983 status
= Write16(state
, EC_SB_REG_TR_MODE__A
, EC_SB_REG_TR_MODE_2K
, 0x0000);
1993 switch (p
->guard_interval
) {
1994 case GUARD_INTERVAL_1_4
:
1995 transmissionParams
|= SC_RA_RAM_OP_PARAM_GUARD_4
;
1997 case GUARD_INTERVAL_1_8
:
1998 transmissionParams
|= SC_RA_RAM_OP_PARAM_GUARD_8
;
2000 case GUARD_INTERVAL_1_16
:
2001 transmissionParams
|= SC_RA_RAM_OP_PARAM_GUARD_16
;
2003 case GUARD_INTERVAL_1_32
:
2004 transmissionParams
|= SC_RA_RAM_OP_PARAM_GUARD_32
;
2006 default: /* Not set, detect it automatically */
2007 operationMode
|= SC_RA_RAM_OP_AUTO_GUARD__M
;
2008 /* try first guess 1/4 */
2009 transmissionParams
|= SC_RA_RAM_OP_PARAM_GUARD_4
;
2013 switch (p
->hierarchy
) {
2015 transmissionParams
|= SC_RA_RAM_OP_PARAM_HIER_A1
;
2016 if (state
->type_A
) {
2017 status
= Write16(state
, EQ_REG_OT_ALPHA__A
, 0x0001, 0x0000);
2020 status
= Write16(state
, EC_SB_REG_ALPHA__A
, 0x0001, 0x0000);
2024 qpskTdTpsPwr
= EQ_TD_TPS_PWR_UNKNOWN
;
2025 qam16TdTpsPwr
= EQ_TD_TPS_PWR_QAM16_ALPHA1
;
2026 qam64TdTpsPwr
= EQ_TD_TPS_PWR_QAM64_ALPHA1
;
2029 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE
;
2031 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE
;
2033 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE
;
2036 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE
;
2038 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE
;
2040 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE
;
2045 transmissionParams
|= SC_RA_RAM_OP_PARAM_HIER_A2
;
2046 if (state
->type_A
) {
2047 status
= Write16(state
, EQ_REG_OT_ALPHA__A
, 0x0002, 0x0000);
2050 status
= Write16(state
, EC_SB_REG_ALPHA__A
, 0x0002, 0x0000);
2054 qpskTdTpsPwr
= EQ_TD_TPS_PWR_UNKNOWN
;
2055 qam16TdTpsPwr
= EQ_TD_TPS_PWR_QAM16_ALPHA2
;
2056 qam64TdTpsPwr
= EQ_TD_TPS_PWR_QAM64_ALPHA2
;
2059 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE
;
2061 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE
;
2063 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE
;
2066 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE
;
2068 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE
;
2070 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE
;
2074 transmissionParams
|= SC_RA_RAM_OP_PARAM_HIER_A4
;
2075 if (state
->type_A
) {
2076 status
= Write16(state
, EQ_REG_OT_ALPHA__A
, 0x0003, 0x0000);
2079 status
= Write16(state
, EC_SB_REG_ALPHA__A
, 0x0003, 0x0000);
2083 qpskTdTpsPwr
= EQ_TD_TPS_PWR_UNKNOWN
;
2084 qam16TdTpsPwr
= EQ_TD_TPS_PWR_QAM16_ALPHA4
;
2085 qam64TdTpsPwr
= EQ_TD_TPS_PWR_QAM64_ALPHA4
;
2088 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE
;
2090 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE
;
2092 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE
;
2095 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE
;
2097 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE
;
2099 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE
;
2102 case HIERARCHY_AUTO
:
2104 /* Not set, detect it automatically, start with none */
2105 operationMode
|= SC_RA_RAM_OP_AUTO_HIER__M
;
2106 transmissionParams
|= SC_RA_RAM_OP_PARAM_HIER_NO
;
2107 if (state
->type_A
) {
2108 status
= Write16(state
, EQ_REG_OT_ALPHA__A
, 0x0000, 0x0000);
2111 status
= Write16(state
, EC_SB_REG_ALPHA__A
, 0x0000, 0x0000);
2115 qpskTdTpsPwr
= EQ_TD_TPS_PWR_QPSK
;
2116 qam16TdTpsPwr
= EQ_TD_TPS_PWR_QAM16_ALPHAN
;
2117 qam64TdTpsPwr
= EQ_TD_TPS_PWR_QAM64_ALPHAN
;
2120 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE
;
2122 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE
;
2124 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE
;
2127 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE
;
2129 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE
;
2131 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE
;
2138 switch (p
->modulation
) {
2140 operationMode
|= SC_RA_RAM_OP_AUTO_CONST__M
;
2141 fallthrough
; /* try first guess DRX_CONSTELLATION_QAM64 */
2143 transmissionParams
|= SC_RA_RAM_OP_PARAM_CONST_QAM64
;
2144 if (state
->type_A
) {
2145 status
= Write16(state
, EQ_REG_OT_CONST__A
, 0x0002, 0x0000);
2148 status
= Write16(state
, EC_SB_REG_CONST__A
, EC_SB_REG_CONST_64QAM
, 0x0000);
2151 status
= Write16(state
, EC_SB_REG_SCALE_MSB__A
, 0x0020, 0x0000);
2154 status
= Write16(state
, EC_SB_REG_SCALE_BIT2__A
, 0x0008, 0x0000);
2157 status
= Write16(state
, EC_SB_REG_SCALE_LSB__A
, 0x0002, 0x0000);
2161 status
= Write16(state
, EQ_REG_TD_TPS_PWR_OFS__A
, qam64TdTpsPwr
, 0x0000);
2164 status
= Write16(state
, EQ_REG_SN_CEGAIN__A
, qam64SnCeGain
, 0x0000);
2167 status
= Write16(state
, EQ_REG_IS_GAIN_MAN__A
, qam64IsGainMan
, 0x0000);
2170 status
= Write16(state
, EQ_REG_IS_GAIN_EXP__A
, qam64IsGainExp
, 0x0000);
2176 transmissionParams
|= SC_RA_RAM_OP_PARAM_CONST_QPSK
;
2177 if (state
->type_A
) {
2178 status
= Write16(state
, EQ_REG_OT_CONST__A
, 0x0000, 0x0000);
2181 status
= Write16(state
, EC_SB_REG_CONST__A
, EC_SB_REG_CONST_QPSK
, 0x0000);
2184 status
= Write16(state
, EC_SB_REG_SCALE_MSB__A
, 0x0010, 0x0000);
2187 status
= Write16(state
, EC_SB_REG_SCALE_BIT2__A
, 0x0000, 0x0000);
2190 status
= Write16(state
, EC_SB_REG_SCALE_LSB__A
, 0x0000, 0x0000);
2194 status
= Write16(state
, EQ_REG_TD_TPS_PWR_OFS__A
, qpskTdTpsPwr
, 0x0000);
2197 status
= Write16(state
, EQ_REG_SN_CEGAIN__A
, qpskSnCeGain
, 0x0000);
2200 status
= Write16(state
, EQ_REG_IS_GAIN_MAN__A
, qpskIsGainMan
, 0x0000);
2203 status
= Write16(state
, EQ_REG_IS_GAIN_EXP__A
, qpskIsGainExp
, 0x0000);
2210 transmissionParams
|= SC_RA_RAM_OP_PARAM_CONST_QAM16
;
2211 if (state
->type_A
) {
2212 status
= Write16(state
, EQ_REG_OT_CONST__A
, 0x0001, 0x0000);
2215 status
= Write16(state
, EC_SB_REG_CONST__A
, EC_SB_REG_CONST_16QAM
, 0x0000);
2218 status
= Write16(state
, EC_SB_REG_SCALE_MSB__A
, 0x0010, 0x0000);
2221 status
= Write16(state
, EC_SB_REG_SCALE_BIT2__A
, 0x0004, 0x0000);
2224 status
= Write16(state
, EC_SB_REG_SCALE_LSB__A
, 0x0000, 0x0000);
2228 status
= Write16(state
, EQ_REG_TD_TPS_PWR_OFS__A
, qam16TdTpsPwr
, 0x0000);
2231 status
= Write16(state
, EQ_REG_SN_CEGAIN__A
, qam16SnCeGain
, 0x0000);
2234 status
= Write16(state
, EQ_REG_IS_GAIN_MAN__A
, qam16IsGainMan
, 0x0000);
2237 status
= Write16(state
, EQ_REG_IS_GAIN_EXP__A
, qam16IsGainExp
, 0x0000);
2247 switch (DRX_CHANNEL_HIGH
) {
2249 case DRX_CHANNEL_AUTO
:
2250 case DRX_CHANNEL_LOW
:
2251 transmissionParams
|= SC_RA_RAM_OP_PARAM_PRIO_LO
;
2252 status
= Write16(state
, EC_SB_REG_PRIOR__A
, EC_SB_REG_PRIOR_LO
, 0x0000);
2254 case DRX_CHANNEL_HIGH
:
2255 transmissionParams
|= SC_RA_RAM_OP_PARAM_PRIO_HI
;
2256 status
= Write16(state
, EC_SB_REG_PRIOR__A
, EC_SB_REG_PRIOR_HI
, 0x0000);
2260 switch (p
->code_rate_HP
) {
2262 transmissionParams
|= SC_RA_RAM_OP_PARAM_RATE_1_2
;
2264 status
= Write16(state
, EC_VD_REG_SET_CODERATE__A
, EC_VD_REG_SET_CODERATE_C1_2
, 0x0000);
2267 operationMode
|= SC_RA_RAM_OP_AUTO_RATE__M
;
2270 transmissionParams
|= SC_RA_RAM_OP_PARAM_RATE_2_3
;
2272 status
= Write16(state
, EC_VD_REG_SET_CODERATE__A
, EC_VD_REG_SET_CODERATE_C2_3
, 0x0000);
2275 transmissionParams
|= SC_RA_RAM_OP_PARAM_RATE_3_4
;
2277 status
= Write16(state
, EC_VD_REG_SET_CODERATE__A
, EC_VD_REG_SET_CODERATE_C3_4
, 0x0000);
2280 transmissionParams
|= SC_RA_RAM_OP_PARAM_RATE_5_6
;
2282 status
= Write16(state
, EC_VD_REG_SET_CODERATE__A
, EC_VD_REG_SET_CODERATE_C5_6
, 0x0000);
2285 transmissionParams
|= SC_RA_RAM_OP_PARAM_RATE_7_8
;
2287 status
= Write16(state
, EC_VD_REG_SET_CODERATE__A
, EC_VD_REG_SET_CODERATE_C7_8
, 0x0000);
2293 /* First determine real bandwidth (Hz) */
2294 /* Also set delay for impulse noise cruncher (only A2) */
2295 /* Also set parameters for EC_OC fix, note
2296 EC_OC_REG_TMD_HIL_MAR is changed
2297 by SC for fix for some 8K,1/8 guard but is restored by
2300 switch (p
->bandwidth_hz
) {
2302 p
->bandwidth_hz
= 8000000;
2305 /* (64/7)*(8/8)*1000000 */
2306 bandwidth
= DRXD_BANDWIDTH_8MHZ_IN_HZ
;
2309 status
= Write16(state
,
2310 FE_AG_REG_IND_DEL__A
, 50, 0x0000);
2313 /* (64/7)*(7/8)*1000000 */
2314 bandwidth
= DRXD_BANDWIDTH_7MHZ_IN_HZ
;
2315 bandwidthParam
= 0x4807; /*binary:0100 1000 0000 0111 */
2316 status
= Write16(state
,
2317 FE_AG_REG_IND_DEL__A
, 59, 0x0000);
2320 /* (64/7)*(6/8)*1000000 */
2321 bandwidth
= DRXD_BANDWIDTH_6MHZ_IN_HZ
;
2322 bandwidthParam
= 0x0F07; /*binary: 0000 1111 0000 0111 */
2323 status
= Write16(state
,
2324 FE_AG_REG_IND_DEL__A
, 71, 0x0000);
2332 status
= Write16(state
, SC_RA_RAM_BAND__A
, bandwidthParam
, 0x0000);
2338 status
= Read16(state
, SC_RA_RAM_CONFIG__A
, &sc_config
, 0);
2342 /* enable SLAVE mode in 2k 1/32 to
2343 prevent timing change glitches */
2344 if ((p
->transmission_mode
== TRANSMISSION_MODE_2K
) &&
2345 (p
->guard_interval
== GUARD_INTERVAL_1_32
)) {
2347 sc_config
|= SC_RA_RAM_CONFIG_SLAVE__M
;
2350 sc_config
&= ~SC_RA_RAM_CONFIG_SLAVE__M
;
2352 status
= Write16(state
, SC_RA_RAM_CONFIG__A
, sc_config
, 0);
2357 status
= SetCfgNoiseCalibration(state
, &state
->noise_cal
);
2361 if (state
->cscd_state
== CSCD_INIT
) {
2362 /* switch on SRMM scan in SC */
2363 status
= Write16(state
, SC_RA_RAM_SAMPLE_RATE_COUNT__A
, DRXD_OSCDEV_DO_SCAN
, 0x0000);
2366 /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2367 state
->cscd_state
= CSCD_SET
;
2370 /* Now compute FE_IF_REG_INCR */
2371 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2372 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2373 feIfIncr
= MulDiv32(state
->sys_clock_freq
* 1000,
2374 (1ULL << 21), bandwidth
) - (1 << 23);
2375 status
= Write16(state
, FE_IF_REG_INCR0__A
, (u16
) (feIfIncr
& FE_IF_REG_INCR0__M
), 0x0000);
2378 status
= Write16(state
, FE_IF_REG_INCR1__A
, (u16
) ((feIfIncr
>> FE_IF_REG_INCR0__W
) & FE_IF_REG_INCR1__M
), 0x0000);
2381 /* Bandwidth setting done */
2383 /* Mirror & frequency offset */
2384 SetFrequencyShift(state
, off
, mirrorFreqSpect
);
2386 /* Start SC, write channel settings to SC */
2388 /* Enable SC after setting all other parameters */
2389 status
= Write16(state
, SC_COMM_STATE__A
, 0, 0x0000);
2392 status
= Write16(state
, SC_COMM_EXEC__A
, 1, 0x0000);
2396 /* Write SC parameter registers, operation mode */
2398 operationMode
= (SC_RA_RAM_OP_AUTO_MODE__M
|
2399 SC_RA_RAM_OP_AUTO_GUARD__M
|
2400 SC_RA_RAM_OP_AUTO_CONST__M
|
2401 SC_RA_RAM_OP_AUTO_HIER__M
|
2402 SC_RA_RAM_OP_AUTO_RATE__M
);
2404 status
= SC_SetPrefParamCommand(state
, 0x0000, transmissionParams
, operationMode
);
2408 /* Start correct processes to get in lock */
2409 status
= SC_ProcStartCommand(state
, SC_RA_RAM_PROC_LOCKTRACK
, SC_RA_RAM_SW_EVENT_RUN_NMASK__M
, SC_RA_RAM_LOCKTRACK_MIN
);
2413 status
= StartOC(state
);
2417 if (state
->operation_mode
!= OM_Default
) {
2418 status
= StartDiversity(state
);
2423 state
->drxd_state
= DRXD_STARTED
;
2429 static int CDRXD(struct drxd_state
*state
, u32 IntermediateFrequency
)
2431 u32 ulRfAgcOutputLevel
= 0xffffffff;
2432 u32 ulRfAgcSettleLevel
= 528; /* Optimum value for MT2060 */
2433 u32 ulRfAgcMinLevel
= 0; /* Currently unused */
2434 u32 ulRfAgcMaxLevel
= DRXD_FE_CTRL_MAX
; /* Currently unused */
2435 u32 ulRfAgcSpeed
= 0; /* Currently unused */
2436 u32 ulRfAgcMode
= 0; /*2; Off */
2437 u32 ulRfAgcR1
= 820;
2438 u32 ulRfAgcR2
= 2200;
2439 u32 ulRfAgcR3
= 150;
2440 u32 ulIfAgcMode
= 0; /* Auto */
2441 u32 ulIfAgcOutputLevel
= 0xffffffff;
2442 u32 ulIfAgcSettleLevel
= 0xffffffff;
2443 u32 ulIfAgcMinLevel
= 0xffffffff;
2444 u32 ulIfAgcMaxLevel
= 0xffffffff;
2445 u32 ulIfAgcSpeed
= 0xffffffff;
2446 u32 ulIfAgcR1
= 820;
2447 u32 ulIfAgcR2
= 2200;
2448 u32 ulIfAgcR3
= 150;
2449 u32 ulClock
= state
->config
.clock
;
2450 u32 ulSerialMode
= 0;
2451 u32 ulEcOcRegOcModeLop
= 4; /* Dynamic DTO source */
2452 u32 ulHiI2cDelay
= HI_I2C_DELAY
;
2453 u32 ulHiI2cBridgeDelay
= HI_I2C_BRIDGE_DELAY
;
2454 u32 ulHiI2cPatch
= 0;
2455 u32 ulEnvironment
= APPENV_PORTABLE
;
2456 u32 ulEnvironmentDiversity
= APPENV_MOBILE
;
2457 u32 ulIFFilter
= IFFILTER_SAW
;
2459 state
->if_agc_cfg
.ctrlMode
= AGC_CTRL_AUTO
;
2460 state
->if_agc_cfg
.outputLevel
= 0;
2461 state
->if_agc_cfg
.settleLevel
= 140;
2462 state
->if_agc_cfg
.minOutputLevel
= 0;
2463 state
->if_agc_cfg
.maxOutputLevel
= 1023;
2464 state
->if_agc_cfg
.speed
= 904;
2466 if (ulIfAgcMode
== 1 && ulIfAgcOutputLevel
<= DRXD_FE_CTRL_MAX
) {
2467 state
->if_agc_cfg
.ctrlMode
= AGC_CTRL_USER
;
2468 state
->if_agc_cfg
.outputLevel
= (u16
) (ulIfAgcOutputLevel
);
2471 if (ulIfAgcMode
== 0 &&
2472 ulIfAgcSettleLevel
<= DRXD_FE_CTRL_MAX
&&
2473 ulIfAgcMinLevel
<= DRXD_FE_CTRL_MAX
&&
2474 ulIfAgcMaxLevel
<= DRXD_FE_CTRL_MAX
&&
2475 ulIfAgcSpeed
<= DRXD_FE_CTRL_MAX
) {
2476 state
->if_agc_cfg
.ctrlMode
= AGC_CTRL_AUTO
;
2477 state
->if_agc_cfg
.settleLevel
= (u16
) (ulIfAgcSettleLevel
);
2478 state
->if_agc_cfg
.minOutputLevel
= (u16
) (ulIfAgcMinLevel
);
2479 state
->if_agc_cfg
.maxOutputLevel
= (u16
) (ulIfAgcMaxLevel
);
2480 state
->if_agc_cfg
.speed
= (u16
) (ulIfAgcSpeed
);
2483 state
->if_agc_cfg
.R1
= (u16
) (ulIfAgcR1
);
2484 state
->if_agc_cfg
.R2
= (u16
) (ulIfAgcR2
);
2485 state
->if_agc_cfg
.R3
= (u16
) (ulIfAgcR3
);
2487 state
->rf_agc_cfg
.R1
= (u16
) (ulRfAgcR1
);
2488 state
->rf_agc_cfg
.R2
= (u16
) (ulRfAgcR2
);
2489 state
->rf_agc_cfg
.R3
= (u16
) (ulRfAgcR3
);
2491 state
->rf_agc_cfg
.ctrlMode
= AGC_CTRL_AUTO
;
2492 /* rest of the RFAgcCfg structure currently unused */
2493 if (ulRfAgcMode
== 1 && ulRfAgcOutputLevel
<= DRXD_FE_CTRL_MAX
) {
2494 state
->rf_agc_cfg
.ctrlMode
= AGC_CTRL_USER
;
2495 state
->rf_agc_cfg
.outputLevel
= (u16
) (ulRfAgcOutputLevel
);
2498 if (ulRfAgcMode
== 0 &&
2499 ulRfAgcSettleLevel
<= DRXD_FE_CTRL_MAX
&&
2500 ulRfAgcMinLevel
<= DRXD_FE_CTRL_MAX
&&
2501 ulRfAgcMaxLevel
<= DRXD_FE_CTRL_MAX
&&
2502 ulRfAgcSpeed
<= DRXD_FE_CTRL_MAX
) {
2503 state
->rf_agc_cfg
.ctrlMode
= AGC_CTRL_AUTO
;
2504 state
->rf_agc_cfg
.settleLevel
= (u16
) (ulRfAgcSettleLevel
);
2505 state
->rf_agc_cfg
.minOutputLevel
= (u16
) (ulRfAgcMinLevel
);
2506 state
->rf_agc_cfg
.maxOutputLevel
= (u16
) (ulRfAgcMaxLevel
);
2507 state
->rf_agc_cfg
.speed
= (u16
) (ulRfAgcSpeed
);
2510 if (ulRfAgcMode
== 2)
2511 state
->rf_agc_cfg
.ctrlMode
= AGC_CTRL_OFF
;
2513 if (ulEnvironment
<= 2)
2514 state
->app_env_default
= (enum app_env
)
2516 if (ulEnvironmentDiversity
<= 2)
2517 state
->app_env_diversity
= (enum app_env
)
2518 (ulEnvironmentDiversity
);
2520 if (ulIFFilter
== IFFILTER_DISCRETE
) {
2521 /* discrete filter */
2522 state
->noise_cal
.cpOpt
= 0;
2523 state
->noise_cal
.cpNexpOfs
= 40;
2524 state
->noise_cal
.tdCal2k
= -40;
2525 state
->noise_cal
.tdCal8k
= -24;
2528 state
->noise_cal
.cpOpt
= 1;
2529 state
->noise_cal
.cpNexpOfs
= 0;
2530 state
->noise_cal
.tdCal2k
= -21;
2531 state
->noise_cal
.tdCal8k
= -24;
2533 state
->m_EcOcRegOcModeLop
= (u16
) (ulEcOcRegOcModeLop
);
2535 state
->chip_adr
= (state
->config
.demod_address
<< 1) | 1;
2536 switch (ulHiI2cPatch
) {
2538 state
->m_HiI2cPatch
= DRXD_HiI2cPatch_1
;
2541 state
->m_HiI2cPatch
= DRXD_HiI2cPatch_3
;
2544 state
->m_HiI2cPatch
= NULL
;
2547 /* modify tuner and clock attributes */
2548 state
->intermediate_freq
= (u16
) (IntermediateFrequency
/ 1000);
2549 /* expected system clock frequency in kHz */
2550 state
->expected_sys_clock_freq
= 48000;
2551 /* real system clock frequency in kHz */
2552 state
->sys_clock_freq
= 48000;
2553 state
->osc_clock_freq
= (u16
) ulClock
;
2554 state
->osc_clock_deviation
= 0;
2555 state
->cscd_state
= CSCD_INIT
;
2556 state
->drxd_state
= DRXD_UNINITIALIZED
;
2560 state
->tuner_mirrors
= 0;
2562 /* modify MPEG output attributes */
2563 state
->insert_rs_byte
= state
->config
.insert_rs_byte
;
2564 state
->enable_parallel
= (ulSerialMode
!= 1);
2566 /* Timing div, 250ns/Psys */
2567 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2569 state
->hi_cfg_timing_div
= (u16
) ((state
->sys_clock_freq
/ 1000) *
2570 ulHiI2cDelay
) / 1000;
2571 /* Bridge delay, uses oscilator clock */
2572 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2573 state
->hi_cfg_bridge_delay
= (u16
) ((state
->osc_clock_freq
/ 1000) *
2574 ulHiI2cBridgeDelay
) / 1000;
2576 state
->m_FeAgRegAgPwd
= DRXD_DEF_AG_PWD_CONSUMER
;
2577 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2578 state
->m_FeAgRegAgAgcSio
= DRXD_DEF_AG_AGC_SIO
;
2582 static int DRXD_init(struct drxd_state
*state
, const u8
*fw
, u32 fw_size
)
2587 if (state
->init_done
)
2590 CDRXD(state
, state
->config
.IF
? state
->config
.IF
: 36000000);
2593 state
->operation_mode
= OM_Default
;
2595 status
= SetDeviceTypeId(state
);
2599 /* Apply I2c address patch to B1 */
2600 if (!state
->type_A
&& state
->m_HiI2cPatch
) {
2601 status
= WriteTable(state
, state
->m_HiI2cPatch
);
2606 if (state
->type_A
) {
2607 /* HI firmware patch for UIO readout,
2608 avoid clearing of result register */
2609 status
= Write16(state
, 0x43012D, 0x047f, 0);
2614 status
= HI_ResetCommand(state
);
2618 status
= StopAllProcessors(state
);
2621 status
= InitCC(state
);
2625 state
->osc_clock_deviation
= 0;
2627 if (state
->config
.osc_deviation
)
2628 state
->osc_clock_deviation
=
2629 state
->config
.osc_deviation(state
->priv
, 0, 0);
2631 /* Handle clock deviation */
2633 s32 devA
= (s32
) (state
->osc_clock_deviation
) *
2634 (s32
) (state
->expected_sys_clock_freq
);
2635 /* deviation in kHz */
2636 s32 deviation
= (devA
/ (1000000L));
2637 /* rounding, signed */
2642 if ((devB
* (devA
% 1000000L) > 1000000L)) {
2644 deviation
+= (devB
/ 2);
2647 state
->sys_clock_freq
=
2648 (u16
) ((state
->expected_sys_clock_freq
) +
2651 status
= InitHI(state
);
2654 status
= InitAtomicRead(state
);
2658 status
= EnableAndResetMB(state
);
2661 if (state
->type_A
) {
2662 status
= ResetCEFR(state
);
2667 status
= DownloadMicrocode(state
, fw
, fw_size
);
2671 status
= DownloadMicrocode(state
, state
->microcode
, state
->microcode_length
);
2677 state
->m_FeAgRegAgPwd
= DRXD_DEF_AG_PWD_PRO
;
2678 SetCfgPga(state
, 0); /* PGA = 0 dB */
2680 state
->m_FeAgRegAgPwd
= DRXD_DEF_AG_PWD_CONSUMER
;
2683 state
->m_FeAgRegAgAgcSio
= DRXD_DEF_AG_AGC_SIO
;
2685 status
= InitFE(state
);
2688 status
= InitFT(state
);
2691 status
= InitCP(state
);
2694 status
= InitCE(state
);
2697 status
= InitEQ(state
);
2700 status
= InitEC(state
);
2703 status
= InitSC(state
);
2707 status
= SetCfgIfAgc(state
, &state
->if_agc_cfg
);
2710 status
= SetCfgRfAgc(state
, &state
->rf_agc_cfg
);
2714 state
->cscd_state
= CSCD_INIT
;
2715 status
= Write16(state
, SC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
2718 status
= Write16(state
, LC_COMM_EXEC__A
, SC_COMM_EXEC_CTL_STOP
, 0);
2722 driverVersion
= (((VERSION_MAJOR
/ 10) << 4) +
2723 (VERSION_MAJOR
% 10)) << 24;
2724 driverVersion
+= (((VERSION_MINOR
/ 10) << 4) +
2725 (VERSION_MINOR
% 10)) << 16;
2726 driverVersion
+= ((VERSION_PATCH
/ 1000) << 12) +
2727 ((VERSION_PATCH
/ 100) << 8) +
2728 ((VERSION_PATCH
/ 10) << 4) + (VERSION_PATCH
% 10);
2730 status
= Write32(state
, SC_RA_RAM_DRIVER_VERSION__AX
, driverVersion
, 0);
2734 status
= StopOC(state
);
2738 state
->drxd_state
= DRXD_STOPPED
;
2739 state
->init_done
= 1;
2745 static int DRXD_status(struct drxd_state
*state
, u32
*pLockStatus
)
2747 DRX_GetLockStatus(state
, pLockStatus
);
2749 /*if (*pLockStatus&DRX_LOCK_MPEG) */
2750 if (*pLockStatus
& DRX_LOCK_FEC
) {
2751 ConfigureMPEGOutput(state
, 1);
2752 /* Get status again, in case we have MPEG lock now */
2753 /*DRX_GetLockStatus(state, pLockStatus); */
2759 /****************************************************************************/
2760 /****************************************************************************/
2761 /****************************************************************************/
2763 static int drxd_read_signal_strength(struct dvb_frontend
*fe
, u16
* strength
)
2765 struct drxd_state
*state
= fe
->demodulator_priv
;
2769 res
= ReadIFAgc(state
, &value
);
2773 *strength
= 0xffff - (value
<< 4);
2777 static int drxd_read_status(struct dvb_frontend
*fe
, enum fe_status
*status
)
2779 struct drxd_state
*state
= fe
->demodulator_priv
;
2782 DRXD_status(state
, &lock
);
2784 /* No MPEG lock in V255 firmware, bug ? */
2786 if (lock
& DRX_LOCK_MPEG
)
2787 *status
|= FE_HAS_LOCK
;
2789 if (lock
& DRX_LOCK_FEC
)
2790 *status
|= FE_HAS_LOCK
;
2792 if (lock
& DRX_LOCK_FEC
)
2793 *status
|= FE_HAS_VITERBI
| FE_HAS_SYNC
;
2794 if (lock
& DRX_LOCK_DEMOD
)
2795 *status
|= FE_HAS_CARRIER
| FE_HAS_SIGNAL
;
2800 static int drxd_init(struct dvb_frontend
*fe
)
2802 struct drxd_state
*state
= fe
->demodulator_priv
;
2804 return DRXD_init(state
, NULL
, 0);
2807 static int drxd_config_i2c(struct dvb_frontend
*fe
, int onoff
)
2809 struct drxd_state
*state
= fe
->demodulator_priv
;
2811 if (state
->config
.disable_i2c_gate_ctrl
== 1)
2814 return DRX_ConfigureI2CBridge(state
, onoff
);
2817 static int drxd_get_tune_settings(struct dvb_frontend
*fe
,
2818 struct dvb_frontend_tune_settings
*sets
)
2820 sets
->min_delay_ms
= 10000;
2821 sets
->max_drift
= 0;
2822 sets
->step_size
= 0;
2826 static int drxd_read_ber(struct dvb_frontend
*fe
, u32
* ber
)
2832 static int drxd_read_snr(struct dvb_frontend
*fe
, u16
* snr
)
2838 static int drxd_read_ucblocks(struct dvb_frontend
*fe
, u32
* ucblocks
)
2844 static int drxd_sleep(struct dvb_frontend
*fe
)
2846 struct drxd_state
*state
= fe
->demodulator_priv
;
2848 ConfigureMPEGOutput(state
, 0);
2852 static int drxd_i2c_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
2854 return drxd_config_i2c(fe
, enable
);
2857 static int drxd_set_frontend(struct dvb_frontend
*fe
)
2859 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
2860 struct drxd_state
*state
= fe
->demodulator_priv
;
2866 if (fe
->ops
.tuner_ops
.set_params
) {
2867 fe
->ops
.tuner_ops
.set_params(fe
);
2868 if (fe
->ops
.i2c_gate_ctrl
)
2869 fe
->ops
.i2c_gate_ctrl(fe
, 0);
2874 return DRX_Start(state
, off
);
2877 static void drxd_release(struct dvb_frontend
*fe
)
2879 struct drxd_state
*state
= fe
->demodulator_priv
;
2884 static const struct dvb_frontend_ops drxd_ops
= {
2885 .delsys
= { SYS_DVBT
},
2887 .name
= "Micronas DRXD DVB-T",
2888 .frequency_min_hz
= 47125 * kHz
,
2889 .frequency_max_hz
= 855250 * kHz
,
2890 .frequency_stepsize_hz
= 166667,
2891 .caps
= FE_CAN_FEC_1_2
| FE_CAN_FEC_2_3
|
2892 FE_CAN_FEC_3_4
| FE_CAN_FEC_5_6
| FE_CAN_FEC_7_8
|
2894 FE_CAN_QAM_16
| FE_CAN_QAM_64
|
2896 FE_CAN_TRANSMISSION_MODE_AUTO
|
2897 FE_CAN_GUARD_INTERVAL_AUTO
|
2898 FE_CAN_HIERARCHY_AUTO
| FE_CAN_RECOVER
| FE_CAN_MUTE_TS
},
2900 .release
= drxd_release
,
2902 .sleep
= drxd_sleep
,
2903 .i2c_gate_ctrl
= drxd_i2c_gate_ctrl
,
2905 .set_frontend
= drxd_set_frontend
,
2906 .get_tune_settings
= drxd_get_tune_settings
,
2908 .read_status
= drxd_read_status
,
2909 .read_ber
= drxd_read_ber
,
2910 .read_signal_strength
= drxd_read_signal_strength
,
2911 .read_snr
= drxd_read_snr
,
2912 .read_ucblocks
= drxd_read_ucblocks
,
2915 struct dvb_frontend
*drxd_attach(const struct drxd_config
*config
,
2916 void *priv
, struct i2c_adapter
*i2c
,
2919 struct drxd_state
*state
= NULL
;
2921 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
2925 state
->ops
= drxd_ops
;
2927 state
->config
= *config
;
2931 mutex_init(&state
->mutex
);
2933 if (Read16(state
, 0, NULL
, 0) < 0)
2936 state
->frontend
.ops
= drxd_ops
;
2937 state
->frontend
.demodulator_priv
= state
;
2938 ConfigureMPEGOutput(state
, 0);
2939 /* add few initialization to allow gate control */
2940 CDRXD(state
, state
->config
.IF
? state
->config
.IF
: 36000000);
2943 return &state
->frontend
;
2946 printk(KERN_ERR
"drxd: not found\n");
2950 EXPORT_SYMBOL(drxd_attach
);
2952 MODULE_DESCRIPTION("DRXD driver");
2953 MODULE_AUTHOR("Micronas");
2954 MODULE_LICENSE("GPL");