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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / media / i2c / adv7842.c
blob0855f648416d1d2fcf511efe9afec582235781aa
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * adv7842 - Analog Devices ADV7842 video decoder driver
4 *
5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 */
7
8 /*
9 * References (c = chapter, p = page):
10 * REF_01 - Analog devices, ADV7842,
11 * Register Settings Recommendations, Rev. 1.9, April 2011
12 * REF_02 - Analog devices, Software User Guide, UG-206,
13 * ADV7842 I2C Register Maps, Rev. 0, November 2010
14 * REF_03 - Analog devices, Hardware User Guide, UG-214,
15 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
16 * Decoder and Digitizer , Rev. 0, January 2011
17 */
18
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/i2c.h>
24 #include <linux/delay.h>
25 #include <linux/videodev2.h>
26 #include <linux/workqueue.h>
27 #include <linux/v4l2-dv-timings.h>
28 #include <linux/hdmi.h>
29 #include <media/cec.h>
30 #include <media/v4l2-device.h>
31 #include <media/v4l2-event.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-dv-timings.h>
34 #include <media/i2c/adv7842.h>
35
36 static int debug;
37 module_param(debug, int, 0644);
38 MODULE_PARM_DESC(debug, "debug level (0-2)");
39
40 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
41 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
42 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
43 MODULE_LICENSE("GPL");
44
45 /* ADV7842 system clock frequency */
46 #define ADV7842_fsc (28636360)
47
48 #define ADV7842_RGB_OUT (1 << 1)
49
50 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
51 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
52 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
53
54 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
55 #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5)
56 #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5)
57 #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5)
58 #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5)
59 #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5)
60
61 #define ADV7842_OP_CH_SEL_GBR (0 << 5)
62 #define ADV7842_OP_CH_SEL_GRB (1 << 5)
63 #define ADV7842_OP_CH_SEL_BGR (2 << 5)
64 #define ADV7842_OP_CH_SEL_RGB (3 << 5)
65 #define ADV7842_OP_CH_SEL_BRG (4 << 5)
66 #define ADV7842_OP_CH_SEL_RBG (5 << 5)
67
68 #define ADV7842_OP_SWAP_CB_CR (1 << 0)
69
70 #define ADV7842_MAX_ADDRS (3)
71
72 /*
73 **********************************************************************
74 *
75 * Arrays with configuration parameters for the ADV7842
76 *
77 **********************************************************************
78 */
79
80 struct adv7842_format_info {
81 u32 code;
82 u8 op_ch_sel;
83 bool rgb_out;
84 bool swap_cb_cr;
85 u8 op_format_sel;
86 };
87
88 struct adv7842_state {
89 struct adv7842_platform_data pdata;
90 struct v4l2_subdev sd;
91 struct media_pad pad;
92 struct v4l2_ctrl_handler hdl;
93 enum adv7842_mode mode;
94 struct v4l2_dv_timings timings;
95 enum adv7842_vid_std_select vid_std_select;
96
97 const struct adv7842_format_info *format;
98
99 v4l2_std_id norm;
100 struct {
101 u8 edid[256];
102 u32 present;
103 } hdmi_edid;
104 struct {
105 u8 edid[256];
106 u32 present;
107 } vga_edid;
108 struct v4l2_fract aspect_ratio;
109 u32 rgb_quantization_range;
110 bool is_cea_format;
111 struct delayed_work delayed_work_enable_hotplug;
112 bool restart_stdi_once;
113 bool hdmi_port_a;
114
115 /* i2c clients */
116 struct i2c_client *i2c_sdp_io;
117 struct i2c_client *i2c_sdp;
118 struct i2c_client *i2c_cp;
119 struct i2c_client *i2c_vdp;
120 struct i2c_client *i2c_afe;
121 struct i2c_client *i2c_hdmi;
122 struct i2c_client *i2c_repeater;
123 struct i2c_client *i2c_edid;
124 struct i2c_client *i2c_infoframe;
125 struct i2c_client *i2c_cec;
126 struct i2c_client *i2c_avlink;
127
128 /* controls */
129 struct v4l2_ctrl *detect_tx_5v_ctrl;
130 struct v4l2_ctrl *analog_sampling_phase_ctrl;
131 struct v4l2_ctrl *free_run_color_ctrl_manual;
132 struct v4l2_ctrl *free_run_color_ctrl;
133 struct v4l2_ctrl *rgb_quantization_range_ctrl;
134
135 struct cec_adapter *cec_adap;
136 u8 cec_addr[ADV7842_MAX_ADDRS];
137 u8 cec_valid_addrs;
138 bool cec_enabled_adap;
139 };
140
141 /* Unsupported timings. This device cannot support 720p30. */
142 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
143 V4L2_DV_BT_CEA_1280X720P30,
144 { }
145 };
146
147 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
148 {
149 int i;
150
151 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
152 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false))
153 return false;
154 return true;
155 }
156
157 struct adv7842_video_standards {
158 struct v4l2_dv_timings timings;
159 u8 vid_std;
160 u8 v_freq;
161 };
162
163 /* sorted by number of lines */
164 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
165 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
166 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
167 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
168 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
169 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
170 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
171 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
172 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
173 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
174 /* TODO add 1920x1080P60_RB (CVT timing) */
175 { },
176 };
177
178 /* sorted by number of lines */
179 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
180 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
181 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
182 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
183 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
184 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
185 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
186 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
187 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
188 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
189 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
190 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
191 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
192 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
193 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
194 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
195 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
196 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
197 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
198 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
199 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
200 /* TODO add 1600X1200P60_RB (not a DMT timing) */
201 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
202 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
203 { },
204 };
205
206 /* sorted by number of lines */
207 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
208 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
209 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
210 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
211 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
212 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
213 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
214 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
215 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
216 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
217 { },
218 };
219
220 /* sorted by number of lines */
221 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
222 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
223 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
224 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
225 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
226 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
227 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
228 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
229 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
230 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
231 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
232 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
233 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
234 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
235 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
236 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
237 { },
238 };
239
240 static const struct v4l2_event adv7842_ev_fmt = {
241 .type = V4L2_EVENT_SOURCE_CHANGE,
242 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
243 };
244
245 /* ----------------------------------------------------------------------- */
246
247 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
248 {
249 return container_of(sd, struct adv7842_state, sd);
250 }
251
252 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
253 {
254 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
255 }
256
257 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
258 {
259 return V4L2_DV_BT_BLANKING_WIDTH(t);
260 }
261
262 static inline unsigned htotal(const struct v4l2_bt_timings *t)
263 {
264 return V4L2_DV_BT_FRAME_WIDTH(t);
265 }
266
267 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
268 {
269 return V4L2_DV_BT_BLANKING_HEIGHT(t);
270 }
271
272 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
273 {
274 return V4L2_DV_BT_FRAME_HEIGHT(t);
275 }
276
277
278 /* ----------------------------------------------------------------------- */
279
280 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
281 u8 command, bool check)
282 {
283 union i2c_smbus_data data;
284
285 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
286 I2C_SMBUS_READ, command,
287 I2C_SMBUS_BYTE_DATA, &data))
288 return data.byte;
289 if (check)
290 v4l_err(client, "error reading %02x, %02x\n",
291 client->addr, command);
292 return -EIO;
293 }
294
295 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
296 {
297 int i;
298
299 for (i = 0; i < 3; i++) {
300 int ret = adv_smbus_read_byte_data_check(client, command, true);
301
302 if (ret >= 0) {
303 if (i)
304 v4l_err(client, "read ok after %d retries\n", i);
305 return ret;
306 }
307 }
308 v4l_err(client, "read failed\n");
309 return -EIO;
310 }
311
312 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
313 u8 command, u8 value)
314 {
315 union i2c_smbus_data data;
316 int err;
317 int i;
318
319 data.byte = value;
320 for (i = 0; i < 3; i++) {
321 err = i2c_smbus_xfer(client->adapter, client->addr,
322 client->flags,
323 I2C_SMBUS_WRITE, command,
324 I2C_SMBUS_BYTE_DATA, &data);
325 if (!err)
326 break;
327 }
328 if (err < 0)
329 v4l_err(client, "error writing %02x, %02x, %02x\n",
330 client->addr, command, value);
331 return err;
332 }
333
334 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
335 u8 command, u8 value)
336 {
337 union i2c_smbus_data data;
338 data.byte = value;
339
340 i2c_smbus_xfer(client->adapter, client->addr,
341 client->flags,
342 I2C_SMBUS_WRITE, command,
343 I2C_SMBUS_BYTE_DATA, &data);
344 }
345
346 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
347 u8 command, unsigned length, const u8 *values)
348 {
349 union i2c_smbus_data data;
350
351 if (length > I2C_SMBUS_BLOCK_MAX)
352 length = I2C_SMBUS_BLOCK_MAX;
353 data.block[0] = length;
354 memcpy(data.block + 1, values, length);
355 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
356 I2C_SMBUS_WRITE, command,
357 I2C_SMBUS_I2C_BLOCK_DATA, &data);
358 }
359
360 /* ----------------------------------------------------------------------- */
361
362 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
363 {
364 struct i2c_client *client = v4l2_get_subdevdata(sd);
365
366 return adv_smbus_read_byte_data(client, reg);
367 }
368
369 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
370 {
371 struct i2c_client *client = v4l2_get_subdevdata(sd);
372
373 return adv_smbus_write_byte_data(client, reg, val);
374 }
375
376 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
377 {
378 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
379 }
380
381 static inline int io_write_clr_set(struct v4l2_subdev *sd,
382 u8 reg, u8 mask, u8 val)
383 {
384 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
385 }
386
387 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
388 {
389 struct adv7842_state *state = to_state(sd);
390
391 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
392 }
393
394 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
395 {
396 struct adv7842_state *state = to_state(sd);
397
398 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
399 }
400
401 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
402 {
403 struct adv7842_state *state = to_state(sd);
404
405 return adv_smbus_read_byte_data(state->i2c_cec, reg);
406 }
407
408 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
409 {
410 struct adv7842_state *state = to_state(sd);
411
412 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
413 }
414
415 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
416 {
417 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
418 }
419
420 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
421 {
422 struct adv7842_state *state = to_state(sd);
423
424 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
425 }
426
427 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
428 {
429 struct adv7842_state *state = to_state(sd);
430
431 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
432 }
433
434 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
435 {
436 struct adv7842_state *state = to_state(sd);
437
438 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
439 }
440
441 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
442 {
443 struct adv7842_state *state = to_state(sd);
444
445 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
446 }
447
448 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
449 {
450 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
451 }
452
453 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
454 {
455 struct adv7842_state *state = to_state(sd);
456
457 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
458 }
459
460 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
461 {
462 struct adv7842_state *state = to_state(sd);
463
464 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
465 }
466
467 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
468 {
469 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
470 }
471
472 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
473 {
474 struct adv7842_state *state = to_state(sd);
475
476 return adv_smbus_read_byte_data(state->i2c_afe, reg);
477 }
478
479 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
480 {
481 struct adv7842_state *state = to_state(sd);
482
483 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
484 }
485
486 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
487 {
488 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
489 }
490
491 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
492 {
493 struct adv7842_state *state = to_state(sd);
494
495 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
496 }
497
498 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
499 {
500 struct adv7842_state *state = to_state(sd);
501
502 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
503 }
504
505 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
506 {
507 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
508 }
509
510 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
511 {
512 struct adv7842_state *state = to_state(sd);
513
514 return adv_smbus_read_byte_data(state->i2c_edid, reg);
515 }
516
517 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
518 {
519 struct adv7842_state *state = to_state(sd);
520
521 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
522 }
523
524 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
525 {
526 struct adv7842_state *state = to_state(sd);
527
528 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
529 }
530
531 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
532 {
533 struct adv7842_state *state = to_state(sd);
534
535 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
536 }
537
538 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
539 {
540 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
541 }
542
543 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
544 {
545 struct adv7842_state *state = to_state(sd);
546
547 return adv_smbus_read_byte_data(state->i2c_cp, reg);
548 }
549
550 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
551 {
552 struct adv7842_state *state = to_state(sd);
553
554 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
555 }
556
557 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
558 {
559 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
560 }
561
562 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
563 {
564 struct adv7842_state *state = to_state(sd);
565
566 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
567 }
568
569 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
570 {
571 struct adv7842_state *state = to_state(sd);
572
573 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
574 }
575
576 static void main_reset(struct v4l2_subdev *sd)
577 {
578 struct i2c_client *client = v4l2_get_subdevdata(sd);
579
580 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
581
582 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
583
584 mdelay(5);
585 }
586
587 /* -----------------------------------------------------------------------------
588 * Format helpers
589 */
590
591 static const struct adv7842_format_info adv7842_formats[] = {
592 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false,
593 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT },
594 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false,
595 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
596 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true,
597 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
598 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false,
599 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
600 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true,
601 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
602 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false,
603 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
604 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true,
605 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
606 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false,
607 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
608 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true,
609 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
610 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false,
611 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
612 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true,
613 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
614 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false,
615 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
616 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true,
617 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
618 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false,
619 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
620 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true,
621 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
622 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false,
623 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
624 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true,
625 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
626 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false,
627 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
628 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true,
629 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
630 };
631
632 static const struct adv7842_format_info *
633 adv7842_format_info(struct adv7842_state *state, u32 code)
634 {
635 unsigned int i;
636
637 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) {
638 if (adv7842_formats[i].code == code)
639 return &adv7842_formats[i];
640 }
641
642 return NULL;
643 }
644
645 /* ----------------------------------------------------------------------- */
646
647 static inline bool is_analog_input(struct v4l2_subdev *sd)
648 {
649 struct adv7842_state *state = to_state(sd);
650
651 return ((state->mode == ADV7842_MODE_RGB) ||
652 (state->mode == ADV7842_MODE_COMP));
653 }
654
655 static inline bool is_digital_input(struct v4l2_subdev *sd)
656 {
657 struct adv7842_state *state = to_state(sd);
658
659 return state->mode == ADV7842_MODE_HDMI;
660 }
661
662 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
663 .type = V4L2_DV_BT_656_1120,
664 /* keep this initialization for compatibility with GCC < 4.4.6 */
665 .reserved = { 0 },
666 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
667 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
668 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
669 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
670 V4L2_DV_BT_CAP_CUSTOM)
671 };
672
673 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
674 .type = V4L2_DV_BT_656_1120,
675 /* keep this initialization for compatibility with GCC < 4.4.6 */
676 .reserved = { 0 },
677 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
678 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
679 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
680 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
681 V4L2_DV_BT_CAP_CUSTOM)
682 };
683
684 static inline const struct v4l2_dv_timings_cap *
685 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
686 {
687 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
688 &adv7842_timings_cap_analog;
689 }
690
691 /* ----------------------------------------------------------------------- */
692
693 static u16 adv7842_read_cable_det(struct v4l2_subdev *sd)
694 {
695 u8 reg = io_read(sd, 0x6f);
696 u16 val = 0;
697
698 if (reg & 0x02)
699 val |= 1; /* port A */
700 if (reg & 0x01)
701 val |= 2; /* port B */
702 return val;
703 }
704
705 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
706 {
707 struct delayed_work *dwork = to_delayed_work(work);
708 struct adv7842_state *state = container_of(dwork,
709 struct adv7842_state, delayed_work_enable_hotplug);
710 struct v4l2_subdev *sd = &state->sd;
711 int present = state->hdmi_edid.present;
712 u8 mask = 0;
713
714 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
715 __func__, present);
716
717 if (present & (0x04 << ADV7842_EDID_PORT_A))
718 mask |= 0x20;
719 if (present & (0x04 << ADV7842_EDID_PORT_B))
720 mask |= 0x10;
721 io_write_and_or(sd, 0x20, 0xcf, mask);
722 }
723
724 static int edid_write_vga_segment(struct v4l2_subdev *sd)
725 {
726 struct i2c_client *client = v4l2_get_subdevdata(sd);
727 struct adv7842_state *state = to_state(sd);
728 const u8 *val = state->vga_edid.edid;
729 int err = 0;
730 int i;
731
732 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
733
734 /* HPA disable on port A and B */
735 io_write_and_or(sd, 0x20, 0xcf, 0x00);
736
737 /* Disable I2C access to internal EDID ram from VGA DDC port */
738 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
739
740 /* edid segment pointer '1' for VGA port */
741 rep_write_and_or(sd, 0x77, 0xef, 0x10);
742
743 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
744 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
745 I2C_SMBUS_BLOCK_MAX, val + i);
746 if (err)
747 return err;
748
749 /* Calculates the checksums and enables I2C access
750 * to internal EDID ram from VGA DDC port.
751 */
752 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
753
754 for (i = 0; i < 1000; i++) {
755 if (rep_read(sd, 0x79) & 0x20)
756 break;
757 mdelay(1);
758 }
759 if (i == 1000) {
760 v4l_err(client, "error enabling edid on VGA port\n");
761 return -EIO;
762 }
763
764 /* enable hotplug after 200 ms */
765 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
766
767 return 0;
768 }
769
770 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
771 {
772 struct i2c_client *client = v4l2_get_subdevdata(sd);
773 struct adv7842_state *state = to_state(sd);
774 const u8 *edid = state->hdmi_edid.edid;
775 int spa_loc;
776 u16 pa;
777 int err = 0;
778 int i;
779
780 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n",
781 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
782
783 /* HPA disable on port A and B */
784 io_write_and_or(sd, 0x20, 0xcf, 0x00);
785
786 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
787 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
788
789 if (!state->hdmi_edid.present) {
790 cec_phys_addr_invalidate(state->cec_adap);
791 return 0;
792 }
793
794 pa = v4l2_get_edid_phys_addr(edid, 256, &spa_loc);
795 err = v4l2_phys_addr_validate(pa, &pa, NULL);
796 if (err)
797 return err;
798
799 /*
800 * Return an error if no location of the source physical address
801 * was found.
802 */
803 if (spa_loc == 0)
804 return -EINVAL;
805
806 /* edid segment pointer '0' for HDMI ports */
807 rep_write_and_or(sd, 0x77, 0xef, 0x00);
808
809 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
810 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
811 I2C_SMBUS_BLOCK_MAX, edid + i);
812 if (err)
813 return err;
814
815 if (port == ADV7842_EDID_PORT_A) {
816 rep_write(sd, 0x72, edid[spa_loc]);
817 rep_write(sd, 0x73, edid[spa_loc + 1]);
818 } else {
819 rep_write(sd, 0x74, edid[spa_loc]);
820 rep_write(sd, 0x75, edid[spa_loc + 1]);
821 }
822 rep_write(sd, 0x76, spa_loc & 0xff);
823 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
824
825 /* Calculates the checksums and enables I2C access to internal
826 * EDID ram from HDMI DDC ports
827 */
828 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
829
830 for (i = 0; i < 1000; i++) {
831 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
832 break;
833 mdelay(1);
834 }
835 if (i == 1000) {
836 v4l_err(client, "error enabling edid on port %c\n",
837 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
838 return -EIO;
839 }
840 cec_s_phys_addr(state->cec_adap, pa, false);
841
842 /* enable hotplug after 200 ms */
843 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
844
845 return 0;
846 }
847
848 /* ----------------------------------------------------------------------- */
849
850 #ifdef CONFIG_VIDEO_ADV_DEBUG
851 static void adv7842_inv_register(struct v4l2_subdev *sd)
852 {
853 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
854 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
855 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
856 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
857 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
858 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
859 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
860 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
861 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
862 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
863 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
864 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
865 }
866
867 static int adv7842_g_register(struct v4l2_subdev *sd,
868 struct v4l2_dbg_register *reg)
869 {
870 reg->size = 1;
871 switch (reg->reg >> 8) {
872 case 0:
873 reg->val = io_read(sd, reg->reg & 0xff);
874 break;
875 case 1:
876 reg->val = avlink_read(sd, reg->reg & 0xff);
877 break;
878 case 2:
879 reg->val = cec_read(sd, reg->reg & 0xff);
880 break;
881 case 3:
882 reg->val = infoframe_read(sd, reg->reg & 0xff);
883 break;
884 case 4:
885 reg->val = sdp_io_read(sd, reg->reg & 0xff);
886 break;
887 case 5:
888 reg->val = sdp_read(sd, reg->reg & 0xff);
889 break;
890 case 6:
891 reg->val = afe_read(sd, reg->reg & 0xff);
892 break;
893 case 7:
894 reg->val = rep_read(sd, reg->reg & 0xff);
895 break;
896 case 8:
897 reg->val = edid_read(sd, reg->reg & 0xff);
898 break;
899 case 9:
900 reg->val = hdmi_read(sd, reg->reg & 0xff);
901 break;
902 case 0xa:
903 reg->val = cp_read(sd, reg->reg & 0xff);
904 break;
905 case 0xb:
906 reg->val = vdp_read(sd, reg->reg & 0xff);
907 break;
908 default:
909 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
910 adv7842_inv_register(sd);
911 break;
912 }
913 return 0;
914 }
915
916 static int adv7842_s_register(struct v4l2_subdev *sd,
917 const struct v4l2_dbg_register *reg)
918 {
919 u8 val = reg->val & 0xff;
920
921 switch (reg->reg >> 8) {
922 case 0:
923 io_write(sd, reg->reg & 0xff, val);
924 break;
925 case 1:
926 avlink_write(sd, reg->reg & 0xff, val);
927 break;
928 case 2:
929 cec_write(sd, reg->reg & 0xff, val);
930 break;
931 case 3:
932 infoframe_write(sd, reg->reg & 0xff, val);
933 break;
934 case 4:
935 sdp_io_write(sd, reg->reg & 0xff, val);
936 break;
937 case 5:
938 sdp_write(sd, reg->reg & 0xff, val);
939 break;
940 case 6:
941 afe_write(sd, reg->reg & 0xff, val);
942 break;
943 case 7:
944 rep_write(sd, reg->reg & 0xff, val);
945 break;
946 case 8:
947 edid_write(sd, reg->reg & 0xff, val);
948 break;
949 case 9:
950 hdmi_write(sd, reg->reg & 0xff, val);
951 break;
952 case 0xa:
953 cp_write(sd, reg->reg & 0xff, val);
954 break;
955 case 0xb:
956 vdp_write(sd, reg->reg & 0xff, val);
957 break;
958 default:
959 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
960 adv7842_inv_register(sd);
961 break;
962 }
963 return 0;
964 }
965 #endif
966
967 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
968 {
969 struct adv7842_state *state = to_state(sd);
970 u16 cable_det = adv7842_read_cable_det(sd);
971
972 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det);
973
974 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
975 }
976
977 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
978 u8 prim_mode,
979 const struct adv7842_video_standards *predef_vid_timings,
980 const struct v4l2_dv_timings *timings)
981 {
982 int i;
983
984 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
985 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
986 is_digital_input(sd) ? 250000 : 1000000, false))
987 continue;
988 /* video std */
989 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
990 /* v_freq and prim mode */
991 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
992 return 0;
993 }
994
995 return -1;
996 }
997
998 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
999 struct v4l2_dv_timings *timings)
1000 {
1001 struct adv7842_state *state = to_state(sd);
1002 int err;
1003
1004 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1005
1006 /* reset to default values */
1007 io_write(sd, 0x16, 0x43);
1008 io_write(sd, 0x17, 0x5a);
1009 /* disable embedded syncs for auto graphics mode */
1010 cp_write_and_or(sd, 0x81, 0xef, 0x00);
1011 cp_write(sd, 0x26, 0x00);
1012 cp_write(sd, 0x27, 0x00);
1013 cp_write(sd, 0x28, 0x00);
1014 cp_write(sd, 0x29, 0x00);
1015 cp_write(sd, 0x8f, 0x40);
1016 cp_write(sd, 0x90, 0x00);
1017 cp_write(sd, 0xa5, 0x00);
1018 cp_write(sd, 0xa6, 0x00);
1019 cp_write(sd, 0xa7, 0x00);
1020 cp_write(sd, 0xab, 0x00);
1021 cp_write(sd, 0xac, 0x00);
1022
1023 switch (state->mode) {
1024 case ADV7842_MODE_COMP:
1025 case ADV7842_MODE_RGB:
1026 err = find_and_set_predefined_video_timings(sd,
1027 0x01, adv7842_prim_mode_comp, timings);
1028 if (err)
1029 err = find_and_set_predefined_video_timings(sd,
1030 0x02, adv7842_prim_mode_gr, timings);
1031 break;
1032 case ADV7842_MODE_HDMI:
1033 err = find_and_set_predefined_video_timings(sd,
1034 0x05, adv7842_prim_mode_hdmi_comp, timings);
1035 if (err)
1036 err = find_and_set_predefined_video_timings(sd,
1037 0x06, adv7842_prim_mode_hdmi_gr, timings);
1038 break;
1039 default:
1040 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1041 __func__, state->mode);
1042 err = -1;
1043 break;
1044 }
1045
1046
1047 return err;
1048 }
1049
1050 static void configure_custom_video_timings(struct v4l2_subdev *sd,
1051 const struct v4l2_bt_timings *bt)
1052 {
1053 struct adv7842_state *state = to_state(sd);
1054 struct i2c_client *client = v4l2_get_subdevdata(sd);
1055 u32 width = htotal(bt);
1056 u32 height = vtotal(bt);
1057 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1058 u16 cp_start_eav = width - bt->hfrontporch;
1059 u16 cp_start_vbi = height - bt->vfrontporch + 1;
1060 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
1061 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1062 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1063 const u8 pll[2] = {
1064 0xc0 | ((width >> 8) & 0x1f),
1065 width & 0xff
1066 };
1067
1068 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1069
1070 switch (state->mode) {
1071 case ADV7842_MODE_COMP:
1072 case ADV7842_MODE_RGB:
1073 /* auto graphics */
1074 io_write(sd, 0x00, 0x07); /* video std */
1075 io_write(sd, 0x01, 0x02); /* prim mode */
1076 /* enable embedded syncs for auto graphics mode */
1077 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1078
1079 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1080 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1081 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1082 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
1083 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1084 break;
1085 }
1086
1087 /* active video - horizontal timing */
1088 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1089 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1090 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1091 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1092
1093 /* active video - vertical timing */
1094 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1095 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1096 ((cp_end_vbi >> 8) & 0xf));
1097 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1098 break;
1099 case ADV7842_MODE_HDMI:
1100 /* set default prim_mode/vid_std for HDMI
1101 according to [REF_03, c. 4.2] */
1102 io_write(sd, 0x00, 0x02); /* video std */
1103 io_write(sd, 0x01, 0x06); /* prim mode */
1104 break;
1105 default:
1106 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1107 __func__, state->mode);
1108 break;
1109 }
1110
1111 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1112 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1113 cp_write(sd, 0xab, (height >> 4) & 0xff);
1114 cp_write(sd, 0xac, (height & 0x0f) << 4);
1115 }
1116
1117 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1118 {
1119 struct adv7842_state *state = to_state(sd);
1120 u8 offset_buf[4];
1121
1122 if (auto_offset) {
1123 offset_a = 0x3ff;
1124 offset_b = 0x3ff;
1125 offset_c = 0x3ff;
1126 }
1127
1128 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1129 __func__, auto_offset ? "Auto" : "Manual",
1130 offset_a, offset_b, offset_c);
1131
1132 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1133 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1134 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1135 offset_buf[3] = offset_c & 0x0ff;
1136
1137 /* Registers must be written in this order with no i2c access in between */
1138 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
1139 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1140 }
1141
1142 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1143 {
1144 struct adv7842_state *state = to_state(sd);
1145 u8 gain_buf[4];
1146 u8 gain_man = 1;
1147 u8 agc_mode_man = 1;
1148
1149 if (auto_gain) {
1150 gain_man = 0;
1151 agc_mode_man = 0;
1152 gain_a = 0x100;
1153 gain_b = 0x100;
1154 gain_c = 0x100;
1155 }
1156
1157 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1158 __func__, auto_gain ? "Auto" : "Manual",
1159 gain_a, gain_b, gain_c);
1160
1161 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1162 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1163 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1164 gain_buf[3] = ((gain_c & 0x0ff));
1165
1166 /* Registers must be written in this order with no i2c access in between */
1167 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
1168 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1169 }
1170
1171 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1172 {
1173 struct adv7842_state *state = to_state(sd);
1174 bool rgb_output = io_read(sd, 0x02) & 0x02;
1175 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1176 u8 y = HDMI_COLORSPACE_RGB;
1177
1178 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1179 y = infoframe_read(sd, 0x01) >> 5;
1180
1181 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1182 __func__, state->rgb_quantization_range,
1183 rgb_output, hdmi_signal);
1184
1185 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1186 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
1187 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1188
1189 switch (state->rgb_quantization_range) {
1190 case V4L2_DV_RGB_RANGE_AUTO:
1191 if (state->mode == ADV7842_MODE_RGB) {
1192 /* Receiving analog RGB signal
1193 * Set RGB full range (0-255) */
1194 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1195 break;
1196 }
1197
1198 if (state->mode == ADV7842_MODE_COMP) {
1199 /* Receiving analog YPbPr signal
1200 * Set automode */
1201 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1202 break;
1203 }
1204
1205 if (hdmi_signal) {
1206 /* Receiving HDMI signal
1207 * Set automode */
1208 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1209 break;
1210 }
1211
1212 /* Receiving DVI-D signal
1213 * ADV7842 selects RGB limited range regardless of
1214 * input format (CE/IT) in automatic mode */
1215 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1216 /* RGB limited range (16-235) */
1217 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1218 } else {
1219 /* RGB full range (0-255) */
1220 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1221
1222 if (is_digital_input(sd) && rgb_output) {
1223 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1224 } else {
1225 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1226 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1227 }
1228 }
1229 break;
1230 case V4L2_DV_RGB_RANGE_LIMITED:
1231 if (state->mode == ADV7842_MODE_COMP) {
1232 /* YCrCb limited range (16-235) */
1233 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1234 break;
1235 }
1236
1237 if (y != HDMI_COLORSPACE_RGB)
1238 break;
1239
1240 /* RGB limited range (16-235) */
1241 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1242
1243 break;
1244 case V4L2_DV_RGB_RANGE_FULL:
1245 if (state->mode == ADV7842_MODE_COMP) {
1246 /* YCrCb full range (0-255) */
1247 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1248 break;
1249 }
1250
1251 if (y != HDMI_COLORSPACE_RGB)
1252 break;
1253
1254 /* RGB full range (0-255) */
1255 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1256
1257 if (is_analog_input(sd) || hdmi_signal)
1258 break;
1259
1260 /* Adjust gain/offset for DVI-D signals only */
1261 if (rgb_output) {
1262 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1263 } else {
1264 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1265 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1266 }
1267 break;
1268 }
1269 }
1270
1271 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1272 {
1273 struct v4l2_subdev *sd = to_sd(ctrl);
1274 struct adv7842_state *state = to_state(sd);
1275
1276 /* TODO SDP ctrls
1277 contrast/brightness/hue/free run is acting a bit strange,
1278 not sure if sdp csc is correct.
1279 */
1280 switch (ctrl->id) {
1281 /* standard ctrls */
1282 case V4L2_CID_BRIGHTNESS:
1283 cp_write(sd, 0x3c, ctrl->val);
1284 sdp_write(sd, 0x14, ctrl->val);
1285 /* ignore lsb sdp 0x17[3:2] */
1286 return 0;
1287 case V4L2_CID_CONTRAST:
1288 cp_write(sd, 0x3a, ctrl->val);
1289 sdp_write(sd, 0x13, ctrl->val);
1290 /* ignore lsb sdp 0x17[1:0] */
1291 return 0;
1292 case V4L2_CID_SATURATION:
1293 cp_write(sd, 0x3b, ctrl->val);
1294 sdp_write(sd, 0x15, ctrl->val);
1295 /* ignore lsb sdp 0x17[5:4] */
1296 return 0;
1297 case V4L2_CID_HUE:
1298 cp_write(sd, 0x3d, ctrl->val);
1299 sdp_write(sd, 0x16, ctrl->val);
1300 /* ignore lsb sdp 0x17[7:6] */
1301 return 0;
1302 /* custom ctrls */
1303 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1304 afe_write(sd, 0xc8, ctrl->val);
1305 return 0;
1306 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1307 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1308 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1309 return 0;
1310 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1311 u8 R = (ctrl->val & 0xff0000) >> 16;
1312 u8 G = (ctrl->val & 0x00ff00) >> 8;
1313 u8 B = (ctrl->val & 0x0000ff);
1314 /* RGB -> YUV, numerical approximation */
1315 int Y = 66 * R + 129 * G + 25 * B;
1316 int U = -38 * R - 74 * G + 112 * B;
1317 int V = 112 * R - 94 * G - 18 * B;
1318
1319 /* Scale down to 8 bits with rounding */
1320 Y = (Y + 128) >> 8;
1321 U = (U + 128) >> 8;
1322 V = (V + 128) >> 8;
1323 /* make U,V positive */
1324 Y += 16;
1325 U += 128;
1326 V += 128;
1327
1328 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1329 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1330
1331 /* CP */
1332 cp_write(sd, 0xc1, R);
1333 cp_write(sd, 0xc0, G);
1334 cp_write(sd, 0xc2, B);
1335 /* SDP */
1336 sdp_write(sd, 0xde, Y);
1337 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1338 return 0;
1339 }
1340 case V4L2_CID_DV_RX_RGB_RANGE:
1341 state->rgb_quantization_range = ctrl->val;
1342 set_rgb_quantization_range(sd);
1343 return 0;
1344 }
1345 return -EINVAL;
1346 }
1347
1348 static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1349 {
1350 struct v4l2_subdev *sd = to_sd(ctrl);
1351
1352 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1353 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1354 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1355 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1356 return 0;
1357 }
1358 return -EINVAL;
1359 }
1360
1361 static inline bool no_power(struct v4l2_subdev *sd)
1362 {
1363 return io_read(sd, 0x0c) & 0x24;
1364 }
1365
1366 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1367 {
1368 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1369 }
1370
1371 static inline bool is_hdmi(struct v4l2_subdev *sd)
1372 {
1373 return hdmi_read(sd, 0x05) & 0x80;
1374 }
1375
1376 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1377 {
1378 struct adv7842_state *state = to_state(sd);
1379
1380 *status = 0;
1381
1382 if (io_read(sd, 0x0c) & 0x24)
1383 *status |= V4L2_IN_ST_NO_POWER;
1384
1385 if (state->mode == ADV7842_MODE_SDP) {
1386 /* status from SDP block */
1387 if (!(sdp_read(sd, 0x5A) & 0x01))
1388 *status |= V4L2_IN_ST_NO_SIGNAL;
1389
1390 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1391 __func__, *status);
1392 return 0;
1393 }
1394 /* status from CP block */
1395 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1396 !(cp_read(sd, 0xb1) & 0x80))
1397 /* TODO channel 2 */
1398 *status |= V4L2_IN_ST_NO_SIGNAL;
1399
1400 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1401 *status |= V4L2_IN_ST_NO_SIGNAL;
1402
1403 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1404 __func__, *status);
1405
1406 return 0;
1407 }
1408
1409 struct stdi_readback {
1410 u16 bl, lcf, lcvs;
1411 u8 hs_pol, vs_pol;
1412 bool interlaced;
1413 };
1414
1415 static int stdi2dv_timings(struct v4l2_subdev *sd,
1416 struct stdi_readback *stdi,
1417 struct v4l2_dv_timings *timings)
1418 {
1419 struct adv7842_state *state = to_state(sd);
1420 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1421 u32 pix_clk;
1422 int i;
1423
1424 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1425 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1426
1427 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1428 adv7842_get_dv_timings_cap(sd),
1429 adv7842_check_dv_timings, NULL))
1430 continue;
1431 if (vtotal(bt) != stdi->lcf + 1)
1432 continue;
1433 if (bt->vsync != stdi->lcvs)
1434 continue;
1435
1436 pix_clk = hfreq * htotal(bt);
1437
1438 if ((pix_clk < bt->pixelclock + 1000000) &&
1439 (pix_clk > bt->pixelclock - 1000000)) {
1440 *timings = v4l2_dv_timings_presets[i];
1441 return 0;
1442 }
1443 }
1444
1445 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1446 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1447 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1448 false, timings))
1449 return 0;
1450 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1451 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1452 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1453 false, state->aspect_ratio, timings))
1454 return 0;
1455
1456 v4l2_dbg(2, debug, sd,
1457 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1458 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1459 stdi->hs_pol, stdi->vs_pol);
1460 return -1;
1461 }
1462
1463 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1464 {
1465 u32 status;
1466
1467 adv7842_g_input_status(sd, &status);
1468 if (status & V4L2_IN_ST_NO_SIGNAL) {
1469 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1470 return -ENOLINK;
1471 }
1472
1473 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1474 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1475 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1476
1477 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1478 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1479 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1480 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1481 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1482 } else {
1483 stdi->hs_pol = 'x';
1484 stdi->vs_pol = 'x';
1485 }
1486 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1487
1488 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1489 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1490 return -ENOLINK;
1491 }
1492
1493 v4l2_dbg(2, debug, sd,
1494 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1495 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1496 stdi->hs_pol, stdi->vs_pol,
1497 stdi->interlaced ? "interlaced" : "progressive");
1498
1499 return 0;
1500 }
1501
1502 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1503 struct v4l2_enum_dv_timings *timings)
1504 {
1505 if (timings->pad != 0)
1506 return -EINVAL;
1507
1508 return v4l2_enum_dv_timings_cap(timings,
1509 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1510 }
1511
1512 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1513 struct v4l2_dv_timings_cap *cap)
1514 {
1515 if (cap->pad != 0)
1516 return -EINVAL;
1517
1518 *cap = *adv7842_get_dv_timings_cap(sd);
1519 return 0;
1520 }
1521
1522 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1523 if the format is listed in adv7842_timings[] */
1524 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1525 struct v4l2_dv_timings *timings)
1526 {
1527 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1528 is_digital_input(sd) ? 250000 : 1000000,
1529 adv7842_check_dv_timings, NULL);
1530 timings->bt.flags |= V4L2_DV_FL_CAN_DETECT_REDUCED_FPS;
1531 }
1532
1533 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1534 struct v4l2_dv_timings *timings)
1535 {
1536 struct adv7842_state *state = to_state(sd);
1537 struct v4l2_bt_timings *bt = &timings->bt;
1538 struct stdi_readback stdi = { 0 };
1539
1540 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1541
1542 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1543
1544 /* SDP block */
1545 if (state->mode == ADV7842_MODE_SDP)
1546 return -ENODATA;
1547
1548 /* read STDI */
1549 if (read_stdi(sd, &stdi)) {
1550 state->restart_stdi_once = true;
1551 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1552 return -ENOLINK;
1553 }
1554 bt->interlaced = stdi.interlaced ?
1555 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1556 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1557 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1558
1559 if (is_digital_input(sd)) {
1560 u32 freq;
1561
1562 timings->type = V4L2_DV_BT_656_1120;
1563
1564 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1565 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1566 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1567 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
1568 if (is_hdmi(sd)) {
1569 /* adjust for deep color mode */
1570 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
1571 }
1572 bt->pixelclock = freq;
1573 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1574 hdmi_read(sd, 0x21);
1575 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1576 hdmi_read(sd, 0x23);
1577 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1578 hdmi_read(sd, 0x25);
1579 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1580 hdmi_read(sd, 0x2b)) / 2;
1581 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1582 hdmi_read(sd, 0x2f)) / 2;
1583 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1584 hdmi_read(sd, 0x33)) / 2;
1585 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1586 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1587 if (bt->interlaced == V4L2_DV_INTERLACED) {
1588 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1589 hdmi_read(sd, 0x0c);
1590 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1591 hdmi_read(sd, 0x2d)) / 2;
1592 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1593 hdmi_read(sd, 0x31)) / 2;
1594 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1595 hdmi_read(sd, 0x35)) / 2;
1596 } else {
1597 bt->il_vfrontporch = 0;
1598 bt->il_vsync = 0;
1599 bt->il_vbackporch = 0;
1600 }
1601 adv7842_fill_optional_dv_timings_fields(sd, timings);
1602 if ((timings->bt.flags & V4L2_DV_FL_CAN_REDUCE_FPS) &&
1603 freq < bt->pixelclock) {
1604 u32 reduced_freq = ((u32)bt->pixelclock / 1001) * 1000;
1605 u32 delta_freq = abs(freq - reduced_freq);
1606
1607 if (delta_freq < ((u32)bt->pixelclock - reduced_freq) / 2)
1608 timings->bt.flags |= V4L2_DV_FL_REDUCED_FPS;
1609 }
1610 } else {
1611 /* find format
1612 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1613 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1614 */
1615 if (!stdi2dv_timings(sd, &stdi, timings))
1616 goto found;
1617 stdi.lcvs += 1;
1618 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1619 if (!stdi2dv_timings(sd, &stdi, timings))
1620 goto found;
1621 stdi.lcvs -= 2;
1622 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1623 if (stdi2dv_timings(sd, &stdi, timings)) {
1624 /*
1625 * The STDI block may measure wrong values, especially
1626 * for lcvs and lcf. If the driver can not find any
1627 * valid timing, the STDI block is restarted to measure
1628 * the video timings again. The function will return an
1629 * error, but the restart of STDI will generate a new
1630 * STDI interrupt and the format detection process will
1631 * restart.
1632 */
1633 if (state->restart_stdi_once) {
1634 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1635 /* TODO restart STDI for Sync Channel 2 */
1636 /* enter one-shot mode */
1637 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1638 /* trigger STDI restart */
1639 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1640 /* reset to continuous mode */
1641 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1642 state->restart_stdi_once = false;
1643 return -ENOLINK;
1644 }
1645 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1646 return -ERANGE;
1647 }
1648 state->restart_stdi_once = true;
1649 }
1650 found:
1651
1652 if (debug > 1)
1653 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1654 timings, true);
1655 return 0;
1656 }
1657
1658 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1659 struct v4l2_dv_timings *timings)
1660 {
1661 struct adv7842_state *state = to_state(sd);
1662 struct v4l2_bt_timings *bt;
1663 int err;
1664
1665 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1666
1667 if (state->mode == ADV7842_MODE_SDP)
1668 return -ENODATA;
1669
1670 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1671 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1672 return 0;
1673 }
1674
1675 bt = &timings->bt;
1676
1677 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1678 adv7842_check_dv_timings, NULL))
1679 return -ERANGE;
1680
1681 adv7842_fill_optional_dv_timings_fields(sd, timings);
1682
1683 state->timings = *timings;
1684
1685 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1686
1687 /* Use prim_mode and vid_std when available */
1688 err = configure_predefined_video_timings(sd, timings);
1689 if (err) {
1690 /* custom settings when the video format
1691 does not have prim_mode/vid_std */
1692 configure_custom_video_timings(sd, bt);
1693 }
1694
1695 set_rgb_quantization_range(sd);
1696
1697
1698 if (debug > 1)
1699 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1700 timings, true);
1701 return 0;
1702 }
1703
1704 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1705 struct v4l2_dv_timings *timings)
1706 {
1707 struct adv7842_state *state = to_state(sd);
1708
1709 if (state->mode == ADV7842_MODE_SDP)
1710 return -ENODATA;
1711 *timings = state->timings;
1712 return 0;
1713 }
1714
1715 static void enable_input(struct v4l2_subdev *sd)
1716 {
1717 struct adv7842_state *state = to_state(sd);
1718
1719 set_rgb_quantization_range(sd);
1720 switch (state->mode) {
1721 case ADV7842_MODE_SDP:
1722 case ADV7842_MODE_COMP:
1723 case ADV7842_MODE_RGB:
1724 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1725 break;
1726 case ADV7842_MODE_HDMI:
1727 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1728 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1729 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1730 break;
1731 default:
1732 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1733 __func__, state->mode);
1734 break;
1735 }
1736 }
1737
1738 static void disable_input(struct v4l2_subdev *sd)
1739 {
1740 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1741 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
1742 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1743 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1744 }
1745
1746 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1747 const struct adv7842_sdp_csc_coeff *c)
1748 {
1749 /* csc auto/manual */
1750 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1751
1752 if (!c->manual)
1753 return;
1754
1755 /* csc scaling */
1756 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1757
1758 /* A coeff */
1759 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1760 sdp_io_write(sd, 0xe1, c->A1);
1761 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1762 sdp_io_write(sd, 0xe3, c->A2);
1763 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1764 sdp_io_write(sd, 0xe5, c->A3);
1765
1766 /* A scale */
1767 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1768 sdp_io_write(sd, 0xe7, c->A4);
1769
1770 /* B coeff */
1771 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1772 sdp_io_write(sd, 0xe9, c->B1);
1773 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1774 sdp_io_write(sd, 0xeb, c->B2);
1775 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1776 sdp_io_write(sd, 0xed, c->B3);
1777
1778 /* B scale */
1779 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1780 sdp_io_write(sd, 0xef, c->B4);
1781
1782 /* C coeff */
1783 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1784 sdp_io_write(sd, 0xf1, c->C1);
1785 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1786 sdp_io_write(sd, 0xf3, c->C2);
1787 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1788 sdp_io_write(sd, 0xf5, c->C3);
1789
1790 /* C scale */
1791 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1792 sdp_io_write(sd, 0xf7, c->C4);
1793 }
1794
1795 static void select_input(struct v4l2_subdev *sd,
1796 enum adv7842_vid_std_select vid_std_select)
1797 {
1798 struct adv7842_state *state = to_state(sd);
1799
1800 switch (state->mode) {
1801 case ADV7842_MODE_SDP:
1802 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1803 io_write(sd, 0x01, 0); /* prim mode */
1804 /* enable embedded syncs for auto graphics mode */
1805 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1806
1807 afe_write(sd, 0x00, 0x00); /* power up ADC */
1808 afe_write(sd, 0xc8, 0x00); /* phase control */
1809
1810 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1811 /* script says register 0xde, which don't exist in manual */
1812
1813 /* Manual analog input muxing mode, CVBS (6.4)*/
1814 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1815 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1816 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1817 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1818 } else {
1819 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1820 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1821 }
1822 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1823 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1824
1825 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1826 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1827
1828 /* SDP recommended settings */
1829 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1830 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1831
1832 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1833 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1834 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1835 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1836 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1837 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1838 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1839
1840 /* deinterlacer enabled and 3D comb */
1841 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1842
1843 break;
1844
1845 case ADV7842_MODE_COMP:
1846 case ADV7842_MODE_RGB:
1847 /* Automatic analog input muxing mode */
1848 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1849 /* set mode and select free run resolution */
1850 io_write(sd, 0x00, vid_std_select); /* video std */
1851 io_write(sd, 0x01, 0x02); /* prim mode */
1852 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1853 for auto graphics mode */
1854
1855 afe_write(sd, 0x00, 0x00); /* power up ADC */
1856 afe_write(sd, 0xc8, 0x00); /* phase control */
1857 if (state->mode == ADV7842_MODE_COMP) {
1858 /* force to YCrCb */
1859 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1860 } else {
1861 /* force to RGB */
1862 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1863 }
1864
1865 /* set ADI recommended settings for digitizer */
1866 /* "ADV7842 Register Settings Recommendations
1867 * (rev. 1.8, November 2010)" p. 9. */
1868 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1869 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1870
1871 /* set to default gain for RGB */
1872 cp_write(sd, 0x73, 0x10);
1873 cp_write(sd, 0x74, 0x04);
1874 cp_write(sd, 0x75, 0x01);
1875 cp_write(sd, 0x76, 0x00);
1876
1877 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1878 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1879 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1880 break;
1881
1882 case ADV7842_MODE_HDMI:
1883 /* Automatic analog input muxing mode */
1884 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1885 /* set mode and select free run resolution */
1886 if (state->hdmi_port_a)
1887 hdmi_write(sd, 0x00, 0x02); /* select port A */
1888 else
1889 hdmi_write(sd, 0x00, 0x03); /* select port B */
1890 io_write(sd, 0x00, vid_std_select); /* video std */
1891 io_write(sd, 0x01, 5); /* prim mode */
1892 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1893 for auto graphics mode */
1894
1895 /* set ADI recommended settings for HDMI: */
1896 /* "ADV7842 Register Settings Recommendations
1897 * (rev. 1.8, November 2010)" p. 3. */
1898 hdmi_write(sd, 0xc0, 0x00);
1899 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1900 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1901 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1902 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1903 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1904 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1905 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1906 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1907 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1908 Improve robustness */
1909 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1910 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1911 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1912 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1913 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1914 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1915 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1916 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1917 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1918 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1919
1920 afe_write(sd, 0x00, 0xff); /* power down ADC */
1921 afe_write(sd, 0xc8, 0x40); /* phase control */
1922
1923 /* set to default gain for HDMI */
1924 cp_write(sd, 0x73, 0x10);
1925 cp_write(sd, 0x74, 0x04);
1926 cp_write(sd, 0x75, 0x01);
1927 cp_write(sd, 0x76, 0x00);
1928
1929 /* reset ADI recommended settings for digitizer */
1930 /* "ADV7842 Register Settings Recommendations
1931 * (rev. 2.5, June 2010)" p. 17. */
1932 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1933 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1934 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1935
1936 /* CP coast control */
1937 cp_write(sd, 0xc3, 0x33); /* Component mode */
1938
1939 /* color space conversion, autodetect color space */
1940 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1941 break;
1942
1943 default:
1944 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1945 __func__, state->mode);
1946 break;
1947 }
1948 }
1949
1950 static int adv7842_s_routing(struct v4l2_subdev *sd,
1951 u32 input, u32 output, u32 config)
1952 {
1953 struct adv7842_state *state = to_state(sd);
1954
1955 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1956
1957 switch (input) {
1958 case ADV7842_SELECT_HDMI_PORT_A:
1959 state->mode = ADV7842_MODE_HDMI;
1960 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1961 state->hdmi_port_a = true;
1962 break;
1963 case ADV7842_SELECT_HDMI_PORT_B:
1964 state->mode = ADV7842_MODE_HDMI;
1965 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1966 state->hdmi_port_a = false;
1967 break;
1968 case ADV7842_SELECT_VGA_COMP:
1969 state->mode = ADV7842_MODE_COMP;
1970 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1971 break;
1972 case ADV7842_SELECT_VGA_RGB:
1973 state->mode = ADV7842_MODE_RGB;
1974 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1975 break;
1976 case ADV7842_SELECT_SDP_CVBS:
1977 state->mode = ADV7842_MODE_SDP;
1978 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1979 break;
1980 case ADV7842_SELECT_SDP_YC:
1981 state->mode = ADV7842_MODE_SDP;
1982 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1983 break;
1984 default:
1985 return -EINVAL;
1986 }
1987
1988 disable_input(sd);
1989 select_input(sd, state->vid_std_select);
1990 enable_input(sd);
1991
1992 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
1993
1994 return 0;
1995 }
1996
1997 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
1998 struct v4l2_subdev_pad_config *cfg,
1999 struct v4l2_subdev_mbus_code_enum *code)
2000 {
2001 if (code->index >= ARRAY_SIZE(adv7842_formats))
2002 return -EINVAL;
2003 code->code = adv7842_formats[code->index].code;
2004 return 0;
2005 }
2006
2007 static void adv7842_fill_format(struct adv7842_state *state,
2008 struct v4l2_mbus_framefmt *format)
2009 {
2010 memset(format, 0, sizeof(*format));
2011
2012 format->width = state->timings.bt.width;
2013 format->height = state->timings.bt.height;
2014 format->field = V4L2_FIELD_NONE;
2015 format->colorspace = V4L2_COLORSPACE_SRGB;
2016
2017 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
2018 format->colorspace = (state->timings.bt.height <= 576) ?
2019 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
2020 }
2021
2022 /*
2023 * Compute the op_ch_sel value required to obtain on the bus the component order
2024 * corresponding to the selected format taking into account bus reordering
2025 * applied by the board at the output of the device.
2026 *
2027 * The following table gives the op_ch_value from the format component order
2028 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
2029 * adv7842_bus_order value in row).
2030 *
2031 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
2032 * ----------+-------------------------------------------------
2033 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
2034 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
2035 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
2036 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
2037 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
2038 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
2039 */
2040 static unsigned int adv7842_op_ch_sel(struct adv7842_state *state)
2041 {
2042 #define _SEL(a, b, c, d, e, f) { \
2043 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \
2044 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f }
2045 #define _BUS(x) [ADV7842_BUS_ORDER_##x]
2046
2047 static const unsigned int op_ch_sel[6][6] = {
2048 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
2049 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
2050 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
2051 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
2052 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
2053 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
2054 };
2055
2056 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
2057 }
2058
2059 static void adv7842_setup_format(struct adv7842_state *state)
2060 {
2061 struct v4l2_subdev *sd = &state->sd;
2062
2063 io_write_clr_set(sd, 0x02, 0x02,
2064 state->format->rgb_out ? ADV7842_RGB_OUT : 0);
2065 io_write(sd, 0x03, state->format->op_format_sel |
2066 state->pdata.op_format_mode_sel);
2067 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
2068 io_write_clr_set(sd, 0x05, 0x01,
2069 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);
2070 set_rgb_quantization_range(sd);
2071 }
2072
2073 static int adv7842_get_format(struct v4l2_subdev *sd,
2074 struct v4l2_subdev_pad_config *cfg,
2075 struct v4l2_subdev_format *format)
2076 {
2077 struct adv7842_state *state = to_state(sd);
2078
2079 if (format->pad != ADV7842_PAD_SOURCE)
2080 return -EINVAL;
2081
2082 if (state->mode == ADV7842_MODE_SDP) {
2083 /* SPD block */
2084 if (!(sdp_read(sd, 0x5a) & 0x01))
2085 return -EINVAL;
2086 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;
2087 format->format.width = 720;
2088 /* valid signal */
2089 if (state->norm & V4L2_STD_525_60)
2090 format->format.height = 480;
2091 else
2092 format->format.height = 576;
2093 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
2094 return 0;
2095 }
2096
2097 adv7842_fill_format(state, &format->format);
2098
2099 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2100 struct v4l2_mbus_framefmt *fmt;
2101
2102 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2103 format->format.code = fmt->code;
2104 } else {
2105 format->format.code = state->format->code;
2106 }
2107
2108 return 0;
2109 }
2110
2111 static int adv7842_set_format(struct v4l2_subdev *sd,
2112 struct v4l2_subdev_pad_config *cfg,
2113 struct v4l2_subdev_format *format)
2114 {
2115 struct adv7842_state *state = to_state(sd);
2116 const struct adv7842_format_info *info;
2117
2118 if (format->pad != ADV7842_PAD_SOURCE)
2119 return -EINVAL;
2120
2121 if (state->mode == ADV7842_MODE_SDP)
2122 return adv7842_get_format(sd, cfg, format);
2123
2124 info = adv7842_format_info(state, format->format.code);
2125 if (info == NULL)
2126 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2127
2128 adv7842_fill_format(state, &format->format);
2129 format->format.code = info->code;
2130
2131 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2132 struct v4l2_mbus_framefmt *fmt;
2133
2134 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2135 fmt->code = format->format.code;
2136 } else {
2137 state->format = info;
2138 adv7842_setup_format(state);
2139 }
2140
2141 return 0;
2142 }
2143
2144 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
2145 {
2146 if (enable) {
2147 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
2148 io_write(sd, 0x46, 0x9c);
2149 /* ESDP_50HZ_DET interrupt */
2150 io_write(sd, 0x5a, 0x10);
2151 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
2152 io_write(sd, 0x73, 0x03);
2153 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2154 io_write(sd, 0x78, 0x03);
2155 /* Enable SDP Standard Detection Change and SDP Video Detected */
2156 io_write(sd, 0xa0, 0x09);
2157 /* Enable HDMI_MODE interrupt */
2158 io_write(sd, 0x69, 0x08);
2159 } else {
2160 io_write(sd, 0x46, 0x0);
2161 io_write(sd, 0x5a, 0x0);
2162 io_write(sd, 0x73, 0x0);
2163 io_write(sd, 0x78, 0x0);
2164 io_write(sd, 0xa0, 0x0);
2165 io_write(sd, 0x69, 0x0);
2166 }
2167 }
2168
2169 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2170 static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
2171 {
2172 struct adv7842_state *state = to_state(sd);
2173
2174 if ((cec_read(sd, 0x11) & 0x01) == 0) {
2175 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
2176 return;
2177 }
2178
2179 if (tx_raw_status & 0x02) {
2180 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2181 __func__);
2182 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
2183 1, 0, 0, 0);
2184 return;
2185 }
2186 if (tx_raw_status & 0x04) {
2187 u8 status;
2188 u8 nack_cnt;
2189 u8 low_drive_cnt;
2190
2191 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2192 /*
2193 * We set this status bit since this hardware performs
2194 * retransmissions.
2195 */
2196 status = CEC_TX_STATUS_MAX_RETRIES;
2197 nack_cnt = cec_read(sd, 0x14) & 0xf;
2198 if (nack_cnt)
2199 status |= CEC_TX_STATUS_NACK;
2200 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2201 if (low_drive_cnt)
2202 status |= CEC_TX_STATUS_LOW_DRIVE;
2203 cec_transmit_done(state->cec_adap, status,
2204 0, nack_cnt, low_drive_cnt, 0);
2205 return;
2206 }
2207 if (tx_raw_status & 0x01) {
2208 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2209 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2210 return;
2211 }
2212 }
2213
2214 static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled)
2215 {
2216 u8 cec_irq;
2217
2218 /* cec controller */
2219 cec_irq = io_read(sd, 0x93) & 0x0f;
2220 if (!cec_irq)
2221 return;
2222
2223 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2224 adv7842_cec_tx_raw_status(sd, cec_irq);
2225 if (cec_irq & 0x08) {
2226 struct adv7842_state *state = to_state(sd);
2227 struct cec_msg msg;
2228
2229 msg.len = cec_read(sd, 0x25) & 0x1f;
2230 if (msg.len > 16)
2231 msg.len = 16;
2232
2233 if (msg.len) {
2234 u8 i;
2235
2236 for (i = 0; i < msg.len; i++)
2237 msg.msg[i] = cec_read(sd, i + 0x15);
2238 cec_write(sd, 0x26, 0x01); /* re-enable rx */
2239 cec_received_msg(state->cec_adap, &msg);
2240 }
2241 }
2242
2243 io_write(sd, 0x94, cec_irq);
2244
2245 if (handled)
2246 *handled = true;
2247 }
2248
2249 static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable)
2250 {
2251 struct adv7842_state *state = cec_get_drvdata(adap);
2252 struct v4l2_subdev *sd = &state->sd;
2253
2254 if (!state->cec_enabled_adap && enable) {
2255 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2256 cec_write(sd, 0x2c, 0x01); /* cec soft reset */
2257 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2258 /* enabled irqs: */
2259 /* tx: ready */
2260 /* tx: arbitration lost */
2261 /* tx: retry timeout */
2262 /* rx: ready */
2263 io_write_clr_set(sd, 0x96, 0x0f, 0x0f);
2264 cec_write(sd, 0x26, 0x01); /* enable rx */
2265 } else if (state->cec_enabled_adap && !enable) {
2266 /* disable cec interrupts */
2267 io_write_clr_set(sd, 0x96, 0x0f, 0x00);
2268 /* disable address mask 1-3 */
2269 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2270 /* power down cec section */
2271 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2272 state->cec_valid_addrs = 0;
2273 }
2274 state->cec_enabled_adap = enable;
2275 return 0;
2276 }
2277
2278 static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2279 {
2280 struct adv7842_state *state = cec_get_drvdata(adap);
2281 struct v4l2_subdev *sd = &state->sd;
2282 unsigned int i, free_idx = ADV7842_MAX_ADDRS;
2283
2284 if (!state->cec_enabled_adap)
2285 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2286
2287 if (addr == CEC_LOG_ADDR_INVALID) {
2288 cec_write_clr_set(sd, 0x27, 0x70, 0);
2289 state->cec_valid_addrs = 0;
2290 return 0;
2291 }
2292
2293 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2294 bool is_valid = state->cec_valid_addrs & (1 << i);
2295
2296 if (free_idx == ADV7842_MAX_ADDRS && !is_valid)
2297 free_idx = i;
2298 if (is_valid && state->cec_addr[i] == addr)
2299 return 0;
2300 }
2301 if (i == ADV7842_MAX_ADDRS) {
2302 i = free_idx;
2303 if (i == ADV7842_MAX_ADDRS)
2304 return -ENXIO;
2305 }
2306 state->cec_addr[i] = addr;
2307 state->cec_valid_addrs |= 1 << i;
2308
2309 switch (i) {
2310 case 0:
2311 /* enable address mask 0 */
2312 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2313 /* set address for mask 0 */
2314 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2315 break;
2316 case 1:
2317 /* enable address mask 1 */
2318 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2319 /* set address for mask 1 */
2320 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2321 break;
2322 case 2:
2323 /* enable address mask 2 */
2324 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2325 /* set address for mask 1 */
2326 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2327 break;
2328 }
2329 return 0;
2330 }
2331
2332 static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2333 u32 signal_free_time, struct cec_msg *msg)
2334 {
2335 struct adv7842_state *state = cec_get_drvdata(adap);
2336 struct v4l2_subdev *sd = &state->sd;
2337 u8 len = msg->len;
2338 unsigned int i;
2339
2340 /*
2341 * The number of retries is the number of attempts - 1, but retry
2342 * at least once. It's not clear if a value of 0 is allowed, so
2343 * let's do at least one retry.
2344 */
2345 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2346
2347 if (len > 16) {
2348 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2349 return -EINVAL;
2350 }
2351
2352 /* write data */
2353 for (i = 0; i < len; i++)
2354 cec_write(sd, i, msg->msg[i]);
2355
2356 /* set length (data + header) */
2357 cec_write(sd, 0x10, len);
2358 /* start transmit, enable tx */
2359 cec_write(sd, 0x11, 0x01);
2360 return 0;
2361 }
2362
2363 static const struct cec_adap_ops adv7842_cec_adap_ops = {
2364 .adap_enable = adv7842_cec_adap_enable,
2365 .adap_log_addr = adv7842_cec_adap_log_addr,
2366 .adap_transmit = adv7842_cec_adap_transmit,
2367 };
2368 #endif
2369
2370 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2371 {
2372 struct adv7842_state *state = to_state(sd);
2373 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
2374 u8 irq_status[6];
2375
2376 adv7842_irq_enable(sd, false);
2377
2378 /* read status */
2379 irq_status[0] = io_read(sd, 0x43);
2380 irq_status[1] = io_read(sd, 0x57);
2381 irq_status[2] = io_read(sd, 0x70);
2382 irq_status[3] = io_read(sd, 0x75);
2383 irq_status[4] = io_read(sd, 0x9d);
2384 irq_status[5] = io_read(sd, 0x66);
2385
2386 /* and clear */
2387 if (irq_status[0])
2388 io_write(sd, 0x44, irq_status[0]);
2389 if (irq_status[1])
2390 io_write(sd, 0x58, irq_status[1]);
2391 if (irq_status[2])
2392 io_write(sd, 0x71, irq_status[2]);
2393 if (irq_status[3])
2394 io_write(sd, 0x76, irq_status[3]);
2395 if (irq_status[4])
2396 io_write(sd, 0x9e, irq_status[4]);
2397 if (irq_status[5])
2398 io_write(sd, 0x67, irq_status[5]);
2399
2400 adv7842_irq_enable(sd, true);
2401
2402 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
2403 irq_status[0], irq_status[1], irq_status[2],
2404 irq_status[3], irq_status[4], irq_status[5]);
2405
2406 /* format change CP */
2407 fmt_change_cp = irq_status[0] & 0x9c;
2408
2409 /* format change SDP */
2410 if (state->mode == ADV7842_MODE_SDP)
2411 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
2412 else
2413 fmt_change_sdp = 0;
2414
2415 /* digital format CP */
2416 if (is_digital_input(sd))
2417 fmt_change_digital = irq_status[3] & 0x03;
2418 else
2419 fmt_change_digital = 0;
2420
2421 /* format change */
2422 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
2423 v4l2_dbg(1, debug, sd,
2424 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
2425 __func__, fmt_change_cp, fmt_change_digital,
2426 fmt_change_sdp);
2427 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
2428 if (handled)
2429 *handled = true;
2430 }
2431
2432 /* HDMI/DVI mode */
2433 if (irq_status[5] & 0x08) {
2434 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2435 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
2436 set_rgb_quantization_range(sd);
2437 if (handled)
2438 *handled = true;
2439 }
2440
2441 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2442 /* cec */
2443 adv7842_cec_isr(sd, handled);
2444 #endif
2445
2446 /* tx 5v detect */
2447 if (irq_status[2] & 0x3) {
2448 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2449 adv7842_s_detect_tx_5v_ctrl(sd);
2450 if (handled)
2451 *handled = true;
2452 }
2453 return 0;
2454 }
2455
2456 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2457 {
2458 struct adv7842_state *state = to_state(sd);
2459 u8 *data = NULL;
2460
2461 memset(edid->reserved, 0, sizeof(edid->reserved));
2462
2463 switch (edid->pad) {
2464 case ADV7842_EDID_PORT_A:
2465 case ADV7842_EDID_PORT_B:
2466 if (state->hdmi_edid.present & (0x04 << edid->pad))
2467 data = state->hdmi_edid.edid;
2468 break;
2469 case ADV7842_EDID_PORT_VGA:
2470 if (state->vga_edid.present)
2471 data = state->vga_edid.edid;
2472 break;
2473 default:
2474 return -EINVAL;
2475 }
2476
2477 if (edid->start_block == 0 && edid->blocks == 0) {
2478 edid->blocks = data ? 2 : 0;
2479 return 0;
2480 }
2481
2482 if (!data)
2483 return -ENODATA;
2484
2485 if (edid->start_block >= 2)
2486 return -EINVAL;
2487
2488 if (edid->start_block + edid->blocks > 2)
2489 edid->blocks = 2 - edid->start_block;
2490
2491 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2492
2493 return 0;
2494 }
2495
2496 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
2497 {
2498 struct adv7842_state *state = to_state(sd);
2499 int err = 0;
2500
2501 memset(e->reserved, 0, sizeof(e->reserved));
2502
2503 if (e->pad > ADV7842_EDID_PORT_VGA)
2504 return -EINVAL;
2505 if (e->start_block != 0)
2506 return -EINVAL;
2507 if (e->blocks > 2) {
2508 e->blocks = 2;
2509 return -E2BIG;
2510 }
2511
2512 /* todo, per edid */
2513 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
2514 e->edid[0x16]);
2515
2516 switch (e->pad) {
2517 case ADV7842_EDID_PORT_VGA:
2518 memset(&state->vga_edid.edid, 0, 256);
2519 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
2520 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
2521 err = edid_write_vga_segment(sd);
2522 break;
2523 case ADV7842_EDID_PORT_A:
2524 case ADV7842_EDID_PORT_B:
2525 memset(&state->hdmi_edid.edid, 0, 256);
2526 if (e->blocks) {
2527 state->hdmi_edid.present |= 0x04 << e->pad;
2528 } else {
2529 state->hdmi_edid.present &= ~(0x04 << e->pad);
2530 adv7842_s_detect_tx_5v_ctrl(sd);
2531 }
2532 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
2533 err = edid_write_hdmi_segment(sd, e->pad);
2534 break;
2535 default:
2536 return -EINVAL;
2537 }
2538 if (err < 0)
2539 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2540 return err;
2541 }
2542
2543 struct adv7842_cfg_read_infoframe {
2544 const char *desc;
2545 u8 present_mask;
2546 u8 head_addr;
2547 u8 payload_addr;
2548 };
2549
2550 static void log_infoframe(struct v4l2_subdev *sd, const struct adv7842_cfg_read_infoframe *cri)
2551 {
2552 int i;
2553 u8 buffer[32];
2554 union hdmi_infoframe frame;
2555 u8 len;
2556 struct i2c_client *client = v4l2_get_subdevdata(sd);
2557 struct device *dev = &client->dev;
2558
2559 if (!(io_read(sd, 0x60) & cri->present_mask)) {
2560 v4l2_info(sd, "%s infoframe not received\n", cri->desc);
2561 return;
2562 }
2563
2564 for (i = 0; i < 3; i++)
2565 buffer[i] = infoframe_read(sd, cri->head_addr + i);
2566
2567 len = buffer[2] + 1;
2568
2569 if (len + 3 > sizeof(buffer)) {
2570 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
2571 return;
2572 }
2573
2574 for (i = 0; i < len; i++)
2575 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
2576
2577 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) {
2578 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
2579 return;
2580 }
2581
2582 hdmi_infoframe_log(KERN_INFO, dev, &frame);
2583 }
2584
2585 static void adv7842_log_infoframes(struct v4l2_subdev *sd)
2586 {
2587 int i;
2588 static const struct adv7842_cfg_read_infoframe cri[] = {
2589 { "AVI", 0x01, 0xe0, 0x00 },
2590 { "Audio", 0x02, 0xe3, 0x1c },
2591 { "SDP", 0x04, 0xe6, 0x2a },
2592 { "Vendor", 0x10, 0xec, 0x54 }
2593 };
2594
2595 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2596 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2597 return;
2598 }
2599
2600 for (i = 0; i < ARRAY_SIZE(cri); i++)
2601 log_infoframe(sd, &cri[i]);
2602 }
2603
2604 #if 0
2605 /* Let's keep it here for now, as it could be useful for debug */
2606 static const char * const prim_mode_txt[] = {
2607 "SDP",
2608 "Component",
2609 "Graphics",
2610 "Reserved",
2611 "CVBS & HDMI AUDIO",
2612 "HDMI-Comp",
2613 "HDMI-GR",
2614 "Reserved",
2615 "Reserved",
2616 "Reserved",
2617 "Reserved",
2618 "Reserved",
2619 "Reserved",
2620 "Reserved",
2621 "Reserved",
2622 "Reserved",
2623 };
2624 #endif
2625
2626 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2627 {
2628 /* SDP (Standard definition processor) block */
2629 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2630
2631 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2632 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2633 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2634
2635 v4l2_info(sd, "SDP: free run: %s\n",
2636 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2637 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2638 "valid SD/PR signal detected" : "invalid/no signal");
2639 if (sdp_signal_detected) {
2640 static const char * const sdp_std_txt[] = {
2641 "NTSC-M/J",
2642 "1?",
2643 "NTSC-443",
2644 "60HzSECAM",
2645 "PAL-M",
2646 "5?",
2647 "PAL-60",
2648 "7?", "8?", "9?", "a?", "b?",
2649 "PAL-CombN",
2650 "d?",
2651 "PAL-BGHID",
2652 "SECAM"
2653 };
2654 v4l2_info(sd, "SDP: standard %s\n",
2655 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2656 v4l2_info(sd, "SDP: %s\n",
2657 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2658 v4l2_info(sd, "SDP: %s\n",
2659 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2660 v4l2_info(sd, "SDP: deinterlacer %s\n",
2661 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2662 v4l2_info(sd, "SDP: csc %s mode\n",
2663 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2664 }
2665 return 0;
2666 }
2667
2668 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2669 {
2670 /* CP block */
2671 struct adv7842_state *state = to_state(sd);
2672 struct v4l2_dv_timings timings;
2673 u8 reg_io_0x02 = io_read(sd, 0x02);
2674 u8 reg_io_0x21 = io_read(sd, 0x21);
2675 u8 reg_rep_0x77 = rep_read(sd, 0x77);
2676 u8 reg_rep_0x7d = rep_read(sd, 0x7d);
2677 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2678 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2679 bool audio_mute = io_read(sd, 0x65) & 0x40;
2680
2681 static const char * const csc_coeff_sel_rb[16] = {
2682 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2683 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2684 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2685 "reserved", "reserved", "reserved", "reserved", "manual"
2686 };
2687 static const char * const input_color_space_txt[16] = {
2688 "RGB limited range (16-235)", "RGB full range (0-255)",
2689 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2690 "xvYCC Bt.601", "xvYCC Bt.709",
2691 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2692 "invalid", "invalid", "invalid", "invalid", "invalid",
2693 "invalid", "invalid", "automatic"
2694 };
2695 static const char * const rgb_quantization_range_txt[] = {
2696 "Automatic",
2697 "RGB limited range (16-235)",
2698 "RGB full range (0-255)",
2699 };
2700 static const char * const deep_color_mode_txt[4] = {
2701 "8-bits per channel",
2702 "10-bits per channel",
2703 "12-bits per channel",
2704 "16-bits per channel (not supported)"
2705 };
2706
2707 v4l2_info(sd, "-----Chip status-----\n");
2708 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2709 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2710 state->hdmi_port_a ? "A" : "B");
2711 v4l2_info(sd, "EDID A %s, B %s\n",
2712 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2713 "enabled" : "disabled",
2714 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2715 "enabled" : "disabled");
2716 v4l2_info(sd, "HPD A %s, B %s\n",
2717 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2718 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2719 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2720 "enabled" : "disabled");
2721 if (state->cec_enabled_adap) {
2722 int i;
2723
2724 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2725 bool is_valid = state->cec_valid_addrs & (1 << i);
2726
2727 if (is_valid)
2728 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2729 state->cec_addr[i]);
2730 }
2731 }
2732
2733 v4l2_info(sd, "-----Signal status-----\n");
2734 if (state->hdmi_port_a) {
2735 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2736 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2737 v4l2_info(sd, "TMDS signal detected: %s\n",
2738 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2739 v4l2_info(sd, "TMDS signal locked: %s\n",
2740 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2741 } else {
2742 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2743 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2744 v4l2_info(sd, "TMDS signal detected: %s\n",
2745 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2746 v4l2_info(sd, "TMDS signal locked: %s\n",
2747 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2748 }
2749 v4l2_info(sd, "CP free run: %s\n",
2750 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2751 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2752 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2753 (io_read(sd, 0x01) & 0x70) >> 4);
2754
2755 v4l2_info(sd, "-----Video Timings-----\n");
2756 if (no_cp_signal(sd)) {
2757 v4l2_info(sd, "STDI: not locked\n");
2758 } else {
2759 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2760 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2761 u32 lcvs = cp_read(sd, 0xb3) >> 3;
2762 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2763 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2764 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2765 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2766 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2767 v4l2_info(sd,
2768 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2769 lcf, bl, lcvs, fcl,
2770 (cp_read(sd, 0xb1) & 0x40) ?
2771 "interlaced" : "progressive",
2772 hs_pol, vs_pol);
2773 }
2774 if (adv7842_query_dv_timings(sd, &timings))
2775 v4l2_info(sd, "No video detected\n");
2776 else
2777 v4l2_print_dv_timings(sd->name, "Detected format: ",
2778 &timings, true);
2779 v4l2_print_dv_timings(sd->name, "Configured format: ",
2780 &state->timings, true);
2781
2782 if (no_cp_signal(sd))
2783 return 0;
2784
2785 v4l2_info(sd, "-----Color space-----\n");
2786 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2787 rgb_quantization_range_txt[state->rgb_quantization_range]);
2788 v4l2_info(sd, "Input color space: %s\n",
2789 input_color_space_txt[reg_io_0x02 >> 4]);
2790 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2791 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2792 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2793 "(16-235)" : "(0-255)",
2794 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2795 v4l2_info(sd, "Color space conversion: %s\n",
2796 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2797
2798 if (!is_digital_input(sd))
2799 return 0;
2800
2801 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2802 v4l2_info(sd, "HDCP encrypted content: %s\n",
2803 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2804 v4l2_info(sd, "HDCP keys read: %s%s\n",
2805 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2806 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2807 if (!is_hdmi(sd))
2808 return 0;
2809
2810 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2811 audio_pll_locked ? "locked" : "not locked",
2812 audio_sample_packet_detect ? "detected" : "not detected",
2813 audio_mute ? "muted" : "enabled");
2814 if (audio_pll_locked && audio_sample_packet_detect) {
2815 v4l2_info(sd, "Audio format: %s\n",
2816 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2817 }
2818 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2819 (hdmi_read(sd, 0x5c) << 8) +
2820 (hdmi_read(sd, 0x5d) & 0xf0));
2821 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2822 (hdmi_read(sd, 0x5e) << 8) +
2823 hdmi_read(sd, 0x5f));
2824 v4l2_info(sd, "AV Mute: %s\n",
2825 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2826 v4l2_info(sd, "Deep color mode: %s\n",
2827 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2828
2829 adv7842_log_infoframes(sd);
2830
2831 return 0;
2832 }
2833
2834 static int adv7842_log_status(struct v4l2_subdev *sd)
2835 {
2836 struct adv7842_state *state = to_state(sd);
2837
2838 if (state->mode == ADV7842_MODE_SDP)
2839 return adv7842_sdp_log_status(sd);
2840 return adv7842_cp_log_status(sd);
2841 }
2842
2843 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2844 {
2845 struct adv7842_state *state = to_state(sd);
2846
2847 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2848
2849 if (state->mode != ADV7842_MODE_SDP)
2850 return -ENODATA;
2851
2852 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2853 *std = 0;
2854 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2855 return 0;
2856 }
2857
2858 switch (sdp_read(sd, 0x52) & 0x0f) {
2859 case 0:
2860 /* NTSC-M/J */
2861 *std &= V4L2_STD_NTSC;
2862 break;
2863 case 2:
2864 /* NTSC-443 */
2865 *std &= V4L2_STD_NTSC_443;
2866 break;
2867 case 3:
2868 /* 60HzSECAM */
2869 *std &= V4L2_STD_SECAM;
2870 break;
2871 case 4:
2872 /* PAL-M */
2873 *std &= V4L2_STD_PAL_M;
2874 break;
2875 case 6:
2876 /* PAL-60 */
2877 *std &= V4L2_STD_PAL_60;
2878 break;
2879 case 0xc:
2880 /* PAL-CombN */
2881 *std &= V4L2_STD_PAL_Nc;
2882 break;
2883 case 0xe:
2884 /* PAL-BGHID */
2885 *std &= V4L2_STD_PAL;
2886 break;
2887 case 0xf:
2888 /* SECAM */
2889 *std &= V4L2_STD_SECAM;
2890 break;
2891 default:
2892 *std &= V4L2_STD_ALL;
2893 break;
2894 }
2895 return 0;
2896 }
2897
2898 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2899 {
2900 if (s && s->adjust) {
2901 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2902 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2903 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2904 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2905 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2906 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2907 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2908 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2909 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2910 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2911 sdp_io_write(sd, 0xaa, s->vs_end_o);
2912 sdp_io_write(sd, 0xab, s->vs_end_e);
2913 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2914 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2915 sdp_io_write(sd, 0xae, s->de_v_end_o);
2916 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2917 } else {
2918 /* set to default */
2919 sdp_io_write(sd, 0x94, 0x00);
2920 sdp_io_write(sd, 0x95, 0x00);
2921 sdp_io_write(sd, 0x96, 0x00);
2922 sdp_io_write(sd, 0x97, 0x20);
2923 sdp_io_write(sd, 0x98, 0x00);
2924 sdp_io_write(sd, 0x99, 0x00);
2925 sdp_io_write(sd, 0x9a, 0x00);
2926 sdp_io_write(sd, 0x9b, 0x00);
2927 sdp_io_write(sd, 0xa8, 0x04);
2928 sdp_io_write(sd, 0xa9, 0x04);
2929 sdp_io_write(sd, 0xaa, 0x04);
2930 sdp_io_write(sd, 0xab, 0x04);
2931 sdp_io_write(sd, 0xac, 0x04);
2932 sdp_io_write(sd, 0xad, 0x04);
2933 sdp_io_write(sd, 0xae, 0x04);
2934 sdp_io_write(sd, 0xaf, 0x04);
2935 }
2936 }
2937
2938 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2939 {
2940 struct adv7842_state *state = to_state(sd);
2941 struct adv7842_platform_data *pdata = &state->pdata;
2942
2943 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2944
2945 if (state->mode != ADV7842_MODE_SDP)
2946 return -ENODATA;
2947
2948 if (norm & V4L2_STD_625_50)
2949 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2950 else if (norm & V4L2_STD_525_60)
2951 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2952 else
2953 adv7842_s_sdp_io(sd, NULL);
2954
2955 if (norm & V4L2_STD_ALL) {
2956 state->norm = norm;
2957 return 0;
2958 }
2959 return -EINVAL;
2960 }
2961
2962 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2963 {
2964 struct adv7842_state *state = to_state(sd);
2965
2966 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2967
2968 if (state->mode != ADV7842_MODE_SDP)
2969 return -ENODATA;
2970
2971 *norm = state->norm;
2972 return 0;
2973 }
2974
2975 /* ----------------------------------------------------------------------- */
2976
2977 static int adv7842_core_init(struct v4l2_subdev *sd)
2978 {
2979 struct adv7842_state *state = to_state(sd);
2980 struct adv7842_platform_data *pdata = &state->pdata;
2981 hdmi_write(sd, 0x48,
2982 (pdata->disable_pwrdnb ? 0x80 : 0) |
2983 (pdata->disable_cable_det_rst ? 0x40 : 0));
2984
2985 disable_input(sd);
2986
2987 /*
2988 * Disable I2C access to internal EDID ram from HDMI DDC ports
2989 * Disable auto edid enable when leaving powerdown mode
2990 */
2991 rep_write_and_or(sd, 0x77, 0xd3, 0x20);
2992
2993 /* power */
2994 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2995 io_write(sd, 0x15, 0x80); /* Power up pads */
2996
2997 /* video format */
2998 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3);
2999 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
3000 pdata->insert_av_codes << 2 |
3001 pdata->replicate_av_codes << 1);
3002 adv7842_setup_format(state);
3003
3004 /* HDMI audio */
3005 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
3006
3007 /* Drive strength */
3008 io_write_and_or(sd, 0x14, 0xc0,
3009 pdata->dr_str_data << 4 |
3010 pdata->dr_str_clk << 2 |
3011 pdata->dr_str_sync);
3012
3013 /* HDMI free run */
3014 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
3015 (pdata->hdmi_free_run_mode << 1));
3016
3017 /* SPD free run */
3018 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
3019 (pdata->sdp_free_run_cbar_en << 1) |
3020 (pdata->sdp_free_run_man_col_en << 2) |
3021 (pdata->sdp_free_run_auto << 3));
3022
3023 /* TODO from platform data */
3024 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
3025 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
3026 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
3027 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
3028
3029 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
3030 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
3031
3032 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
3033
3034 /* todo, improve settings for sdram */
3035 if (pdata->sd_ram_size >= 128) {
3036 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
3037 if (pdata->sd_ram_ddr) {
3038 /* SDP setup for the AD eval board */
3039 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
3040 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
3041 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3042 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3043 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3044 } else {
3045 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
3046 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
3047 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
3048 depends on memory */
3049 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
3050 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3051 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3052 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3053 }
3054 } else {
3055 /*
3056 * Manual UG-214, rev 0 is bit confusing on this bit
3057 * but a '1' disables any signal if the Ram is active.
3058 */
3059 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
3060 }
3061
3062 select_input(sd, pdata->vid_std_select);
3063
3064 enable_input(sd);
3065
3066 if (pdata->hpa_auto) {
3067 /* HPA auto, HPA 0.5s after Edid set and Cable detect */
3068 hdmi_write(sd, 0x69, 0x5c);
3069 } else {
3070 /* HPA manual */
3071 hdmi_write(sd, 0x69, 0xa3);
3072 /* HPA disable on port A and B */
3073 io_write_and_or(sd, 0x20, 0xcf, 0x00);
3074 }
3075
3076 /* LLC */
3077 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
3078 io_write(sd, 0x33, 0x40);
3079
3080 /* interrupts */
3081 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
3082
3083 adv7842_irq_enable(sd, true);
3084
3085 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
3086 }
3087
3088 /* ----------------------------------------------------------------------- */
3089
3090 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
3091 {
3092 /*
3093 * From ADV784x external Memory test.pdf
3094 *
3095 * Reset must just been performed before running test.
3096 * Recommended to reset after test.
3097 */
3098 int i;
3099 int pass = 0;
3100 int fail = 0;
3101 int complete = 0;
3102
3103 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
3104 io_write(sd, 0x01, 0x00); /* Program SDP mode */
3105 afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */
3106 afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */
3107 afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */
3108 afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */
3109 afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */
3110 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
3111 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
3112 io_write(sd, 0x15, 0xBA); /* Enable outputs */
3113 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
3114 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
3115
3116 usleep_range(5000, 6000);
3117
3118 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
3119 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
3120 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
3121 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
3122 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
3123 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
3124 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
3125 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
3126 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
3127 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
3128 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
3129
3130 usleep_range(5000, 6000);
3131
3132 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
3133 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
3134
3135 msleep(20);
3136
3137 for (i = 0; i < 10; i++) {
3138 u8 result = sdp_io_read(sd, 0xdb);
3139 if (result & 0x10) {
3140 complete++;
3141 if (result & 0x20)
3142 fail++;
3143 else
3144 pass++;
3145 }
3146 msleep(20);
3147 }
3148
3149 v4l2_dbg(1, debug, sd,
3150 "Ram Test: completed %d of %d: pass %d, fail %d\n",
3151 complete, i, pass, fail);
3152
3153 if (!complete || fail)
3154 return -EIO;
3155 return 0;
3156 }
3157
3158 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
3159 struct adv7842_platform_data *pdata)
3160 {
3161 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
3162 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
3163 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
3164 io_write(sd, 0xf4, pdata->i2c_cec << 1);
3165 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
3166
3167 io_write(sd, 0xf8, pdata->i2c_afe << 1);
3168 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
3169 io_write(sd, 0xfa, pdata->i2c_edid << 1);
3170 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
3171
3172 io_write(sd, 0xfd, pdata->i2c_cp << 1);
3173 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
3174 }
3175
3176 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
3177 {
3178 struct i2c_client *client = v4l2_get_subdevdata(sd);
3179 struct adv7842_state *state = to_state(sd);
3180 struct adv7842_platform_data *pdata = client->dev.platform_data;
3181 struct v4l2_dv_timings timings;
3182 int ret = 0;
3183
3184 if (!pdata)
3185 return -ENODEV;
3186
3187 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
3188 v4l2_info(sd, "no sdram or no ddr sdram\n");
3189 return -EINVAL;
3190 }
3191
3192 main_reset(sd);
3193
3194 adv7842_rewrite_i2c_addresses(sd, pdata);
3195
3196 /* run ram test */
3197 ret = adv7842_ddr_ram_test(sd);
3198
3199 main_reset(sd);
3200
3201 adv7842_rewrite_i2c_addresses(sd, pdata);
3202
3203 /* and re-init chip and state */
3204 adv7842_core_init(sd);
3205
3206 disable_input(sd);
3207
3208 select_input(sd, state->vid_std_select);
3209
3210 enable_input(sd);
3211
3212 edid_write_vga_segment(sd);
3213 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
3214 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
3215
3216 timings = state->timings;
3217
3218 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
3219
3220 adv7842_s_dv_timings(sd, &timings);
3221
3222 return ret;
3223 }
3224
3225 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
3226 {
3227 switch (cmd) {
3228 case ADV7842_CMD_RAM_TEST:
3229 return adv7842_command_ram_test(sd);
3230 }
3231 return -ENOTTY;
3232 }
3233
3234 static int adv7842_subscribe_event(struct v4l2_subdev *sd,
3235 struct v4l2_fh *fh,
3236 struct v4l2_event_subscription *sub)
3237 {
3238 switch (sub->type) {
3239 case V4L2_EVENT_SOURCE_CHANGE:
3240 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
3241 case V4L2_EVENT_CTRL:
3242 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
3243 default:
3244 return -EINVAL;
3245 }
3246 }
3247
3248 static int adv7842_registered(struct v4l2_subdev *sd)
3249 {
3250 struct adv7842_state *state = to_state(sd);
3251 struct i2c_client *client = v4l2_get_subdevdata(sd);
3252 int err;
3253
3254 err = cec_register_adapter(state->cec_adap, &client->dev);
3255 if (err)
3256 cec_delete_adapter(state->cec_adap);
3257 return err;
3258 }
3259
3260 static void adv7842_unregistered(struct v4l2_subdev *sd)
3261 {
3262 struct adv7842_state *state = to_state(sd);
3263
3264 cec_unregister_adapter(state->cec_adap);
3265 }
3266
3267 /* ----------------------------------------------------------------------- */
3268
3269 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
3270 .s_ctrl = adv7842_s_ctrl,
3271 .g_volatile_ctrl = adv7842_g_volatile_ctrl,
3272 };
3273
3274 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
3275 .log_status = adv7842_log_status,
3276 .ioctl = adv7842_ioctl,
3277 .interrupt_service_routine = adv7842_isr,
3278 .subscribe_event = adv7842_subscribe_event,
3279 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
3280 #ifdef CONFIG_VIDEO_ADV_DEBUG
3281 .g_register = adv7842_g_register,
3282 .s_register = adv7842_s_register,
3283 #endif
3284 };
3285
3286 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
3287 .g_std = adv7842_g_std,
3288 .s_std = adv7842_s_std,
3289 .s_routing = adv7842_s_routing,
3290 .querystd = adv7842_querystd,
3291 .g_input_status = adv7842_g_input_status,
3292 .s_dv_timings = adv7842_s_dv_timings,
3293 .g_dv_timings = adv7842_g_dv_timings,
3294 .query_dv_timings = adv7842_query_dv_timings,
3295 };
3296
3297 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
3298 .enum_mbus_code = adv7842_enum_mbus_code,
3299 .get_fmt = adv7842_get_format,
3300 .set_fmt = adv7842_set_format,
3301 .get_edid = adv7842_get_edid,
3302 .set_edid = adv7842_set_edid,
3303 .enum_dv_timings = adv7842_enum_dv_timings,
3304 .dv_timings_cap = adv7842_dv_timings_cap,
3305 };
3306
3307 static const struct v4l2_subdev_ops adv7842_ops = {
3308 .core = &adv7842_core_ops,
3309 .video = &adv7842_video_ops,
3310 .pad = &adv7842_pad_ops,
3311 };
3312
3313 static const struct v4l2_subdev_internal_ops adv7842_int_ops = {
3314 .registered = adv7842_registered,
3315 .unregistered = adv7842_unregistered,
3316 };
3317
3318 /* -------------------------- custom ctrls ---------------------------------- */
3319
3320 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
3321 .ops = &adv7842_ctrl_ops,
3322 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
3323 .name = "Analog Sampling Phase",
3324 .type = V4L2_CTRL_TYPE_INTEGER,
3325 .min = 0,
3326 .max = 0x1f,
3327 .step = 1,
3328 .def = 0,
3329 };
3330
3331 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
3332 .ops = &adv7842_ctrl_ops,
3333 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
3334 .name = "Free Running Color, Manual",
3335 .type = V4L2_CTRL_TYPE_BOOLEAN,
3336 .max = 1,
3337 .step = 1,
3338 .def = 1,
3339 };
3340
3341 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
3342 .ops = &adv7842_ctrl_ops,
3343 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
3344 .name = "Free Running Color",
3345 .type = V4L2_CTRL_TYPE_INTEGER,
3346 .max = 0xffffff,
3347 .step = 0x1,
3348 };
3349
3350
3351 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
3352 {
3353 struct adv7842_state *state = to_state(sd);
3354 i2c_unregister_device(state->i2c_avlink);
3355 i2c_unregister_device(state->i2c_cec);
3356 i2c_unregister_device(state->i2c_infoframe);
3357 i2c_unregister_device(state->i2c_sdp_io);
3358 i2c_unregister_device(state->i2c_sdp);
3359 i2c_unregister_device(state->i2c_afe);
3360 i2c_unregister_device(state->i2c_repeater);
3361 i2c_unregister_device(state->i2c_edid);
3362 i2c_unregister_device(state->i2c_hdmi);
3363 i2c_unregister_device(state->i2c_cp);
3364 i2c_unregister_device(state->i2c_vdp);
3365
3366 state->i2c_avlink = NULL;
3367 state->i2c_cec = NULL;
3368 state->i2c_infoframe = NULL;
3369 state->i2c_sdp_io = NULL;
3370 state->i2c_sdp = NULL;
3371 state->i2c_afe = NULL;
3372 state->i2c_repeater = NULL;
3373 state->i2c_edid = NULL;
3374 state->i2c_hdmi = NULL;
3375 state->i2c_cp = NULL;
3376 state->i2c_vdp = NULL;
3377 }
3378
3379 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
3380 u8 addr, u8 io_reg)
3381 {
3382 struct i2c_client *client = v4l2_get_subdevdata(sd);
3383 struct i2c_client *cp;
3384
3385 io_write(sd, io_reg, addr << 1);
3386
3387 if (addr == 0) {
3388 v4l2_err(sd, "no %s i2c addr configured\n", desc);
3389 return NULL;
3390 }
3391
3392 cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1);
3393 if (IS_ERR(cp)) {
3394 v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n",
3395 desc, addr, PTR_ERR(cp));
3396 cp = NULL;
3397 }
3398
3399 return cp;
3400 }
3401
3402 static int adv7842_register_clients(struct v4l2_subdev *sd)
3403 {
3404 struct adv7842_state *state = to_state(sd);
3405 struct adv7842_platform_data *pdata = &state->pdata;
3406
3407 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
3408 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
3409 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3410 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3411 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3412 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3413 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3414 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3415 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3416 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3417 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3418
3419 if (!state->i2c_avlink ||
3420 !state->i2c_cec ||
3421 !state->i2c_infoframe ||
3422 !state->i2c_sdp_io ||
3423 !state->i2c_sdp ||
3424 !state->i2c_afe ||
3425 !state->i2c_repeater ||
3426 !state->i2c_edid ||
3427 !state->i2c_hdmi ||
3428 !state->i2c_cp ||
3429 !state->i2c_vdp)
3430 return -1;
3431
3432 return 0;
3433 }
3434
3435 static int adv7842_probe(struct i2c_client *client,
3436 const struct i2c_device_id *id)
3437 {
3438 struct adv7842_state *state;
3439 static const struct v4l2_dv_timings cea640x480 =
3440 V4L2_DV_BT_CEA_640X480P59_94;
3441 struct adv7842_platform_data *pdata = client->dev.platform_data;
3442 struct v4l2_ctrl_handler *hdl;
3443 struct v4l2_ctrl *ctrl;
3444 struct v4l2_subdev *sd;
3445 u16 rev;
3446 int err;
3447
3448 /* Check if the adapter supports the needed features */
3449 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3450 return -EIO;
3451
3452 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
3453 client->addr << 1);
3454
3455 if (!pdata) {
3456 v4l_err(client, "No platform data!\n");
3457 return -ENODEV;
3458 }
3459
3460 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3461 if (!state)
3462 return -ENOMEM;
3463
3464 /* platform data */
3465 state->pdata = *pdata;
3466 state->timings = cea640x480;
3467 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3468
3469 sd = &state->sd;
3470 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
3471 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3472 sd->internal_ops = &adv7842_int_ops;
3473 state->mode = pdata->mode;
3474
3475 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
3476 state->restart_stdi_once = true;
3477
3478 /* i2c access to adv7842? */
3479 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3480 adv_smbus_read_byte_data_check(client, 0xeb, false);
3481 if (rev != 0x2012) {
3482 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3483 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3484 adv_smbus_read_byte_data_check(client, 0xeb, false);
3485 }
3486 if (rev != 0x2012) {
3487 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3488 client->addr << 1, rev);
3489 return -ENODEV;
3490 }
3491
3492 if (pdata->chip_reset)
3493 main_reset(sd);
3494
3495 /* control handlers */
3496 hdl = &state->hdl;
3497 v4l2_ctrl_handler_init(hdl, 6);
3498
3499 /* add in ascending ID order */
3500 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3501 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3502 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3503 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3504 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3505 V4L2_CID_SATURATION, 0, 255, 1, 128);
3506 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3507 V4L2_CID_HUE, 0, 128, 1, 0);
3508 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3509 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3510 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3511 if (ctrl)
3512 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3513
3514 /* custom controls */
3515 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3516 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3517 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3518 &adv7842_ctrl_analog_sampling_phase, NULL);
3519 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3520 &adv7842_ctrl_free_run_color_manual, NULL);
3521 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3522 &adv7842_ctrl_free_run_color, NULL);
3523 state->rgb_quantization_range_ctrl =
3524 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3525 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3526 0, V4L2_DV_RGB_RANGE_AUTO);
3527 sd->ctrl_handler = hdl;
3528 if (hdl->error) {
3529 err = hdl->error;
3530 goto err_hdl;
3531 }
3532 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3533 err = -ENODEV;
3534 goto err_hdl;
3535 }
3536
3537 if (adv7842_register_clients(sd) < 0) {
3538 err = -ENOMEM;
3539 v4l2_err(sd, "failed to create all i2c clients\n");
3540 goto err_i2c;
3541 }
3542
3543
3544 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3545 adv7842_delayed_work_enable_hotplug);
3546
3547 sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3548 state->pad.flags = MEDIA_PAD_FL_SOURCE;
3549 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
3550 if (err)
3551 goto err_work_queues;
3552
3553 err = adv7842_core_init(sd);
3554 if (err)
3555 goto err_entity;
3556
3557 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
3558 state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops,
3559 state, dev_name(&client->dev),
3560 CEC_CAP_DEFAULTS, ADV7842_MAX_ADDRS);
3561 err = PTR_ERR_OR_ZERO(state->cec_adap);
3562 if (err)
3563 goto err_entity;
3564 #endif
3565
3566 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3567 client->addr << 1, client->adapter->name);
3568 return 0;
3569
3570 err_entity:
3571 media_entity_cleanup(&sd->entity);
3572 err_work_queues:
3573 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3574 err_i2c:
3575 adv7842_unregister_clients(sd);
3576 err_hdl:
3577 v4l2_ctrl_handler_free(hdl);
3578 return err;
3579 }
3580
3581 /* ----------------------------------------------------------------------- */
3582
3583 static int adv7842_remove(struct i2c_client *client)
3584 {
3585 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3586 struct adv7842_state *state = to_state(sd);
3587
3588 adv7842_irq_enable(sd, false);
3589 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3590 v4l2_device_unregister_subdev(sd);
3591 media_entity_cleanup(&sd->entity);
3592 adv7842_unregister_clients(sd);
3593 v4l2_ctrl_handler_free(sd->ctrl_handler);
3594 return 0;
3595 }
3596
3597 /* ----------------------------------------------------------------------- */
3598
3599 static const struct i2c_device_id adv7842_id[] = {
3600 { "adv7842", 0 },
3601 { }
3602 };
3603 MODULE_DEVICE_TABLE(i2c, adv7842_id);
3604
3605 /* ----------------------------------------------------------------------- */
3606
3607 static struct i2c_driver adv7842_driver = {
3608 .driver = {
3609 .name = "adv7842",
3610 },
3611 .probe = adv7842_probe,
3612 .remove = adv7842_remove,
3613 .id_table = adv7842_id,
3614 };
3615
3616 module_i2c_driver(adv7842_driver);
Linux with added FPC-III support