1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Samsung S5K6AAFX SXGA 1/6" 1.3M CMOS Image Sensor
4 * with embedded SoC ISP.
6 * Copyright (C) 2011, Samsung Electronics Co., Ltd.
7 * Sylwester Nawrocki <s.nawrocki@samsung.com>
9 * Based on a driver authored by Dongsoo Nathaniel Kim.
10 * Copyright (C) 2009, Dongsoo Nathaniel Kim <dongsoo45.kim@samsung.com>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/gpio.h>
16 #include <linux/i2c.h>
17 #include <linux/media.h>
18 #include <linux/module.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/slab.h>
22 #include <media/media-entity.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-subdev.h>
26 #include <media/v4l2-mediabus.h>
27 #include <media/i2c/s5k6aa.h>
30 module_param(debug
, int, 0644);
32 #define DRIVER_NAME "S5K6AA"
34 /* The token to indicate array termination */
35 #define S5K6AA_TERM 0xffff
36 #define S5K6AA_OUT_WIDTH_DEF 640
37 #define S5K6AA_OUT_HEIGHT_DEF 480
38 #define S5K6AA_WIN_WIDTH_MAX 1280
39 #define S5K6AA_WIN_HEIGHT_MAX 1024
40 #define S5K6AA_WIN_WIDTH_MIN 8
41 #define S5K6AA_WIN_HEIGHT_MIN 8
44 * H/W register Interface (0xD0000000 - 0xD0000FFF)
46 #define AHB_MSB_ADDR_PTR 0xfcfc
47 #define GEN_REG_OFFSH 0xd000
48 #define REG_CMDWR_ADDRH 0x0028
49 #define REG_CMDWR_ADDRL 0x002a
50 #define REG_CMDRD_ADDRH 0x002c
51 #define REG_CMDRD_ADDRL 0x002e
52 #define REG_CMDBUF0_ADDR 0x0f12
53 #define REG_CMDBUF1_ADDR 0x0f10
56 * Host S/W Register interface (0x70000000 - 0x70002000)
57 * The value of the two most significant address bytes is 0x7000,
58 * (HOST_SWIF_OFFS_H). The register addresses below specify 2 LSBs.
60 #define HOST_SWIF_OFFSH 0x7000
62 /* Initialization parameters */
63 /* Master clock frequency in KHz */
64 #define REG_I_INCLK_FREQ_L 0x01b8
65 #define REG_I_INCLK_FREQ_H 0x01ba
66 #define MIN_MCLK_FREQ_KHZ 6000U
67 #define MAX_MCLK_FREQ_KHZ 27000U
68 #define REG_I_USE_NPVI_CLOCKS 0x01c6
69 #define REG_I_USE_NMIPI_CLOCKS 0x01c8
71 /* Clock configurations, n = 0..2. REG_I_* frequency unit is 4 kHz. */
72 #define REG_I_OPCLK_4KHZ(n) ((n) * 6 + 0x01cc)
73 #define REG_I_MIN_OUTRATE_4KHZ(n) ((n) * 6 + 0x01ce)
74 #define REG_I_MAX_OUTRATE_4KHZ(n) ((n) * 6 + 0x01d0)
75 #define SYS_PLL_OUT_FREQ (48000000 / 4000)
76 #define PCLK_FREQ_MIN (24000000 / 4000)
77 #define PCLK_FREQ_MAX (48000000 / 4000)
78 #define REG_I_INIT_PARAMS_UPDATED 0x01e0
79 #define REG_I_ERROR_INFO 0x01e2
81 /* General purpose parameters */
82 #define REG_USER_BRIGHTNESS 0x01e4
83 #define REG_USER_CONTRAST 0x01e6
84 #define REG_USER_SATURATION 0x01e8
85 #define REG_USER_SHARPBLUR 0x01ea
87 #define REG_G_SPEC_EFFECTS 0x01ee
88 #define REG_G_ENABLE_PREV 0x01f0
89 #define REG_G_ENABLE_PREV_CHG 0x01f2
90 #define REG_G_NEW_CFG_SYNC 0x01f8
91 #define REG_G_PREVZOOM_IN_WIDTH 0x020a
92 #define REG_G_PREVZOOM_IN_HEIGHT 0x020c
93 #define REG_G_PREVZOOM_IN_XOFFS 0x020e
94 #define REG_G_PREVZOOM_IN_YOFFS 0x0210
95 #define REG_G_INPUTS_CHANGE_REQ 0x021a
96 #define REG_G_ACTIVE_PREV_CFG 0x021c
97 #define REG_G_PREV_CFG_CHG 0x021e
98 #define REG_G_PREV_OPEN_AFTER_CH 0x0220
99 #define REG_G_PREV_CFG_ERROR 0x0222
101 /* Preview control section. n = 0...4. */
102 #define PREG(n, x) ((n) * 0x26 + x)
103 #define REG_P_OUT_WIDTH(n) PREG(n, 0x0242)
104 #define REG_P_OUT_HEIGHT(n) PREG(n, 0x0244)
105 #define REG_P_FMT(n) PREG(n, 0x0246)
106 #define REG_P_MAX_OUT_RATE(n) PREG(n, 0x0248)
107 #define REG_P_MIN_OUT_RATE(n) PREG(n, 0x024a)
108 #define REG_P_PVI_MASK(n) PREG(n, 0x024c)
109 #define REG_P_CLK_INDEX(n) PREG(n, 0x024e)
110 #define REG_P_FR_RATE_TYPE(n) PREG(n, 0x0250)
111 #define FR_RATE_DYNAMIC 0
112 #define FR_RATE_FIXED 1
113 #define FR_RATE_FIXED_ACCURATE 2
114 #define REG_P_FR_RATE_Q_TYPE(n) PREG(n, 0x0252)
115 #define FR_RATE_Q_BEST_FRRATE 1 /* Binning enabled */
116 #define FR_RATE_Q_BEST_QUALITY 2 /* Binning disabled */
117 /* Frame period in 0.1 ms units */
118 #define REG_P_MAX_FR_TIME(n) PREG(n, 0x0254)
119 #define REG_P_MIN_FR_TIME(n) PREG(n, 0x0256)
120 /* Conversion to REG_P_[MAX/MIN]_FR_TIME value; __t: time in us */
121 #define US_TO_FR_TIME(__t) ((__t) / 100)
122 #define S5K6AA_MIN_FR_TIME 33300 /* us */
123 #define S5K6AA_MAX_FR_TIME 650000 /* us */
124 #define S5K6AA_MAX_HIGHRES_FR_TIME 666 /* x100 us */
125 /* The below 5 registers are for "device correction" values */
126 #define REG_P_COLORTEMP(n) PREG(n, 0x025e)
127 #define REG_P_PREV_MIRROR(n) PREG(n, 0x0262)
129 /* Extended image property controls */
130 /* Exposure time in 10 us units */
131 #define REG_SF_USR_EXPOSURE_L 0x03c6
132 #define REG_SF_USR_EXPOSURE_H 0x03c8
133 #define REG_SF_USR_EXPOSURE_CHG 0x03ca
134 #define REG_SF_USR_TOT_GAIN 0x03cc
135 #define REG_SF_USR_TOT_GAIN_CHG 0x03ce
136 #define REG_SF_RGAIN 0x03d0
137 #define REG_SF_RGAIN_CHG 0x03d2
138 #define REG_SF_GGAIN 0x03d4
139 #define REG_SF_GGAIN_CHG 0x03d6
140 #define REG_SF_BGAIN 0x03d8
141 #define REG_SF_BGAIN_CHG 0x03da
142 #define REG_SF_FLICKER_QUANT 0x03dc
143 #define REG_SF_FLICKER_QUANT_CHG 0x03de
145 /* Output interface (parallel/MIPI) setup */
146 #define REG_OIF_EN_MIPI_LANES 0x03fa
147 #define REG_OIF_EN_PACKETS 0x03fc
148 #define REG_OIF_CFG_CHG 0x03fe
150 /* Auto-algorithms enable mask */
151 #define REG_DBG_AUTOALG_EN 0x0400
152 #define AALG_ALL_EN_MASK (1 << 0)
153 #define AALG_AE_EN_MASK (1 << 1)
154 #define AALG_DIVLEI_EN_MASK (1 << 2)
155 #define AALG_WB_EN_MASK (1 << 3)
156 #define AALG_FLICKER_EN_MASK (1 << 5)
157 #define AALG_FIT_EN_MASK (1 << 6)
158 #define AALG_WRHW_EN_MASK (1 << 7)
160 /* Firmware revision information */
161 #define REG_FW_APIVER 0x012e
162 #define S5K6AAFX_FW_APIVER 0x0001
163 #define REG_FW_REVISION 0x0130
165 /* For now we use only one user configuration register set */
166 #define S5K6AA_MAX_PRESETS 1
168 static const char * const s5k6aa_supply_names
[] = {
169 "vdd_core", /* Digital core supply 1.5V (1.4V to 1.6V) */
170 "vdda", /* Analog power supply 2.8V (2.6V to 3.0V) */
171 "vdd_reg", /* Regulator input power 1.8V (1.7V to 1.9V)
172 or 2.8V (2.6V to 3.0) */
173 "vddio", /* I/O supply 1.8V (1.65V to 1.95V)
174 or 2.8V (2.5V to 3.1V) */
176 #define S5K6AA_NUM_SUPPLIES ARRAY_SIZE(s5k6aa_supply_names)
178 enum s5k6aa_gpio_id
{
184 struct s5k6aa_regval
{
189 struct s5k6aa_pixfmt
{
192 /* REG_P_FMT(x) register value */
196 struct s5k6aa_preset
{
197 /* output pixel format and resolution */
198 struct v4l2_mbus_framefmt mbus_fmt
;
203 struct s5k6aa_ctrls
{
204 struct v4l2_ctrl_handler handler
;
205 /* Auto / manual white balance cluster */
206 struct v4l2_ctrl
*awb
;
207 struct v4l2_ctrl
*gain_red
;
208 struct v4l2_ctrl
*gain_blue
;
209 struct v4l2_ctrl
*gain_green
;
211 struct v4l2_ctrl
*hflip
;
212 struct v4l2_ctrl
*vflip
;
213 /* Auto exposure / manual exposure and gain cluster */
214 struct v4l2_ctrl
*auto_exp
;
215 struct v4l2_ctrl
*exposure
;
216 struct v4l2_ctrl
*gain
;
219 struct s5k6aa_interval
{
221 struct v4l2_fract interval
;
222 /* Maximum rectangle for the interval */
223 struct v4l2_frmsize_discrete size
;
227 struct v4l2_subdev sd
;
228 struct media_pad pad
;
230 enum v4l2_mbus_type bus_type
;
233 int (*s_power
)(int enable
);
234 struct regulator_bulk_data supplies
[S5K6AA_NUM_SUPPLIES
];
235 struct s5k6aa_gpio gpio
[GPIO_NUM
];
237 /* external master clock frequency */
238 unsigned long mclk_frequency
;
239 /* ISP internal master clock frequency */
241 /* output pixel clock frequency range */
245 unsigned int inv_hflip
:1;
246 unsigned int inv_vflip
:1;
248 /* protects the struct members below */
251 /* sensor matrix scan window */
252 struct v4l2_rect ccd_rect
;
254 struct s5k6aa_ctrls ctrls
;
255 struct s5k6aa_preset presets
[S5K6AA_MAX_PRESETS
];
256 struct s5k6aa_preset
*preset
;
257 const struct s5k6aa_interval
*fiv
;
259 unsigned int streaming
:1;
260 unsigned int apply_cfg
:1;
261 unsigned int apply_crop
:1;
265 static struct s5k6aa_regval s5k6aa_analog_config
[] = {
266 /* Analog settings */
267 { 0x112a, 0x0000 }, { 0x1132, 0x0000 },
268 { 0x113e, 0x0000 }, { 0x115c, 0x0000 },
269 { 0x1164, 0x0000 }, { 0x1174, 0x0000 },
270 { 0x1178, 0x0000 }, { 0x077a, 0x0000 },
271 { 0x077c, 0x0000 }, { 0x077e, 0x0000 },
272 { 0x0780, 0x0000 }, { 0x0782, 0x0000 },
273 { 0x0784, 0x0000 }, { 0x0786, 0x0000 },
274 { 0x0788, 0x0000 }, { 0x07a2, 0x0000 },
275 { 0x07a4, 0x0000 }, { 0x07a6, 0x0000 },
276 { 0x07a8, 0x0000 }, { 0x07b6, 0x0000 },
277 { 0x07b8, 0x0002 }, { 0x07ba, 0x0004 },
278 { 0x07bc, 0x0004 }, { 0x07be, 0x0005 },
279 { 0x07c0, 0x0005 }, { S5K6AA_TERM
, 0 },
282 /* TODO: Add RGB888 and Bayer format */
283 static const struct s5k6aa_pixfmt s5k6aa_formats
[] = {
284 { MEDIA_BUS_FMT_YUYV8_2X8
, V4L2_COLORSPACE_JPEG
, 5 },
286 { MEDIA_BUS_FMT_YUYV8_2X8
, V4L2_COLORSPACE_REC709
, 6 },
287 { MEDIA_BUS_FMT_RGB565_2X8_BE
, V4L2_COLORSPACE_JPEG
, 0 },
290 static const struct s5k6aa_interval s5k6aa_intervals
[] = {
291 { 1000, {10000, 1000000}, {1280, 1024} }, /* 10 fps */
292 { 666, {15000, 1000000}, {1280, 1024} }, /* 15 fps */
293 { 500, {20000, 1000000}, {1280, 720} }, /* 20 fps */
294 { 400, {25000, 1000000}, {640, 480} }, /* 25 fps */
295 { 333, {33300, 1000000}, {640, 480} }, /* 30 fps */
298 #define S5K6AA_INTERVAL_DEF_INDEX 1 /* 15 fps */
300 static inline struct v4l2_subdev
*ctrl_to_sd(struct v4l2_ctrl
*ctrl
)
302 return &container_of(ctrl
->handler
, struct s5k6aa
, ctrls
.handler
)->sd
;
305 static inline struct s5k6aa
*to_s5k6aa(struct v4l2_subdev
*sd
)
307 return container_of(sd
, struct s5k6aa
, sd
);
310 /* Set initial values for all preview presets */
311 static void s5k6aa_presets_data_init(struct s5k6aa
*s5k6aa
)
313 struct s5k6aa_preset
*preset
= &s5k6aa
->presets
[0];
316 for (i
= 0; i
< S5K6AA_MAX_PRESETS
; i
++) {
317 preset
->mbus_fmt
.width
= S5K6AA_OUT_WIDTH_DEF
;
318 preset
->mbus_fmt
.height
= S5K6AA_OUT_HEIGHT_DEF
;
319 preset
->mbus_fmt
.code
= s5k6aa_formats
[0].code
;
325 s5k6aa
->fiv
= &s5k6aa_intervals
[S5K6AA_INTERVAL_DEF_INDEX
];
326 s5k6aa
->preset
= &s5k6aa
->presets
[0];
329 static int s5k6aa_i2c_read(struct i2c_client
*client
, u16 addr
, u16
*val
)
331 u8 wbuf
[2] = {addr
>> 8, addr
& 0xFF};
332 struct i2c_msg msg
[2];
336 msg
[0].addr
= client
->addr
;
341 msg
[1].addr
= client
->addr
;
342 msg
[1].flags
= I2C_M_RD
;
346 ret
= i2c_transfer(client
->adapter
, msg
, 2);
347 *val
= be16_to_cpu(*((__be16
*)rbuf
));
349 v4l2_dbg(3, debug
, client
, "i2c_read: 0x%04X : 0x%04x\n", addr
, *val
);
351 return ret
== 2 ? 0 : ret
;
354 static int s5k6aa_i2c_write(struct i2c_client
*client
, u16 addr
, u16 val
)
356 u8 buf
[4] = {addr
>> 8, addr
& 0xFF, val
>> 8, val
& 0xFF};
358 int ret
= i2c_master_send(client
, buf
, 4);
359 v4l2_dbg(3, debug
, client
, "i2c_write: 0x%04X : 0x%04x\n", addr
, val
);
361 return ret
== 4 ? 0 : ret
;
364 /* The command register write, assumes Command_Wr_addH = 0x7000. */
365 static int s5k6aa_write(struct i2c_client
*c
, u16 addr
, u16 val
)
367 int ret
= s5k6aa_i2c_write(c
, REG_CMDWR_ADDRL
, addr
);
370 return s5k6aa_i2c_write(c
, REG_CMDBUF0_ADDR
, val
);
373 /* The command register read, assumes Command_Rd_addH = 0x7000. */
374 static int s5k6aa_read(struct i2c_client
*client
, u16 addr
, u16
*val
)
376 int ret
= s5k6aa_i2c_write(client
, REG_CMDRD_ADDRL
, addr
);
379 return s5k6aa_i2c_read(client
, REG_CMDBUF0_ADDR
, val
);
382 static int s5k6aa_write_array(struct v4l2_subdev
*sd
,
383 const struct s5k6aa_regval
*msg
)
385 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
389 while (msg
->addr
!= S5K6AA_TERM
) {
391 ret
= s5k6aa_i2c_write(client
, REG_CMDWR_ADDRL
,
395 ret
= s5k6aa_i2c_write(client
, REG_CMDBUF0_ADDR
, msg
->val
);
398 /* Assume that msg->addr is always less than 0xfffc */
399 addr_incr
= (msg
+ 1)->addr
- msg
->addr
;
406 /* Configure the AHB high address bytes for GTG registers access */
407 static int s5k6aa_set_ahb_address(struct i2c_client
*client
)
409 int ret
= s5k6aa_i2c_write(client
, AHB_MSB_ADDR_PTR
, GEN_REG_OFFSH
);
412 ret
= s5k6aa_i2c_write(client
, REG_CMDRD_ADDRH
, HOST_SWIF_OFFSH
);
415 return s5k6aa_i2c_write(client
, REG_CMDWR_ADDRH
, HOST_SWIF_OFFSH
);
419 * s5k6aa_configure_pixel_clock - apply ISP main clock/PLL configuration
420 * @s5k6aa: pointer to &struct s5k6aa describing the device
422 * Configure the internal ISP PLL for the required output frequency.
423 * Locking: called with s5k6aa.lock mutex held.
425 static int s5k6aa_configure_pixel_clocks(struct s5k6aa
*s5k6aa
)
427 struct i2c_client
*c
= v4l2_get_subdevdata(&s5k6aa
->sd
);
428 unsigned long fmclk
= s5k6aa
->mclk_frequency
/ 1000;
432 if (WARN(fmclk
< MIN_MCLK_FREQ_KHZ
|| fmclk
> MAX_MCLK_FREQ_KHZ
,
433 "Invalid clock frequency: %ld\n", fmclk
))
436 s5k6aa
->pclk_fmin
= PCLK_FREQ_MIN
;
437 s5k6aa
->pclk_fmax
= PCLK_FREQ_MAX
;
438 s5k6aa
->clk_fop
= SYS_PLL_OUT_FREQ
;
440 /* External input clock frequency in kHz */
441 ret
= s5k6aa_write(c
, REG_I_INCLK_FREQ_H
, fmclk
>> 16);
443 ret
= s5k6aa_write(c
, REG_I_INCLK_FREQ_L
, fmclk
& 0xFFFF);
445 ret
= s5k6aa_write(c
, REG_I_USE_NPVI_CLOCKS
, 1);
446 /* Internal PLL frequency */
448 ret
= s5k6aa_write(c
, REG_I_OPCLK_4KHZ(0), s5k6aa
->clk_fop
);
450 ret
= s5k6aa_write(c
, REG_I_MIN_OUTRATE_4KHZ(0),
453 ret
= s5k6aa_write(c
, REG_I_MAX_OUTRATE_4KHZ(0),
456 ret
= s5k6aa_write(c
, REG_I_INIT_PARAMS_UPDATED
, 1);
458 ret
= s5k6aa_read(c
, REG_I_ERROR_INFO
, &status
);
460 return ret
? ret
: (status
? -EINVAL
: 0);
463 /* Set horizontal and vertical image flipping */
464 static int s5k6aa_set_mirror(struct s5k6aa
*s5k6aa
, int horiz_flip
)
466 struct i2c_client
*client
= v4l2_get_subdevdata(&s5k6aa
->sd
);
467 int index
= s5k6aa
->preset
->index
;
469 unsigned int vflip
= s5k6aa
->ctrls
.vflip
->val
^ s5k6aa
->inv_vflip
;
470 unsigned int flip
= (horiz_flip
^ s5k6aa
->inv_hflip
) | (vflip
<< 1);
472 return s5k6aa_write(client
, REG_P_PREV_MIRROR(index
), flip
);
475 /* Configure auto/manual white balance and R/G/B gains */
476 static int s5k6aa_set_awb(struct s5k6aa
*s5k6aa
, int awb
)
478 struct i2c_client
*c
= v4l2_get_subdevdata(&s5k6aa
->sd
);
479 struct s5k6aa_ctrls
*ctrls
= &s5k6aa
->ctrls
;
482 int ret
= s5k6aa_read(c
, REG_DBG_AUTOALG_EN
, ®
);
485 ret
= s5k6aa_write(c
, REG_SF_RGAIN
, ctrls
->gain_red
->val
);
487 ret
= s5k6aa_write(c
, REG_SF_RGAIN_CHG
, 1);
491 ret
= s5k6aa_write(c
, REG_SF_GGAIN
, ctrls
->gain_green
->val
);
493 ret
= s5k6aa_write(c
, REG_SF_GGAIN_CHG
, 1);
497 ret
= s5k6aa_write(c
, REG_SF_BGAIN
, ctrls
->gain_blue
->val
);
499 ret
= s5k6aa_write(c
, REG_SF_BGAIN_CHG
, 1);
502 reg
= awb
? reg
| AALG_WB_EN_MASK
: reg
& ~AALG_WB_EN_MASK
;
503 ret
= s5k6aa_write(c
, REG_DBG_AUTOALG_EN
, reg
);
509 /* Program FW with exposure time, 'exposure' in us units */
510 static int s5k6aa_set_user_exposure(struct i2c_client
*client
, int exposure
)
512 unsigned int time
= exposure
/ 10;
514 int ret
= s5k6aa_write(client
, REG_SF_USR_EXPOSURE_L
, time
& 0xffff);
516 ret
= s5k6aa_write(client
, REG_SF_USR_EXPOSURE_H
, time
>> 16);
519 return s5k6aa_write(client
, REG_SF_USR_EXPOSURE_CHG
, 1);
522 static int s5k6aa_set_user_gain(struct i2c_client
*client
, int gain
)
524 int ret
= s5k6aa_write(client
, REG_SF_USR_TOT_GAIN
, gain
);
527 return s5k6aa_write(client
, REG_SF_USR_TOT_GAIN_CHG
, 1);
530 /* Set auto/manual exposure and total gain */
531 static int s5k6aa_set_auto_exposure(struct s5k6aa
*s5k6aa
, int value
)
533 struct i2c_client
*c
= v4l2_get_subdevdata(&s5k6aa
->sd
);
534 unsigned int exp_time
= s5k6aa
->ctrls
.exposure
->val
;
537 int ret
= s5k6aa_read(c
, REG_DBG_AUTOALG_EN
, &auto_alg
);
541 v4l2_dbg(1, debug
, c
, "man_exp: %d, auto_exp: %d, a_alg: 0x%x\n",
542 exp_time
, value
, auto_alg
);
544 if (value
== V4L2_EXPOSURE_AUTO
) {
545 auto_alg
|= AALG_AE_EN_MASK
| AALG_DIVLEI_EN_MASK
;
547 ret
= s5k6aa_set_user_exposure(c
, exp_time
);
550 ret
= s5k6aa_set_user_gain(c
, s5k6aa
->ctrls
.gain
->val
);
553 auto_alg
&= ~(AALG_AE_EN_MASK
| AALG_DIVLEI_EN_MASK
);
556 return s5k6aa_write(c
, REG_DBG_AUTOALG_EN
, auto_alg
);
559 static int s5k6aa_set_anti_flicker(struct s5k6aa
*s5k6aa
, int value
)
561 struct i2c_client
*client
= v4l2_get_subdevdata(&s5k6aa
->sd
);
565 ret
= s5k6aa_read(client
, REG_DBG_AUTOALG_EN
, &auto_alg
);
569 if (value
== V4L2_CID_POWER_LINE_FREQUENCY_AUTO
) {
570 auto_alg
|= AALG_FLICKER_EN_MASK
;
572 auto_alg
&= ~AALG_FLICKER_EN_MASK
;
573 /* The V4L2_CID_LINE_FREQUENCY control values match
574 * the register values */
575 ret
= s5k6aa_write(client
, REG_SF_FLICKER_QUANT
, value
);
578 ret
= s5k6aa_write(client
, REG_SF_FLICKER_QUANT_CHG
, 1);
583 return s5k6aa_write(client
, REG_DBG_AUTOALG_EN
, auto_alg
);
586 static int s5k6aa_set_colorfx(struct s5k6aa
*s5k6aa
, int val
)
588 struct i2c_client
*client
= v4l2_get_subdevdata(&s5k6aa
->sd
);
589 static const struct v4l2_control colorfx
[] = {
590 { V4L2_COLORFX_NONE
, 0 },
591 { V4L2_COLORFX_BW
, 1 },
592 { V4L2_COLORFX_NEGATIVE
, 2 },
593 { V4L2_COLORFX_SEPIA
, 3 },
594 { V4L2_COLORFX_SKY_BLUE
, 4 },
595 { V4L2_COLORFX_SKETCH
, 5 },
599 for (i
= 0; i
< ARRAY_SIZE(colorfx
); i
++) {
600 if (colorfx
[i
].id
== val
)
601 return s5k6aa_write(client
, REG_G_SPEC_EFFECTS
,
607 static int s5k6aa_preview_config_status(struct i2c_client
*client
)
610 int ret
= s5k6aa_read(client
, REG_G_PREV_CFG_ERROR
, &error
);
612 v4l2_dbg(1, debug
, client
, "error: 0x%x (%d)\n", error
, ret
);
613 return ret
? ret
: (error
? -EINVAL
: 0);
616 static int s5k6aa_get_pixfmt_index(struct s5k6aa
*s5k6aa
,
617 struct v4l2_mbus_framefmt
*mf
)
621 for (i
= 0; i
< ARRAY_SIZE(s5k6aa_formats
); i
++)
622 if (mf
->colorspace
== s5k6aa_formats
[i
].colorspace
&&
623 mf
->code
== s5k6aa_formats
[i
].code
)
628 static int s5k6aa_set_output_framefmt(struct s5k6aa
*s5k6aa
,
629 struct s5k6aa_preset
*preset
)
631 struct i2c_client
*client
= v4l2_get_subdevdata(&s5k6aa
->sd
);
632 int fmt_index
= s5k6aa_get_pixfmt_index(s5k6aa
, &preset
->mbus_fmt
);
635 ret
= s5k6aa_write(client
, REG_P_OUT_WIDTH(preset
->index
),
636 preset
->mbus_fmt
.width
);
638 ret
= s5k6aa_write(client
, REG_P_OUT_HEIGHT(preset
->index
),
639 preset
->mbus_fmt
.height
);
641 ret
= s5k6aa_write(client
, REG_P_FMT(preset
->index
),
642 s5k6aa_formats
[fmt_index
].reg_p_fmt
);
646 static int s5k6aa_set_input_params(struct s5k6aa
*s5k6aa
)
648 struct i2c_client
*c
= v4l2_get_subdevdata(&s5k6aa
->sd
);
649 struct v4l2_rect
*r
= &s5k6aa
->ccd_rect
;
652 ret
= s5k6aa_write(c
, REG_G_PREVZOOM_IN_WIDTH
, r
->width
);
654 ret
= s5k6aa_write(c
, REG_G_PREVZOOM_IN_HEIGHT
, r
->height
);
656 ret
= s5k6aa_write(c
, REG_G_PREVZOOM_IN_XOFFS
, r
->left
);
658 ret
= s5k6aa_write(c
, REG_G_PREVZOOM_IN_YOFFS
, r
->top
);
660 ret
= s5k6aa_write(c
, REG_G_INPUTS_CHANGE_REQ
, 1);
662 s5k6aa
->apply_crop
= 0;
668 * s5k6aa_configure_video_bus - configure the video output interface
669 * @s5k6aa: pointer to &struct s5k6aa describing the device
670 * @bus_type: video bus type: parallel or MIPI-CSI
671 * @nlanes: number of MIPI lanes to be used (MIPI-CSI only)
673 * Note: Only parallel bus operation has been tested.
675 static int s5k6aa_configure_video_bus(struct s5k6aa
*s5k6aa
,
676 enum v4l2_mbus_type bus_type
, int nlanes
)
678 struct i2c_client
*client
= v4l2_get_subdevdata(&s5k6aa
->sd
);
683 * TODO: The sensor is supposed to support BT.601 and BT.656
684 * but there is nothing indicating how to switch between both
685 * in the datasheet. For now default BT.601 interface is assumed.
687 if (bus_type
== V4L2_MBUS_CSI2_DPHY
)
689 else if (bus_type
!= V4L2_MBUS_PARALLEL
)
692 ret
= s5k6aa_write(client
, REG_OIF_EN_MIPI_LANES
, cfg
);
695 return s5k6aa_write(client
, REG_OIF_CFG_CHG
, 1);
698 /* This function should be called when switching to new user configuration set*/
699 static int s5k6aa_new_config_sync(struct i2c_client
*client
, int timeout
,
702 unsigned long end
= jiffies
+ msecs_to_jiffies(timeout
);
706 ret
= s5k6aa_write(client
, REG_G_ACTIVE_PREV_CFG
, cid
);
708 ret
= s5k6aa_write(client
, REG_G_PREV_CFG_CHG
, 1);
710 ret
= s5k6aa_write(client
, REG_G_NEW_CFG_SYNC
, 1);
714 while (ret
>= 0 && time_is_after_jiffies(end
)) {
715 ret
= s5k6aa_read(client
, REG_G_NEW_CFG_SYNC
, ®
);
718 usleep_range(1000, 5000);
720 return ret
? ret
: -ETIMEDOUT
;
724 * s5k6aa_set_prev_config - write user preview register set
725 * @s5k6aa: pointer to &struct s5k6aa describing the device
726 * @preset: s5kaa preset to be applied
728 * Configure output resolution and color format, pixel clock
729 * frequency range, device frame rate type and frame period range.
731 static int s5k6aa_set_prev_config(struct s5k6aa
*s5k6aa
,
732 struct s5k6aa_preset
*preset
)
734 struct i2c_client
*client
= v4l2_get_subdevdata(&s5k6aa
->sd
);
735 int idx
= preset
->index
;
739 if (s5k6aa
->fiv
->reg_fr_time
>= S5K6AA_MAX_HIGHRES_FR_TIME
)
740 frame_rate_q
= FR_RATE_Q_BEST_FRRATE
;
742 frame_rate_q
= FR_RATE_Q_BEST_QUALITY
;
744 ret
= s5k6aa_set_output_framefmt(s5k6aa
, preset
);
746 ret
= s5k6aa_write(client
, REG_P_MAX_OUT_RATE(idx
),
749 ret
= s5k6aa_write(client
, REG_P_MIN_OUT_RATE(idx
),
752 ret
= s5k6aa_write(client
, REG_P_CLK_INDEX(idx
),
755 ret
= s5k6aa_write(client
, REG_P_FR_RATE_TYPE(idx
),
758 ret
= s5k6aa_write(client
, REG_P_FR_RATE_Q_TYPE(idx
),
761 ret
= s5k6aa_write(client
, REG_P_MAX_FR_TIME(idx
),
762 s5k6aa
->fiv
->reg_fr_time
+ 33);
764 ret
= s5k6aa_write(client
, REG_P_MIN_FR_TIME(idx
),
765 s5k6aa
->fiv
->reg_fr_time
- 33);
767 ret
= s5k6aa_new_config_sync(client
, 250, idx
);
769 ret
= s5k6aa_preview_config_status(client
);
771 s5k6aa
->apply_cfg
= 0;
773 v4l2_dbg(1, debug
, client
, "Frame interval: %d +/- 3.3ms. (%d)\n",
774 s5k6aa
->fiv
->reg_fr_time
, ret
);
779 * s5k6aa_initialize_isp - basic ISP MCU initialization
780 * @sd: pointer to V4L2 sub-device descriptor
782 * Configure AHB addresses for registers read/write; configure PLLs for
783 * required output pixel clock. The ISP power supply needs to be already
784 * enabled, with an optional H/W reset.
785 * Locking: called with s5k6aa.lock mutex held.
787 static int s5k6aa_initialize_isp(struct v4l2_subdev
*sd
)
789 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
790 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
793 s5k6aa
->apply_crop
= 1;
794 s5k6aa
->apply_cfg
= 1;
797 ret
= s5k6aa_set_ahb_address(client
);
800 ret
= s5k6aa_configure_video_bus(s5k6aa
, s5k6aa
->bus_type
,
804 ret
= s5k6aa_write_array(sd
, s5k6aa_analog_config
);
809 return s5k6aa_configure_pixel_clocks(s5k6aa
);
812 static int s5k6aa_gpio_set_value(struct s5k6aa
*priv
, int id
, u32 val
)
814 if (!gpio_is_valid(priv
->gpio
[id
].gpio
))
816 gpio_set_value(priv
->gpio
[id
].gpio
, !!val
);
820 static int s5k6aa_gpio_assert(struct s5k6aa
*priv
, int id
)
822 return s5k6aa_gpio_set_value(priv
, id
, priv
->gpio
[id
].level
);
825 static int s5k6aa_gpio_deassert(struct s5k6aa
*priv
, int id
)
827 return s5k6aa_gpio_set_value(priv
, id
, !priv
->gpio
[id
].level
);
830 static int __s5k6aa_power_on(struct s5k6aa
*s5k6aa
)
834 ret
= regulator_bulk_enable(S5K6AA_NUM_SUPPLIES
, s5k6aa
->supplies
);
837 if (s5k6aa_gpio_deassert(s5k6aa
, STBY
))
838 usleep_range(150, 200);
841 ret
= s5k6aa
->s_power(1);
842 usleep_range(4000, 5000);
844 if (s5k6aa_gpio_deassert(s5k6aa
, RST
))
850 static int __s5k6aa_power_off(struct s5k6aa
*s5k6aa
)
854 if (s5k6aa_gpio_assert(s5k6aa
, RST
))
855 usleep_range(100, 150);
857 if (s5k6aa
->s_power
) {
858 ret
= s5k6aa
->s_power(0);
862 if (s5k6aa_gpio_assert(s5k6aa
, STBY
))
863 usleep_range(50, 100);
864 s5k6aa
->streaming
= 0;
866 return regulator_bulk_disable(S5K6AA_NUM_SUPPLIES
, s5k6aa
->supplies
);
870 * V4L2 subdev core and video operations
872 static int s5k6aa_set_power(struct v4l2_subdev
*sd
, int on
)
874 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
877 mutex_lock(&s5k6aa
->lock
);
879 if (s5k6aa
->power
== !on
) {
881 ret
= __s5k6aa_power_on(s5k6aa
);
883 ret
= s5k6aa_initialize_isp(sd
);
885 ret
= __s5k6aa_power_off(s5k6aa
);
889 s5k6aa
->power
+= on
? 1 : -1;
892 mutex_unlock(&s5k6aa
->lock
);
894 if (!on
|| ret
|| s5k6aa
->power
!= 1)
897 return v4l2_ctrl_handler_setup(sd
->ctrl_handler
);
900 static int __s5k6aa_stream(struct s5k6aa
*s5k6aa
, int enable
)
902 struct i2c_client
*client
= v4l2_get_subdevdata(&s5k6aa
->sd
);
905 ret
= s5k6aa_write(client
, REG_G_ENABLE_PREV
, enable
);
907 ret
= s5k6aa_write(client
, REG_G_ENABLE_PREV_CHG
, 1);
909 s5k6aa
->streaming
= enable
;
914 static int s5k6aa_s_stream(struct v4l2_subdev
*sd
, int on
)
916 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
919 mutex_lock(&s5k6aa
->lock
);
921 if (s5k6aa
->streaming
== !on
) {
922 if (!ret
&& s5k6aa
->apply_cfg
)
923 ret
= s5k6aa_set_prev_config(s5k6aa
, s5k6aa
->preset
);
924 if (s5k6aa
->apply_crop
)
925 ret
= s5k6aa_set_input_params(s5k6aa
);
927 ret
= __s5k6aa_stream(s5k6aa
, !!on
);
929 mutex_unlock(&s5k6aa
->lock
);
934 static int s5k6aa_g_frame_interval(struct v4l2_subdev
*sd
,
935 struct v4l2_subdev_frame_interval
*fi
)
937 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
939 mutex_lock(&s5k6aa
->lock
);
940 fi
->interval
= s5k6aa
->fiv
->interval
;
941 mutex_unlock(&s5k6aa
->lock
);
946 static int __s5k6aa_set_frame_interval(struct s5k6aa
*s5k6aa
,
947 struct v4l2_subdev_frame_interval
*fi
)
949 struct v4l2_mbus_framefmt
*mbus_fmt
= &s5k6aa
->preset
->mbus_fmt
;
950 const struct s5k6aa_interval
*fiv
= &s5k6aa_intervals
[0];
951 unsigned int err
, min_err
= UINT_MAX
;
952 unsigned int i
, fr_time
;
954 if (fi
->interval
.denominator
== 0)
957 fr_time
= fi
->interval
.numerator
* 10000 / fi
->interval
.denominator
;
959 for (i
= 0; i
< ARRAY_SIZE(s5k6aa_intervals
); i
++) {
960 const struct s5k6aa_interval
*iv
= &s5k6aa_intervals
[i
];
962 if (mbus_fmt
->width
> iv
->size
.width
||
963 mbus_fmt
->height
> iv
->size
.height
)
966 err
= abs(iv
->reg_fr_time
- fr_time
);
974 v4l2_dbg(1, debug
, &s5k6aa
->sd
, "Changed frame interval to %d us\n",
975 fiv
->reg_fr_time
* 100);
979 static int s5k6aa_s_frame_interval(struct v4l2_subdev
*sd
,
980 struct v4l2_subdev_frame_interval
*fi
)
982 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
985 v4l2_dbg(1, debug
, sd
, "Setting %d/%d frame interval\n",
986 fi
->interval
.numerator
, fi
->interval
.denominator
);
988 mutex_lock(&s5k6aa
->lock
);
989 ret
= __s5k6aa_set_frame_interval(s5k6aa
, fi
);
990 s5k6aa
->apply_cfg
= 1;
992 mutex_unlock(&s5k6aa
->lock
);
997 * V4L2 subdev pad level and video operations
999 static int s5k6aa_enum_frame_interval(struct v4l2_subdev
*sd
,
1000 struct v4l2_subdev_pad_config
*cfg
,
1001 struct v4l2_subdev_frame_interval_enum
*fie
)
1003 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
1004 const struct s5k6aa_interval
*fi
;
1007 if (fie
->index
>= ARRAY_SIZE(s5k6aa_intervals
))
1010 v4l_bound_align_image(&fie
->width
, S5K6AA_WIN_WIDTH_MIN
,
1011 S5K6AA_WIN_WIDTH_MAX
, 1,
1012 &fie
->height
, S5K6AA_WIN_HEIGHT_MIN
,
1013 S5K6AA_WIN_HEIGHT_MAX
, 1, 0);
1015 mutex_lock(&s5k6aa
->lock
);
1016 fi
= &s5k6aa_intervals
[fie
->index
];
1017 if (fie
->width
> fi
->size
.width
|| fie
->height
> fi
->size
.height
)
1020 fie
->interval
= fi
->interval
;
1021 mutex_unlock(&s5k6aa
->lock
);
1026 static int s5k6aa_enum_mbus_code(struct v4l2_subdev
*sd
,
1027 struct v4l2_subdev_pad_config
*cfg
,
1028 struct v4l2_subdev_mbus_code_enum
*code
)
1030 if (code
->index
>= ARRAY_SIZE(s5k6aa_formats
))
1033 code
->code
= s5k6aa_formats
[code
->index
].code
;
1037 static int s5k6aa_enum_frame_size(struct v4l2_subdev
*sd
,
1038 struct v4l2_subdev_pad_config
*cfg
,
1039 struct v4l2_subdev_frame_size_enum
*fse
)
1041 int i
= ARRAY_SIZE(s5k6aa_formats
);
1047 if (fse
->code
== s5k6aa_formats
[i
].code
)
1050 fse
->code
= s5k6aa_formats
[i
].code
;
1051 fse
->min_width
= S5K6AA_WIN_WIDTH_MIN
;
1052 fse
->max_width
= S5K6AA_WIN_WIDTH_MAX
;
1053 fse
->max_height
= S5K6AA_WIN_HEIGHT_MIN
;
1054 fse
->min_height
= S5K6AA_WIN_HEIGHT_MAX
;
1059 static struct v4l2_rect
*
1060 __s5k6aa_get_crop_rect(struct s5k6aa
*s5k6aa
, struct v4l2_subdev_pad_config
*cfg
,
1061 enum v4l2_subdev_format_whence which
)
1063 if (which
== V4L2_SUBDEV_FORMAT_ACTIVE
)
1064 return &s5k6aa
->ccd_rect
;
1066 WARN_ON(which
!= V4L2_SUBDEV_FORMAT_TRY
);
1067 return v4l2_subdev_get_try_crop(&s5k6aa
->sd
, cfg
, 0);
1070 static void s5k6aa_try_format(struct s5k6aa
*s5k6aa
,
1071 struct v4l2_mbus_framefmt
*mf
)
1075 v4l_bound_align_image(&mf
->width
, S5K6AA_WIN_WIDTH_MIN
,
1076 S5K6AA_WIN_WIDTH_MAX
, 1,
1077 &mf
->height
, S5K6AA_WIN_HEIGHT_MIN
,
1078 S5K6AA_WIN_HEIGHT_MAX
, 1, 0);
1080 if (mf
->colorspace
!= V4L2_COLORSPACE_JPEG
&&
1081 mf
->colorspace
!= V4L2_COLORSPACE_REC709
)
1082 mf
->colorspace
= V4L2_COLORSPACE_JPEG
;
1084 index
= s5k6aa_get_pixfmt_index(s5k6aa
, mf
);
1086 mf
->colorspace
= s5k6aa_formats
[index
].colorspace
;
1087 mf
->code
= s5k6aa_formats
[index
].code
;
1088 mf
->field
= V4L2_FIELD_NONE
;
1091 static int s5k6aa_get_fmt(struct v4l2_subdev
*sd
, struct v4l2_subdev_pad_config
*cfg
,
1092 struct v4l2_subdev_format
*fmt
)
1094 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
1095 struct v4l2_mbus_framefmt
*mf
;
1097 memset(fmt
->reserved
, 0, sizeof(fmt
->reserved
));
1099 if (fmt
->which
== V4L2_SUBDEV_FORMAT_TRY
) {
1100 mf
= v4l2_subdev_get_try_format(sd
, cfg
, 0);
1105 mutex_lock(&s5k6aa
->lock
);
1106 fmt
->format
= s5k6aa
->preset
->mbus_fmt
;
1107 mutex_unlock(&s5k6aa
->lock
);
1112 static int s5k6aa_set_fmt(struct v4l2_subdev
*sd
, struct v4l2_subdev_pad_config
*cfg
,
1113 struct v4l2_subdev_format
*fmt
)
1115 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
1116 struct s5k6aa_preset
*preset
= s5k6aa
->preset
;
1117 struct v4l2_mbus_framefmt
*mf
;
1118 struct v4l2_rect
*crop
;
1121 mutex_lock(&s5k6aa
->lock
);
1122 s5k6aa_try_format(s5k6aa
, &fmt
->format
);
1124 if (fmt
->which
== V4L2_SUBDEV_FORMAT_TRY
) {
1125 mf
= v4l2_subdev_get_try_format(sd
, cfg
, fmt
->pad
);
1126 crop
= v4l2_subdev_get_try_crop(sd
, cfg
, 0);
1128 if (s5k6aa
->streaming
) {
1131 mf
= &preset
->mbus_fmt
;
1132 crop
= &s5k6aa
->ccd_rect
;
1133 s5k6aa
->apply_cfg
= 1;
1138 struct v4l2_subdev_frame_interval fiv
= {
1144 * Make sure the crop window is valid, i.e. its size is
1145 * greater than the output window, as the ISP supports
1146 * only down-scaling.
1148 crop
->width
= clamp_t(unsigned int, crop
->width
, mf
->width
,
1149 S5K6AA_WIN_WIDTH_MAX
);
1150 crop
->height
= clamp_t(unsigned int, crop
->height
, mf
->height
,
1151 S5K6AA_WIN_HEIGHT_MAX
);
1152 crop
->left
= clamp_t(unsigned int, crop
->left
, 0,
1153 S5K6AA_WIN_WIDTH_MAX
- crop
->width
);
1154 crop
->top
= clamp_t(unsigned int, crop
->top
, 0,
1155 S5K6AA_WIN_HEIGHT_MAX
- crop
->height
);
1157 /* Reset to minimum possible frame interval */
1158 ret
= __s5k6aa_set_frame_interval(s5k6aa
, &fiv
);
1160 mutex_unlock(&s5k6aa
->lock
);
1165 static int s5k6aa_get_selection(struct v4l2_subdev
*sd
,
1166 struct v4l2_subdev_pad_config
*cfg
,
1167 struct v4l2_subdev_selection
*sel
)
1169 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
1170 struct v4l2_rect
*rect
;
1172 if (sel
->target
!= V4L2_SEL_TGT_CROP
)
1175 memset(sel
->reserved
, 0, sizeof(sel
->reserved
));
1177 mutex_lock(&s5k6aa
->lock
);
1178 rect
= __s5k6aa_get_crop_rect(s5k6aa
, cfg
, sel
->which
);
1180 mutex_unlock(&s5k6aa
->lock
);
1182 v4l2_dbg(1, debug
, sd
, "Current crop rectangle: (%d,%d)/%dx%d\n",
1183 rect
->left
, rect
->top
, rect
->width
, rect
->height
);
1188 static int s5k6aa_set_selection(struct v4l2_subdev
*sd
,
1189 struct v4l2_subdev_pad_config
*cfg
,
1190 struct v4l2_subdev_selection
*sel
)
1192 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
1193 struct v4l2_mbus_framefmt
*mf
;
1194 unsigned int max_x
, max_y
;
1195 struct v4l2_rect
*crop_r
;
1197 if (sel
->target
!= V4L2_SEL_TGT_CROP
)
1200 mutex_lock(&s5k6aa
->lock
);
1201 crop_r
= __s5k6aa_get_crop_rect(s5k6aa
, cfg
, sel
->which
);
1203 if (sel
->which
== V4L2_SUBDEV_FORMAT_ACTIVE
) {
1204 mf
= &s5k6aa
->preset
->mbus_fmt
;
1205 s5k6aa
->apply_crop
= 1;
1207 mf
= v4l2_subdev_get_try_format(sd
, cfg
, 0);
1209 v4l_bound_align_image(&sel
->r
.width
, mf
->width
,
1210 S5K6AA_WIN_WIDTH_MAX
, 1,
1211 &sel
->r
.height
, mf
->height
,
1212 S5K6AA_WIN_HEIGHT_MAX
, 1, 0);
1214 max_x
= (S5K6AA_WIN_WIDTH_MAX
- sel
->r
.width
) & ~1;
1215 max_y
= (S5K6AA_WIN_HEIGHT_MAX
- sel
->r
.height
) & ~1;
1217 sel
->r
.left
= clamp_t(unsigned int, sel
->r
.left
, 0, max_x
);
1218 sel
->r
.top
= clamp_t(unsigned int, sel
->r
.top
, 0, max_y
);
1222 mutex_unlock(&s5k6aa
->lock
);
1224 v4l2_dbg(1, debug
, sd
, "Set crop rectangle: (%d,%d)/%dx%d\n",
1225 crop_r
->left
, crop_r
->top
, crop_r
->width
, crop_r
->height
);
1230 static const struct v4l2_subdev_pad_ops s5k6aa_pad_ops
= {
1231 .enum_mbus_code
= s5k6aa_enum_mbus_code
,
1232 .enum_frame_size
= s5k6aa_enum_frame_size
,
1233 .enum_frame_interval
= s5k6aa_enum_frame_interval
,
1234 .get_fmt
= s5k6aa_get_fmt
,
1235 .set_fmt
= s5k6aa_set_fmt
,
1236 .get_selection
= s5k6aa_get_selection
,
1237 .set_selection
= s5k6aa_set_selection
,
1240 static const struct v4l2_subdev_video_ops s5k6aa_video_ops
= {
1241 .g_frame_interval
= s5k6aa_g_frame_interval
,
1242 .s_frame_interval
= s5k6aa_s_frame_interval
,
1243 .s_stream
= s5k6aa_s_stream
,
1247 * V4L2 subdev controls
1250 static int s5k6aa_s_ctrl(struct v4l2_ctrl
*ctrl
)
1252 struct v4l2_subdev
*sd
= ctrl_to_sd(ctrl
);
1253 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
1254 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
1257 v4l2_dbg(1, debug
, sd
, "ctrl: 0x%x, value: %d\n", ctrl
->id
, ctrl
->val
);
1259 mutex_lock(&s5k6aa
->lock
);
1261 * If the device is not powered up by the host driver do
1262 * not apply any controls to H/W at this time. Instead
1263 * the controls will be restored right after power-up.
1265 if (s5k6aa
->power
== 0)
1267 idx
= s5k6aa
->preset
->index
;
1270 case V4L2_CID_AUTO_WHITE_BALANCE
:
1271 err
= s5k6aa_set_awb(s5k6aa
, ctrl
->val
);
1274 case V4L2_CID_BRIGHTNESS
:
1275 err
= s5k6aa_write(client
, REG_USER_BRIGHTNESS
, ctrl
->val
);
1278 case V4L2_CID_COLORFX
:
1279 err
= s5k6aa_set_colorfx(s5k6aa
, ctrl
->val
);
1282 case V4L2_CID_CONTRAST
:
1283 err
= s5k6aa_write(client
, REG_USER_CONTRAST
, ctrl
->val
);
1286 case V4L2_CID_EXPOSURE_AUTO
:
1287 err
= s5k6aa_set_auto_exposure(s5k6aa
, ctrl
->val
);
1290 case V4L2_CID_HFLIP
:
1291 err
= s5k6aa_set_mirror(s5k6aa
, ctrl
->val
);
1294 err
= s5k6aa_write(client
, REG_G_PREV_CFG_CHG
, 1);
1297 case V4L2_CID_POWER_LINE_FREQUENCY
:
1298 err
= s5k6aa_set_anti_flicker(s5k6aa
, ctrl
->val
);
1301 case V4L2_CID_SATURATION
:
1302 err
= s5k6aa_write(client
, REG_USER_SATURATION
, ctrl
->val
);
1305 case V4L2_CID_SHARPNESS
:
1306 err
= s5k6aa_write(client
, REG_USER_SHARPBLUR
, ctrl
->val
);
1309 case V4L2_CID_WHITE_BALANCE_TEMPERATURE
:
1310 err
= s5k6aa_write(client
, REG_P_COLORTEMP(idx
), ctrl
->val
);
1313 err
= s5k6aa_write(client
, REG_G_PREV_CFG_CHG
, 1);
1317 mutex_unlock(&s5k6aa
->lock
);
1321 static const struct v4l2_ctrl_ops s5k6aa_ctrl_ops
= {
1322 .s_ctrl
= s5k6aa_s_ctrl
,
1325 static int s5k6aa_log_status(struct v4l2_subdev
*sd
)
1327 v4l2_ctrl_handler_log_status(sd
->ctrl_handler
, sd
->name
);
1331 #define V4L2_CID_RED_GAIN (V4L2_CTRL_CLASS_CAMERA | 0x1001)
1332 #define V4L2_CID_GREEN_GAIN (V4L2_CTRL_CLASS_CAMERA | 0x1002)
1333 #define V4L2_CID_BLUE_GAIN (V4L2_CTRL_CLASS_CAMERA | 0x1003)
1335 static const struct v4l2_ctrl_config s5k6aa_ctrls
[] = {
1337 .ops
= &s5k6aa_ctrl_ops
,
1338 .id
= V4L2_CID_RED_GAIN
,
1339 .type
= V4L2_CTRL_TYPE_INTEGER
,
1340 .name
= "Gain, Red",
1346 .ops
= &s5k6aa_ctrl_ops
,
1347 .id
= V4L2_CID_GREEN_GAIN
,
1348 .type
= V4L2_CTRL_TYPE_INTEGER
,
1349 .name
= "Gain, Green",
1355 .ops
= &s5k6aa_ctrl_ops
,
1356 .id
= V4L2_CID_BLUE_GAIN
,
1357 .type
= V4L2_CTRL_TYPE_INTEGER
,
1358 .name
= "Gain, Blue",
1366 static int s5k6aa_initialize_ctrls(struct s5k6aa
*s5k6aa
)
1368 const struct v4l2_ctrl_ops
*ops
= &s5k6aa_ctrl_ops
;
1369 struct s5k6aa_ctrls
*ctrls
= &s5k6aa
->ctrls
;
1370 struct v4l2_ctrl_handler
*hdl
= &ctrls
->handler
;
1372 int ret
= v4l2_ctrl_handler_init(hdl
, 16);
1375 /* Auto white balance cluster */
1376 ctrls
->awb
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_AUTO_WHITE_BALANCE
,
1378 ctrls
->gain_red
= v4l2_ctrl_new_custom(hdl
, &s5k6aa_ctrls
[0], NULL
);
1379 ctrls
->gain_green
= v4l2_ctrl_new_custom(hdl
, &s5k6aa_ctrls
[1], NULL
);
1380 ctrls
->gain_blue
= v4l2_ctrl_new_custom(hdl
, &s5k6aa_ctrls
[2], NULL
);
1381 v4l2_ctrl_auto_cluster(4, &ctrls
->awb
, 0, false);
1383 ctrls
->hflip
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_HFLIP
, 0, 1, 1, 0);
1384 ctrls
->vflip
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_VFLIP
, 0, 1, 1, 0);
1385 v4l2_ctrl_cluster(2, &ctrls
->hflip
);
1387 ctrls
->auto_exp
= v4l2_ctrl_new_std_menu(hdl
, ops
,
1388 V4L2_CID_EXPOSURE_AUTO
,
1389 V4L2_EXPOSURE_MANUAL
, 0, V4L2_EXPOSURE_AUTO
);
1390 /* Exposure time: x 1 us */
1391 ctrls
->exposure
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_EXPOSURE
,
1392 0, 6000000U, 1, 100000U);
1393 /* Total gain: 256 <=> 1x */
1394 ctrls
->gain
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_GAIN
,
1396 v4l2_ctrl_auto_cluster(3, &ctrls
->auto_exp
, 0, false);
1398 v4l2_ctrl_new_std_menu(hdl
, ops
, V4L2_CID_POWER_LINE_FREQUENCY
,
1399 V4L2_CID_POWER_LINE_FREQUENCY_AUTO
, 0,
1400 V4L2_CID_POWER_LINE_FREQUENCY_AUTO
);
1402 v4l2_ctrl_new_std_menu(hdl
, ops
, V4L2_CID_COLORFX
,
1403 V4L2_COLORFX_SKY_BLUE
, ~0x6f, V4L2_COLORFX_NONE
);
1405 v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_WHITE_BALANCE_TEMPERATURE
,
1408 v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_SATURATION
, -127, 127, 1, 0);
1409 v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_BRIGHTNESS
, -127, 127, 1, 0);
1410 v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_CONTRAST
, -127, 127, 1, 0);
1411 v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_SHARPNESS
, -127, 127, 1, 0);
1415 v4l2_ctrl_handler_free(hdl
);
1419 s5k6aa
->sd
.ctrl_handler
= hdl
;
1424 * V4L2 subdev internal operations
1426 static int s5k6aa_open(struct v4l2_subdev
*sd
, struct v4l2_subdev_fh
*fh
)
1428 struct v4l2_mbus_framefmt
*format
= v4l2_subdev_get_try_format(sd
, fh
->pad
, 0);
1429 struct v4l2_rect
*crop
= v4l2_subdev_get_try_crop(sd
, fh
->pad
, 0);
1431 format
->colorspace
= s5k6aa_formats
[0].colorspace
;
1432 format
->code
= s5k6aa_formats
[0].code
;
1433 format
->width
= S5K6AA_OUT_WIDTH_DEF
;
1434 format
->height
= S5K6AA_OUT_HEIGHT_DEF
;
1435 format
->field
= V4L2_FIELD_NONE
;
1437 crop
->width
= S5K6AA_WIN_WIDTH_MAX
;
1438 crop
->height
= S5K6AA_WIN_HEIGHT_MAX
;
1445 static int s5k6aa_check_fw_revision(struct s5k6aa
*s5k6aa
)
1447 struct i2c_client
*client
= v4l2_get_subdevdata(&s5k6aa
->sd
);
1448 u16 api_ver
= 0, fw_rev
= 0;
1450 int ret
= s5k6aa_set_ahb_address(client
);
1453 ret
= s5k6aa_read(client
, REG_FW_APIVER
, &api_ver
);
1455 ret
= s5k6aa_read(client
, REG_FW_REVISION
, &fw_rev
);
1457 v4l2_err(&s5k6aa
->sd
, "FW revision check failed!\n");
1461 v4l2_info(&s5k6aa
->sd
, "FW API ver.: 0x%X, FW rev.: 0x%X\n",
1464 return api_ver
== S5K6AAFX_FW_APIVER
? 0 : -ENODEV
;
1467 static int s5k6aa_registered(struct v4l2_subdev
*sd
)
1469 struct s5k6aa
*s5k6aa
= to_s5k6aa(sd
);
1472 mutex_lock(&s5k6aa
->lock
);
1473 ret
= __s5k6aa_power_on(s5k6aa
);
1476 ret
= s5k6aa_check_fw_revision(s5k6aa
);
1477 __s5k6aa_power_off(s5k6aa
);
1479 mutex_unlock(&s5k6aa
->lock
);
1484 static const struct v4l2_subdev_internal_ops s5k6aa_subdev_internal_ops
= {
1485 .registered
= s5k6aa_registered
,
1486 .open
= s5k6aa_open
,
1489 static const struct v4l2_subdev_core_ops s5k6aa_core_ops
= {
1490 .s_power
= s5k6aa_set_power
,
1491 .log_status
= s5k6aa_log_status
,
1494 static const struct v4l2_subdev_ops s5k6aa_subdev_ops
= {
1495 .core
= &s5k6aa_core_ops
,
1496 .pad
= &s5k6aa_pad_ops
,
1497 .video
= &s5k6aa_video_ops
,
1504 static int s5k6aa_configure_gpios(struct s5k6aa
*s5k6aa
,
1505 const struct s5k6aa_platform_data
*pdata
)
1507 struct i2c_client
*client
= v4l2_get_subdevdata(&s5k6aa
->sd
);
1508 const struct s5k6aa_gpio
*gpio
;
1509 unsigned long flags
;
1512 s5k6aa
->gpio
[STBY
].gpio
= -EINVAL
;
1513 s5k6aa
->gpio
[RST
].gpio
= -EINVAL
;
1515 gpio
= &pdata
->gpio_stby
;
1516 if (gpio_is_valid(gpio
->gpio
)) {
1517 flags
= (gpio
->level
? GPIOF_OUT_INIT_HIGH
: GPIOF_OUT_INIT_LOW
)
1519 ret
= devm_gpio_request_one(&client
->dev
, gpio
->gpio
, flags
,
1524 s5k6aa
->gpio
[STBY
] = *gpio
;
1527 gpio
= &pdata
->gpio_reset
;
1528 if (gpio_is_valid(gpio
->gpio
)) {
1529 flags
= (gpio
->level
? GPIOF_OUT_INIT_HIGH
: GPIOF_OUT_INIT_LOW
)
1531 ret
= devm_gpio_request_one(&client
->dev
, gpio
->gpio
, flags
,
1536 s5k6aa
->gpio
[RST
] = *gpio
;
1542 static int s5k6aa_probe(struct i2c_client
*client
,
1543 const struct i2c_device_id
*id
)
1545 const struct s5k6aa_platform_data
*pdata
= client
->dev
.platform_data
;
1546 struct v4l2_subdev
*sd
;
1547 struct s5k6aa
*s5k6aa
;
1550 if (pdata
== NULL
) {
1551 dev_err(&client
->dev
, "Platform data not specified\n");
1555 if (pdata
->mclk_frequency
== 0) {
1556 dev_err(&client
->dev
, "MCLK frequency not specified\n");
1560 s5k6aa
= devm_kzalloc(&client
->dev
, sizeof(*s5k6aa
), GFP_KERNEL
);
1564 mutex_init(&s5k6aa
->lock
);
1566 s5k6aa
->mclk_frequency
= pdata
->mclk_frequency
;
1567 s5k6aa
->bus_type
= pdata
->bus_type
;
1568 s5k6aa
->mipi_lanes
= pdata
->nlanes
;
1569 s5k6aa
->s_power
= pdata
->set_power
;
1570 s5k6aa
->inv_hflip
= pdata
->horiz_flip
;
1571 s5k6aa
->inv_vflip
= pdata
->vert_flip
;
1574 v4l2_i2c_subdev_init(sd
, client
, &s5k6aa_subdev_ops
);
1575 /* Static name; NEVER use in new drivers! */
1576 strscpy(sd
->name
, DRIVER_NAME
, sizeof(sd
->name
));
1578 sd
->internal_ops
= &s5k6aa_subdev_internal_ops
;
1579 sd
->flags
|= V4L2_SUBDEV_FL_HAS_DEVNODE
;
1581 s5k6aa
->pad
.flags
= MEDIA_PAD_FL_SOURCE
;
1582 sd
->entity
.function
= MEDIA_ENT_F_CAM_SENSOR
;
1583 ret
= media_entity_pads_init(&sd
->entity
, 1, &s5k6aa
->pad
);
1587 ret
= s5k6aa_configure_gpios(s5k6aa
, pdata
);
1591 for (i
= 0; i
< S5K6AA_NUM_SUPPLIES
; i
++)
1592 s5k6aa
->supplies
[i
].supply
= s5k6aa_supply_names
[i
];
1594 ret
= devm_regulator_bulk_get(&client
->dev
, S5K6AA_NUM_SUPPLIES
,
1597 dev_err(&client
->dev
, "Failed to get regulators\n");
1601 ret
= s5k6aa_initialize_ctrls(s5k6aa
);
1605 s5k6aa_presets_data_init(s5k6aa
);
1607 s5k6aa
->ccd_rect
.width
= S5K6AA_WIN_WIDTH_MAX
;
1608 s5k6aa
->ccd_rect
.height
= S5K6AA_WIN_HEIGHT_MAX
;
1609 s5k6aa
->ccd_rect
.left
= 0;
1610 s5k6aa
->ccd_rect
.top
= 0;
1615 media_entity_cleanup(&s5k6aa
->sd
.entity
);
1619 static int s5k6aa_remove(struct i2c_client
*client
)
1621 struct v4l2_subdev
*sd
= i2c_get_clientdata(client
);
1623 v4l2_device_unregister_subdev(sd
);
1624 v4l2_ctrl_handler_free(sd
->ctrl_handler
);
1625 media_entity_cleanup(&sd
->entity
);
1630 static const struct i2c_device_id s5k6aa_id
[] = {
1634 MODULE_DEVICE_TABLE(i2c
, s5k6aa_id
);
1637 static struct i2c_driver s5k6aa_i2c_driver
= {
1641 .probe
= s5k6aa_probe
,
1642 .remove
= s5k6aa_remove
,
1643 .id_table
= s5k6aa_id
,
1646 module_i2c_driver(s5k6aa_i2c_driver
);
1648 MODULE_DESCRIPTION("Samsung S5K6AA(FX) SXGA camera driver");
1649 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1650 MODULE_LICENSE("GPL");