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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / media / platform / rockchip / rkisp1 / rkisp1-isp.c
blob889982d8ca41d1763a57ac5247f46deb90fe65e6
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Rockchip ISP1 Driver - ISP Subdevice
4 *
5 * Copyright (C) 2019 Collabora, Ltd.
6 *
7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
9 */
10
11 #include <linux/iopoll.h>
12 #include <linux/phy/phy.h>
13 #include <linux/phy/phy-mipi-dphy.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/videodev2.h>
16 #include <linux/vmalloc.h>
17 #include <media/v4l2-event.h>
18
19 #include "rkisp1-common.h"
20
21 #define RKISP1_DEF_SINK_PAD_FMT MEDIA_BUS_FMT_SRGGB10_1X10
22 #define RKISP1_DEF_SRC_PAD_FMT MEDIA_BUS_FMT_YUYV8_2X8
23
24 #define RKISP1_ISP_DEV_NAME RKISP1_DRIVER_NAME "_isp"
25
26 /*
27 * NOTE: MIPI controller and input MUX are also configured in this file.
28 * This is because ISP Subdev describes not only ISP submodule (input size,
29 * format, output size, format), but also a virtual route device.
30 */
31
32 /*
33 * There are many variables named with format/frame in below code,
34 * please see here for their meaning.
35 * Cropping in the sink pad defines the image region from the sensor.
36 * Cropping in the source pad defines the region for the Image Stabilizer (IS)
37 *
38 * Cropping regions of ISP
39 *
40 * +---------------------------------------------------------+
41 * | Sensor image |
42 * | +---------------------------------------------------+ |
43 * | | CIF_ISP_ACQ (for black level) | |
44 * | | sink pad format | |
45 * | | +--------------------------------------------+ | |
46 * | | | CIF_ISP_OUT | | |
47 * | | | sink pad crop | | |
48 * | | | +---------------------------------+ | | |
49 * | | | | CIF_ISP_IS | | | |
50 * | | | | source pad crop and format | | | |
51 * | | | +---------------------------------+ | | |
52 * | | +--------------------------------------------+ | |
53 * | +---------------------------------------------------+ |
54 * +---------------------------------------------------------+
55 */
56
57 static const struct rkisp1_isp_mbus_info rkisp1_isp_formats[] = {
58 {
59 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
60 .pixel_enc = V4L2_PIXEL_ENC_YUV,
61 .direction = RKISP1_ISP_SD_SRC,
62 }, {
63 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
64 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
65 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
66 .bayer_pat = RKISP1_RAW_RGGB,
67 .bus_width = 10,
68 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
69 }, {
70 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
71 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
72 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
73 .bayer_pat = RKISP1_RAW_BGGR,
74 .bus_width = 10,
75 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
76 }, {
77 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
78 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
79 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
80 .bayer_pat = RKISP1_RAW_GBRG,
81 .bus_width = 10,
82 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
83 }, {
84 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
85 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
86 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
87 .bayer_pat = RKISP1_RAW_GRBG,
88 .bus_width = 10,
89 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
90 }, {
91 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
92 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
93 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
94 .bayer_pat = RKISP1_RAW_RGGB,
95 .bus_width = 12,
96 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
97 }, {
98 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
99 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
100 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
101 .bayer_pat = RKISP1_RAW_BGGR,
102 .bus_width = 12,
103 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
104 }, {
105 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
106 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
107 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
108 .bayer_pat = RKISP1_RAW_GBRG,
109 .bus_width = 12,
110 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
111 }, {
112 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
113 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
114 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
115 .bayer_pat = RKISP1_RAW_GRBG,
116 .bus_width = 12,
117 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
118 }, {
119 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
120 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
121 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
122 .bayer_pat = RKISP1_RAW_RGGB,
123 .bus_width = 8,
124 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
125 }, {
126 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
127 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
128 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
129 .bayer_pat = RKISP1_RAW_BGGR,
130 .bus_width = 8,
131 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
132 }, {
133 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
134 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
135 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
136 .bayer_pat = RKISP1_RAW_GBRG,
137 .bus_width = 8,
138 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
139 }, {
140 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
141 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
142 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
143 .bayer_pat = RKISP1_RAW_GRBG,
144 .bus_width = 8,
145 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
146 }, {
147 .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16,
148 .pixel_enc = V4L2_PIXEL_ENC_YUV,
149 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
150 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCBYCR,
151 .bus_width = 16,
152 .direction = RKISP1_ISP_SD_SINK,
153 }, {
154 .mbus_code = MEDIA_BUS_FMT_YVYU8_1X16,
155 .pixel_enc = V4L2_PIXEL_ENC_YUV,
156 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
157 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCRYCB,
158 .bus_width = 16,
159 .direction = RKISP1_ISP_SD_SINK,
160 }, {
161 .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16,
162 .pixel_enc = V4L2_PIXEL_ENC_YUV,
163 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
164 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CBYCRY,
165 .bus_width = 16,
166 .direction = RKISP1_ISP_SD_SINK,
167 }, {
168 .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16,
169 .pixel_enc = V4L2_PIXEL_ENC_YUV,
170 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
171 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CRYCBY,
172 .bus_width = 16,
173 .direction = RKISP1_ISP_SD_SINK,
174 },
175 };
176
177 /* ----------------------------------------------------------------------------
178 * Helpers
179 */
180
181 const struct rkisp1_isp_mbus_info *rkisp1_isp_mbus_info_get(u32 mbus_code)
182 {
183 unsigned int i;
184
185 for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) {
186 const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i];
187
188 if (fmt->mbus_code == mbus_code)
189 return fmt;
190 }
191
192 return NULL;
193 }
194
195 static struct v4l2_subdev *rkisp1_get_remote_sensor(struct v4l2_subdev *sd)
196 {
197 struct media_pad *local, *remote;
198 struct media_entity *sensor_me;
199
200 local = &sd->entity.pads[RKISP1_ISP_PAD_SINK_VIDEO];
201 remote = media_entity_remote_pad(local);
202 if (!remote)
203 return NULL;
204
205 sensor_me = remote->entity;
206 return media_entity_to_v4l2_subdev(sensor_me);
207 }
208
209 static struct v4l2_mbus_framefmt *
210 rkisp1_isp_get_pad_fmt(struct rkisp1_isp *isp,
211 struct v4l2_subdev_pad_config *cfg,
212 unsigned int pad, u32 which)
213 {
214 if (which == V4L2_SUBDEV_FORMAT_TRY)
215 return v4l2_subdev_get_try_format(&isp->sd, cfg, pad);
216 else
217 return v4l2_subdev_get_try_format(&isp->sd, isp->pad_cfg, pad);
218 }
219
220 static struct v4l2_rect *
221 rkisp1_isp_get_pad_crop(struct rkisp1_isp *isp,
222 struct v4l2_subdev_pad_config *cfg,
223 unsigned int pad, u32 which)
224 {
225 if (which == V4L2_SUBDEV_FORMAT_TRY)
226 return v4l2_subdev_get_try_crop(&isp->sd, cfg, pad);
227 else
228 return v4l2_subdev_get_try_crop(&isp->sd, isp->pad_cfg, pad);
229 }
230
231 /* ----------------------------------------------------------------------------
232 * Camera Interface registers configurations
233 */
234
235 /*
236 * Image Stabilization.
237 * This should only be called when configuring CIF
238 * or at the frame end interrupt
239 */
240 static void rkisp1_config_ism(struct rkisp1_device *rkisp1)
241 {
242 struct v4l2_rect *src_crop =
243 rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL,
244 RKISP1_ISP_PAD_SOURCE_VIDEO,
245 V4L2_SUBDEV_FORMAT_ACTIVE);
246 u32 val;
247
248 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_RECENTER);
249 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DX);
250 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DY);
251 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_DISPLACE);
252 rkisp1_write(rkisp1, src_crop->left, RKISP1_CIF_ISP_IS_H_OFFS);
253 rkisp1_write(rkisp1, src_crop->top, RKISP1_CIF_ISP_IS_V_OFFS);
254 rkisp1_write(rkisp1, src_crop->width, RKISP1_CIF_ISP_IS_H_SIZE);
255 rkisp1_write(rkisp1, src_crop->height, RKISP1_CIF_ISP_IS_V_SIZE);
256
257 /* IS(Image Stabilization) is always on, working as output crop */
258 rkisp1_write(rkisp1, 1, RKISP1_CIF_ISP_IS_CTRL);
259 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
260 val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD;
261 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
262 }
263
264 /*
265 * configure ISP blocks with input format, size......
266 */
267 static int rkisp1_config_isp(struct rkisp1_device *rkisp1)
268 {
269 u32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, signal = 0;
270 const struct rkisp1_isp_mbus_info *src_fmt, *sink_fmt;
271 struct rkisp1_sensor_async *sensor;
272 struct v4l2_mbus_framefmt *sink_frm;
273 struct v4l2_rect *sink_crop;
274
275 sensor = rkisp1->active_sensor;
276 sink_fmt = rkisp1->isp.sink_fmt;
277 src_fmt = rkisp1->isp.src_fmt;
278 sink_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL,
279 RKISP1_ISP_PAD_SINK_VIDEO,
280 V4L2_SUBDEV_FORMAT_ACTIVE);
281 sink_crop = rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL,
282 RKISP1_ISP_PAD_SINK_VIDEO,
283 V4L2_SUBDEV_FORMAT_ACTIVE);
284
285 if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
286 acq_mult = 1;
287 if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
288 if (sensor->mbus_type == V4L2_MBUS_BT656)
289 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656;
290 else
291 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT;
292 } else {
293 rkisp1_write(rkisp1, RKISP1_CIF_ISP_DEMOSAIC_TH(0xc),
294 RKISP1_CIF_ISP_DEMOSAIC);
295
296 if (sensor->mbus_type == V4L2_MBUS_BT656)
297 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656;
298 else
299 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601;
300 }
301 } else if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_YUV) {
302 acq_mult = 2;
303 if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
304 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601;
305 } else {
306 if (sensor->mbus_type == V4L2_MBUS_BT656)
307 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU656;
308 else
309 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601;
310 }
311
312 irq_mask |= RKISP1_CIF_ISP_DATA_LOSS;
313 }
314
315 /* Set up input acquisition properties */
316 if (sensor->mbus_type == V4L2_MBUS_BT656 ||
317 sensor->mbus_type == V4L2_MBUS_PARALLEL) {
318 if (sensor->mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
319 signal = RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE;
320 }
321
322 if (sensor->mbus_type == V4L2_MBUS_PARALLEL) {
323 if (sensor->mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
324 signal |= RKISP1_CIF_ISP_ACQ_PROP_VSYNC_LOW;
325
326 if (sensor->mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
327 signal |= RKISP1_CIF_ISP_ACQ_PROP_HSYNC_LOW;
328 }
329
330 rkisp1_write(rkisp1, isp_ctrl, RKISP1_CIF_ISP_CTRL);
331 rkisp1_write(rkisp1, signal | sink_fmt->yuv_seq |
332 RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT(sink_fmt->bayer_pat) |
333 RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL,
334 RKISP1_CIF_ISP_ACQ_PROP);
335 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_NR_FRAMES);
336
337 /* Acquisition Size */
338 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_H_OFFS);
339 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_V_OFFS);
340 rkisp1_write(rkisp1,
341 acq_mult * sink_frm->width, RKISP1_CIF_ISP_ACQ_H_SIZE);
342 rkisp1_write(rkisp1, sink_frm->height, RKISP1_CIF_ISP_ACQ_V_SIZE);
343
344 /* ISP Out Area */
345 rkisp1_write(rkisp1, sink_crop->left, RKISP1_CIF_ISP_OUT_H_OFFS);
346 rkisp1_write(rkisp1, sink_crop->top, RKISP1_CIF_ISP_OUT_V_OFFS);
347 rkisp1_write(rkisp1, sink_crop->width, RKISP1_CIF_ISP_OUT_H_SIZE);
348 rkisp1_write(rkisp1, sink_crop->height, RKISP1_CIF_ISP_OUT_V_SIZE);
349
350 irq_mask |= RKISP1_CIF_ISP_FRAME | RKISP1_CIF_ISP_V_START |
351 RKISP1_CIF_ISP_PIC_SIZE_ERROR;
352 rkisp1_write(rkisp1, irq_mask, RKISP1_CIF_ISP_IMSC);
353
354 if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
355 rkisp1_params_disable(&rkisp1->params);
356 } else {
357 struct v4l2_mbus_framefmt *src_frm;
358
359 src_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL,
360 RKISP1_ISP_PAD_SINK_VIDEO,
361 V4L2_SUBDEV_FORMAT_ACTIVE);
362 rkisp1_params_configure(&rkisp1->params, sink_fmt->bayer_pat,
363 src_frm->quantization);
364 }
365
366 return 0;
367 }
368
369 static int rkisp1_config_dvp(struct rkisp1_device *rkisp1)
370 {
371 const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt;
372 u32 val, input_sel;
373
374 switch (sink_fmt->bus_width) {
375 case 8:
376 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO;
377 break;
378 case 10:
379 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO;
380 break;
381 case 12:
382 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B;
383 break;
384 default:
385 dev_err(rkisp1->dev, "Invalid bus width\n");
386 return -EINVAL;
387 }
388
389 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ACQ_PROP);
390 rkisp1_write(rkisp1, val | input_sel, RKISP1_CIF_ISP_ACQ_PROP);
391
392 return 0;
393 }
394
395 static int rkisp1_config_mipi(struct rkisp1_device *rkisp1)
396 {
397 const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt;
398 unsigned int lanes = rkisp1->active_sensor->lanes;
399 u32 mipi_ctrl;
400
401 if (lanes < 1 || lanes > 4)
402 return -EINVAL;
403
404 mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) |
405 RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) |
406 RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP |
407 RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA;
408
409 rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL);
410
411 /* Configure Data Type and Virtual Channel */
412 rkisp1_write(rkisp1,
413 RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) |
414 RKISP1_CIF_MIPI_DATA_SEL_VC(0),
415 RKISP1_CIF_MIPI_IMG_DATA_SEL);
416
417 /* Clear MIPI interrupts */
418 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR);
419 /*
420 * Disable RKISP1_CIF_MIPI_ERR_DPHY interrupt here temporary for
421 * isp bus may be dead when switch isp.
422 */
423 rkisp1_write(rkisp1,
424 RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI |
425 RKISP1_CIF_MIPI_ERR_DPHY |
426 RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) |
427 RKISP1_CIF_MIPI_ADD_DATA_OVFLW,
428 RKISP1_CIF_MIPI_IMSC);
429
430 dev_dbg(rkisp1->dev, "\n MIPI_CTRL 0x%08x\n"
431 " MIPI_IMG_DATA_SEL 0x%08x\n"
432 " MIPI_STATUS 0x%08x\n"
433 " MIPI_IMSC 0x%08x\n",
434 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL),
435 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL),
436 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_STATUS),
437 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC));
438
439 return 0;
440 }
441
442 /* Configure MUX */
443 static int rkisp1_config_path(struct rkisp1_device *rkisp1)
444 {
445 struct rkisp1_sensor_async *sensor = rkisp1->active_sensor;
446 u32 dpcl = rkisp1_read(rkisp1, RKISP1_CIF_VI_DPCL);
447 int ret = 0;
448
449 if (sensor->mbus_type == V4L2_MBUS_BT656 ||
450 sensor->mbus_type == V4L2_MBUS_PARALLEL) {
451 ret = rkisp1_config_dvp(rkisp1);
452 dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_PARALLEL;
453 } else if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
454 ret = rkisp1_config_mipi(rkisp1);
455 dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_MIPI;
456 }
457
458 rkisp1_write(rkisp1, dpcl, RKISP1_CIF_VI_DPCL);
459
460 return ret;
461 }
462
463 /* Hardware configure Entry */
464 static int rkisp1_config_cif(struct rkisp1_device *rkisp1)
465 {
466 u32 cif_id;
467 int ret;
468
469 cif_id = rkisp1_read(rkisp1, RKISP1_CIF_VI_ID);
470 dev_dbg(rkisp1->dev, "CIF_ID 0x%08x\n", cif_id);
471
472 ret = rkisp1_config_isp(rkisp1);
473 if (ret)
474 return ret;
475 ret = rkisp1_config_path(rkisp1);
476 if (ret)
477 return ret;
478 rkisp1_config_ism(rkisp1);
479
480 return 0;
481 }
482
483 static void rkisp1_isp_stop(struct rkisp1_device *rkisp1)
484 {
485 u32 val;
486
487 /*
488 * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
489 * Stop ISP(isp) ->wait for ISP isp off
490 */
491 /* stop and clear MI, MIPI, and ISP interrupts */
492 rkisp1_write(rkisp1, 0, RKISP1_CIF_MIPI_IMSC);
493 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR);
494
495 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IMSC);
496 rkisp1_write(rkisp1, ~0, RKISP1_CIF_ISP_ICR);
497
498 rkisp1_write(rkisp1, 0, RKISP1_CIF_MI_IMSC);
499 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MI_ICR);
500 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
501 rkisp1_write(rkisp1, val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA),
502 RKISP1_CIF_MIPI_CTRL);
503 /* stop ISP */
504 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
505 val &= ~(RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE |
506 RKISP1_CIF_ISP_CTRL_ISP_ENABLE);
507 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
508
509 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
510 rkisp1_write(rkisp1, val | RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD,
511 RKISP1_CIF_ISP_CTRL);
512
513 readx_poll_timeout(readl, rkisp1->base_addr + RKISP1_CIF_ISP_RIS,
514 val, val & RKISP1_CIF_ISP_OFF, 20, 100);
515 rkisp1_write(rkisp1,
516 RKISP1_CIF_IRCL_MIPI_SW_RST | RKISP1_CIF_IRCL_ISP_SW_RST,
517 RKISP1_CIF_IRCL);
518 rkisp1_write(rkisp1, 0x0, RKISP1_CIF_IRCL);
519 }
520
521 static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
522 {
523 u32 val = RKISP1_CIF_ICCL_ISP_CLK | RKISP1_CIF_ICCL_CP_CLK |
524 RKISP1_CIF_ICCL_MRSZ_CLK | RKISP1_CIF_ICCL_SRSZ_CLK |
525 RKISP1_CIF_ICCL_JPEG_CLK | RKISP1_CIF_ICCL_MI_CLK |
526 RKISP1_CIF_ICCL_IE_CLK | RKISP1_CIF_ICCL_MIPI_CLK |
527 RKISP1_CIF_ICCL_DCROP_CLK;
528
529 rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
530 }
531
532 static void rkisp1_isp_start(struct rkisp1_device *rkisp1)
533 {
534 struct rkisp1_sensor_async *sensor = rkisp1->active_sensor;
535 u32 val;
536
537 rkisp1_config_clk(rkisp1);
538
539 /* Activate MIPI */
540 if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
541 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
542 rkisp1_write(rkisp1, val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA,
543 RKISP1_CIF_MIPI_CTRL);
544 }
545 /* Activate ISP */
546 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
547 val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD |
548 RKISP1_CIF_ISP_CTRL_ISP_ENABLE |
549 RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE;
550 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
551
552 /*
553 * CIF spec says to wait for sufficient time after enabling
554 * the MIPI interface and before starting the sensor output.
555 */
556 usleep_range(1000, 1200);
557 }
558
559 /* ----------------------------------------------------------------------------
560 * Subdev pad operations
561 */
562
563 static int rkisp1_isp_enum_mbus_code(struct v4l2_subdev *sd,
564 struct v4l2_subdev_pad_config *cfg,
565 struct v4l2_subdev_mbus_code_enum *code)
566 {
567 unsigned int i, dir;
568 int pos = 0;
569
570 if (code->pad == RKISP1_ISP_PAD_SINK_VIDEO) {
571 dir = RKISP1_ISP_SD_SINK;
572 } else if (code->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) {
573 dir = RKISP1_ISP_SD_SRC;
574 } else {
575 if (code->index > 0)
576 return -EINVAL;
577 code->code = MEDIA_BUS_FMT_METADATA_FIXED;
578 return 0;
579 }
580
581 if (code->index >= ARRAY_SIZE(rkisp1_isp_formats))
582 return -EINVAL;
583
584 for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) {
585 const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i];
586
587 if (fmt->direction & dir)
588 pos++;
589
590 if (code->index == pos - 1) {
591 code->code = fmt->mbus_code;
592 if (fmt->pixel_enc == V4L2_PIXEL_ENC_YUV &&
593 dir == RKISP1_ISP_SD_SRC)
594 code->flags =
595 V4L2_SUBDEV_MBUS_CODE_CSC_QUANTIZATION;
596 return 0;
597 }
598 }
599
600 return -EINVAL;
601 }
602
603 static int rkisp1_isp_init_config(struct v4l2_subdev *sd,
604 struct v4l2_subdev_pad_config *cfg)
605 {
606 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
607 struct v4l2_rect *sink_crop, *src_crop;
608
609 sink_fmt = v4l2_subdev_get_try_format(sd, cfg,
610 RKISP1_ISP_PAD_SINK_VIDEO);
611 sink_fmt->width = RKISP1_DEFAULT_WIDTH;
612 sink_fmt->height = RKISP1_DEFAULT_HEIGHT;
613 sink_fmt->field = V4L2_FIELD_NONE;
614 sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT;
615
616 sink_crop = v4l2_subdev_get_try_crop(sd, cfg,
617 RKISP1_ISP_PAD_SINK_VIDEO);
618 sink_crop->width = RKISP1_DEFAULT_WIDTH;
619 sink_crop->height = RKISP1_DEFAULT_HEIGHT;
620 sink_crop->left = 0;
621 sink_crop->top = 0;
622
623 src_fmt = v4l2_subdev_get_try_format(sd, cfg,
624 RKISP1_ISP_PAD_SOURCE_VIDEO);
625 *src_fmt = *sink_fmt;
626 src_fmt->code = RKISP1_DEF_SRC_PAD_FMT;
627
628 src_crop = v4l2_subdev_get_try_crop(sd, cfg,
629 RKISP1_ISP_PAD_SOURCE_VIDEO);
630 *src_crop = *sink_crop;
631
632 sink_fmt = v4l2_subdev_get_try_format(sd, cfg,
633 RKISP1_ISP_PAD_SINK_PARAMS);
634 src_fmt = v4l2_subdev_get_try_format(sd, cfg,
635 RKISP1_ISP_PAD_SOURCE_STATS);
636 sink_fmt->width = 0;
637 sink_fmt->height = 0;
638 sink_fmt->field = V4L2_FIELD_NONE;
639 sink_fmt->code = MEDIA_BUS_FMT_METADATA_FIXED;
640 *src_fmt = *sink_fmt;
641
642 return 0;
643 }
644
645 static void rkisp1_isp_set_src_fmt(struct rkisp1_isp *isp,
646 struct v4l2_subdev_pad_config *cfg,
647 struct v4l2_mbus_framefmt *format,
648 unsigned int which)
649 {
650 const struct rkisp1_isp_mbus_info *mbus_info;
651 struct v4l2_mbus_framefmt *src_fmt;
652 const struct v4l2_rect *src_crop;
653
654 src_fmt = rkisp1_isp_get_pad_fmt(isp, cfg,
655 RKISP1_ISP_PAD_SOURCE_VIDEO, which);
656 src_crop = rkisp1_isp_get_pad_crop(isp, cfg,
657 RKISP1_ISP_PAD_SOURCE_VIDEO, which);
658
659 src_fmt->code = format->code;
660 mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code);
661 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SRC)) {
662 src_fmt->code = RKISP1_DEF_SRC_PAD_FMT;
663 mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code);
664 }
665 if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
666 isp->src_fmt = mbus_info;
667 src_fmt->width = src_crop->width;
668 src_fmt->height = src_crop->height;
669
670 /*
671 * The CSC API is used to allow userspace to force full
672 * quantization on YUV formats.
673 */
674 if (format->flags & V4L2_MBUS_FRAMEFMT_SET_CSC &&
675 format->quantization == V4L2_QUANTIZATION_FULL_RANGE &&
676 mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV)
677 src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
678 else if (mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV)
679 src_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE;
680 else
681 src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
682
683 *format = *src_fmt;
684 }
685
686 static void rkisp1_isp_set_src_crop(struct rkisp1_isp *isp,
687 struct v4l2_subdev_pad_config *cfg,
688 struct v4l2_rect *r, unsigned int which)
689 {
690 struct v4l2_mbus_framefmt *src_fmt;
691 const struct v4l2_rect *sink_crop;
692 struct v4l2_rect *src_crop;
693
694 src_crop = rkisp1_isp_get_pad_crop(isp, cfg,
695 RKISP1_ISP_PAD_SOURCE_VIDEO,
696 which);
697 sink_crop = rkisp1_isp_get_pad_crop(isp, cfg,
698 RKISP1_ISP_PAD_SINK_VIDEO,
699 which);
700
701 src_crop->left = ALIGN(r->left, 2);
702 src_crop->width = ALIGN(r->width, 2);
703 src_crop->top = r->top;
704 src_crop->height = r->height;
705 rkisp1_sd_adjust_crop_rect(src_crop, sink_crop);
706
707 *r = *src_crop;
708
709 /* Propagate to out format */
710 src_fmt = rkisp1_isp_get_pad_fmt(isp, cfg,
711 RKISP1_ISP_PAD_SOURCE_VIDEO, which);
712 rkisp1_isp_set_src_fmt(isp, cfg, src_fmt, which);
713 }
714
715 static void rkisp1_isp_set_sink_crop(struct rkisp1_isp *isp,
716 struct v4l2_subdev_pad_config *cfg,
717 struct v4l2_rect *r, unsigned int which)
718 {
719 struct v4l2_rect *sink_crop, *src_crop;
720 struct v4l2_mbus_framefmt *sink_fmt;
721
722 sink_crop = rkisp1_isp_get_pad_crop(isp, cfg, RKISP1_ISP_PAD_SINK_VIDEO,
723 which);
724 sink_fmt = rkisp1_isp_get_pad_fmt(isp, cfg, RKISP1_ISP_PAD_SINK_VIDEO,
725 which);
726
727 sink_crop->left = ALIGN(r->left, 2);
728 sink_crop->width = ALIGN(r->width, 2);
729 sink_crop->top = r->top;
730 sink_crop->height = r->height;
731 rkisp1_sd_adjust_crop(sink_crop, sink_fmt);
732
733 *r = *sink_crop;
734
735 /* Propagate to out crop */
736 src_crop = rkisp1_isp_get_pad_crop(isp, cfg,
737 RKISP1_ISP_PAD_SOURCE_VIDEO, which);
738 rkisp1_isp_set_src_crop(isp, cfg, src_crop, which);
739 }
740
741 static void rkisp1_isp_set_sink_fmt(struct rkisp1_isp *isp,
742 struct v4l2_subdev_pad_config *cfg,
743 struct v4l2_mbus_framefmt *format,
744 unsigned int which)
745 {
746 const struct rkisp1_isp_mbus_info *mbus_info;
747 struct v4l2_mbus_framefmt *sink_fmt;
748 struct v4l2_rect *sink_crop;
749
750 sink_fmt = rkisp1_isp_get_pad_fmt(isp, cfg, RKISP1_ISP_PAD_SINK_VIDEO,
751 which);
752 sink_fmt->code = format->code;
753 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
754 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SINK)) {
755 sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT;
756 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
757 }
758 if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
759 isp->sink_fmt = mbus_info;
760
761 sink_fmt->width = clamp_t(u32, format->width,
762 RKISP1_ISP_MIN_WIDTH,
763 RKISP1_ISP_MAX_WIDTH);
764 sink_fmt->height = clamp_t(u32, format->height,
765 RKISP1_ISP_MIN_HEIGHT,
766 RKISP1_ISP_MAX_HEIGHT);
767
768 *format = *sink_fmt;
769
770 /* Propagate to in crop */
771 sink_crop = rkisp1_isp_get_pad_crop(isp, cfg, RKISP1_ISP_PAD_SINK_VIDEO,
772 which);
773 rkisp1_isp_set_sink_crop(isp, cfg, sink_crop, which);
774 }
775
776 static int rkisp1_isp_get_fmt(struct v4l2_subdev *sd,
777 struct v4l2_subdev_pad_config *cfg,
778 struct v4l2_subdev_format *fmt)
779 {
780 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
781
782 mutex_lock(&isp->ops_lock);
783 fmt->format = *rkisp1_isp_get_pad_fmt(isp, cfg, fmt->pad, fmt->which);
784 mutex_unlock(&isp->ops_lock);
785 return 0;
786 }
787
788 static int rkisp1_isp_set_fmt(struct v4l2_subdev *sd,
789 struct v4l2_subdev_pad_config *cfg,
790 struct v4l2_subdev_format *fmt)
791 {
792 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
793
794 mutex_lock(&isp->ops_lock);
795 if (fmt->pad == RKISP1_ISP_PAD_SINK_VIDEO)
796 rkisp1_isp_set_sink_fmt(isp, cfg, &fmt->format, fmt->which);
797 else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_VIDEO)
798 rkisp1_isp_set_src_fmt(isp, cfg, &fmt->format, fmt->which);
799 else
800 fmt->format = *rkisp1_isp_get_pad_fmt(isp, cfg, fmt->pad,
801 fmt->which);
802
803 mutex_unlock(&isp->ops_lock);
804 return 0;
805 }
806
807 static int rkisp1_isp_get_selection(struct v4l2_subdev *sd,
808 struct v4l2_subdev_pad_config *cfg,
809 struct v4l2_subdev_selection *sel)
810 {
811 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
812 int ret = 0;
813
814 if (sel->pad != RKISP1_ISP_PAD_SOURCE_VIDEO &&
815 sel->pad != RKISP1_ISP_PAD_SINK_VIDEO)
816 return -EINVAL;
817
818 mutex_lock(&isp->ops_lock);
819 switch (sel->target) {
820 case V4L2_SEL_TGT_CROP_BOUNDS:
821 if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO) {
822 struct v4l2_mbus_framefmt *fmt;
823
824 fmt = rkisp1_isp_get_pad_fmt(isp, cfg, sel->pad,
825 sel->which);
826 sel->r.height = fmt->height;
827 sel->r.width = fmt->width;
828 sel->r.left = 0;
829 sel->r.top = 0;
830 } else {
831 sel->r = *rkisp1_isp_get_pad_crop(isp, cfg,
832 RKISP1_ISP_PAD_SINK_VIDEO,
833 sel->which);
834 }
835 break;
836 case V4L2_SEL_TGT_CROP:
837 sel->r = *rkisp1_isp_get_pad_crop(isp, cfg, sel->pad,
838 sel->which);
839 break;
840 default:
841 ret = -EINVAL;
842 }
843 mutex_unlock(&isp->ops_lock);
844 return ret;
845 }
846
847 static int rkisp1_isp_set_selection(struct v4l2_subdev *sd,
848 struct v4l2_subdev_pad_config *cfg,
849 struct v4l2_subdev_selection *sel)
850 {
851 struct rkisp1_device *rkisp1 =
852 container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev);
853 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
854 int ret = 0;
855
856 if (sel->target != V4L2_SEL_TGT_CROP)
857 return -EINVAL;
858
859 dev_dbg(rkisp1->dev, "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__,
860 sel->pad, sel->r.left, sel->r.top, sel->r.width, sel->r.height);
861 mutex_lock(&isp->ops_lock);
862 if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO)
863 rkisp1_isp_set_sink_crop(isp, cfg, &sel->r, sel->which);
864 else if (sel->pad == RKISP1_ISP_PAD_SOURCE_VIDEO)
865 rkisp1_isp_set_src_crop(isp, cfg, &sel->r, sel->which);
866 else
867 ret = -EINVAL;
868
869 mutex_unlock(&isp->ops_lock);
870 return ret;
871 }
872
873 static int rkisp1_subdev_link_validate(struct media_link *link)
874 {
875 if (link->sink->index == RKISP1_ISP_PAD_SINK_PARAMS)
876 return 0;
877
878 return v4l2_subdev_link_validate(link);
879 }
880
881 static const struct v4l2_subdev_pad_ops rkisp1_isp_pad_ops = {
882 .enum_mbus_code = rkisp1_isp_enum_mbus_code,
883 .get_selection = rkisp1_isp_get_selection,
884 .set_selection = rkisp1_isp_set_selection,
885 .init_cfg = rkisp1_isp_init_config,
886 .get_fmt = rkisp1_isp_get_fmt,
887 .set_fmt = rkisp1_isp_set_fmt,
888 .link_validate = v4l2_subdev_link_validate_default,
889 };
890
891 /* ----------------------------------------------------------------------------
892 * Stream operations
893 */
894
895 static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp,
896 struct rkisp1_sensor_async *sensor)
897 {
898 struct rkisp1_device *rkisp1 =
899 container_of(isp->sd.v4l2_dev, struct rkisp1_device, v4l2_dev);
900 union phy_configure_opts opts;
901 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
902 s64 pixel_clock;
903
904 if (!sensor->pixel_rate_ctrl) {
905 dev_warn(rkisp1->dev, "No pixel rate control in sensor subdev\n");
906 return -EPIPE;
907 }
908
909 pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl);
910 if (!pixel_clock) {
911 dev_err(rkisp1->dev, "Invalid pixel rate value\n");
912 return -EINVAL;
913 }
914
915 phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
916 sensor->lanes, cfg);
917 phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
918 phy_configure(sensor->dphy, &opts);
919 phy_power_on(sensor->dphy);
920
921 return 0;
922 }
923
924 static void rkisp1_mipi_csi2_stop(struct rkisp1_sensor_async *sensor)
925 {
926 phy_power_off(sensor->dphy);
927 }
928
929 static int rkisp1_isp_s_stream(struct v4l2_subdev *sd, int enable)
930 {
931 struct rkisp1_device *rkisp1 =
932 container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev);
933 struct rkisp1_isp *isp = &rkisp1->isp;
934 struct v4l2_subdev *sensor_sd;
935 int ret = 0;
936
937 if (!enable) {
938 rkisp1_isp_stop(rkisp1);
939 rkisp1_mipi_csi2_stop(rkisp1->active_sensor);
940 return 0;
941 }
942
943 sensor_sd = rkisp1_get_remote_sensor(sd);
944 if (!sensor_sd) {
945 dev_warn(rkisp1->dev, "No link between isp and sensor\n");
946 return -ENODEV;
947 }
948
949 rkisp1->active_sensor = container_of(sensor_sd->asd,
950 struct rkisp1_sensor_async, asd);
951
952 if (rkisp1->active_sensor->mbus_type != V4L2_MBUS_CSI2_DPHY)
953 return -EINVAL;
954
955 rkisp1->isp.frame_sequence = -1;
956 mutex_lock(&isp->ops_lock);
957 ret = rkisp1_config_cif(rkisp1);
958 if (ret)
959 goto mutex_unlock;
960
961 ret = rkisp1_mipi_csi2_start(&rkisp1->isp, rkisp1->active_sensor);
962 if (ret)
963 goto mutex_unlock;
964
965 rkisp1_isp_start(rkisp1);
966
967 mutex_unlock:
968 mutex_unlock(&isp->ops_lock);
969 return ret;
970 }
971
972 static int rkisp1_isp_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh,
973 struct v4l2_event_subscription *sub)
974 {
975 if (sub->type != V4L2_EVENT_FRAME_SYNC)
976 return -EINVAL;
977
978 /* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */
979 if (sub->id != 0)
980 return -EINVAL;
981
982 return v4l2_event_subscribe(fh, sub, 0, NULL);
983 }
984
985 static const struct media_entity_operations rkisp1_isp_media_ops = {
986 .link_validate = rkisp1_subdev_link_validate,
987 };
988
989 static const struct v4l2_subdev_video_ops rkisp1_isp_video_ops = {
990 .s_stream = rkisp1_isp_s_stream,
991 };
992
993 static const struct v4l2_subdev_core_ops rkisp1_isp_core_ops = {
994 .subscribe_event = rkisp1_isp_subs_evt,
995 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
996 };
997
998 static const struct v4l2_subdev_ops rkisp1_isp_ops = {
999 .core = &rkisp1_isp_core_ops,
1000 .video = &rkisp1_isp_video_ops,
1001 .pad = &rkisp1_isp_pad_ops,
1002 };
1003
1004 int rkisp1_isp_register(struct rkisp1_device *rkisp1)
1005 {
1006 struct rkisp1_isp *isp = &rkisp1->isp;
1007 struct media_pad *pads = isp->pads;
1008 struct v4l2_subdev *sd = &isp->sd;
1009 int ret;
1010
1011 v4l2_subdev_init(sd, &rkisp1_isp_ops);
1012 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1013 sd->entity.ops = &rkisp1_isp_media_ops;
1014 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1015 sd->owner = THIS_MODULE;
1016 strscpy(sd->name, RKISP1_ISP_DEV_NAME, sizeof(sd->name));
1017
1018 pads[RKISP1_ISP_PAD_SINK_VIDEO].flags = MEDIA_PAD_FL_SINK |
1019 MEDIA_PAD_FL_MUST_CONNECT;
1020 pads[RKISP1_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK;
1021 pads[RKISP1_ISP_PAD_SOURCE_VIDEO].flags = MEDIA_PAD_FL_SOURCE;
1022 pads[RKISP1_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE;
1023
1024 isp->sink_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SINK_PAD_FMT);
1025 isp->src_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SRC_PAD_FMT);
1026
1027 mutex_init(&isp->ops_lock);
1028 ret = media_entity_pads_init(&sd->entity, RKISP1_ISP_PAD_MAX, pads);
1029 if (ret)
1030 return ret;
1031
1032 ret = v4l2_device_register_subdev(&rkisp1->v4l2_dev, sd);
1033 if (ret) {
1034 dev_err(rkisp1->dev, "Failed to register isp subdev\n");
1035 goto err_cleanup_media_entity;
1036 }
1037
1038 rkisp1_isp_init_config(sd, rkisp1->isp.pad_cfg);
1039 return 0;
1040
1041 err_cleanup_media_entity:
1042 media_entity_cleanup(&sd->entity);
1043
1044 return ret;
1045 }
1046
1047 void rkisp1_isp_unregister(struct rkisp1_device *rkisp1)
1048 {
1049 struct v4l2_subdev *sd = &rkisp1->isp.sd;
1050
1051 v4l2_device_unregister_subdev(sd);
1052 media_entity_cleanup(&sd->entity);
1053 }
1054
1055 /* ----------------------------------------------------------------------------
1056 * Interrupt handlers
1057 */
1058
1059 void rkisp1_mipi_isr(struct rkisp1_device *rkisp1)
1060 {
1061 u32 val, status;
1062
1063 status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS);
1064 if (!status)
1065 return;
1066
1067 rkisp1_write(rkisp1, status, RKISP1_CIF_MIPI_ICR);
1068
1069 /*
1070 * Disable DPHY errctrl interrupt, because this dphy
1071 * erctrl signal is asserted until the next changes
1072 * of line state. This time is may be too long and cpu
1073 * is hold in this interrupt.
1074 */
1075 if (status & RKISP1_CIF_MIPI_ERR_CTRL(0x0f)) {
1076 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
1077 rkisp1_write(rkisp1, val & ~RKISP1_CIF_MIPI_ERR_CTRL(0x0f),
1078 RKISP1_CIF_MIPI_IMSC);
1079 rkisp1->isp.is_dphy_errctrl_disabled = true;
1080 }
1081
1082 /*
1083 * Enable DPHY errctrl interrupt again, if mipi have receive
1084 * the whole frame without any error.
1085 */
1086 if (status == RKISP1_CIF_MIPI_FRAME_END) {
1087 /*
1088 * Enable DPHY errctrl interrupt again, if mipi have receive
1089 * the whole frame without any error.
1090 */
1091 if (rkisp1->isp.is_dphy_errctrl_disabled) {
1092 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
1093 val |= RKISP1_CIF_MIPI_ERR_CTRL(0x0f);
1094 rkisp1_write(rkisp1, val, RKISP1_CIF_MIPI_IMSC);
1095 rkisp1->isp.is_dphy_errctrl_disabled = false;
1096 }
1097 } else {
1098 rkisp1->debug.mipi_error++;
1099 }
1100 }
1101
1102 static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp)
1103 {
1104 struct v4l2_event event = {
1105 .type = V4L2_EVENT_FRAME_SYNC,
1106 };
1107 event.u.frame_sync.frame_sequence = isp->frame_sequence;
1108
1109 v4l2_event_queue(isp->sd.devnode, &event);
1110 }
1111
1112 void rkisp1_isp_isr(struct rkisp1_device *rkisp1)
1113 {
1114 u32 status, isp_err;
1115
1116 status = rkisp1_read(rkisp1, RKISP1_CIF_ISP_MIS);
1117 if (!status)
1118 return;
1119
1120 rkisp1_write(rkisp1, status, RKISP1_CIF_ISP_ICR);
1121
1122 /* Vertical sync signal, starting generating new frame */
1123 if (status & RKISP1_CIF_ISP_V_START) {
1124 rkisp1->isp.frame_sequence++;
1125 rkisp1_isp_queue_event_sof(&rkisp1->isp);
1126 if (status & RKISP1_CIF_ISP_FRAME) {
1127 WARN_ONCE(1, "irq delay is too long, buffers might not be in sync\n");
1128 rkisp1->debug.irq_delay++;
1129 }
1130 }
1131 if (status & RKISP1_CIF_ISP_PIC_SIZE_ERROR) {
1132 /* Clear pic_size_error */
1133 isp_err = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ERR);
1134 if (isp_err & RKISP1_CIF_ISP_ERR_INFORM_SIZE)
1135 rkisp1->debug.inform_size_error++;
1136 if (isp_err & RKISP1_CIF_ISP_ERR_IS_SIZE)
1137 rkisp1->debug.img_stabilization_size_error++;
1138 if (isp_err & RKISP1_CIF_ISP_ERR_OUTFORM_SIZE)
1139 rkisp1->debug.outform_size_error++;
1140 rkisp1_write(rkisp1, isp_err, RKISP1_CIF_ISP_ERR_CLR);
1141 } else if (status & RKISP1_CIF_ISP_DATA_LOSS) {
1142 /* keep track of data_loss in debugfs */
1143 rkisp1->debug.data_loss++;
1144 }
1145
1146 if (status & RKISP1_CIF_ISP_FRAME) {
1147 u32 isp_ris;
1148
1149 /* New frame from the sensor received */
1150 isp_ris = rkisp1_read(rkisp1, RKISP1_CIF_ISP_RIS);
1151 if (isp_ris & RKISP1_STATS_MEAS_MASK)
1152 rkisp1_stats_isr(&rkisp1->stats, isp_ris);
1153 /*
1154 * Then update changed configs. Some of them involve
1155 * lot of register writes. Do those only one per frame.
1156 * Do the updates in the order of the processing flow.
1157 */
1158 rkisp1_params_isr(rkisp1);
1159 }
1160 }
Linux with added FPC-III support