1 // SPDX-License-Identifier: GPL-2.0+
3 * vsp1_drm.c -- R-Car VSP1 DRM/KMS Interface
5 * Copyright (C) 2015 Renesas Electronics Corporation
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/slab.h>
14 #include <media/media-entity.h>
15 #include <media/v4l2-subdev.h>
16 #include <media/vsp1.h>
23 #include "vsp1_pipe.h"
24 #include "vsp1_rwpf.h"
27 #define BRX_NAME(e) (e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"
29 /* -----------------------------------------------------------------------------
33 static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline
*pipe
,
34 unsigned int completion
)
36 struct vsp1_drm_pipeline
*drm_pipe
= to_vsp1_drm_pipeline(pipe
);
38 if (drm_pipe
->du_complete
) {
39 struct vsp1_entity
*uif
= drm_pipe
->uif
;
40 unsigned int status
= completion
41 & (VSP1_DU_STATUS_COMPLETE
|
42 VSP1_DU_STATUS_WRITEBACK
);
45 crc
= uif
? vsp1_uif_get_crc(to_uif(&uif
->subdev
)) : 0;
46 drm_pipe
->du_complete(drm_pipe
->du_private
, status
, crc
);
49 if (completion
& VSP1_DL_FRAME_END_INTERNAL
) {
50 drm_pipe
->force_brx_release
= false;
51 wake_up(&drm_pipe
->wait_queue
);
55 /* -----------------------------------------------------------------------------
56 * Pipeline Configuration
60 * Insert the UIF in the pipeline between the prev and next entities. If no UIF
61 * is available connect the two entities directly.
63 static int vsp1_du_insert_uif(struct vsp1_device
*vsp1
,
64 struct vsp1_pipeline
*pipe
,
65 struct vsp1_entity
*uif
,
66 struct vsp1_entity
*prev
, unsigned int prev_pad
,
67 struct vsp1_entity
*next
, unsigned int next_pad
)
69 struct v4l2_subdev_format format
;
74 * If there's no UIF to be inserted, connect the previous and
75 * next entities directly.
78 prev
->sink_pad
= next_pad
;
83 prev
->sink_pad
= UIF_PAD_SINK
;
85 memset(&format
, 0, sizeof(format
));
86 format
.which
= V4L2_SUBDEV_FORMAT_ACTIVE
;
87 format
.pad
= prev_pad
;
89 ret
= v4l2_subdev_call(&prev
->subdev
, pad
, get_fmt
, NULL
, &format
);
93 format
.pad
= UIF_PAD_SINK
;
95 ret
= v4l2_subdev_call(&uif
->subdev
, pad
, set_fmt
, NULL
, &format
);
99 dev_dbg(vsp1
->dev
, "%s: set format %ux%u (%x) on UIF sink\n",
100 __func__
, format
.format
.width
, format
.format
.height
,
104 * The UIF doesn't mangle the format between its sink and source pads,
105 * so there is no need to retrieve the format on its source pad.
109 uif
->sink_pad
= next_pad
;
114 /* Setup one RPF and the connected BRx sink pad. */
115 static int vsp1_du_pipeline_setup_rpf(struct vsp1_device
*vsp1
,
116 struct vsp1_pipeline
*pipe
,
117 struct vsp1_rwpf
*rpf
,
118 struct vsp1_entity
*uif
,
119 unsigned int brx_input
)
121 struct v4l2_subdev_selection sel
;
122 struct v4l2_subdev_format format
;
123 const struct v4l2_rect
*crop
;
127 * Configure the format on the RPF sink pad and propagate it up to the
130 crop
= &vsp1
->drm
->inputs
[rpf
->entity
.index
].crop
;
132 memset(&format
, 0, sizeof(format
));
133 format
.which
= V4L2_SUBDEV_FORMAT_ACTIVE
;
134 format
.pad
= RWPF_PAD_SINK
;
135 format
.format
.width
= crop
->width
+ crop
->left
;
136 format
.format
.height
= crop
->height
+ crop
->top
;
137 format
.format
.code
= rpf
->fmtinfo
->mbus
;
138 format
.format
.field
= V4L2_FIELD_NONE
;
140 ret
= v4l2_subdev_call(&rpf
->entity
.subdev
, pad
, set_fmt
, NULL
,
146 "%s: set format %ux%u (%x) on RPF%u sink\n",
147 __func__
, format
.format
.width
, format
.format
.height
,
148 format
.format
.code
, rpf
->entity
.index
);
150 memset(&sel
, 0, sizeof(sel
));
151 sel
.which
= V4L2_SUBDEV_FORMAT_ACTIVE
;
152 sel
.pad
= RWPF_PAD_SINK
;
153 sel
.target
= V4L2_SEL_TGT_CROP
;
156 ret
= v4l2_subdev_call(&rpf
->entity
.subdev
, pad
, set_selection
, NULL
,
162 "%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
163 __func__
, sel
.r
.left
, sel
.r
.top
, sel
.r
.width
, sel
.r
.height
,
167 * RPF source, hardcode the format to ARGB8888 to turn on format
168 * conversion if needed.
170 format
.pad
= RWPF_PAD_SOURCE
;
172 ret
= v4l2_subdev_call(&rpf
->entity
.subdev
, pad
, get_fmt
, NULL
,
178 "%s: got format %ux%u (%x) on RPF%u source\n",
179 __func__
, format
.format
.width
, format
.format
.height
,
180 format
.format
.code
, rpf
->entity
.index
);
182 format
.format
.code
= MEDIA_BUS_FMT_ARGB8888_1X32
;
184 ret
= v4l2_subdev_call(&rpf
->entity
.subdev
, pad
, set_fmt
, NULL
,
189 /* Insert and configure the UIF if available. */
190 ret
= vsp1_du_insert_uif(vsp1
, pipe
, uif
, &rpf
->entity
, RWPF_PAD_SOURCE
,
191 pipe
->brx
, brx_input
);
195 /* BRx sink, propagate the format from the RPF source. */
196 format
.pad
= brx_input
;
198 ret
= v4l2_subdev_call(&pipe
->brx
->subdev
, pad
, set_fmt
, NULL
,
203 dev_dbg(vsp1
->dev
, "%s: set format %ux%u (%x) on %s pad %u\n",
204 __func__
, format
.format
.width
, format
.format
.height
,
205 format
.format
.code
, BRX_NAME(pipe
->brx
), format
.pad
);
208 sel
.target
= V4L2_SEL_TGT_COMPOSE
;
209 sel
.r
= vsp1
->drm
->inputs
[rpf
->entity
.index
].compose
;
211 ret
= v4l2_subdev_call(&pipe
->brx
->subdev
, pad
, set_selection
, NULL
,
216 dev_dbg(vsp1
->dev
, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",
217 __func__
, sel
.r
.left
, sel
.r
.top
, sel
.r
.width
, sel
.r
.height
,
218 BRX_NAME(pipe
->brx
), sel
.pad
);
223 /* Setup the BRx source pad. */
224 static int vsp1_du_pipeline_setup_inputs(struct vsp1_device
*vsp1
,
225 struct vsp1_pipeline
*pipe
);
226 static void vsp1_du_pipeline_configure(struct vsp1_pipeline
*pipe
);
228 static int vsp1_du_pipeline_setup_brx(struct vsp1_device
*vsp1
,
229 struct vsp1_pipeline
*pipe
)
231 struct vsp1_drm_pipeline
*drm_pipe
= to_vsp1_drm_pipeline(pipe
);
232 struct v4l2_subdev_format format
= {
233 .which
= V4L2_SUBDEV_FORMAT_ACTIVE
,
235 struct vsp1_entity
*brx
;
240 * - If we need more than two inputs, use the BRU.
241 * - Otherwise, if we are not forced to release our BRx, keep it.
242 * - Else, use any free BRx (randomly starting with the BRU).
244 if (pipe
->num_inputs
> 2)
245 brx
= &vsp1
->bru
->entity
;
246 else if (pipe
->brx
&& !drm_pipe
->force_brx_release
)
248 else if (!vsp1
->bru
->entity
.pipe
)
249 brx
= &vsp1
->bru
->entity
;
251 brx
= &vsp1
->brs
->entity
;
253 /* Switch BRx if needed. */
254 if (brx
!= pipe
->brx
) {
255 struct vsp1_entity
*released_brx
= NULL
;
257 /* Release our BRx if we have one. */
259 dev_dbg(vsp1
->dev
, "%s: pipe %u: releasing %s\n",
260 __func__
, pipe
->lif
->index
,
261 BRX_NAME(pipe
->brx
));
264 * The BRx might be acquired by the other pipeline in
265 * the next step. We must thus remove it from the list
266 * of entities for this pipeline. The other pipeline's
267 * hardware configuration will reconfigure the BRx
270 * However, if the other pipeline doesn't acquire our
271 * BRx, we need to keep it in the list, otherwise the
272 * hardware configuration step won't disconnect it from
273 * the pipeline. To solve this, store the released BRx
274 * pointer to add it back to the list of entities later
275 * if it isn't acquired by the other pipeline.
277 released_brx
= pipe
->brx
;
279 list_del(&pipe
->brx
->list_pipe
);
280 pipe
->brx
->sink
= NULL
;
281 pipe
->brx
->pipe
= NULL
;
286 * If the BRx we need is in use, force the owner pipeline to
287 * switch to the other BRx and wait until the switch completes.
290 struct vsp1_drm_pipeline
*owner_pipe
;
292 dev_dbg(vsp1
->dev
, "%s: pipe %u: waiting for %s\n",
293 __func__
, pipe
->lif
->index
, BRX_NAME(brx
));
295 owner_pipe
= to_vsp1_drm_pipeline(brx
->pipe
);
296 owner_pipe
->force_brx_release
= true;
298 vsp1_du_pipeline_setup_inputs(vsp1
, &owner_pipe
->pipe
);
299 vsp1_du_pipeline_configure(&owner_pipe
->pipe
);
301 ret
= wait_event_timeout(owner_pipe
->wait_queue
,
302 !owner_pipe
->force_brx_release
,
303 msecs_to_jiffies(500));
306 "DRM pipeline %u reconfiguration timeout\n",
307 owner_pipe
->pipe
.lif
->index
);
311 * If the BRx we have released previously hasn't been acquired
312 * by the other pipeline, add it back to the entities list (with
313 * the pipe pointer NULL) to let vsp1_du_pipeline_configure()
314 * disconnect it from the hardware pipeline.
316 if (released_brx
&& !released_brx
->pipe
)
317 list_add_tail(&released_brx
->list_pipe
,
320 /* Add the BRx to the pipeline. */
321 dev_dbg(vsp1
->dev
, "%s: pipe %u: acquired %s\n",
322 __func__
, pipe
->lif
->index
, BRX_NAME(brx
));
325 pipe
->brx
->pipe
= pipe
;
326 pipe
->brx
->sink
= &pipe
->output
->entity
;
327 pipe
->brx
->sink_pad
= 0;
329 list_add_tail(&pipe
->brx
->list_pipe
, &pipe
->entities
);
333 * Configure the format on the BRx source and verify that it matches the
334 * requested format. We don't set the media bus code as it is configured
335 * on the BRx sink pad 0 and propagated inside the entity, not on the
338 format
.pad
= brx
->source_pad
;
339 format
.format
.width
= drm_pipe
->width
;
340 format
.format
.height
= drm_pipe
->height
;
341 format
.format
.field
= V4L2_FIELD_NONE
;
343 ret
= v4l2_subdev_call(&brx
->subdev
, pad
, set_fmt
, NULL
,
348 dev_dbg(vsp1
->dev
, "%s: set format %ux%u (%x) on %s pad %u\n",
349 __func__
, format
.format
.width
, format
.format
.height
,
350 format
.format
.code
, BRX_NAME(brx
), brx
->source_pad
);
352 if (format
.format
.width
!= drm_pipe
->width
||
353 format
.format
.height
!= drm_pipe
->height
) {
354 dev_dbg(vsp1
->dev
, "%s: format mismatch\n", __func__
);
361 static unsigned int rpf_zpos(struct vsp1_device
*vsp1
, struct vsp1_rwpf
*rpf
)
363 return vsp1
->drm
->inputs
[rpf
->entity
.index
].zpos
;
366 /* Setup the input side of the pipeline (RPFs and BRx). */
367 static int vsp1_du_pipeline_setup_inputs(struct vsp1_device
*vsp1
,
368 struct vsp1_pipeline
*pipe
)
370 struct vsp1_drm_pipeline
*drm_pipe
= to_vsp1_drm_pipeline(pipe
);
371 struct vsp1_rwpf
*inputs
[VSP1_MAX_RPF
] = { NULL
, };
372 struct vsp1_entity
*uif
;
373 bool use_uif
= false;
374 struct vsp1_brx
*brx
;
378 /* Count the number of enabled inputs and sort them by Z-order. */
379 pipe
->num_inputs
= 0;
381 for (i
= 0; i
< vsp1
->info
->rpf_count
; ++i
) {
382 struct vsp1_rwpf
*rpf
= vsp1
->rpf
[i
];
385 if (!pipe
->inputs
[i
])
388 /* Insert the RPF in the sorted RPFs array. */
389 for (j
= pipe
->num_inputs
++; j
> 0; --j
) {
390 if (rpf_zpos(vsp1
, inputs
[j
-1]) <= rpf_zpos(vsp1
, rpf
))
392 inputs
[j
] = inputs
[j
-1];
399 * Setup the BRx. This must be done before setting up the RPF input
400 * pipelines as the BRx sink compose rectangles depend on the BRx source
403 ret
= vsp1_du_pipeline_setup_brx(vsp1
, pipe
);
405 dev_err(vsp1
->dev
, "%s: failed to setup %s source\n", __func__
,
406 BRX_NAME(pipe
->brx
));
410 brx
= to_brx(&pipe
->brx
->subdev
);
412 /* Setup the RPF input pipeline for every enabled input. */
413 for (i
= 0; i
< pipe
->brx
->source_pad
; ++i
) {
414 struct vsp1_rwpf
*rpf
= inputs
[i
];
417 brx
->inputs
[i
].rpf
= NULL
;
421 if (!rpf
->entity
.pipe
) {
422 rpf
->entity
.pipe
= pipe
;
423 list_add_tail(&rpf
->entity
.list_pipe
, &pipe
->entities
);
426 brx
->inputs
[i
].rpf
= rpf
;
428 rpf
->entity
.sink
= pipe
->brx
;
429 rpf
->entity
.sink_pad
= i
;
431 dev_dbg(vsp1
->dev
, "%s: connecting RPF.%u to %s:%u\n",
432 __func__
, rpf
->entity
.index
, BRX_NAME(pipe
->brx
), i
);
434 uif
= drm_pipe
->crc
.source
== VSP1_DU_CRC_PLANE
&&
435 drm_pipe
->crc
.index
== i
? drm_pipe
->uif
: NULL
;
438 ret
= vsp1_du_pipeline_setup_rpf(vsp1
, pipe
, rpf
, uif
, i
);
441 "%s: failed to setup RPF.%u\n",
442 __func__
, rpf
->entity
.index
);
447 /* Insert and configure the UIF at the BRx output if available. */
448 uif
= drm_pipe
->crc
.source
== VSP1_DU_CRC_OUTPUT
? drm_pipe
->uif
: NULL
;
451 ret
= vsp1_du_insert_uif(vsp1
, pipe
, uif
,
452 pipe
->brx
, pipe
->brx
->source_pad
,
453 &pipe
->output
->entity
, 0);
455 dev_err(vsp1
->dev
, "%s: failed to setup UIF after %s\n",
456 __func__
, BRX_NAME(pipe
->brx
));
459 * If the UIF is not in use schedule it for removal by setting its pipe
460 * pointer to NULL, vsp1_du_pipeline_configure() will remove it from the
461 * hardware pipeline and from the pipeline's list of entities. Otherwise
462 * make sure it is present in the pipeline's list of entities if it
466 drm_pipe
->uif
->pipe
= NULL
;
467 } else if (!drm_pipe
->uif
->pipe
) {
468 drm_pipe
->uif
->pipe
= pipe
;
469 list_add_tail(&drm_pipe
->uif
->list_pipe
, &pipe
->entities
);
475 /* Setup the output side of the pipeline (WPF and LIF). */
476 static int vsp1_du_pipeline_setup_output(struct vsp1_device
*vsp1
,
477 struct vsp1_pipeline
*pipe
)
479 struct vsp1_drm_pipeline
*drm_pipe
= to_vsp1_drm_pipeline(pipe
);
480 struct v4l2_subdev_format format
= { 0, };
483 format
.which
= V4L2_SUBDEV_FORMAT_ACTIVE
;
484 format
.pad
= RWPF_PAD_SINK
;
485 format
.format
.width
= drm_pipe
->width
;
486 format
.format
.height
= drm_pipe
->height
;
487 format
.format
.code
= MEDIA_BUS_FMT_ARGB8888_1X32
;
488 format
.format
.field
= V4L2_FIELD_NONE
;
490 ret
= v4l2_subdev_call(&pipe
->output
->entity
.subdev
, pad
, set_fmt
, NULL
,
495 dev_dbg(vsp1
->dev
, "%s: set format %ux%u (%x) on WPF%u sink\n",
496 __func__
, format
.format
.width
, format
.format
.height
,
497 format
.format
.code
, pipe
->output
->entity
.index
);
499 format
.pad
= RWPF_PAD_SOURCE
;
500 ret
= v4l2_subdev_call(&pipe
->output
->entity
.subdev
, pad
, get_fmt
, NULL
,
505 dev_dbg(vsp1
->dev
, "%s: got format %ux%u (%x) on WPF%u source\n",
506 __func__
, format
.format
.width
, format
.format
.height
,
507 format
.format
.code
, pipe
->output
->entity
.index
);
509 format
.pad
= LIF_PAD_SINK
;
510 ret
= v4l2_subdev_call(&pipe
->lif
->subdev
, pad
, set_fmt
, NULL
,
515 dev_dbg(vsp1
->dev
, "%s: set format %ux%u (%x) on LIF%u sink\n",
516 __func__
, format
.format
.width
, format
.format
.height
,
517 format
.format
.code
, pipe
->lif
->index
);
520 * Verify that the format at the output of the pipeline matches the
521 * requested frame size and media bus code.
523 if (format
.format
.width
!= drm_pipe
->width
||
524 format
.format
.height
!= drm_pipe
->height
||
525 format
.format
.code
!= MEDIA_BUS_FMT_ARGB8888_1X32
) {
526 dev_dbg(vsp1
->dev
, "%s: format mismatch on LIF%u\n", __func__
,
534 /* Configure all entities in the pipeline. */
535 static void vsp1_du_pipeline_configure(struct vsp1_pipeline
*pipe
)
537 struct vsp1_drm_pipeline
*drm_pipe
= to_vsp1_drm_pipeline(pipe
);
538 struct vsp1_entity
*entity
;
539 struct vsp1_entity
*next
;
540 struct vsp1_dl_list
*dl
;
541 struct vsp1_dl_body
*dlb
;
542 unsigned int dl_flags
= 0;
544 if (drm_pipe
->force_brx_release
)
545 dl_flags
|= VSP1_DL_FRAME_END_INTERNAL
;
546 if (pipe
->output
->writeback
)
547 dl_flags
|= VSP1_DL_FRAME_END_WRITEBACK
;
549 dl
= vsp1_dl_list_get(pipe
->output
->dlm
);
550 dlb
= vsp1_dl_list_get_body0(dl
);
552 list_for_each_entry_safe(entity
, next
, &pipe
->entities
, list_pipe
) {
553 /* Disconnect unused entities from the pipeline. */
555 vsp1_dl_body_write(dlb
, entity
->route
->reg
,
556 VI6_DPR_NODE_UNUSED
);
559 list_del(&entity
->list_pipe
);
564 vsp1_entity_route_setup(entity
, pipe
, dlb
);
565 vsp1_entity_configure_stream(entity
, pipe
, dl
, dlb
);
566 vsp1_entity_configure_frame(entity
, pipe
, dl
, dlb
);
567 vsp1_entity_configure_partition(entity
, pipe
, dl
, dlb
);
570 vsp1_dl_list_commit(dl
, dl_flags
);
573 static int vsp1_du_pipeline_set_rwpf_format(struct vsp1_device
*vsp1
,
574 struct vsp1_rwpf
*rwpf
,
575 u32 pixelformat
, unsigned int pitch
)
577 const struct vsp1_format_info
*fmtinfo
;
578 unsigned int chroma_hsub
;
580 fmtinfo
= vsp1_get_format_info(vsp1
, pixelformat
);
582 dev_dbg(vsp1
->dev
, "Unsupported pixel format %08x\n",
588 * Only formats with three planes can affect the chroma planes pitch.
589 * All formats with two planes have a horizontal subsampling value of 2,
590 * but combine U and V in a single chroma plane, which thus results in
591 * the luma plane and chroma plane having the same pitch.
593 chroma_hsub
= (fmtinfo
->planes
== 3) ? fmtinfo
->hsub
: 1;
595 rwpf
->fmtinfo
= fmtinfo
;
596 rwpf
->format
.num_planes
= fmtinfo
->planes
;
597 rwpf
->format
.plane_fmt
[0].bytesperline
= pitch
;
598 rwpf
->format
.plane_fmt
[1].bytesperline
= pitch
/ chroma_hsub
;
603 /* -----------------------------------------------------------------------------
607 int vsp1_du_init(struct device
*dev
)
609 struct vsp1_device
*vsp1
= dev_get_drvdata(dev
);
612 return -EPROBE_DEFER
;
616 EXPORT_SYMBOL_GPL(vsp1_du_init
);
619 * vsp1_du_setup_lif - Setup the output part of the VSP pipeline
620 * @dev: the VSP device
621 * @pipe_index: the DRM pipeline index
622 * @cfg: the LIF configuration
624 * Configure the output part of VSP DRM pipeline for the given frame @cfg.width
625 * and @cfg.height. This sets up formats on the BRx source pad, the WPF sink and
626 * source pads, and the LIF sink pad.
628 * The @pipe_index argument selects which DRM pipeline to setup. The number of
629 * available pipelines depend on the VSP instance.
631 * As the media bus code on the blend unit source pad is conditioned by the
632 * configuration of its sink 0 pad, we also set up the formats on all blend unit
633 * sinks, even if the configuration will be overwritten later by
634 * vsp1_du_setup_rpf(). This ensures that the blend unit configuration is set to
635 * a well defined state.
637 * Return 0 on success or a negative error code on failure.
639 int vsp1_du_setup_lif(struct device
*dev
, unsigned int pipe_index
,
640 const struct vsp1_du_lif_config
*cfg
)
642 struct vsp1_device
*vsp1
= dev_get_drvdata(dev
);
643 struct vsp1_drm_pipeline
*drm_pipe
;
644 struct vsp1_pipeline
*pipe
;
649 if (pipe_index
>= vsp1
->info
->lif_count
)
652 drm_pipe
= &vsp1
->drm
->pipe
[pipe_index
];
653 pipe
= &drm_pipe
->pipe
;
656 struct vsp1_brx
*brx
;
658 mutex_lock(&vsp1
->drm
->lock
);
660 brx
= to_brx(&pipe
->brx
->subdev
);
663 * NULL configuration means the CRTC is being disabled, stop
664 * the pipeline and turn the light off.
666 ret
= vsp1_pipeline_stop(pipe
);
667 if (ret
== -ETIMEDOUT
)
668 dev_err(vsp1
->dev
, "DRM pipeline stop timeout\n");
670 for (i
= 0; i
< ARRAY_SIZE(pipe
->inputs
); ++i
) {
671 struct vsp1_rwpf
*rpf
= pipe
->inputs
[i
];
677 * Remove the RPF from the pipe and the list of BRx
680 WARN_ON(!rpf
->entity
.pipe
);
681 rpf
->entity
.pipe
= NULL
;
682 list_del(&rpf
->entity
.list_pipe
);
683 pipe
->inputs
[i
] = NULL
;
685 brx
->inputs
[rpf
->brx_input
].rpf
= NULL
;
688 drm_pipe
->du_complete
= NULL
;
689 pipe
->num_inputs
= 0;
691 dev_dbg(vsp1
->dev
, "%s: pipe %u: releasing %s\n",
692 __func__
, pipe
->lif
->index
,
693 BRX_NAME(pipe
->brx
));
695 list_del(&pipe
->brx
->list_pipe
);
696 pipe
->brx
->pipe
= NULL
;
699 mutex_unlock(&vsp1
->drm
->lock
);
701 vsp1_dlm_reset(pipe
->output
->dlm
);
702 vsp1_device_put(vsp1
);
704 dev_dbg(vsp1
->dev
, "%s: pipeline disabled\n", __func__
);
709 drm_pipe
->width
= cfg
->width
;
710 drm_pipe
->height
= cfg
->height
;
711 pipe
->interlaced
= cfg
->interlaced
;
713 dev_dbg(vsp1
->dev
, "%s: configuring LIF%u with format %ux%u%s\n",
714 __func__
, pipe_index
, cfg
->width
, cfg
->height
,
715 pipe
->interlaced
? "i" : "");
717 mutex_lock(&vsp1
->drm
->lock
);
719 /* Setup formats through the pipeline. */
720 ret
= vsp1_du_pipeline_setup_inputs(vsp1
, pipe
);
724 ret
= vsp1_du_pipeline_setup_output(vsp1
, pipe
);
728 /* Enable the VSP1. */
729 ret
= vsp1_device_get(vsp1
);
734 * Register a callback to allow us to notify the DRM driver of frame
737 drm_pipe
->du_complete
= cfg
->callback
;
738 drm_pipe
->du_private
= cfg
->callback_data
;
740 /* Disable the display interrupts. */
741 vsp1_write(vsp1
, VI6_DISP_IRQ_STA(pipe_index
), 0);
742 vsp1_write(vsp1
, VI6_DISP_IRQ_ENB(pipe_index
), 0);
744 /* Configure all entities in the pipeline. */
745 vsp1_du_pipeline_configure(pipe
);
748 mutex_unlock(&vsp1
->drm
->lock
);
753 /* Start the pipeline. */
754 spin_lock_irqsave(&pipe
->irqlock
, flags
);
755 vsp1_pipeline_run(pipe
);
756 spin_unlock_irqrestore(&pipe
->irqlock
, flags
);
758 dev_dbg(vsp1
->dev
, "%s: pipeline enabled\n", __func__
);
762 EXPORT_SYMBOL_GPL(vsp1_du_setup_lif
);
765 * vsp1_du_atomic_begin - Prepare for an atomic update
766 * @dev: the VSP device
767 * @pipe_index: the DRM pipeline index
769 void vsp1_du_atomic_begin(struct device
*dev
, unsigned int pipe_index
)
772 EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin
);
775 * vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline
776 * @dev: the VSP device
777 * @pipe_index: the DRM pipeline index
778 * @rpf_index: index of the RPF to setup (0-based)
779 * @cfg: the RPF configuration
781 * Configure the VSP to perform image composition through RPF @rpf_index as
782 * described by the @cfg configuration. The image to compose is referenced by
783 * @cfg.mem and composed using the @cfg.src crop rectangle and the @cfg.dst
784 * composition rectangle. The Z-order is configurable with higher @zpos values
787 * If the @cfg configuration is NULL, the RPF will be disabled. Calling the
788 * function on a disabled RPF is allowed.
790 * Image format as stored in memory is expressed as a V4L2 @cfg.pixelformat
791 * value. The memory pitch is configurable to allow for padding at end of lines,
792 * or simply for images that extend beyond the crop rectangle boundaries. The
793 * @cfg.pitch value is expressed in bytes and applies to all planes for
794 * multiplanar formats.
796 * The source memory buffer is referenced by the DMA address of its planes in
797 * the @cfg.mem array. Up to two planes are supported. The second plane DMA
798 * address is ignored for formats using a single plane.
800 * This function isn't reentrant, the caller needs to serialize calls.
802 * Return 0 on success or a negative error code on failure.
804 int vsp1_du_atomic_update(struct device
*dev
, unsigned int pipe_index
,
805 unsigned int rpf_index
,
806 const struct vsp1_du_atomic_config
*cfg
)
808 struct vsp1_device
*vsp1
= dev_get_drvdata(dev
);
809 struct vsp1_drm_pipeline
*drm_pipe
= &vsp1
->drm
->pipe
[pipe_index
];
810 struct vsp1_rwpf
*rpf
;
813 if (rpf_index
>= vsp1
->info
->rpf_count
)
816 rpf
= vsp1
->rpf
[rpf_index
];
819 dev_dbg(vsp1
->dev
, "%s: RPF%u: disable requested\n", __func__
,
823 * Remove the RPF from the pipeline's inputs. Keep it in the
824 * pipeline's entity list to let vsp1_du_pipeline_configure()
825 * remove it from the hardware pipeline.
827 rpf
->entity
.pipe
= NULL
;
828 drm_pipe
->pipe
.inputs
[rpf_index
] = NULL
;
833 "%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%08x), pitch %u dma { %pad, %pad, %pad } zpos %u\n",
835 cfg
->src
.left
, cfg
->src
.top
, cfg
->src
.width
, cfg
->src
.height
,
836 cfg
->dst
.left
, cfg
->dst
.top
, cfg
->dst
.width
, cfg
->dst
.height
,
837 cfg
->pixelformat
, cfg
->pitch
, &cfg
->mem
[0], &cfg
->mem
[1],
838 &cfg
->mem
[2], cfg
->zpos
);
841 * Store the format, stride, memory buffer address, crop and compose
842 * rectangles and Z-order position and for the input.
844 ret
= vsp1_du_pipeline_set_rwpf_format(vsp1
, rpf
, cfg
->pixelformat
,
849 rpf
->alpha
= cfg
->alpha
;
851 rpf
->mem
.addr
[0] = cfg
->mem
[0];
852 rpf
->mem
.addr
[1] = cfg
->mem
[1];
853 rpf
->mem
.addr
[2] = cfg
->mem
[2];
855 vsp1
->drm
->inputs
[rpf_index
].crop
= cfg
->src
;
856 vsp1
->drm
->inputs
[rpf_index
].compose
= cfg
->dst
;
857 vsp1
->drm
->inputs
[rpf_index
].zpos
= cfg
->zpos
;
859 drm_pipe
->pipe
.inputs
[rpf_index
] = rpf
;
863 EXPORT_SYMBOL_GPL(vsp1_du_atomic_update
);
866 * vsp1_du_atomic_flush - Commit an atomic update
867 * @dev: the VSP device
868 * @pipe_index: the DRM pipeline index
869 * @cfg: atomic pipe configuration
871 void vsp1_du_atomic_flush(struct device
*dev
, unsigned int pipe_index
,
872 const struct vsp1_du_atomic_pipe_config
*cfg
)
874 struct vsp1_device
*vsp1
= dev_get_drvdata(dev
);
875 struct vsp1_drm_pipeline
*drm_pipe
= &vsp1
->drm
->pipe
[pipe_index
];
876 struct vsp1_pipeline
*pipe
= &drm_pipe
->pipe
;
879 drm_pipe
->crc
= cfg
->crc
;
881 mutex_lock(&vsp1
->drm
->lock
);
883 if (cfg
->writeback
.pixelformat
) {
884 const struct vsp1_du_writeback_config
*wb_cfg
= &cfg
->writeback
;
886 ret
= vsp1_du_pipeline_set_rwpf_format(vsp1
, pipe
->output
,
889 if (WARN_ON(ret
< 0))
892 pipe
->output
->mem
.addr
[0] = wb_cfg
->mem
[0];
893 pipe
->output
->mem
.addr
[1] = wb_cfg
->mem
[1];
894 pipe
->output
->mem
.addr
[2] = wb_cfg
->mem
[2];
895 pipe
->output
->writeback
= true;
898 vsp1_du_pipeline_setup_inputs(vsp1
, pipe
);
899 vsp1_du_pipeline_configure(pipe
);
902 mutex_unlock(&vsp1
->drm
->lock
);
904 EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush
);
906 int vsp1_du_map_sg(struct device
*dev
, struct sg_table
*sgt
)
908 struct vsp1_device
*vsp1
= dev_get_drvdata(dev
);
911 * As all the buffers allocated by the DU driver are coherent, we can
912 * skip cache sync. This will need to be revisited when support for
913 * non-coherent buffers will be added to the DU driver.
915 return dma_map_sgtable(vsp1
->bus_master
, sgt
, DMA_TO_DEVICE
,
916 DMA_ATTR_SKIP_CPU_SYNC
);
918 EXPORT_SYMBOL_GPL(vsp1_du_map_sg
);
920 void vsp1_du_unmap_sg(struct device
*dev
, struct sg_table
*sgt
)
922 struct vsp1_device
*vsp1
= dev_get_drvdata(dev
);
924 dma_unmap_sgtable(vsp1
->bus_master
, sgt
, DMA_TO_DEVICE
,
925 DMA_ATTR_SKIP_CPU_SYNC
);
927 EXPORT_SYMBOL_GPL(vsp1_du_unmap_sg
);
929 /* -----------------------------------------------------------------------------
933 int vsp1_drm_init(struct vsp1_device
*vsp1
)
937 vsp1
->drm
= devm_kzalloc(vsp1
->dev
, sizeof(*vsp1
->drm
), GFP_KERNEL
);
941 mutex_init(&vsp1
->drm
->lock
);
943 /* Create one DRM pipeline per LIF. */
944 for (i
= 0; i
< vsp1
->info
->lif_count
; ++i
) {
945 struct vsp1_drm_pipeline
*drm_pipe
= &vsp1
->drm
->pipe
[i
];
946 struct vsp1_pipeline
*pipe
= &drm_pipe
->pipe
;
948 init_waitqueue_head(&drm_pipe
->wait_queue
);
950 vsp1_pipeline_init(pipe
);
952 pipe
->frame_end
= vsp1_du_pipeline_frame_end
;
955 * The output side of the DRM pipeline is static, add the
956 * corresponding entities manually.
958 pipe
->output
= vsp1
->wpf
[i
];
959 pipe
->lif
= &vsp1
->lif
[i
]->entity
;
961 pipe
->output
->entity
.pipe
= pipe
;
962 pipe
->output
->entity
.sink
= pipe
->lif
;
963 pipe
->output
->entity
.sink_pad
= 0;
964 list_add_tail(&pipe
->output
->entity
.list_pipe
, &pipe
->entities
);
966 pipe
->lif
->pipe
= pipe
;
967 list_add_tail(&pipe
->lif
->list_pipe
, &pipe
->entities
);
970 * CRC computation is initially disabled, don't add the UIF to
973 if (i
< vsp1
->info
->uif_count
)
974 drm_pipe
->uif
= &vsp1
->uif
[i
]->entity
;
977 /* Disable all RPFs initially. */
978 for (i
= 0; i
< vsp1
->info
->rpf_count
; ++i
) {
979 struct vsp1_rwpf
*input
= vsp1
->rpf
[i
];
981 INIT_LIST_HEAD(&input
->entity
.list_pipe
);
987 void vsp1_drm_cleanup(struct vsp1_device
*vsp1
)
989 mutex_destroy(&vsp1
->drm
->lock
);