2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pnp.h>
29 #include <linux/interrupt.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <media/rc-core.h>
33 #include <linux/pci_ids.h>
35 #include "nuvoton-cir.h"
37 static void nvt_clear_cir_wake_fifo(struct nvt_dev
*nvt
);
39 static const struct nvt_chip nvt_chips
[] = {
40 { "w83667hg", NVT_W83667HG
},
41 { "NCT6775F", NVT_6775F
},
42 { "NCT6776F", NVT_6776F
},
43 { "NCT6779D", NVT_6779D
},
46 static inline struct device
*nvt_get_dev(const struct nvt_dev
*nvt
)
48 return nvt
->rdev
->dev
.parent
;
51 static inline bool is_w83667hg(struct nvt_dev
*nvt
)
53 return nvt
->chip_ver
== NVT_W83667HG
;
56 /* write val to config reg */
57 static inline void nvt_cr_write(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
59 outb(reg
, nvt
->cr_efir
);
60 outb(val
, nvt
->cr_efdr
);
63 /* read val from config reg */
64 static inline u8
nvt_cr_read(struct nvt_dev
*nvt
, u8 reg
)
66 outb(reg
, nvt
->cr_efir
);
67 return inb(nvt
->cr_efdr
);
70 /* update config register bit without changing other bits */
71 static inline void nvt_set_reg_bit(struct nvt_dev
*nvt
, u8 val
, u8 reg
)
73 u8 tmp
= nvt_cr_read(nvt
, reg
) | val
;
74 nvt_cr_write(nvt
, tmp
, reg
);
77 /* enter extended function mode */
78 static inline int nvt_efm_enable(struct nvt_dev
*nvt
)
80 if (!request_muxed_region(nvt
->cr_efir
, 2, NVT_DRIVER_NAME
))
83 /* Enabling Extended Function Mode explicitly requires writing 2x */
84 outb(EFER_EFM_ENABLE
, nvt
->cr_efir
);
85 outb(EFER_EFM_ENABLE
, nvt
->cr_efir
);
90 /* exit extended function mode */
91 static inline void nvt_efm_disable(struct nvt_dev
*nvt
)
93 outb(EFER_EFM_DISABLE
, nvt
->cr_efir
);
95 release_region(nvt
->cr_efir
, 2);
99 * When you want to address a specific logical device, write its logical
100 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
101 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
103 static inline void nvt_select_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
105 nvt_cr_write(nvt
, ldev
, CR_LOGICAL_DEV_SEL
);
108 /* select and enable logical device with setting EFM mode*/
109 static inline void nvt_enable_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
112 nvt_select_logical_dev(nvt
, ldev
);
113 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
114 nvt_efm_disable(nvt
);
117 /* select and disable logical device with setting EFM mode*/
118 static inline void nvt_disable_logical_dev(struct nvt_dev
*nvt
, u8 ldev
)
121 nvt_select_logical_dev(nvt
, ldev
);
122 nvt_cr_write(nvt
, LOGICAL_DEV_DISABLE
, CR_LOGICAL_DEV_EN
);
123 nvt_efm_disable(nvt
);
126 /* write val to cir config register */
127 static inline void nvt_cir_reg_write(struct nvt_dev
*nvt
, u8 val
, u8 offset
)
129 outb(val
, nvt
->cir_addr
+ offset
);
132 /* read val from cir config register */
133 static u8
nvt_cir_reg_read(struct nvt_dev
*nvt
, u8 offset
)
135 return inb(nvt
->cir_addr
+ offset
);
138 /* write val to cir wake register */
139 static inline void nvt_cir_wake_reg_write(struct nvt_dev
*nvt
,
142 outb(val
, nvt
->cir_wake_addr
+ offset
);
145 /* read val from cir wake config register */
146 static u8
nvt_cir_wake_reg_read(struct nvt_dev
*nvt
, u8 offset
)
148 return inb(nvt
->cir_wake_addr
+ offset
);
151 /* don't override io address if one is set already */
152 static void nvt_set_ioaddr(struct nvt_dev
*nvt
, unsigned long *ioaddr
)
154 unsigned long old_addr
;
156 old_addr
= nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8;
157 old_addr
|= nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
);
162 nvt_cr_write(nvt
, *ioaddr
>> 8, CR_CIR_BASE_ADDR_HI
);
163 nvt_cr_write(nvt
, *ioaddr
& 0xff, CR_CIR_BASE_ADDR_LO
);
167 static void nvt_write_wakeup_codes(struct rc_dev
*dev
,
168 const u8
*wbuf
, int count
)
170 u8 tolerance
, config
;
171 struct nvt_dev
*nvt
= dev
->priv
;
175 /* hardcode the tolerance to 10% */
176 tolerance
= DIV_ROUND_UP(count
, 10);
178 spin_lock_irqsave(&nvt
->lock
, flags
);
180 nvt_clear_cir_wake_fifo(nvt
);
181 nvt_cir_wake_reg_write(nvt
, count
, CIR_WAKE_FIFO_CMP_DEEP
);
182 nvt_cir_wake_reg_write(nvt
, tolerance
, CIR_WAKE_FIFO_CMP_TOL
);
184 config
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRCON
);
186 /* enable writes to wake fifo */
187 nvt_cir_wake_reg_write(nvt
, config
| CIR_WAKE_IRCON_MODE1
,
191 pr_info("Wake samples (%d) =", count
);
193 pr_info("Wake sample fifo cleared");
195 for (i
= 0; i
< count
; i
++)
196 nvt_cir_wake_reg_write(nvt
, wbuf
[i
], CIR_WAKE_WR_FIFO_DATA
);
198 nvt_cir_wake_reg_write(nvt
, config
, CIR_WAKE_IRCON
);
200 spin_unlock_irqrestore(&nvt
->lock
, flags
);
203 static ssize_t
wakeup_data_show(struct device
*dev
,
204 struct device_attribute
*attr
,
207 struct rc_dev
*rc_dev
= to_rc_dev(dev
);
208 struct nvt_dev
*nvt
= rc_dev
->priv
;
209 int fifo_len
, duration
;
214 spin_lock_irqsave(&nvt
->lock
, flags
);
216 fifo_len
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
);
217 fifo_len
= min(fifo_len
, WAKEUP_MAX_SIZE
);
219 /* go to first element to be read */
220 while (nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY_IDX
))
221 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
);
223 for (i
= 0; i
< fifo_len
; i
++) {
224 duration
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
);
225 duration
= (duration
& BUF_LEN_MASK
) * SAMPLE_PERIOD
;
226 buf_len
+= scnprintf(buf
+ buf_len
, PAGE_SIZE
- buf_len
,
229 buf_len
+= scnprintf(buf
+ buf_len
, PAGE_SIZE
- buf_len
, "\n");
231 spin_unlock_irqrestore(&nvt
->lock
, flags
);
236 static ssize_t
wakeup_data_store(struct device
*dev
,
237 struct device_attribute
*attr
,
238 const char *buf
, size_t len
)
240 struct rc_dev
*rc_dev
= to_rc_dev(dev
);
241 u8 wake_buf
[WAKEUP_MAX_SIZE
];
247 argv
= argv_split(GFP_KERNEL
, buf
, &count
);
250 if (!count
|| count
> WAKEUP_MAX_SIZE
) {
255 for (i
= 0; i
< count
; i
++) {
256 ret
= kstrtouint(argv
[i
], 10, &val
);
259 val
= DIV_ROUND_CLOSEST(val
, SAMPLE_PERIOD
);
260 if (!val
|| val
> 0x7f) {
265 /* sequence must start with a pulse */
267 wake_buf
[i
] |= BUF_PULSE_BIT
;
270 nvt_write_wakeup_codes(rc_dev
, wake_buf
, count
);
277 static DEVICE_ATTR_RW(wakeup_data
);
279 /* dump current cir register contents */
280 static void cir_dump_regs(struct nvt_dev
*nvt
)
283 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
285 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME
);
286 pr_info(" * CR CIR ACTIVE : 0x%x\n",
287 nvt_cr_read(nvt
, CR_LOGICAL_DEV_EN
));
288 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
289 (nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8) |
290 nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
));
291 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
292 nvt_cr_read(nvt
, CR_CIR_IRQ_RSRC
));
294 nvt_efm_disable(nvt
);
296 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME
);
297 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRCON
));
298 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRSTS
));
299 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IREN
));
300 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_RXFCONT
));
301 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_CP
));
302 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_CC
));
303 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SLCH
));
304 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SLCL
));
305 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FIFOCON
));
306 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRFIFOSTS
));
307 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_SRXFIFO
));
308 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_TXFCONT
));
309 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_STXFIFO
));
310 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FCCH
));
311 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_FCCL
));
312 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt
, CIR_IRFSM
));
315 /* dump current cir wake register contents */
316 static void cir_wake_dump_regs(struct nvt_dev
*nvt
)
321 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
323 pr_info("%s: Dump CIR WAKE logical device registers:\n",
325 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
326 nvt_cr_read(nvt
, CR_LOGICAL_DEV_EN
));
327 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
328 (nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_HI
) << 8) |
329 nvt_cr_read(nvt
, CR_CIR_BASE_ADDR_LO
));
330 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
331 nvt_cr_read(nvt
, CR_CIR_IRQ_RSRC
));
333 nvt_efm_disable(nvt
);
335 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME
);
336 pr_info(" * IRCON: 0x%x\n",
337 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRCON
));
338 pr_info(" * IRSTS: 0x%x\n",
339 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRSTS
));
340 pr_info(" * IREN: 0x%x\n",
341 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IREN
));
342 pr_info(" * FIFO CMP DEEP: 0x%x\n",
343 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_CMP_DEEP
));
344 pr_info(" * FIFO CMP TOL: 0x%x\n",
345 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_CMP_TOL
));
346 pr_info(" * FIFO COUNT: 0x%x\n",
347 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
));
348 pr_info(" * SLCH: 0x%x\n",
349 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SLCH
));
350 pr_info(" * SLCL: 0x%x\n",
351 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SLCL
));
352 pr_info(" * FIFOCON: 0x%x\n",
353 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFOCON
));
354 pr_info(" * SRXFSTS: 0x%x\n",
355 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SRXFSTS
));
356 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
357 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_SAMPLE_RX_FIFO
));
358 pr_info(" * WR FIFO DATA: 0x%x\n",
359 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_WR_FIFO_DATA
));
360 pr_info(" * RD FIFO ONLY: 0x%x\n",
361 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
));
362 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
363 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY_IDX
));
364 pr_info(" * FIFO IGNORE: 0x%x\n",
365 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_IGNORE
));
366 pr_info(" * IRFSM: 0x%x\n",
367 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRFSM
));
369 fifo_len
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFO_COUNT
);
370 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME
, fifo_len
);
371 pr_info("* Contents =");
372 for (i
= 0; i
< fifo_len
; i
++)
374 nvt_cir_wake_reg_read(nvt
, CIR_WAKE_RD_FIFO_ONLY
));
378 static inline const char *nvt_find_chip(struct nvt_dev
*nvt
, int id
)
382 for (i
= 0; i
< ARRAY_SIZE(nvt_chips
); i
++)
383 if ((id
& SIO_ID_MASK
) == nvt_chips
[i
].chip_ver
) {
384 nvt
->chip_ver
= nvt_chips
[i
].chip_ver
;
385 return nvt_chips
[i
].name
;
392 /* detect hardware features */
393 static int nvt_hw_detect(struct nvt_dev
*nvt
)
395 struct device
*dev
= nvt_get_dev(nvt
);
396 const char *chip_name
;
401 /* Check if we're wired for the alternate EFER setup */
402 nvt
->chip_major
= nvt_cr_read(nvt
, CR_CHIP_ID_HI
);
403 if (nvt
->chip_major
== 0xff) {
404 nvt_efm_disable(nvt
);
405 nvt
->cr_efir
= CR_EFIR2
;
406 nvt
->cr_efdr
= CR_EFDR2
;
408 nvt
->chip_major
= nvt_cr_read(nvt
, CR_CHIP_ID_HI
);
410 nvt
->chip_minor
= nvt_cr_read(nvt
, CR_CHIP_ID_LO
);
412 nvt_efm_disable(nvt
);
414 chip_id
= nvt
->chip_major
<< 8 | nvt
->chip_minor
;
415 if (chip_id
== NVT_INVALID
) {
416 dev_err(dev
, "No device found on either EFM port\n");
420 chip_name
= nvt_find_chip(nvt
, chip_id
);
422 /* warn, but still let the driver load, if we don't know this chip */
425 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
426 nvt
->chip_major
, nvt
->chip_minor
);
428 dev_info(dev
, "found %s or compatible: chip id: 0x%02x 0x%02x",
429 chip_name
, nvt
->chip_major
, nvt
->chip_minor
);
434 static void nvt_cir_ldev_init(struct nvt_dev
*nvt
)
436 u8 val
, psreg
, psmask
, psval
;
438 if (is_w83667hg(nvt
)) {
439 psreg
= CR_MULTIFUNC_PIN_SEL
;
440 psmask
= MULTIFUNC_PIN_SEL_MASK
;
441 psval
= MULTIFUNC_ENABLE_CIR
| MULTIFUNC_ENABLE_CIRWB
;
443 psreg
= CR_OUTPUT_PIN_SEL
;
444 psmask
= OUTPUT_PIN_SEL_MASK
;
445 psval
= OUTPUT_ENABLE_CIR
| OUTPUT_ENABLE_CIRWB
;
448 /* output pin selection: enable CIR, with WB sensor enabled */
449 val
= nvt_cr_read(nvt
, psreg
);
452 nvt_cr_write(nvt
, val
, psreg
);
454 /* Select CIR logical device */
455 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR
);
457 nvt_set_ioaddr(nvt
, &nvt
->cir_addr
);
459 nvt_cr_write(nvt
, nvt
->cir_irq
, CR_CIR_IRQ_RSRC
);
461 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
462 nvt
->cir_addr
, nvt
->cir_irq
);
465 static void nvt_cir_wake_ldev_init(struct nvt_dev
*nvt
)
467 /* Select ACPI logical device and anable it */
468 nvt_select_logical_dev(nvt
, LOGICAL_DEV_ACPI
);
469 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
471 /* Enable CIR Wake via PSOUT# (Pin60) */
472 nvt_set_reg_bit(nvt
, CIR_WAKE_ENABLE_BIT
, CR_ACPI_CIR_WAKE
);
474 /* enable pme interrupt of cir wakeup event */
475 nvt_set_reg_bit(nvt
, PME_INTR_CIR_PASS_BIT
, CR_ACPI_IRQ_EVENTS2
);
477 /* Select CIR Wake logical device */
478 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
480 nvt_set_ioaddr(nvt
, &nvt
->cir_wake_addr
);
482 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx",
486 /* clear out the hardware's cir rx fifo */
487 static void nvt_clear_cir_fifo(struct nvt_dev
*nvt
)
489 u8 val
= nvt_cir_reg_read(nvt
, CIR_FIFOCON
);
490 nvt_cir_reg_write(nvt
, val
| CIR_FIFOCON_RXFIFOCLR
, CIR_FIFOCON
);
493 /* clear out the hardware's cir wake rx fifo */
494 static void nvt_clear_cir_wake_fifo(struct nvt_dev
*nvt
)
498 config
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_IRCON
);
500 /* clearing wake fifo works in learning mode only */
501 nvt_cir_wake_reg_write(nvt
, config
& ~CIR_WAKE_IRCON_MODE0
,
504 val
= nvt_cir_wake_reg_read(nvt
, CIR_WAKE_FIFOCON
);
505 nvt_cir_wake_reg_write(nvt
, val
| CIR_WAKE_FIFOCON_RXFIFOCLR
,
508 nvt_cir_wake_reg_write(nvt
, config
, CIR_WAKE_IRCON
);
511 /* clear out the hardware's cir tx fifo */
512 static void nvt_clear_tx_fifo(struct nvt_dev
*nvt
)
516 val
= nvt_cir_reg_read(nvt
, CIR_FIFOCON
);
517 nvt_cir_reg_write(nvt
, val
| CIR_FIFOCON_TXFIFOCLR
, CIR_FIFOCON
);
520 /* enable RX Trigger Level Reach and Packet End interrupts */
521 static void nvt_set_cir_iren(struct nvt_dev
*nvt
)
525 iren
= CIR_IREN_RTR
| CIR_IREN_PE
| CIR_IREN_RFO
;
526 nvt_cir_reg_write(nvt
, iren
, CIR_IREN
);
529 static void nvt_cir_regs_init(struct nvt_dev
*nvt
)
531 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
533 /* set sample limit count (PE interrupt raised when reached) */
534 nvt_cir_reg_write(nvt
, CIR_RX_LIMIT_COUNT
>> 8, CIR_SLCH
);
535 nvt_cir_reg_write(nvt
, CIR_RX_LIMIT_COUNT
& 0xff, CIR_SLCL
);
537 /* set fifo irq trigger levels */
538 nvt_cir_reg_write(nvt
, CIR_FIFOCON_TX_TRIGGER_LEV
|
539 CIR_FIFOCON_RX_TRIGGER_LEV
, CIR_FIFOCON
);
541 /* clear hardware rx and tx fifos */
542 nvt_clear_cir_fifo(nvt
);
543 nvt_clear_tx_fifo(nvt
);
545 nvt_disable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
548 static void nvt_cir_wake_regs_init(struct nvt_dev
*nvt
)
550 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
553 * Disable RX, set specific carrier on = low, off = high,
554 * and sample period (currently 50us)
556 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_IRCON_MODE0
|
557 CIR_WAKE_IRCON_R
| CIR_WAKE_IRCON_RXINV
|
558 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL
,
561 /* clear any and all stray interrupts */
562 nvt_cir_wake_reg_write(nvt
, 0xff, CIR_WAKE_IRSTS
);
565 static void nvt_enable_wake(struct nvt_dev
*nvt
)
571 nvt_select_logical_dev(nvt
, LOGICAL_DEV_ACPI
);
572 nvt_set_reg_bit(nvt
, CIR_WAKE_ENABLE_BIT
, CR_ACPI_CIR_WAKE
);
573 nvt_set_reg_bit(nvt
, PME_INTR_CIR_PASS_BIT
, CR_ACPI_IRQ_EVENTS2
);
575 nvt_select_logical_dev(nvt
, LOGICAL_DEV_CIR_WAKE
);
576 nvt_cr_write(nvt
, LOGICAL_DEV_ENABLE
, CR_LOGICAL_DEV_EN
);
578 nvt_efm_disable(nvt
);
580 spin_lock_irqsave(&nvt
->lock
, flags
);
582 nvt_cir_wake_reg_write(nvt
, CIR_WAKE_IRCON_MODE0
| CIR_WAKE_IRCON_RXEN
|
583 CIR_WAKE_IRCON_R
| CIR_WAKE_IRCON_RXINV
|
584 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL
,
586 nvt_cir_wake_reg_write(nvt
, 0xff, CIR_WAKE_IRSTS
);
587 nvt_cir_wake_reg_write(nvt
, 0, CIR_WAKE_IREN
);
589 spin_unlock_irqrestore(&nvt
->lock
, flags
);
592 #if 0 /* Currently unused */
593 /* rx carrier detect only works in learning mode, must be called w/lock */
594 static u32
nvt_rx_carrier_detect(struct nvt_dev
*nvt
)
596 u32 count
, carrier
, duration
= 0;
599 count
= nvt_cir_reg_read(nvt
, CIR_FCCL
) |
600 nvt_cir_reg_read(nvt
, CIR_FCCH
) << 8;
602 for (i
= 0; i
< nvt
->pkts
; i
++) {
603 if (nvt
->buf
[i
] & BUF_PULSE_BIT
)
604 duration
+= nvt
->buf
[i
] & BUF_LEN_MASK
;
607 duration
*= SAMPLE_PERIOD
;
609 if (!count
|| !duration
) {
610 dev_notice(nvt_get_dev(nvt
),
611 "Unable to determine carrier! (c:%u, d:%u)",
616 carrier
= MS_TO_NS(count
) / duration
;
618 if ((carrier
> MAX_CARRIER
) || (carrier
< MIN_CARRIER
))
619 nvt_dbg("WTF? Carrier frequency out of range!");
621 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
622 carrier
, count
, duration
);
628 static int nvt_ir_raw_set_wakeup_filter(struct rc_dev
*dev
,
629 struct rc_scancode_filter
*sc_filter
)
634 struct ir_raw_event
*raw
;
635 u8 wake_buf
[WAKEUP_MAX_SIZE
];
638 /* Require mask to be set */
639 if (!sc_filter
->mask
)
642 raw
= kmalloc_array(WAKEUP_MAX_SIZE
, sizeof(*raw
), GFP_KERNEL
);
646 ret
= ir_raw_encode_scancode(dev
->wakeup_protocol
, sc_filter
->data
,
647 raw
, WAKEUP_MAX_SIZE
);
648 complete
= (ret
!= -ENOBUFS
);
650 ret
= WAKEUP_MAX_SIZE
;
654 /* Inspect the ir samples */
655 for (i
= 0, count
= 0; i
< ret
&& count
< WAKEUP_MAX_SIZE
; ++i
) {
656 val
= raw
[i
].duration
/ SAMPLE_PERIOD
;
658 /* Split too large values into several smaller ones */
659 while (val
> 0 && count
< WAKEUP_MAX_SIZE
) {
660 /* Skip last value for better comparison tolerance */
661 if (complete
&& i
== ret
- 1 && val
< BUF_LEN_MASK
)
664 /* Clamp values to BUF_LEN_MASK at most */
665 buf_val
= (val
> BUF_LEN_MASK
) ? BUF_LEN_MASK
: val
;
667 wake_buf
[count
] = buf_val
;
670 wake_buf
[count
] |= BUF_PULSE_BIT
;
675 nvt_write_wakeup_codes(dev
, wake_buf
, count
);
683 /* dump contents of the last rx buffer we got from the hw rx fifo */
684 static void nvt_dump_rx_buf(struct nvt_dev
*nvt
)
688 printk(KERN_DEBUG
"%s (len %d): ", __func__
, nvt
->pkts
);
689 for (i
= 0; (i
< nvt
->pkts
) && (i
< RX_BUF_LEN
); i
++)
690 printk(KERN_CONT
"0x%02x ", nvt
->buf
[i
]);
691 printk(KERN_CONT
"\n");
695 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
696 * trigger decode when appropriate.
698 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
699 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
700 * (default 50us) intervals for that pulse/space. A discrete signal is
701 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
702 * to signal more IR coming (repeats) or end of IR, respectively. We store
703 * sample data in the raw event kfifo until we see 0x7<something> (except f)
704 * or 0x80, at which time, we trigger a decode operation.
706 static void nvt_process_rx_ir_data(struct nvt_dev
*nvt
)
708 struct ir_raw_event rawir
= {};
712 nvt_dbg_verbose("%s firing", __func__
);
715 nvt_dump_rx_buf(nvt
);
717 nvt_dbg_verbose("Processing buffer of len %d", nvt
->pkts
);
719 for (i
= 0; i
< nvt
->pkts
; i
++) {
720 sample
= nvt
->buf
[i
];
722 rawir
.pulse
= ((sample
& BUF_PULSE_BIT
) != 0);
723 rawir
.duration
= (sample
& BUF_LEN_MASK
) * SAMPLE_PERIOD
;
725 nvt_dbg("Storing %s with duration %d",
726 rawir
.pulse
? "pulse" : "space", rawir
.duration
);
728 ir_raw_event_store_with_filter(nvt
->rdev
, &rawir
);
733 nvt_dbg("Calling ir_raw_event_handle\n");
734 ir_raw_event_handle(nvt
->rdev
);
736 nvt_dbg_verbose("%s done", __func__
);
739 static void nvt_handle_rx_fifo_overrun(struct nvt_dev
*nvt
)
741 dev_warn(nvt_get_dev(nvt
), "RX FIFO overrun detected, flushing data!");
744 nvt_clear_cir_fifo(nvt
);
745 ir_raw_event_reset(nvt
->rdev
);
748 /* copy data from hardware rx fifo into driver buffer */
749 static void nvt_get_rx_ir_data(struct nvt_dev
*nvt
)
754 /* Get count of how many bytes to read from RX FIFO */
755 fifocount
= nvt_cir_reg_read(nvt
, CIR_RXFCONT
);
757 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount
);
759 /* Read fifocount bytes from CIR Sample RX FIFO register */
760 for (i
= 0; i
< fifocount
; i
++)
761 nvt
->buf
[i
] = nvt_cir_reg_read(nvt
, CIR_SRXFIFO
);
763 nvt
->pkts
= fifocount
;
764 nvt_dbg("%s: pkts now %d", __func__
, nvt
->pkts
);
766 nvt_process_rx_ir_data(nvt
);
769 static void nvt_cir_log_irqs(u8 status
, u8 iren
)
771 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
773 status
& CIR_IRSTS_RDR
? " RDR" : "",
774 status
& CIR_IRSTS_RTR
? " RTR" : "",
775 status
& CIR_IRSTS_PE
? " PE" : "",
776 status
& CIR_IRSTS_RFO
? " RFO" : "",
777 status
& CIR_IRSTS_TE
? " TE" : "",
778 status
& CIR_IRSTS_TTR
? " TTR" : "",
779 status
& CIR_IRSTS_TFU
? " TFU" : "",
780 status
& CIR_IRSTS_GH
? " GH" : "",
781 status
& ~(CIR_IRSTS_RDR
| CIR_IRSTS_RTR
| CIR_IRSTS_PE
|
782 CIR_IRSTS_RFO
| CIR_IRSTS_TE
| CIR_IRSTS_TTR
|
783 CIR_IRSTS_TFU
| CIR_IRSTS_GH
) ? " ?" : "");
786 /* interrupt service routine for incoming and outgoing CIR data */
787 static irqreturn_t
nvt_cir_isr(int irq
, void *data
)
789 struct nvt_dev
*nvt
= data
;
792 nvt_dbg_verbose("%s firing", __func__
);
794 spin_lock(&nvt
->lock
);
797 * Get IR Status register contents. Write 1 to ack/clear
799 * bit: reg name - description
800 * 7: CIR_IRSTS_RDR - RX Data Ready
801 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
802 * 5: CIR_IRSTS_PE - Packet End
803 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
804 * 3: CIR_IRSTS_TE - TX FIFO Empty
805 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
806 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
807 * 0: CIR_IRSTS_GH - Min Length Detected
809 status
= nvt_cir_reg_read(nvt
, CIR_IRSTS
);
810 iren
= nvt_cir_reg_read(nvt
, CIR_IREN
);
812 /* At least NCT6779D creates a spurious interrupt when the
813 * logical device is being disabled.
815 if (status
== 0xff && iren
== 0xff) {
816 spin_unlock(&nvt
->lock
);
817 nvt_dbg_verbose("Spurious interrupt detected");
821 /* IRQ may be shared with CIR WAKE, therefore check for each
822 * status bit whether the related interrupt source is enabled
824 if (!(status
& iren
)) {
825 spin_unlock(&nvt
->lock
);
826 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__
);
830 /* ack/clear all irq flags we've got */
831 nvt_cir_reg_write(nvt
, status
, CIR_IRSTS
);
832 nvt_cir_reg_write(nvt
, 0, CIR_IRSTS
);
834 nvt_cir_log_irqs(status
, iren
);
836 if (status
& CIR_IRSTS_RFO
)
837 nvt_handle_rx_fifo_overrun(nvt
);
838 else if (status
& (CIR_IRSTS_RTR
| CIR_IRSTS_PE
))
839 nvt_get_rx_ir_data(nvt
);
841 spin_unlock(&nvt
->lock
);
843 nvt_dbg_verbose("%s done", __func__
);
847 static void nvt_enable_cir(struct nvt_dev
*nvt
)
851 /* enable the CIR logical device */
852 nvt_enable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
854 spin_lock_irqsave(&nvt
->lock
, flags
);
857 * Enable TX and RX, specify carrier on = low, off = high, and set
858 * sample period (currently 50us)
860 nvt_cir_reg_write(nvt
, CIR_IRCON_TXEN
| CIR_IRCON_RXEN
|
861 CIR_IRCON_RXINV
| CIR_IRCON_SAMPLE_PERIOD_SEL
,
864 /* clear all pending interrupts */
865 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
867 /* enable interrupts */
868 nvt_set_cir_iren(nvt
);
870 spin_unlock_irqrestore(&nvt
->lock
, flags
);
873 static void nvt_disable_cir(struct nvt_dev
*nvt
)
877 spin_lock_irqsave(&nvt
->lock
, flags
);
879 /* disable CIR interrupts */
880 nvt_cir_reg_write(nvt
, 0, CIR_IREN
);
882 /* clear any and all pending interrupts */
883 nvt_cir_reg_write(nvt
, 0xff, CIR_IRSTS
);
885 /* clear all function enable flags */
886 nvt_cir_reg_write(nvt
, 0, CIR_IRCON
);
888 /* clear hardware rx and tx fifos */
889 nvt_clear_cir_fifo(nvt
);
890 nvt_clear_tx_fifo(nvt
);
892 spin_unlock_irqrestore(&nvt
->lock
, flags
);
894 /* disable the CIR logical device */
895 nvt_disable_logical_dev(nvt
, LOGICAL_DEV_CIR
);
898 static int nvt_open(struct rc_dev
*dev
)
900 struct nvt_dev
*nvt
= dev
->priv
;
907 static void nvt_close(struct rc_dev
*dev
)
909 struct nvt_dev
*nvt
= dev
->priv
;
911 nvt_disable_cir(nvt
);
914 /* Allocate memory, probe hardware, and initialize everything */
915 static int nvt_probe(struct pnp_dev
*pdev
, const struct pnp_device_id
*dev_id
)
921 nvt
= devm_kzalloc(&pdev
->dev
, sizeof(struct nvt_dev
), GFP_KERNEL
);
925 /* input device for IR remote */
926 nvt
->rdev
= devm_rc_allocate_device(&pdev
->dev
, RC_DRIVER_IR_RAW
);
931 /* activate pnp device */
932 ret
= pnp_activate_dev(pdev
);
934 dev_err(&pdev
->dev
, "Could not activate PNP device!\n");
938 /* validate pnp resources */
939 if (!pnp_port_valid(pdev
, 0) ||
940 pnp_port_len(pdev
, 0) < CIR_IOREG_LENGTH
) {
941 dev_err(&pdev
->dev
, "IR PNP Port not valid!\n");
945 if (!pnp_irq_valid(pdev
, 0)) {
946 dev_err(&pdev
->dev
, "PNP IRQ not valid!\n");
950 if (!pnp_port_valid(pdev
, 1) ||
951 pnp_port_len(pdev
, 1) < CIR_IOREG_LENGTH
) {
952 dev_err(&pdev
->dev
, "Wake PNP Port not valid!\n");
956 nvt
->cir_addr
= pnp_port_start(pdev
, 0);
957 nvt
->cir_irq
= pnp_irq(pdev
, 0);
959 nvt
->cir_wake_addr
= pnp_port_start(pdev
, 1);
961 nvt
->cr_efir
= CR_EFIR
;
962 nvt
->cr_efdr
= CR_EFDR
;
964 spin_lock_init(&nvt
->lock
);
966 pnp_set_drvdata(pdev
, nvt
);
968 ret
= nvt_hw_detect(nvt
);
972 /* Initialize CIR & CIR Wake Logical Devices */
974 nvt_cir_ldev_init(nvt
);
975 nvt_cir_wake_ldev_init(nvt
);
976 nvt_efm_disable(nvt
);
979 * Initialize CIR & CIR Wake Config Registers
980 * and enable logical devices
982 nvt_cir_regs_init(nvt
);
983 nvt_cir_wake_regs_init(nvt
);
985 /* Set up the rc device */
987 rdev
->allowed_protocols
= RC_PROTO_BIT_ALL_IR_DECODER
;
988 rdev
->allowed_wakeup_protocols
= RC_PROTO_BIT_ALL_IR_ENCODER
;
989 rdev
->encode_wakeup
= true;
990 rdev
->open
= nvt_open
;
991 rdev
->close
= nvt_close
;
992 rdev
->s_wakeup_filter
= nvt_ir_raw_set_wakeup_filter
;
993 rdev
->device_name
= "Nuvoton w836x7hg Infrared Remote Transceiver";
994 rdev
->input_phys
= "nuvoton/cir0";
995 rdev
->input_id
.bustype
= BUS_HOST
;
996 rdev
->input_id
.vendor
= PCI_VENDOR_ID_WINBOND2
;
997 rdev
->input_id
.product
= nvt
->chip_major
;
998 rdev
->input_id
.version
= nvt
->chip_minor
;
999 rdev
->driver_name
= NVT_DRIVER_NAME
;
1000 rdev
->map_name
= RC_MAP_RC6_MCE
;
1001 rdev
->timeout
= MS_TO_US(100);
1002 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1003 rdev
->rx_resolution
= CIR_SAMPLE_PERIOD
;
1005 rdev
->min_timeout
= XYZ
;
1006 rdev
->max_timeout
= XYZ
;
1008 ret
= devm_rc_register_device(&pdev
->dev
, rdev
);
1012 /* now claim resources */
1013 if (!devm_request_region(&pdev
->dev
, nvt
->cir_addr
,
1014 CIR_IOREG_LENGTH
, NVT_DRIVER_NAME
))
1017 ret
= devm_request_irq(&pdev
->dev
, nvt
->cir_irq
, nvt_cir_isr
,
1018 IRQF_SHARED
, NVT_DRIVER_NAME
, nvt
);
1022 if (!devm_request_region(&pdev
->dev
, nvt
->cir_wake_addr
,
1023 CIR_IOREG_LENGTH
, NVT_DRIVER_NAME
"-wake"))
1026 ret
= device_create_file(&rdev
->dev
, &dev_attr_wakeup_data
);
1030 device_init_wakeup(&pdev
->dev
, true);
1032 dev_notice(&pdev
->dev
, "driver has been successfully loaded\n");
1035 cir_wake_dump_regs(nvt
);
1041 static void nvt_remove(struct pnp_dev
*pdev
)
1043 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1045 device_remove_file(&nvt
->rdev
->dev
, &dev_attr_wakeup_data
);
1047 nvt_disable_cir(nvt
);
1049 /* enable CIR Wake (for IR power-on) */
1050 nvt_enable_wake(nvt
);
1053 static int nvt_suspend(struct pnp_dev
*pdev
, pm_message_t state
)
1055 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1057 nvt_dbg("%s called", __func__
);
1059 mutex_lock(&nvt
->rdev
->lock
);
1060 if (nvt
->rdev
->users
)
1061 nvt_disable_cir(nvt
);
1062 mutex_unlock(&nvt
->rdev
->lock
);
1064 /* make sure wake is enabled */
1065 nvt_enable_wake(nvt
);
1070 static int nvt_resume(struct pnp_dev
*pdev
)
1072 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1074 nvt_dbg("%s called", __func__
);
1076 nvt_cir_regs_init(nvt
);
1077 nvt_cir_wake_regs_init(nvt
);
1079 mutex_lock(&nvt
->rdev
->lock
);
1080 if (nvt
->rdev
->users
)
1081 nvt_enable_cir(nvt
);
1082 mutex_unlock(&nvt
->rdev
->lock
);
1087 static void nvt_shutdown(struct pnp_dev
*pdev
)
1089 struct nvt_dev
*nvt
= pnp_get_drvdata(pdev
);
1091 nvt_enable_wake(nvt
);
1094 static const struct pnp_device_id nvt_ids
[] = {
1095 { "WEC0530", 0 }, /* CIR */
1096 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1100 static struct pnp_driver nvt_driver
= {
1101 .name
= NVT_DRIVER_NAME
,
1102 .id_table
= nvt_ids
,
1103 .flags
= PNP_DRIVER_RES_DO_NOT_CHANGE
,
1105 .remove
= nvt_remove
,
1106 .suspend
= nvt_suspend
,
1107 .resume
= nvt_resume
,
1108 .shutdown
= nvt_shutdown
,
1111 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
1112 MODULE_PARM_DESC(debug
, "Enable debugging output");
1114 MODULE_DEVICE_TABLE(pnp
, nvt_ids
);
1115 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1117 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1118 MODULE_LICENSE("GPL");
1120 module_pnp_driver(nvt_driver
);