1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
6 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but
7 * could probably support others (Winbond WEC102X, NatSemi, etc)
8 * with minor modifications.
10 * Original Author: David Härdeman <david@hardeman.nu>
11 * Copyright (C) 2012 Sean Young <sean@mess.org>
12 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
14 * Dedicated to my daughter Matilda, without whose loving attention this
15 * driver would have been finished in half the time and with a fraction
19 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel
20 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff)
26 * o Wake-On-CIR functionality
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/pnp.h>
34 #include <linux/interrupt.h>
35 #include <linux/timer.h>
36 #include <linux/leds.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci_ids.h>
40 #include <linux/bitrev.h>
41 #include <linux/slab.h>
42 #include <linux/wait.h>
43 #include <linux/sched.h>
44 #include <media/rc-core.h>
46 #define DRVNAME "winbond-cir"
48 /* CEIR Wake-Up Registers, relative to data->wbase */
49 #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */
50 #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */
51 #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */
52 #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */
53 #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */
54 #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */
55 #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */
56 #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */
57 #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */
58 #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */
60 /* CEIR Enhanced Functionality Registers, relative to data->ebase */
61 #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */
62 #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */
63 #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */
64 #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */
65 #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */
67 /* SP3 Banked Registers, relative to data->sbase */
68 #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
70 #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */
71 #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
72 #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */
73 #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */
74 #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */
75 #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */
76 #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */
77 #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */
78 #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */
80 #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */
81 #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */
82 #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */
83 #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */
84 #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */
85 #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */
87 #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */
88 #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */
89 #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */
91 #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */
93 #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */
95 #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */
96 #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */
98 #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */
99 #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */
100 #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */
101 #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */
102 #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */
105 * Magic values follow
108 /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
109 #define WBCIR_IRQ_NONE 0x00
110 /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
111 #define WBCIR_IRQ_RX 0x01
112 /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
113 #define WBCIR_IRQ_TX_LOW 0x02
114 /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
115 #define WBCIR_IRQ_ERR 0x04
116 /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
117 #define WBCIR_IRQ_TX_EMPTY 0x20
118 /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
119 #define WBCIR_LED_ENABLE 0x80
120 /* RX data available bit for WBCIR_REG_SP3_LSR */
121 #define WBCIR_RX_AVAIL 0x01
122 /* RX data overrun error bit for WBCIR_REG_SP3_LSR */
123 #define WBCIR_RX_OVERRUN 0x02
124 /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
125 #define WBCIR_TX_EOT 0x04
126 /* RX disable bit for WBCIR_REG_SP3_ASCR */
127 #define WBCIR_RX_DISABLE 0x20
128 /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
129 #define WBCIR_TX_UNDERRUN 0x40
130 /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
131 #define WBCIR_EXT_ENABLE 0x01
132 /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
133 #define WBCIR_REGSEL_COMPARE 0x10
134 /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
135 #define WBCIR_REGSEL_MASK 0x20
136 /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */
137 #define WBCIR_REG_ADDR0 0x00
138 /* Enable carrier counter */
139 #define WBCIR_CNTR_EN 0x01
140 /* Reset carrier counter */
141 #define WBCIR_CNTR_R 0x02
143 #define WBCIR_IRTX_INV 0x04
144 /* Receiver oversampling */
145 #define WBCIR_RX_T_OV 0x40
147 /* Valid banks for the SP3 UART */
159 /* Supported power-on IR Protocols */
160 enum wbcir_protocol
{
161 IR_PROTOCOL_RC5
= 0x0,
162 IR_PROTOCOL_NEC
= 0x1,
163 IR_PROTOCOL_RC6
= 0x2,
166 /* Possible states for IR reception */
168 WBCIR_RXSTATE_INACTIVE
= 0,
169 WBCIR_RXSTATE_ACTIVE
,
173 /* Possible states for IR transmission */
175 WBCIR_TXSTATE_INACTIVE
= 0,
176 WBCIR_TXSTATE_ACTIVE
,
181 #define WBCIR_NAME "Winbond CIR"
182 #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
183 #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */
184 #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */
185 #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */
186 #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */
188 /* Per-device data */
192 struct led_classdev led
;
194 unsigned long wbase
; /* Wake-Up Baseaddr */
195 unsigned long ebase
; /* Enhanced Func. Baseaddr */
196 unsigned long sbase
; /* Serial Port Baseaddr */
197 unsigned int irq
; /* Serial Port IRQ */
201 enum wbcir_rxstate rxstate
;
202 int carrier_report_enabled
;
206 enum wbcir_txstate txstate
;
214 static bool invert
; /* default = 0 */
215 module_param(invert
, bool, 0444);
216 MODULE_PARM_DESC(invert
, "Invert the signal from the IR receiver");
218 static bool txandrx
; /* default = 0 */
219 module_param(txandrx
, bool, 0444);
220 MODULE_PARM_DESC(txandrx
, "Allow simultaneous TX and RX");
223 /*****************************************************************************
227 *****************************************************************************/
229 /* Caller needs to hold wbcir_lock */
231 wbcir_set_bits(unsigned long addr
, u8 bits
, u8 mask
)
236 val
= ((val
& ~mask
) | (bits
& mask
));
240 /* Selects the register bank for the serial port */
242 wbcir_select_bank(struct wbcir_data
*data
, enum wbcir_bank bank
)
244 outb(bank
, data
->sbase
+ WBCIR_REG_SP3_BSR
);
248 wbcir_set_irqmask(struct wbcir_data
*data
, u8 irqmask
)
250 if (data
->irqmask
== irqmask
)
253 wbcir_select_bank(data
, WBCIR_BANK_0
);
254 outb(irqmask
, data
->sbase
+ WBCIR_REG_SP3_IER
);
255 data
->irqmask
= irqmask
;
258 static enum led_brightness
259 wbcir_led_brightness_get(struct led_classdev
*led_cdev
)
261 struct wbcir_data
*data
= container_of(led_cdev
,
265 if (inb(data
->ebase
+ WBCIR_REG_ECEIR_CTS
) & WBCIR_LED_ENABLE
)
272 wbcir_led_brightness_set(struct led_classdev
*led_cdev
,
273 enum led_brightness brightness
)
275 struct wbcir_data
*data
= container_of(led_cdev
,
279 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CTS
,
280 brightness
== LED_OFF
? 0x00 : WBCIR_LED_ENABLE
,
284 /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */
286 wbcir_to_rc6cells(u8 val
)
292 for (i
= 0; i
< 4; i
++) {
294 coded
|= 0x02 << (i
* 2);
296 coded
|= 0x01 << (i
* 2);
303 /*****************************************************************************
305 * INTERRUPT FUNCTIONS
307 *****************************************************************************/
310 wbcir_carrier_report(struct wbcir_data
*data
)
312 unsigned counter
= inb(data
->ebase
+ WBCIR_REG_ECEIR_CNT_LO
) |
313 inb(data
->ebase
+ WBCIR_REG_ECEIR_CNT_HI
) << 8;
315 if (counter
> 0 && counter
< 0xffff) {
316 struct ir_raw_event ev
= {
318 .carrier
= DIV_ROUND_CLOSEST(counter
* 1000000u,
319 data
->pulse_duration
)
322 ir_raw_event_store(data
->dev
, &ev
);
325 /* reset and restart the counter */
326 data
->pulse_duration
= 0;
327 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CCTL
, WBCIR_CNTR_R
,
328 WBCIR_CNTR_EN
| WBCIR_CNTR_R
);
329 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CCTL
, WBCIR_CNTR_EN
,
330 WBCIR_CNTR_EN
| WBCIR_CNTR_R
);
334 wbcir_idle_rx(struct rc_dev
*dev
, bool idle
)
336 struct wbcir_data
*data
= dev
->priv
;
338 if (!idle
&& data
->rxstate
== WBCIR_RXSTATE_INACTIVE
)
339 data
->rxstate
= WBCIR_RXSTATE_ACTIVE
;
341 if (idle
&& data
->rxstate
!= WBCIR_RXSTATE_INACTIVE
) {
342 data
->rxstate
= WBCIR_RXSTATE_INACTIVE
;
344 if (data
->carrier_report_enabled
)
345 wbcir_carrier_report(data
);
347 /* Tell hardware to go idle by setting RXINACTIVE */
348 outb(WBCIR_RX_DISABLE
, data
->sbase
+ WBCIR_REG_SP3_ASCR
);
353 wbcir_irq_rx(struct wbcir_data
*data
, struct pnp_dev
*device
)
356 struct ir_raw_event rawir
= {};
358 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
359 while (inb(data
->sbase
+ WBCIR_REG_SP3_LSR
) & WBCIR_RX_AVAIL
) {
360 irdata
= inb(data
->sbase
+ WBCIR_REG_SP3_RXDATA
);
361 if (data
->rxstate
== WBCIR_RXSTATE_ERROR
)
364 rawir
.duration
= ((irdata
& 0x7F) + 1) *
365 (data
->carrier_report_enabled
? 2 : 10);
366 rawir
.pulse
= irdata
& 0x80 ? false : true;
369 data
->pulse_duration
+= rawir
.duration
;
371 ir_raw_event_store_with_filter(data
->dev
, &rawir
);
374 ir_raw_event_handle(data
->dev
);
378 wbcir_irq_tx(struct wbcir_data
*data
)
388 switch (data
->txstate
) {
389 case WBCIR_TXSTATE_INACTIVE
:
393 case WBCIR_TXSTATE_ACTIVE
:
394 /* TX FIFO low (3 bytes or less) */
397 case WBCIR_TXSTATE_ERROR
:
405 * TX data is run-length coded in bytes: YXXXXXXX
406 * Y = space (1) or pulse (0)
407 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
409 for (used
= 0; used
< space
&& data
->txoff
!= data
->txlen
; used
++) {
410 if (data
->txbuf
[data
->txoff
] == 0) {
414 byte
= min((u32
)0x80, data
->txbuf
[data
->txoff
]);
415 data
->txbuf
[data
->txoff
] -= byte
;
417 byte
|= (data
->txoff
% 2 ? 0x80 : 0x00); /* pulse/space */
421 while (data
->txoff
!= data
->txlen
&& data
->txbuf
[data
->txoff
] == 0)
426 if (data
->txstate
== WBCIR_TXSTATE_ERROR
)
427 /* Clear TX underrun bit */
428 outb(WBCIR_TX_UNDERRUN
, data
->sbase
+ WBCIR_REG_SP3_ASCR
);
429 wbcir_set_irqmask(data
, WBCIR_IRQ_RX
| WBCIR_IRQ_ERR
);
432 data
->txstate
= WBCIR_TXSTATE_INACTIVE
;
433 } else if (data
->txoff
== data
->txlen
) {
434 /* At the end of transmission, tell the hw before last byte */
435 outsb(data
->sbase
+ WBCIR_REG_SP3_TXDATA
, bytes
, used
- 1);
436 outb(WBCIR_TX_EOT
, data
->sbase
+ WBCIR_REG_SP3_ASCR
);
437 outb(bytes
[used
- 1], data
->sbase
+ WBCIR_REG_SP3_TXDATA
);
438 wbcir_set_irqmask(data
, WBCIR_IRQ_RX
| WBCIR_IRQ_ERR
|
441 /* More data to follow... */
442 outsb(data
->sbase
+ WBCIR_REG_SP3_RXDATA
, bytes
, used
);
443 if (data
->txstate
== WBCIR_TXSTATE_INACTIVE
) {
444 wbcir_set_irqmask(data
, WBCIR_IRQ_RX
| WBCIR_IRQ_ERR
|
446 data
->txstate
= WBCIR_TXSTATE_ACTIVE
;
452 wbcir_irq_handler(int irqno
, void *cookie
)
454 struct pnp_dev
*device
= cookie
;
455 struct wbcir_data
*data
= pnp_get_drvdata(device
);
459 spin_lock_irqsave(&data
->spinlock
, flags
);
460 wbcir_select_bank(data
, WBCIR_BANK_0
);
461 status
= inb(data
->sbase
+ WBCIR_REG_SP3_EIR
);
462 status
&= data
->irqmask
;
465 spin_unlock_irqrestore(&data
->spinlock
, flags
);
469 if (status
& WBCIR_IRQ_ERR
) {
470 /* RX overflow? (read clears bit) */
471 if (inb(data
->sbase
+ WBCIR_REG_SP3_LSR
) & WBCIR_RX_OVERRUN
) {
472 data
->rxstate
= WBCIR_RXSTATE_ERROR
;
473 ir_raw_event_reset(data
->dev
);
477 if (inb(data
->sbase
+ WBCIR_REG_SP3_ASCR
) & WBCIR_TX_UNDERRUN
)
478 data
->txstate
= WBCIR_TXSTATE_ERROR
;
481 if (status
& WBCIR_IRQ_RX
)
482 wbcir_irq_rx(data
, device
);
484 if (status
& (WBCIR_IRQ_TX_LOW
| WBCIR_IRQ_TX_EMPTY
))
487 spin_unlock_irqrestore(&data
->spinlock
, flags
);
491 /*****************************************************************************
493 * RC-CORE INTERFACE FUNCTIONS
495 *****************************************************************************/
498 wbcir_set_carrier_report(struct rc_dev
*dev
, int enable
)
500 struct wbcir_data
*data
= dev
->priv
;
503 spin_lock_irqsave(&data
->spinlock
, flags
);
505 if (data
->carrier_report_enabled
== enable
) {
506 spin_unlock_irqrestore(&data
->spinlock
, flags
);
510 data
->pulse_duration
= 0;
511 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CCTL
, WBCIR_CNTR_R
,
512 WBCIR_CNTR_EN
| WBCIR_CNTR_R
);
514 if (enable
&& data
->dev
->idle
)
515 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CCTL
,
516 WBCIR_CNTR_EN
, WBCIR_CNTR_EN
| WBCIR_CNTR_R
);
518 /* Set a higher sampling resolution if carrier reports are enabled */
519 wbcir_select_bank(data
, WBCIR_BANK_2
);
520 data
->dev
->rx_resolution
= enable
? 2 : 10;
521 outb(enable
? 0x03 : 0x0f, data
->sbase
+ WBCIR_REG_SP3_BGDL
);
522 outb(0x00, data
->sbase
+ WBCIR_REG_SP3_BGDH
);
524 /* Enable oversampling if carrier reports are enabled */
525 wbcir_select_bank(data
, WBCIR_BANK_7
);
526 wbcir_set_bits(data
->sbase
+ WBCIR_REG_SP3_RCCFG
,
527 enable
? WBCIR_RX_T_OV
: 0, WBCIR_RX_T_OV
);
529 data
->carrier_report_enabled
= enable
;
530 spin_unlock_irqrestore(&data
->spinlock
, flags
);
536 wbcir_txcarrier(struct rc_dev
*dev
, u32 carrier
)
538 struct wbcir_data
*data
= dev
->priv
;
543 freq
= DIV_ROUND_CLOSEST(carrier
, 1000);
544 if (freq
< 30 || freq
> 60)
564 spin_lock_irqsave(&data
->spinlock
, flags
);
565 if (data
->txstate
!= WBCIR_TXSTATE_INACTIVE
) {
566 spin_unlock_irqrestore(&data
->spinlock
, flags
);
570 if (data
->txcarrier
!= freq
) {
571 wbcir_select_bank(data
, WBCIR_BANK_7
);
572 wbcir_set_bits(data
->sbase
+ WBCIR_REG_SP3_IRTXMC
, val
, 0x1F);
573 data
->txcarrier
= freq
;
576 spin_unlock_irqrestore(&data
->spinlock
, flags
);
581 wbcir_txmask(struct rc_dev
*dev
, u32 mask
)
583 struct wbcir_data
*data
= dev
->priv
;
587 /* return the number of transmitters */
591 /* Four outputs, only one output can be enabled at a time */
609 spin_lock_irqsave(&data
->spinlock
, flags
);
610 if (data
->txstate
!= WBCIR_TXSTATE_INACTIVE
) {
611 spin_unlock_irqrestore(&data
->spinlock
, flags
);
615 if (data
->txmask
!= mask
) {
616 wbcir_set_bits(data
->ebase
+ WBCIR_REG_ECEIR_CTS
, val
, 0x0c);
620 spin_unlock_irqrestore(&data
->spinlock
, flags
);
625 wbcir_tx(struct rc_dev
*dev
, unsigned *b
, unsigned count
)
627 struct wbcir_data
*data
= dev
->priv
;
632 buf
= kmalloc_array(count
, sizeof(*b
), GFP_KERNEL
);
636 /* Convert values to multiples of 10us */
637 for (i
= 0; i
< count
; i
++)
638 buf
[i
] = DIV_ROUND_CLOSEST(b
[i
], 10);
640 /* Not sure if this is possible, but better safe than sorry */
641 spin_lock_irqsave(&data
->spinlock
, flags
);
642 if (data
->txstate
!= WBCIR_TXSTATE_INACTIVE
) {
643 spin_unlock_irqrestore(&data
->spinlock
, flags
);
648 /* Fill the TX fifo once, the irq handler will do the rest */
655 spin_unlock_irqrestore(&data
->spinlock
, flags
);
659 /*****************************************************************************
661 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS
663 *****************************************************************************/
666 wbcir_shutdown(struct pnp_dev
*device
)
668 struct device
*dev
= &device
->dev
;
669 struct wbcir_data
*data
= pnp_get_drvdata(device
);
670 struct rc_dev
*rc
= data
->dev
;
676 u32 wake_sc
= rc
->scancode_wakeup_filter
.data
;
677 u32 mask_sc
= rc
->scancode_wakeup_filter
.mask
;
680 memset(match
, 0, sizeof(match
));
681 memset(mask
, 0, sizeof(mask
));
683 if (!mask_sc
|| !device_may_wakeup(dev
)) {
688 switch (rc
->wakeup_protocol
) {
690 /* Mask = 13 bits, ex toggle */
691 mask
[0] = (mask_sc
& 0x003f);
692 mask
[0] |= (mask_sc
& 0x0300) >> 2;
693 mask
[1] = (mask_sc
& 0x1c00) >> 10;
694 if (mask_sc
& 0x0040) /* 2nd start bit */
697 match
[0] = (wake_sc
& 0x003F); /* 6 command bits */
698 match
[0] |= (wake_sc
& 0x0300) >> 2; /* 2 address bits */
699 match
[1] = (wake_sc
& 0x1c00) >> 10; /* 3 address bits */
700 if (!(wake_sc
& 0x0040)) /* 2nd start bit */
703 proto
= IR_PROTOCOL_RC5
;
707 mask
[1] = bitrev8(mask_sc
);
709 mask
[3] = bitrev8(mask_sc
>> 8);
712 match
[1] = bitrev8(wake_sc
);
713 match
[0] = ~match
[1];
714 match
[3] = bitrev8(wake_sc
>> 8);
715 match
[2] = ~match
[3];
717 proto
= IR_PROTOCOL_NEC
;
721 mask
[1] = bitrev8(mask_sc
);
723 mask
[2] = bitrev8(mask_sc
>> 8);
724 mask
[3] = bitrev8(mask_sc
>> 16);
726 match
[1] = bitrev8(wake_sc
);
727 match
[0] = ~match
[1];
728 match
[2] = bitrev8(wake_sc
>> 8);
729 match
[3] = bitrev8(wake_sc
>> 16);
731 proto
= IR_PROTOCOL_NEC
;
735 mask
[0] = bitrev8(mask_sc
);
736 mask
[1] = bitrev8(mask_sc
>> 8);
737 mask
[2] = bitrev8(mask_sc
>> 16);
738 mask
[3] = bitrev8(mask_sc
>> 24);
740 match
[0] = bitrev8(wake_sc
);
741 match
[1] = bitrev8(wake_sc
>> 8);
742 match
[2] = bitrev8(wake_sc
>> 16);
743 match
[3] = bitrev8(wake_sc
>> 24);
745 proto
= IR_PROTOCOL_NEC
;
750 match
[0] = wbcir_to_rc6cells(wake_sc
>> 0);
751 mask
[0] = wbcir_to_rc6cells(mask_sc
>> 0);
752 match
[1] = wbcir_to_rc6cells(wake_sc
>> 4);
753 mask
[1] = wbcir_to_rc6cells(mask_sc
>> 4);
756 match
[2] = wbcir_to_rc6cells(wake_sc
>> 8);
757 mask
[2] = wbcir_to_rc6cells(mask_sc
>> 8);
758 match
[3] = wbcir_to_rc6cells(wake_sc
>> 12);
759 mask
[3] = wbcir_to_rc6cells(mask_sc
>> 12);
762 match
[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
764 match
[5] = 0x09; /* start bit = 1, mode2 = 0 */
768 proto
= IR_PROTOCOL_RC6
;
771 case RC_PROTO_RC6_6A_24
:
772 case RC_PROTO_RC6_6A_32
:
773 case RC_PROTO_RC6_MCE
:
777 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 0);
778 mask
[i
++] = wbcir_to_rc6cells(mask_sc
>> 0);
779 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 4);
780 mask
[i
++] = wbcir_to_rc6cells(mask_sc
>> 4);
782 /* Address + Toggle */
783 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 8);
784 mask
[i
++] = wbcir_to_rc6cells(mask_sc
>> 8);
785 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 12);
786 mask
[i
++] = wbcir_to_rc6cells(mask_sc
>> 12);
788 /* Customer bits 7 - 0 */
789 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 16);
790 mask
[i
++] = wbcir_to_rc6cells(mask_sc
>> 16);
792 if (rc
->wakeup_protocol
== RC_PROTO_RC6_6A_20
) {
795 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 20);
796 mask
[i
++] = wbcir_to_rc6cells(mask_sc
>> 20);
798 if (rc
->wakeup_protocol
== RC_PROTO_RC6_6A_24
) {
801 /* Customer range bit and bits 15 - 8 */
802 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 24);
803 mask
[i
++] = wbcir_to_rc6cells(mask_sc
>> 24);
804 match
[i
] = wbcir_to_rc6cells(wake_sc
>> 28);
805 mask
[i
++] = wbcir_to_rc6cells(mask_sc
>> 28);
811 match
[i
] = 0x93; /* mode1 = mode0 = 1, submode = 0 */
813 match
[i
] = 0x0A; /* start bit = 1, mode2 = 1 */
815 proto
= IR_PROTOCOL_RC6
;
824 /* Set compare and compare mask */
825 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_INDEX
,
826 WBCIR_REGSEL_COMPARE
| WBCIR_REG_ADDR0
,
828 outsb(data
->wbase
+ WBCIR_REG_WCEIR_DATA
, match
, 11);
829 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_INDEX
,
830 WBCIR_REGSEL_MASK
| WBCIR_REG_ADDR0
,
832 outsb(data
->wbase
+ WBCIR_REG_WCEIR_DATA
, mask
, 11);
834 /* RC6 Compare String Len */
835 outb(rc6_csl
, data
->wbase
+ WBCIR_REG_WCEIR_CSL
);
837 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
838 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_STS
, 0x17, 0x17);
840 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */
841 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_EV_EN
, 0x01, 0x07);
844 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_CTL
,
845 (proto
<< 4) | 0x01, 0x31);
848 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
849 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_EV_EN
, 0x00, 0x07);
852 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_CTL
, 0x00, 0x01);
856 * ACPI will set the HW disable bit for SP3 which means that the
857 * output signals are left in an undefined state which may cause
858 * spurious interrupts which we need to ignore until the hardware
861 wbcir_set_irqmask(data
, WBCIR_IRQ_NONE
);
862 disable_irq(data
->irq
);
866 * Wakeup handling is done on shutdown.
869 wbcir_set_wakeup_filter(struct rc_dev
*rc
, struct rc_scancode_filter
*filter
)
875 wbcir_suspend(struct pnp_dev
*device
, pm_message_t state
)
877 struct wbcir_data
*data
= pnp_get_drvdata(device
);
878 led_classdev_suspend(&data
->led
);
879 wbcir_shutdown(device
);
884 wbcir_init_hw(struct wbcir_data
*data
)
886 /* Disable interrupts */
887 wbcir_set_irqmask(data
, WBCIR_IRQ_NONE
);
889 /* Set RX_INV, Clear CEIR_EN (needed for the led) */
890 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_CTL
, invert
? 8 : 0, 0x09);
892 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
893 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_STS
, 0x17, 0x17);
895 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
896 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_EV_EN
, 0x00, 0x07);
898 /* Set RC5 cell time to correspond to 36 kHz */
899 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_CFG1
, 0x4A, 0x7F);
903 outb(WBCIR_IRTX_INV
, data
->ebase
+ WBCIR_REG_ECEIR_CCTL
);
905 outb(0x00, data
->ebase
+ WBCIR_REG_ECEIR_CCTL
);
908 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
909 * set SP3_IRRX_SW to binary 01, helpfully not documented
911 outb(0x10, data
->ebase
+ WBCIR_REG_ECEIR_CTS
);
914 /* Enable extended mode */
915 wbcir_select_bank(data
, WBCIR_BANK_2
);
916 outb(WBCIR_EXT_ENABLE
, data
->sbase
+ WBCIR_REG_SP3_EXCR1
);
919 * Configure baud generator, IR data will be sampled at
920 * a bitrate of: (24Mhz * prescaler) / (divisor * 16).
922 * The ECIR registers include a flag to change the
923 * 24Mhz clock freq to 48Mhz.
925 * It's not documented in the specs, but fifo levels
926 * other than 16 seems to be unsupported.
929 /* prescaler 1.0, tx/rx fifo lvl 16 */
930 outb(0x30, data
->sbase
+ WBCIR_REG_SP3_EXCR2
);
932 /* Set baud divisor to sample every 10 us */
933 outb(0x0f, data
->sbase
+ WBCIR_REG_SP3_BGDL
);
934 outb(0x00, data
->sbase
+ WBCIR_REG_SP3_BGDH
);
937 wbcir_select_bank(data
, WBCIR_BANK_0
);
938 outb(0xC0, data
->sbase
+ WBCIR_REG_SP3_MCR
);
939 inb(data
->sbase
+ WBCIR_REG_SP3_LSR
); /* Clear LSR */
940 inb(data
->sbase
+ WBCIR_REG_SP3_MSR
); /* Clear MSR */
942 /* Disable RX demod, enable run-length enc/dec, set freq span */
943 wbcir_select_bank(data
, WBCIR_BANK_7
);
944 outb(0x90, data
->sbase
+ WBCIR_REG_SP3_RCCFG
);
947 wbcir_select_bank(data
, WBCIR_BANK_4
);
948 outb(0x00, data
->sbase
+ WBCIR_REG_SP3_IRCR1
);
950 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
951 wbcir_select_bank(data
, WBCIR_BANK_5
);
952 outb(txandrx
? 0x03 : 0x02, data
->sbase
+ WBCIR_REG_SP3_IRCR2
);
955 wbcir_select_bank(data
, WBCIR_BANK_6
);
956 outb(0x20, data
->sbase
+ WBCIR_REG_SP3_IRCR3
);
958 /* Set RX demodulation freq, not really used */
959 wbcir_select_bank(data
, WBCIR_BANK_7
);
960 outb(0xF2, data
->sbase
+ WBCIR_REG_SP3_IRRXDC
);
962 /* Set TX modulation, 36kHz, 7us pulse width */
963 outb(0x69, data
->sbase
+ WBCIR_REG_SP3_IRTXMC
);
964 data
->txcarrier
= 36000;
966 /* Set invert and pin direction */
968 outb(0x10, data
->sbase
+ WBCIR_REG_SP3_IRCFG4
);
970 outb(0x00, data
->sbase
+ WBCIR_REG_SP3_IRCFG4
);
972 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */
973 wbcir_select_bank(data
, WBCIR_BANK_0
);
974 outb(0x97, data
->sbase
+ WBCIR_REG_SP3_FCR
);
976 /* Clear AUX status bits */
977 outb(0xE0, data
->sbase
+ WBCIR_REG_SP3_ASCR
);
980 data
->rxstate
= WBCIR_RXSTATE_INACTIVE
;
981 wbcir_idle_rx(data
->dev
, true);
984 if (data
->txstate
== WBCIR_TXSTATE_ACTIVE
) {
987 data
->txstate
= WBCIR_TXSTATE_INACTIVE
;
990 /* Enable interrupts */
991 wbcir_set_irqmask(data
, WBCIR_IRQ_RX
| WBCIR_IRQ_ERR
);
995 wbcir_resume(struct pnp_dev
*device
)
997 struct wbcir_data
*data
= pnp_get_drvdata(device
);
1000 ir_raw_event_reset(data
->dev
);
1001 enable_irq(data
->irq
);
1002 led_classdev_resume(&data
->led
);
1008 wbcir_probe(struct pnp_dev
*device
, const struct pnp_device_id
*dev_id
)
1010 struct device
*dev
= &device
->dev
;
1011 struct wbcir_data
*data
;
1014 if (!(pnp_port_len(device
, 0) == EHFUNC_IOMEM_LEN
&&
1015 pnp_port_len(device
, 1) == WAKEUP_IOMEM_LEN
&&
1016 pnp_port_len(device
, 2) == SP_IOMEM_LEN
)) {
1017 dev_err(dev
, "Invalid resources\n");
1021 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
1027 pnp_set_drvdata(device
, data
);
1029 spin_lock_init(&data
->spinlock
);
1030 data
->ebase
= pnp_port_start(device
, 0);
1031 data
->wbase
= pnp_port_start(device
, 1);
1032 data
->sbase
= pnp_port_start(device
, 2);
1033 data
->irq
= pnp_irq(device
, 0);
1035 if (data
->wbase
== 0 || data
->ebase
== 0 ||
1036 data
->sbase
== 0 || data
->irq
== -1) {
1038 dev_err(dev
, "Invalid resources\n");
1039 goto exit_free_data
;
1042 dev_dbg(&device
->dev
, "Found device (w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
1043 data
->wbase
, data
->ebase
, data
->sbase
, data
->irq
);
1045 data
->led
.name
= "cir::activity";
1046 data
->led
.default_trigger
= "rc-feedback";
1047 data
->led
.brightness_set
= wbcir_led_brightness_set
;
1048 data
->led
.brightness_get
= wbcir_led_brightness_get
;
1049 err
= led_classdev_register(&device
->dev
, &data
->led
);
1051 goto exit_free_data
;
1053 data
->dev
= rc_allocate_device(RC_DRIVER_IR_RAW
);
1056 goto exit_unregister_led
;
1059 data
->dev
->driver_name
= DRVNAME
;
1060 data
->dev
->device_name
= WBCIR_NAME
;
1061 data
->dev
->input_phys
= "wbcir/cir0";
1062 data
->dev
->input_id
.bustype
= BUS_HOST
;
1063 data
->dev
->input_id
.vendor
= PCI_VENDOR_ID_WINBOND
;
1064 data
->dev
->input_id
.product
= WBCIR_ID_FAMILY
;
1065 data
->dev
->input_id
.version
= WBCIR_ID_CHIP
;
1066 data
->dev
->map_name
= RC_MAP_RC6_MCE
;
1067 data
->dev
->s_idle
= wbcir_idle_rx
;
1068 data
->dev
->s_carrier_report
= wbcir_set_carrier_report
;
1069 data
->dev
->s_tx_mask
= wbcir_txmask
;
1070 data
->dev
->s_tx_carrier
= wbcir_txcarrier
;
1071 data
->dev
->tx_ir
= wbcir_tx
;
1072 data
->dev
->priv
= data
;
1073 data
->dev
->dev
.parent
= &device
->dev
;
1074 data
->dev
->min_timeout
= 1;
1075 data
->dev
->timeout
= IR_DEFAULT_TIMEOUT
;
1076 data
->dev
->max_timeout
= 10 * IR_DEFAULT_TIMEOUT
;
1077 data
->dev
->rx_resolution
= 2;
1078 data
->dev
->allowed_protocols
= RC_PROTO_BIT_ALL_IR_DECODER
;
1079 data
->dev
->allowed_wakeup_protocols
= RC_PROTO_BIT_NEC
|
1080 RC_PROTO_BIT_NECX
| RC_PROTO_BIT_NEC32
| RC_PROTO_BIT_RC5
|
1081 RC_PROTO_BIT_RC6_0
| RC_PROTO_BIT_RC6_6A_20
|
1082 RC_PROTO_BIT_RC6_6A_24
| RC_PROTO_BIT_RC6_6A_32
|
1083 RC_PROTO_BIT_RC6_MCE
;
1084 data
->dev
->wakeup_protocol
= RC_PROTO_RC6_MCE
;
1085 data
->dev
->scancode_wakeup_filter
.data
= 0x800f040c;
1086 data
->dev
->scancode_wakeup_filter
.mask
= 0xffff7fff;
1087 data
->dev
->s_wakeup_filter
= wbcir_set_wakeup_filter
;
1089 err
= rc_register_device(data
->dev
);
1093 if (!request_region(data
->wbase
, WAKEUP_IOMEM_LEN
, DRVNAME
)) {
1094 dev_err(dev
, "Region 0x%lx-0x%lx already in use!\n",
1095 data
->wbase
, data
->wbase
+ WAKEUP_IOMEM_LEN
- 1);
1097 goto exit_unregister_device
;
1100 if (!request_region(data
->ebase
, EHFUNC_IOMEM_LEN
, DRVNAME
)) {
1101 dev_err(dev
, "Region 0x%lx-0x%lx already in use!\n",
1102 data
->ebase
, data
->ebase
+ EHFUNC_IOMEM_LEN
- 1);
1104 goto exit_release_wbase
;
1107 if (!request_region(data
->sbase
, SP_IOMEM_LEN
, DRVNAME
)) {
1108 dev_err(dev
, "Region 0x%lx-0x%lx already in use!\n",
1109 data
->sbase
, data
->sbase
+ SP_IOMEM_LEN
- 1);
1111 goto exit_release_ebase
;
1114 err
= request_irq(data
->irq
, wbcir_irq_handler
,
1115 0, DRVNAME
, device
);
1117 dev_err(dev
, "Failed to claim IRQ %u\n", data
->irq
);
1119 goto exit_release_sbase
;
1122 device_init_wakeup(&device
->dev
, 1);
1124 wbcir_init_hw(data
);
1129 release_region(data
->sbase
, SP_IOMEM_LEN
);
1131 release_region(data
->ebase
, EHFUNC_IOMEM_LEN
);
1133 release_region(data
->wbase
, WAKEUP_IOMEM_LEN
);
1134 exit_unregister_device
:
1135 rc_unregister_device(data
->dev
);
1138 rc_free_device(data
->dev
);
1139 exit_unregister_led
:
1140 led_classdev_unregister(&data
->led
);
1143 pnp_set_drvdata(device
, NULL
);
1149 wbcir_remove(struct pnp_dev
*device
)
1151 struct wbcir_data
*data
= pnp_get_drvdata(device
);
1153 /* Disable interrupts */
1154 wbcir_set_irqmask(data
, WBCIR_IRQ_NONE
);
1155 free_irq(data
->irq
, device
);
1157 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
1158 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_STS
, 0x17, 0x17);
1161 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_CTL
, 0x00, 0x01);
1163 /* Clear BUFF_EN, END_EN, MATCH_EN */
1164 wbcir_set_bits(data
->wbase
+ WBCIR_REG_WCEIR_EV_EN
, 0x00, 0x07);
1166 rc_unregister_device(data
->dev
);
1168 led_classdev_unregister(&data
->led
);
1170 /* This is ok since &data->led isn't actually used */
1171 wbcir_led_brightness_set(&data
->led
, LED_OFF
);
1173 release_region(data
->wbase
, WAKEUP_IOMEM_LEN
);
1174 release_region(data
->ebase
, EHFUNC_IOMEM_LEN
);
1175 release_region(data
->sbase
, SP_IOMEM_LEN
);
1179 pnp_set_drvdata(device
, NULL
);
1182 static const struct pnp_device_id wbcir_ids
[] = {
1186 MODULE_DEVICE_TABLE(pnp
, wbcir_ids
);
1188 static struct pnp_driver wbcir_driver
= {
1190 .id_table
= wbcir_ids
,
1191 .probe
= wbcir_probe
,
1192 .remove
= wbcir_remove
,
1193 .suspend
= wbcir_suspend
,
1194 .resume
= wbcir_resume
,
1195 .shutdown
= wbcir_shutdown
1203 ret
= pnp_register_driver(&wbcir_driver
);
1205 pr_err("Unable to register driver\n");
1213 pnp_unregister_driver(&wbcir_driver
);
1216 module_init(wbcir_init
);
1217 module_exit(wbcir_exit
);
1219 MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
1220 MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver");
1221 MODULE_LICENSE("GPL");