Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / misc / habanalabs / common / habanalabs.h
blobe0d7f5fbaa5c3f2950068d4618b2d5fb5b540a9c
1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2019 HabanaLabs, Ltd.
4 * All Rights Reserved.
6 */
8 #ifndef HABANALABSP_H_
9 #define HABANALABSP_H_
11 #include "../include/common/cpucp_if.h"
12 #include "../include/common/qman_if.h"
13 #include "../include/hw_ip/mmu/mmu_general.h"
14 #include <uapi/misc/habanalabs.h>
16 #include <linux/cdev.h>
17 #include <linux/iopoll.h>
18 #include <linux/irqreturn.h>
19 #include <linux/dma-direction.h>
20 #include <linux/scatterlist.h>
21 #include <linux/hashtable.h>
22 #include <linux/bitfield.h>
23 #include <linux/genalloc.h>
24 #include <linux/sched/signal.h>
25 #include <linux/io-64-nonatomic-lo-hi.h>
26 #include <linux/coresight.h>
28 #define HL_NAME "habanalabs"
30 /* Use upper bits of mmap offset to store habana driver specific information.
31 * bits[63:62] - Encode mmap type
32 * bits[45:0] - mmap offset value
34 * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these
35 * defines are w.r.t to PAGE_SIZE
37 #define HL_MMAP_TYPE_SHIFT (62 - PAGE_SHIFT)
38 #define HL_MMAP_TYPE_MASK (0x3ull << HL_MMAP_TYPE_SHIFT)
39 #define HL_MMAP_TYPE_CB (0x2ull << HL_MMAP_TYPE_SHIFT)
41 #define HL_MMAP_OFFSET_VALUE_MASK (0x3FFFFFFFFFFFull >> PAGE_SHIFT)
42 #define HL_MMAP_OFFSET_VALUE_GET(off) (off & HL_MMAP_OFFSET_VALUE_MASK)
44 #define HL_PENDING_RESET_PER_SEC 10
45 #define HL_PENDING_RESET_MAX_TRIALS 60 /* 10 minutes */
46 #define HL_PENDING_RESET_LONG_SEC 60
48 #define HL_HARD_RESET_MAX_TIMEOUT 120
50 #define HL_DEVICE_TIMEOUT_USEC 1000000 /* 1 s */
52 #define HL_HEARTBEAT_PER_USEC 5000000 /* 5 s */
54 #define HL_PLL_LOW_JOB_FREQ_USEC 5000000 /* 5 s */
56 #define HL_CPUCP_INFO_TIMEOUT_USEC 10000000 /* 10s */
57 #define HL_CPUCP_EEPROM_TIMEOUT_USEC 10000000 /* 10s */
59 #define HL_PCI_ELBI_TIMEOUT_MSEC 10 /* 10ms */
61 #define HL_SIM_MAX_TIMEOUT_US 10000000 /* 10s */
63 #define HL_IDLE_BUSY_TS_ARR_SIZE 4096
65 /* Memory */
66 #define MEM_HASH_TABLE_BITS 7 /* 1 << 7 buckets */
68 /* MMU */
69 #define MMU_HASH_TABLE_BITS 7 /* 1 << 7 buckets */
71 /**
72 * enum hl_mmu_page_table_locaion - mmu page table location
73 * @MMU_DR_PGT: page-table is located on device DRAM.
74 * @MMU_HR_PGT: page-table is located on host memory.
75 * @MMU_NUM_PGT_LOCATIONS: number of page-table locations currently supported.
77 enum hl_mmu_page_table_location {
78 MMU_DR_PGT = 0, /* device-dram-resident MMU PGT */
79 MMU_HR_PGT, /* host resident MMU PGT */
80 MMU_NUM_PGT_LOCATIONS /* num of PGT locations */
84 * HL_RSVD_SOBS 'sync stream' reserved sync objects per QMAN stream
85 * HL_RSVD_MONS 'sync stream' reserved monitors per QMAN stream
87 #define HL_RSVD_SOBS 2
88 #define HL_RSVD_MONS 1
91 * HL_COLLECTIVE_RSVD_MSTR_MONS 'collective' reserved monitors per QMAN stream
93 #define HL_COLLECTIVE_RSVD_MSTR_MONS 2
95 #define HL_MAX_SOB_VAL (1 << 15)
97 #define IS_POWER_OF_2(n) (n != 0 && ((n & (n - 1)) == 0))
98 #define IS_MAX_PENDING_CS_VALID(n) (IS_POWER_OF_2(n) && (n > 1))
100 #define HL_PCI_NUM_BARS 6
102 #define HL_MAX_DCORES 4
104 #define HL_MAX_SOBS_PER_MONITOR 8
107 * struct hl_gen_wait_properties - properties for generating a wait CB
108 * @data: command buffer
109 * @q_idx: queue id is used to extract fence register address
110 * @size: offset in command buffer
111 * @sob_base: SOB base to use in this wait CB
112 * @sob_val: SOB value to wait for
113 * @mon_id: monitor to use in this wait CB
114 * @sob_mask: each bit represents a SOB offset from sob_base to be used
116 struct hl_gen_wait_properties {
117 void *data;
118 u32 q_idx;
119 u32 size;
120 u16 sob_base;
121 u16 sob_val;
122 u16 mon_id;
123 u8 sob_mask;
127 * struct pgt_info - MMU hop page info.
128 * @node: hash linked-list node for the pgts shadow hash of pgts.
129 * @phys_addr: physical address of the pgt.
130 * @shadow_addr: shadow hop in the host.
131 * @ctx: pointer to the owner ctx.
132 * @num_of_ptes: indicates how many ptes are used in the pgt.
134 * The MMU page tables hierarchy is placed on the DRAM. When a new level (hop)
135 * is needed during mapping, a new page is allocated and this structure holds
136 * its essential information. During unmapping, if no valid PTEs remained in the
137 * page, it is freed with its pgt_info structure.
139 struct pgt_info {
140 struct hlist_node node;
141 u64 phys_addr;
142 u64 shadow_addr;
143 struct hl_ctx *ctx;
144 int num_of_ptes;
147 struct hl_device;
148 struct hl_fpriv;
151 * enum hl_pci_match_mode - pci match mode per region
152 * @PCI_ADDRESS_MATCH_MODE: address match mode
153 * @PCI_BAR_MATCH_MODE: bar match mode
155 enum hl_pci_match_mode {
156 PCI_ADDRESS_MATCH_MODE,
157 PCI_BAR_MATCH_MODE
161 * enum hl_fw_component - F/W components to read version through registers.
162 * @FW_COMP_UBOOT: u-boot.
163 * @FW_COMP_PREBOOT: preboot.
165 enum hl_fw_component {
166 FW_COMP_UBOOT,
167 FW_COMP_PREBOOT
171 * enum hl_fw_types - F/W types to load
172 * @FW_TYPE_LINUX: Linux image for device CPU
173 * @FW_TYPE_BOOT_CPU: Boot image for device CPU
174 * @FW_TYPE_ALL_TYPES: Mask for all types
176 enum hl_fw_types {
177 FW_TYPE_LINUX = 0x1,
178 FW_TYPE_BOOT_CPU = 0x2,
179 FW_TYPE_ALL_TYPES = (FW_TYPE_LINUX | FW_TYPE_BOOT_CPU)
183 * enum hl_queue_type - Supported QUEUE types.
184 * @QUEUE_TYPE_NA: queue is not available.
185 * @QUEUE_TYPE_EXT: external queue which is a DMA channel that may access the
186 * host.
187 * @QUEUE_TYPE_INT: internal queue that performs DMA inside the device's
188 * memories and/or operates the compute engines.
189 * @QUEUE_TYPE_CPU: S/W queue for communication with the device's CPU.
190 * @QUEUE_TYPE_HW: queue of DMA and compute engines jobs, for which completion
191 * notifications are sent by H/W.
193 enum hl_queue_type {
194 QUEUE_TYPE_NA,
195 QUEUE_TYPE_EXT,
196 QUEUE_TYPE_INT,
197 QUEUE_TYPE_CPU,
198 QUEUE_TYPE_HW
201 enum hl_cs_type {
202 CS_TYPE_DEFAULT,
203 CS_TYPE_SIGNAL,
204 CS_TYPE_WAIT,
205 CS_TYPE_COLLECTIVE_WAIT
209 * struct hl_inbound_pci_region - inbound region descriptor
210 * @mode: pci match mode for this region
211 * @addr: region target address
212 * @size: region size in bytes
213 * @offset_in_bar: offset within bar (address match mode)
214 * @bar: bar id
216 struct hl_inbound_pci_region {
217 enum hl_pci_match_mode mode;
218 u64 addr;
219 u64 size;
220 u64 offset_in_bar;
221 u8 bar;
225 * struct hl_outbound_pci_region - outbound region descriptor
226 * @addr: region target address
227 * @size: region size in bytes
229 struct hl_outbound_pci_region {
230 u64 addr;
231 u64 size;
235 * enum queue_cb_alloc_flags - Indicates queue support for CBs that
236 * allocated by Kernel or by User
237 * @CB_ALLOC_KERNEL: support only CBs that allocated by Kernel
238 * @CB_ALLOC_USER: support only CBs that allocated by User
240 enum queue_cb_alloc_flags {
241 CB_ALLOC_KERNEL = 0x1,
242 CB_ALLOC_USER = 0x2
246 * struct hl_hw_sob - H/W SOB info.
247 * @hdev: habanalabs device structure.
248 * @kref: refcount of this SOB. The SOB will reset once the refcount is zero.
249 * @sob_id: id of this SOB.
250 * @q_idx: the H/W queue that uses this SOB.
252 struct hl_hw_sob {
253 struct hl_device *hdev;
254 struct kref kref;
255 u32 sob_id;
256 u32 q_idx;
259 enum hl_collective_mode {
260 HL_COLLECTIVE_NOT_SUPPORTED = 0x0,
261 HL_COLLECTIVE_MASTER = 0x1,
262 HL_COLLECTIVE_SLAVE = 0x2
266 * struct hw_queue_properties - queue information.
267 * @type: queue type.
268 * @queue_cb_alloc_flags: bitmap which indicates if the hw queue supports CB
269 * that allocated by the Kernel driver and therefore,
270 * a CB handle can be provided for jobs on this queue.
271 * Otherwise, a CB address must be provided.
272 * @collective_mode: collective mode of current queue
273 * @driver_only: true if only the driver is allowed to send a job to this queue,
274 * false otherwise.
275 * @supports_sync_stream: True if queue supports sync stream
277 struct hw_queue_properties {
278 enum hl_queue_type type;
279 enum queue_cb_alloc_flags cb_alloc_flags;
280 enum hl_collective_mode collective_mode;
281 u8 driver_only;
282 u8 supports_sync_stream;
286 * enum vm_type_t - virtual memory mapping request information.
287 * @VM_TYPE_USERPTR: mapping of user memory to device virtual address.
288 * @VM_TYPE_PHYS_PACK: mapping of DRAM memory to device virtual address.
290 enum vm_type_t {
291 VM_TYPE_USERPTR = 0x1,
292 VM_TYPE_PHYS_PACK = 0x2
296 * enum hl_device_hw_state - H/W device state. use this to understand whether
297 * to do reset before hw_init or not
298 * @HL_DEVICE_HW_STATE_CLEAN: H/W state is clean. i.e. after hard reset
299 * @HL_DEVICE_HW_STATE_DIRTY: H/W state is dirty. i.e. we started to execute
300 * hw_init
302 enum hl_device_hw_state {
303 HL_DEVICE_HW_STATE_CLEAN = 0,
304 HL_DEVICE_HW_STATE_DIRTY
307 #define HL_MMU_VA_ALIGNMENT_NOT_NEEDED 0
310 * struct hl_mmu_properties - ASIC specific MMU address translation properties.
311 * @start_addr: virtual start address of the memory region.
312 * @end_addr: virtual end address of the memory region.
313 * @hop0_shift: shift of hop 0 mask.
314 * @hop1_shift: shift of hop 1 mask.
315 * @hop2_shift: shift of hop 2 mask.
316 * @hop3_shift: shift of hop 3 mask.
317 * @hop4_shift: shift of hop 4 mask.
318 * @hop5_shift: shift of hop 5 mask.
319 * @hop0_mask: mask to get the PTE address in hop 0.
320 * @hop1_mask: mask to get the PTE address in hop 1.
321 * @hop2_mask: mask to get the PTE address in hop 2.
322 * @hop3_mask: mask to get the PTE address in hop 3.
323 * @hop4_mask: mask to get the PTE address in hop 4.
324 * @hop5_mask: mask to get the PTE address in hop 5.
325 * @page_size: default page size used to allocate memory.
326 * @num_hops: The amount of hops supported by the translation table.
327 * @host_resident: Should the MMU page table reside in host memory or in the
328 * device DRAM.
330 struct hl_mmu_properties {
331 u64 start_addr;
332 u64 end_addr;
333 u64 hop0_shift;
334 u64 hop1_shift;
335 u64 hop2_shift;
336 u64 hop3_shift;
337 u64 hop4_shift;
338 u64 hop5_shift;
339 u64 hop0_mask;
340 u64 hop1_mask;
341 u64 hop2_mask;
342 u64 hop3_mask;
343 u64 hop4_mask;
344 u64 hop5_mask;
345 u32 page_size;
346 u32 num_hops;
347 u8 host_resident;
351 * struct asic_fixed_properties - ASIC specific immutable properties.
352 * @hw_queues_props: H/W queues properties.
353 * @cpucp_info: received various information from CPU-CP regarding the H/W, e.g.
354 * available sensors.
355 * @uboot_ver: F/W U-boot version.
356 * @preboot_ver: F/W Preboot version.
357 * @dmmu: DRAM MMU address translation properties.
358 * @pmmu: PCI (host) MMU address translation properties.
359 * @pmmu_huge: PCI (host) MMU address translation properties for memory
360 * allocated with huge pages.
361 * @sram_base_address: SRAM physical start address.
362 * @sram_end_address: SRAM physical end address.
363 * @sram_user_base_address - SRAM physical start address for user access.
364 * @dram_base_address: DRAM physical start address.
365 * @dram_end_address: DRAM physical end address.
366 * @dram_user_base_address: DRAM physical start address for user access.
367 * @dram_size: DRAM total size.
368 * @dram_pci_bar_size: size of PCI bar towards DRAM.
369 * @max_power_default: max power of the device after reset
370 * @dram_size_for_default_page_mapping: DRAM size needed to map to avoid page
371 * fault.
372 * @pcie_dbi_base_address: Base address of the PCIE_DBI block.
373 * @pcie_aux_dbi_reg_addr: Address of the PCIE_AUX DBI register.
374 * @mmu_pgt_addr: base physical address in DRAM of MMU page tables.
375 * @mmu_dram_default_page_addr: DRAM default page physical address.
376 * @cb_va_start_addr: virtual start address of command buffers which are mapped
377 * to the device's MMU.
378 * @cb_va_end_addr: virtual end address of command buffers which are mapped to
379 * the device's MMU.
380 * @mmu_pgt_size: MMU page tables total size.
381 * @mmu_pte_size: PTE size in MMU page tables.
382 * @mmu_hop_table_size: MMU hop table size.
383 * @mmu_hop0_tables_total_size: total size of MMU hop0 tables.
384 * @dram_page_size: page size for MMU DRAM allocation.
385 * @cfg_size: configuration space size on SRAM.
386 * @sram_size: total size of SRAM.
387 * @max_asid: maximum number of open contexts (ASIDs).
388 * @num_of_events: number of possible internal H/W IRQs.
389 * @psoc_pci_pll_nr: PCI PLL NR value.
390 * @psoc_pci_pll_nf: PCI PLL NF value.
391 * @psoc_pci_pll_od: PCI PLL OD value.
392 * @psoc_pci_pll_div_factor: PCI PLL DIV FACTOR 1 value.
393 * @psoc_timestamp_frequency: frequency of the psoc timestamp clock.
394 * @high_pll: high PLL frequency used by the device.
395 * @cb_pool_cb_cnt: number of CBs in the CB pool.
396 * @cb_pool_cb_size: size of each CB in the CB pool.
397 * @max_pending_cs: maximum of concurrent pending command submissions
398 * @max_queues: maximum amount of queues in the system
399 * @fw_boot_cpu_security_map: bitmap representation of boot cpu security status
400 * reported by FW, bit description can be found in
401 * CPU_BOOT_DEV_STS*
402 * @fw_app_security_map: bitmap representation of application security status
403 * reported by FW, bit description can be found in
404 * CPU_BOOT_DEV_STS*
405 * @collective_first_sob: first sync object available for collective use
406 * @collective_first_mon: first monitor available for collective use
407 * @sync_stream_first_sob: first sync object available for sync stream use
408 * @sync_stream_first_mon: first monitor available for sync stream use
409 * @first_available_user_sob: first sob available for the user
410 * @first_available_user_mon: first monitor available for the user
411 * @tpc_enabled_mask: which TPCs are enabled.
412 * @completion_queues_count: number of completion queues.
413 * @fw_security_disabled: true if security measures are disabled in firmware,
414 * false otherwise
415 * @fw_security_status_valid: security status bits are valid and can be fetched
416 * from BOOT_DEV_STS0
417 * @dram_supports_virtual_memory: is there an MMU towards the DRAM
418 * @hard_reset_done_by_fw: true if firmware is handling hard reset flow
420 struct asic_fixed_properties {
421 struct hw_queue_properties *hw_queues_props;
422 struct cpucp_info cpucp_info;
423 char uboot_ver[VERSION_MAX_LEN];
424 char preboot_ver[VERSION_MAX_LEN];
425 struct hl_mmu_properties dmmu;
426 struct hl_mmu_properties pmmu;
427 struct hl_mmu_properties pmmu_huge;
428 u64 sram_base_address;
429 u64 sram_end_address;
430 u64 sram_user_base_address;
431 u64 dram_base_address;
432 u64 dram_end_address;
433 u64 dram_user_base_address;
434 u64 dram_size;
435 u64 dram_pci_bar_size;
436 u64 max_power_default;
437 u64 dram_size_for_default_page_mapping;
438 u64 pcie_dbi_base_address;
439 u64 pcie_aux_dbi_reg_addr;
440 u64 mmu_pgt_addr;
441 u64 mmu_dram_default_page_addr;
442 u64 cb_va_start_addr;
443 u64 cb_va_end_addr;
444 u32 mmu_pgt_size;
445 u32 mmu_pte_size;
446 u32 mmu_hop_table_size;
447 u32 mmu_hop0_tables_total_size;
448 u32 dram_page_size;
449 u32 cfg_size;
450 u32 sram_size;
451 u32 max_asid;
452 u32 num_of_events;
453 u32 psoc_pci_pll_nr;
454 u32 psoc_pci_pll_nf;
455 u32 psoc_pci_pll_od;
456 u32 psoc_pci_pll_div_factor;
457 u32 psoc_timestamp_frequency;
458 u32 high_pll;
459 u32 cb_pool_cb_cnt;
460 u32 cb_pool_cb_size;
461 u32 max_pending_cs;
462 u32 max_queues;
463 u32 fw_boot_cpu_security_map;
464 u32 fw_app_security_map;
465 u16 collective_first_sob;
466 u16 collective_first_mon;
467 u16 sync_stream_first_sob;
468 u16 sync_stream_first_mon;
469 u16 first_available_user_sob[HL_MAX_DCORES];
470 u16 first_available_user_mon[HL_MAX_DCORES];
471 u8 tpc_enabled_mask;
472 u8 completion_queues_count;
473 u8 fw_security_disabled;
474 u8 fw_security_status_valid;
475 u8 dram_supports_virtual_memory;
476 u8 hard_reset_done_by_fw;
480 * struct hl_fence - software synchronization primitive
481 * @completion: fence is implemented using completion
482 * @refcount: refcount for this fence
483 * @error: mark this fence with error
484 * @timestamp: timestamp upon completion
487 struct hl_fence {
488 struct completion completion;
489 struct kref refcount;
490 int error;
491 ktime_t timestamp;
495 * struct hl_cs_compl - command submission completion object.
496 * @base_fence: hl fence object.
497 * @lock: spinlock to protect fence.
498 * @hdev: habanalabs device structure.
499 * @hw_sob: the H/W SOB used in this signal/wait CS.
500 * @cs_seq: command submission sequence number.
501 * @type: type of the CS - signal/wait.
502 * @sob_val: the SOB value that is used in this signal/wait CS.
503 * @sob_group: the SOB group that is used in this collective wait CS.
505 struct hl_cs_compl {
506 struct hl_fence base_fence;
507 spinlock_t lock;
508 struct hl_device *hdev;
509 struct hl_hw_sob *hw_sob;
510 u64 cs_seq;
511 enum hl_cs_type type;
512 u16 sob_val;
513 u16 sob_group;
517 * Command Buffers
521 * struct hl_cb_mgr - describes a Command Buffer Manager.
522 * @cb_lock: protects cb_handles.
523 * @cb_handles: an idr to hold all command buffer handles.
525 struct hl_cb_mgr {
526 spinlock_t cb_lock;
527 struct idr cb_handles; /* protected by cb_lock */
531 * struct hl_cb - describes a Command Buffer.
532 * @refcount: reference counter for usage of the CB.
533 * @hdev: pointer to device this CB belongs to.
534 * @ctx: pointer to the CB owner's context.
535 * @lock: spinlock to protect mmap flows.
536 * @debugfs_list: node in debugfs list of command buffers.
537 * @pool_list: node in pool list of command buffers.
538 * @va_block_list: list of virtual addresses blocks of the CB if it is mapped to
539 * the device's MMU.
540 * @id: the CB's ID.
541 * @kernel_address: Holds the CB's kernel virtual address.
542 * @bus_address: Holds the CB's DMA address.
543 * @mmap_size: Holds the CB's size that was mmaped.
544 * @size: holds the CB's size.
545 * @cs_cnt: holds number of CS that this CB participates in.
546 * @mmap: true if the CB is currently mmaped to user.
547 * @is_pool: true if CB was acquired from the pool, false otherwise.
548 * @is_internal: internaly allocated
549 * @is_mmu_mapped: true if the CB is mapped to the device's MMU.
551 struct hl_cb {
552 struct kref refcount;
553 struct hl_device *hdev;
554 struct hl_ctx *ctx;
555 spinlock_t lock;
556 struct list_head debugfs_list;
557 struct list_head pool_list;
558 struct list_head va_block_list;
559 u64 id;
560 void *kernel_address;
561 dma_addr_t bus_address;
562 u32 mmap_size;
563 u32 size;
564 atomic_t cs_cnt;
565 u8 mmap;
566 u8 is_pool;
567 u8 is_internal;
568 u8 is_mmu_mapped;
573 * QUEUES
576 struct hl_cs;
577 struct hl_cs_job;
579 /* Queue length of external and HW queues */
580 #define HL_QUEUE_LENGTH 4096
581 #define HL_QUEUE_SIZE_IN_BYTES (HL_QUEUE_LENGTH * HL_BD_SIZE)
583 #if (HL_MAX_JOBS_PER_CS > HL_QUEUE_LENGTH)
584 #error "HL_QUEUE_LENGTH must be greater than HL_MAX_JOBS_PER_CS"
585 #endif
587 /* HL_CQ_LENGTH is in units of struct hl_cq_entry */
588 #define HL_CQ_LENGTH HL_QUEUE_LENGTH
589 #define HL_CQ_SIZE_IN_BYTES (HL_CQ_LENGTH * HL_CQ_ENTRY_SIZE)
591 /* Must be power of 2 */
592 #define HL_EQ_LENGTH 64
593 #define HL_EQ_SIZE_IN_BYTES (HL_EQ_LENGTH * HL_EQ_ENTRY_SIZE)
595 /* Host <-> CPU-CP shared memory size */
596 #define HL_CPU_ACCESSIBLE_MEM_SIZE SZ_2M
599 * struct hl_sync_stream_properties -
600 * describes a H/W queue sync stream properties
601 * @hw_sob: array of the used H/W SOBs by this H/W queue.
602 * @next_sob_val: the next value to use for the currently used SOB.
603 * @base_sob_id: the base SOB id of the SOBs used by this queue.
604 * @base_mon_id: the base MON id of the MONs used by this queue.
605 * @collective_mstr_mon_id: the MON ids of the MONs used by this master queue
606 * in order to sync with all slave queues.
607 * @collective_slave_mon_id: the MON id used by this slave queue in order to
608 * sync with its master queue.
609 * @collective_sob_id: current SOB id used by this collective slave queue
610 * to signal its collective master queue upon completion.
611 * @curr_sob_offset: the id offset to the currently used SOB from the
612 * HL_RSVD_SOBS that are being used by this queue.
614 struct hl_sync_stream_properties {
615 struct hl_hw_sob hw_sob[HL_RSVD_SOBS];
616 u16 next_sob_val;
617 u16 base_sob_id;
618 u16 base_mon_id;
619 u16 collective_mstr_mon_id[HL_COLLECTIVE_RSVD_MSTR_MONS];
620 u16 collective_slave_mon_id;
621 u16 collective_sob_id;
622 u8 curr_sob_offset;
626 * struct hl_hw_queue - describes a H/W transport queue.
627 * @shadow_queue: pointer to a shadow queue that holds pointers to jobs.
628 * @sync_stream_prop: sync stream queue properties
629 * @queue_type: type of queue.
630 * @collective_mode: collective mode of current queue
631 * @kernel_address: holds the queue's kernel virtual address.
632 * @bus_address: holds the queue's DMA address.
633 * @pi: holds the queue's pi value.
634 * @ci: holds the queue's ci value, AS CALCULATED BY THE DRIVER (not real ci).
635 * @hw_queue_id: the id of the H/W queue.
636 * @cq_id: the id for the corresponding CQ for this H/W queue.
637 * @msi_vec: the IRQ number of the H/W queue.
638 * @int_queue_len: length of internal queue (number of entries).
639 * @valid: is the queue valid (we have array of 32 queues, not all of them
640 * exist).
641 * @supports_sync_stream: True if queue supports sync stream
643 struct hl_hw_queue {
644 struct hl_cs_job **shadow_queue;
645 struct hl_sync_stream_properties sync_stream_prop;
646 enum hl_queue_type queue_type;
647 enum hl_collective_mode collective_mode;
648 void *kernel_address;
649 dma_addr_t bus_address;
650 u32 pi;
651 atomic_t ci;
652 u32 hw_queue_id;
653 u32 cq_id;
654 u32 msi_vec;
655 u16 int_queue_len;
656 u8 valid;
657 u8 supports_sync_stream;
661 * struct hl_cq - describes a completion queue
662 * @hdev: pointer to the device structure
663 * @kernel_address: holds the queue's kernel virtual address
664 * @bus_address: holds the queue's DMA address
665 * @cq_idx: completion queue index in array
666 * @hw_queue_id: the id of the matching H/W queue
667 * @ci: ci inside the queue
668 * @pi: pi inside the queue
669 * @free_slots_cnt: counter of free slots in queue
671 struct hl_cq {
672 struct hl_device *hdev;
673 void *kernel_address;
674 dma_addr_t bus_address;
675 u32 cq_idx;
676 u32 hw_queue_id;
677 u32 ci;
678 u32 pi;
679 atomic_t free_slots_cnt;
683 * struct hl_eq - describes the event queue (single one per device)
684 * @hdev: pointer to the device structure
685 * @kernel_address: holds the queue's kernel virtual address
686 * @bus_address: holds the queue's DMA address
687 * @ci: ci inside the queue
689 struct hl_eq {
690 struct hl_device *hdev;
691 void *kernel_address;
692 dma_addr_t bus_address;
693 u32 ci;
698 * ASICs
702 * enum hl_asic_type - supported ASIC types.
703 * @ASIC_INVALID: Invalid ASIC type.
704 * @ASIC_GOYA: Goya device.
705 * @ASIC_GAUDI: Gaudi device.
707 enum hl_asic_type {
708 ASIC_INVALID,
709 ASIC_GOYA,
710 ASIC_GAUDI
713 struct hl_cs_parser;
716 * enum hl_pm_mng_profile - power management profile.
717 * @PM_AUTO: internal clock is set by the Linux driver.
718 * @PM_MANUAL: internal clock is set by the user.
719 * @PM_LAST: last power management type.
721 enum hl_pm_mng_profile {
722 PM_AUTO = 1,
723 PM_MANUAL,
724 PM_LAST
728 * enum hl_pll_frequency - PLL frequency.
729 * @PLL_HIGH: high frequency.
730 * @PLL_LOW: low frequency.
731 * @PLL_LAST: last frequency values that were configured by the user.
733 enum hl_pll_frequency {
734 PLL_HIGH = 1,
735 PLL_LOW,
736 PLL_LAST
739 #define PLL_REF_CLK 50
741 enum div_select_defs {
742 DIV_SEL_REF_CLK = 0,
743 DIV_SEL_PLL_CLK = 1,
744 DIV_SEL_DIVIDED_REF = 2,
745 DIV_SEL_DIVIDED_PLL = 3,
749 * struct hl_asic_funcs - ASIC specific functions that are can be called from
750 * common code.
751 * @early_init: sets up early driver state (pre sw_init), doesn't configure H/W.
752 * @early_fini: tears down what was done in early_init.
753 * @late_init: sets up late driver/hw state (post hw_init) - Optional.
754 * @late_fini: tears down what was done in late_init (pre hw_fini) - Optional.
755 * @sw_init: sets up driver state, does not configure H/W.
756 * @sw_fini: tears down driver state, does not configure H/W.
757 * @hw_init: sets up the H/W state.
758 * @hw_fini: tears down the H/W state.
759 * @halt_engines: halt engines, needed for reset sequence. This also disables
760 * interrupts from the device. Should be called before
761 * hw_fini and before CS rollback.
762 * @suspend: handles IP specific H/W or SW changes for suspend.
763 * @resume: handles IP specific H/W or SW changes for resume.
764 * @cb_mmap: maps a CB.
765 * @ring_doorbell: increment PI on a given QMAN.
766 * @pqe_write: Write the PQ entry to the PQ. This is ASIC-specific
767 * function because the PQs are located in different memory areas
768 * per ASIC (SRAM, DRAM, Host memory) and therefore, the method of
769 * writing the PQE must match the destination memory area
770 * properties.
771 * @asic_dma_alloc_coherent: Allocate coherent DMA memory by calling
772 * dma_alloc_coherent(). This is ASIC function because
773 * its implementation is not trivial when the driver
774 * is loaded in simulation mode (not upstreamed).
775 * @asic_dma_free_coherent: Free coherent DMA memory by calling
776 * dma_free_coherent(). This is ASIC function because
777 * its implementation is not trivial when the driver
778 * is loaded in simulation mode (not upstreamed).
779 * @scrub_device_mem: Scrub device memory given an address and size
780 * @get_int_queue_base: get the internal queue base address.
781 * @test_queues: run simple test on all queues for sanity check.
782 * @asic_dma_pool_zalloc: small DMA allocation of coherent memory from DMA pool.
783 * size of allocation is HL_DMA_POOL_BLK_SIZE.
784 * @asic_dma_pool_free: free small DMA allocation from pool.
785 * @cpu_accessible_dma_pool_alloc: allocate CPU PQ packet from DMA pool.
786 * @cpu_accessible_dma_pool_free: free CPU PQ packet from DMA pool.
787 * @hl_dma_unmap_sg: DMA unmap scatter-gather list.
788 * @cs_parser: parse Command Submission.
789 * @asic_dma_map_sg: DMA map scatter-gather list.
790 * @get_dma_desc_list_size: get number of LIN_DMA packets required for CB.
791 * @add_end_of_cb_packets: Add packets to the end of CB, if device requires it.
792 * @update_eq_ci: update event queue CI.
793 * @context_switch: called upon ASID context switch.
794 * @restore_phase_topology: clear all SOBs amd MONs.
795 * @debugfs_read32: debug interface for reading u32 from DRAM/SRAM.
796 * @debugfs_write32: debug interface for writing u32 to DRAM/SRAM.
797 * @add_device_attr: add ASIC specific device attributes.
798 * @handle_eqe: handle event queue entry (IRQ) from CPU-CP.
799 * @set_pll_profile: change PLL profile (manual/automatic).
800 * @get_events_stat: retrieve event queue entries histogram.
801 * @read_pte: read MMU page table entry from DRAM.
802 * @write_pte: write MMU page table entry to DRAM.
803 * @mmu_invalidate_cache: flush MMU STLB host/DRAM cache, either with soft
804 * (L1 only) or hard (L0 & L1) flush.
805 * @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with
806 * ASID-VA-size mask.
807 * @send_heartbeat: send is-alive packet to CPU-CP and verify response.
808 * @set_clock_gating: enable/disable clock gating per engine according to
809 * clock gating mask in hdev
810 * @disable_clock_gating: disable clock gating completely
811 * @debug_coresight: perform certain actions on Coresight for debugging.
812 * @is_device_idle: return true if device is idle, false otherwise.
813 * @soft_reset_late_init: perform certain actions needed after soft reset.
814 * @hw_queues_lock: acquire H/W queues lock.
815 * @hw_queues_unlock: release H/W queues lock.
816 * @get_pci_id: retrieve PCI ID.
817 * @get_eeprom_data: retrieve EEPROM data from F/W.
818 * @send_cpu_message: send message to F/W. If the message is timedout, the
819 * driver will eventually reset the device. The timeout can
820 * be determined by the calling function or it can be 0 and
821 * then the timeout is the default timeout for the specific
822 * ASIC
823 * @get_hw_state: retrieve the H/W state
824 * @pci_bars_map: Map PCI BARs.
825 * @init_iatu: Initialize the iATU unit inside the PCI controller.
826 * @rreg: Read a register. Needed for simulator support.
827 * @wreg: Write a register. Needed for simulator support.
828 * @halt_coresight: stop the ETF and ETR traces.
829 * @ctx_init: context dependent initialization.
830 * @ctx_fini: context dependent cleanup.
831 * @get_clk_rate: Retrieve the ASIC current and maximum clock rate in MHz
832 * @get_queue_id_for_cq: Get the H/W queue id related to the given CQ index.
833 * @read_device_fw_version: read the device's firmware versions that are
834 * contained in registers
835 * @load_firmware_to_device: load the firmware to the device's memory
836 * @load_boot_fit_to_device: load boot fit to device's memory
837 * @get_signal_cb_size: Get signal CB size.
838 * @get_wait_cb_size: Get wait CB size.
839 * @gen_signal_cb: Generate a signal CB.
840 * @gen_wait_cb: Generate a wait CB.
841 * @reset_sob: Reset a SOB.
842 * @reset_sob_group: Reset SOB group
843 * @set_dma_mask_from_fw: set the DMA mask in the driver according to the
844 * firmware configuration
845 * @get_device_time: Get the device time.
846 * @collective_wait_init_cs: Generate collective master/slave packets
847 * and place them in the relevant cs jobs
848 * @collective_wait_create_jobs: allocate collective wait cs jobs
850 struct hl_asic_funcs {
851 int (*early_init)(struct hl_device *hdev);
852 int (*early_fini)(struct hl_device *hdev);
853 int (*late_init)(struct hl_device *hdev);
854 void (*late_fini)(struct hl_device *hdev);
855 int (*sw_init)(struct hl_device *hdev);
856 int (*sw_fini)(struct hl_device *hdev);
857 int (*hw_init)(struct hl_device *hdev);
858 void (*hw_fini)(struct hl_device *hdev, bool hard_reset);
859 void (*halt_engines)(struct hl_device *hdev, bool hard_reset);
860 int (*suspend)(struct hl_device *hdev);
861 int (*resume)(struct hl_device *hdev);
862 int (*cb_mmap)(struct hl_device *hdev, struct vm_area_struct *vma,
863 void *cpu_addr, dma_addr_t dma_addr, size_t size);
864 void (*ring_doorbell)(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
865 void (*pqe_write)(struct hl_device *hdev, __le64 *pqe,
866 struct hl_bd *bd);
867 void* (*asic_dma_alloc_coherent)(struct hl_device *hdev, size_t size,
868 dma_addr_t *dma_handle, gfp_t flag);
869 void (*asic_dma_free_coherent)(struct hl_device *hdev, size_t size,
870 void *cpu_addr, dma_addr_t dma_handle);
871 int (*scrub_device_mem)(struct hl_device *hdev, u64 addr, u64 size);
872 void* (*get_int_queue_base)(struct hl_device *hdev, u32 queue_id,
873 dma_addr_t *dma_handle, u16 *queue_len);
874 int (*test_queues)(struct hl_device *hdev);
875 void* (*asic_dma_pool_zalloc)(struct hl_device *hdev, size_t size,
876 gfp_t mem_flags, dma_addr_t *dma_handle);
877 void (*asic_dma_pool_free)(struct hl_device *hdev, void *vaddr,
878 dma_addr_t dma_addr);
879 void* (*cpu_accessible_dma_pool_alloc)(struct hl_device *hdev,
880 size_t size, dma_addr_t *dma_handle);
881 void (*cpu_accessible_dma_pool_free)(struct hl_device *hdev,
882 size_t size, void *vaddr);
883 void (*hl_dma_unmap_sg)(struct hl_device *hdev,
884 struct scatterlist *sgl, int nents,
885 enum dma_data_direction dir);
886 int (*cs_parser)(struct hl_device *hdev, struct hl_cs_parser *parser);
887 int (*asic_dma_map_sg)(struct hl_device *hdev,
888 struct scatterlist *sgl, int nents,
889 enum dma_data_direction dir);
890 u32 (*get_dma_desc_list_size)(struct hl_device *hdev,
891 struct sg_table *sgt);
892 void (*add_end_of_cb_packets)(struct hl_device *hdev,
893 void *kernel_address, u32 len,
894 u64 cq_addr, u32 cq_val, u32 msix_num,
895 bool eb);
896 void (*update_eq_ci)(struct hl_device *hdev, u32 val);
897 int (*context_switch)(struct hl_device *hdev, u32 asid);
898 void (*restore_phase_topology)(struct hl_device *hdev);
899 int (*debugfs_read32)(struct hl_device *hdev, u64 addr, u32 *val);
900 int (*debugfs_write32)(struct hl_device *hdev, u64 addr, u32 val);
901 int (*debugfs_read64)(struct hl_device *hdev, u64 addr, u64 *val);
902 int (*debugfs_write64)(struct hl_device *hdev, u64 addr, u64 val);
903 void (*add_device_attr)(struct hl_device *hdev,
904 struct attribute_group *dev_attr_grp);
905 void (*handle_eqe)(struct hl_device *hdev,
906 struct hl_eq_entry *eq_entry);
907 void (*set_pll_profile)(struct hl_device *hdev,
908 enum hl_pll_frequency freq);
909 void* (*get_events_stat)(struct hl_device *hdev, bool aggregate,
910 u32 *size);
911 u64 (*read_pte)(struct hl_device *hdev, u64 addr);
912 void (*write_pte)(struct hl_device *hdev, u64 addr, u64 val);
913 int (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard,
914 u32 flags);
915 int (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard,
916 u32 asid, u64 va, u64 size);
917 int (*send_heartbeat)(struct hl_device *hdev);
918 void (*set_clock_gating)(struct hl_device *hdev);
919 void (*disable_clock_gating)(struct hl_device *hdev);
920 int (*debug_coresight)(struct hl_device *hdev, void *data);
921 bool (*is_device_idle)(struct hl_device *hdev, u64 *mask,
922 struct seq_file *s);
923 int (*soft_reset_late_init)(struct hl_device *hdev);
924 void (*hw_queues_lock)(struct hl_device *hdev);
925 void (*hw_queues_unlock)(struct hl_device *hdev);
926 u32 (*get_pci_id)(struct hl_device *hdev);
927 int (*get_eeprom_data)(struct hl_device *hdev, void *data,
928 size_t max_size);
929 int (*send_cpu_message)(struct hl_device *hdev, u32 *msg,
930 u16 len, u32 timeout, u64 *result);
931 int (*pci_bars_map)(struct hl_device *hdev);
932 int (*init_iatu)(struct hl_device *hdev);
933 u32 (*rreg)(struct hl_device *hdev, u32 reg);
934 void (*wreg)(struct hl_device *hdev, u32 reg, u32 val);
935 void (*halt_coresight)(struct hl_device *hdev);
936 int (*ctx_init)(struct hl_ctx *ctx);
937 void (*ctx_fini)(struct hl_ctx *ctx);
938 int (*get_clk_rate)(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
939 u32 (*get_queue_id_for_cq)(struct hl_device *hdev, u32 cq_idx);
940 int (*read_device_fw_version)(struct hl_device *hdev,
941 enum hl_fw_component fwc);
942 int (*load_firmware_to_device)(struct hl_device *hdev);
943 int (*load_boot_fit_to_device)(struct hl_device *hdev);
944 u32 (*get_signal_cb_size)(struct hl_device *hdev);
945 u32 (*get_wait_cb_size)(struct hl_device *hdev);
946 u32 (*gen_signal_cb)(struct hl_device *hdev, void *data, u16 sob_id,
947 u32 size, bool eb);
948 u32 (*gen_wait_cb)(struct hl_device *hdev,
949 struct hl_gen_wait_properties *prop);
950 void (*reset_sob)(struct hl_device *hdev, void *data);
951 void (*reset_sob_group)(struct hl_device *hdev, u16 sob_group);
952 void (*set_dma_mask_from_fw)(struct hl_device *hdev);
953 u64 (*get_device_time)(struct hl_device *hdev);
954 void (*collective_wait_init_cs)(struct hl_cs *cs);
955 int (*collective_wait_create_jobs)(struct hl_device *hdev,
956 struct hl_ctx *ctx, struct hl_cs *cs, u32 wait_queue_id,
957 u32 collective_engine_id);
962 * CONTEXTS
965 #define HL_KERNEL_ASID_ID 0
968 * enum hl_va_range_type - virtual address range type.
969 * @HL_VA_RANGE_TYPE_HOST: range type of host pages
970 * @HL_VA_RANGE_TYPE_HOST_HUGE: range type of host huge pages
971 * @HL_VA_RANGE_TYPE_DRAM: range type of dram pages
973 enum hl_va_range_type {
974 HL_VA_RANGE_TYPE_HOST,
975 HL_VA_RANGE_TYPE_HOST_HUGE,
976 HL_VA_RANGE_TYPE_DRAM,
977 HL_VA_RANGE_TYPE_MAX
981 * struct hl_va_range - virtual addresses range.
982 * @lock: protects the virtual addresses list.
983 * @list: list of virtual addresses blocks available for mappings.
984 * @start_addr: range start address.
985 * @end_addr: range end address.
986 * @page_size: page size of this va range.
988 struct hl_va_range {
989 struct mutex lock;
990 struct list_head list;
991 u64 start_addr;
992 u64 end_addr;
993 u32 page_size;
997 * struct hl_cs_counters_atomic - command submission counters
998 * @out_of_mem_drop_cnt: dropped due to memory allocation issue
999 * @parsing_drop_cnt: dropped due to error in packet parsing
1000 * @queue_full_drop_cnt: dropped due to queue full
1001 * @device_in_reset_drop_cnt: dropped due to device in reset
1002 * @max_cs_in_flight_drop_cnt: dropped due to maximum CS in-flight
1003 * @validation_drop_cnt: dropped due to error in validation
1005 struct hl_cs_counters_atomic {
1006 atomic64_t out_of_mem_drop_cnt;
1007 atomic64_t parsing_drop_cnt;
1008 atomic64_t queue_full_drop_cnt;
1009 atomic64_t device_in_reset_drop_cnt;
1010 atomic64_t max_cs_in_flight_drop_cnt;
1011 atomic64_t validation_drop_cnt;
1015 * struct hl_ctx - user/kernel context.
1016 * @mem_hash: holds mapping from virtual address to virtual memory area
1017 * descriptor (hl_vm_phys_pg_list or hl_userptr).
1018 * @mmu_shadow_hash: holds a mapping from shadow address to pgt_info structure.
1019 * @hpriv: pointer to the private (Kernel Driver) data of the process (fd).
1020 * @hdev: pointer to the device structure.
1021 * @refcount: reference counter for the context. Context is released only when
1022 * this hits 0l. It is incremented on CS and CS_WAIT.
1023 * @cs_pending: array of hl fence objects representing pending CS.
1024 * @va_range: holds available virtual addresses for host and dram mappings.
1025 * @mem_hash_lock: protects the mem_hash.
1026 * @mmu_lock: protects the MMU page tables. Any change to the PGT, modifying the
1027 * MMU hash or walking the PGT requires talking this lock.
1028 * @debugfs_list: node in debugfs list of contexts.
1029 * @cs_counters: context command submission counters.
1030 * @cb_va_pool: device VA pool for command buffers which are mapped to the
1031 * device's MMU.
1032 * @cs_sequence: sequence number for CS. Value is assigned to a CS and passed
1033 * to user so user could inquire about CS. It is used as
1034 * index to cs_pending array.
1035 * @dram_default_hops: array that holds all hops addresses needed for default
1036 * DRAM mapping.
1037 * @cs_lock: spinlock to protect cs_sequence.
1038 * @dram_phys_mem: amount of used physical DRAM memory by this context.
1039 * @thread_ctx_switch_token: token to prevent multiple threads of the same
1040 * context from running the context switch phase.
1041 * Only a single thread should run it.
1042 * @thread_ctx_switch_wait_token: token to prevent the threads that didn't run
1043 * the context switch phase from moving to their
1044 * execution phase before the context switch phase
1045 * has finished.
1046 * @asid: context's unique address space ID in the device's MMU.
1047 * @handle: context's opaque handle for user
1049 struct hl_ctx {
1050 DECLARE_HASHTABLE(mem_hash, MEM_HASH_TABLE_BITS);
1051 DECLARE_HASHTABLE(mmu_shadow_hash, MMU_HASH_TABLE_BITS);
1052 struct hl_fpriv *hpriv;
1053 struct hl_device *hdev;
1054 struct kref refcount;
1055 struct hl_fence **cs_pending;
1056 struct hl_va_range *va_range[HL_VA_RANGE_TYPE_MAX];
1057 struct mutex mem_hash_lock;
1058 struct mutex mmu_lock;
1059 struct list_head debugfs_list;
1060 struct hl_cs_counters_atomic cs_counters;
1061 struct gen_pool *cb_va_pool;
1062 u64 cs_sequence;
1063 u64 *dram_default_hops;
1064 spinlock_t cs_lock;
1065 atomic64_t dram_phys_mem;
1066 atomic_t thread_ctx_switch_token;
1067 u32 thread_ctx_switch_wait_token;
1068 u32 asid;
1069 u32 handle;
1073 * struct hl_ctx_mgr - for handling multiple contexts.
1074 * @ctx_lock: protects ctx_handles.
1075 * @ctx_handles: idr to hold all ctx handles.
1077 struct hl_ctx_mgr {
1078 struct mutex ctx_lock;
1079 struct idr ctx_handles;
1085 * COMMAND SUBMISSIONS
1089 * struct hl_userptr - memory mapping chunk information
1090 * @vm_type: type of the VM.
1091 * @job_node: linked-list node for hanging the object on the Job's list.
1092 * @vec: pointer to the frame vector.
1093 * @sgt: pointer to the scatter-gather table that holds the pages.
1094 * @dir: for DMA unmapping, the direction must be supplied, so save it.
1095 * @debugfs_list: node in debugfs list of command submissions.
1096 * @addr: user-space virtual address of the start of the memory area.
1097 * @size: size of the memory area to pin & map.
1098 * @dma_mapped: true if the SG was mapped to DMA addresses, false otherwise.
1100 struct hl_userptr {
1101 enum vm_type_t vm_type; /* must be first */
1102 struct list_head job_node;
1103 struct frame_vector *vec;
1104 struct sg_table *sgt;
1105 enum dma_data_direction dir;
1106 struct list_head debugfs_list;
1107 u64 addr;
1108 u32 size;
1109 u8 dma_mapped;
1113 * struct hl_cs - command submission.
1114 * @jobs_in_queue_cnt: per each queue, maintain counter of submitted jobs.
1115 * @ctx: the context this CS belongs to.
1116 * @job_list: list of the CS's jobs in the various queues.
1117 * @job_lock: spinlock for the CS's jobs list. Needed for free_job.
1118 * @refcount: reference counter for usage of the CS.
1119 * @fence: pointer to the fence object of this CS.
1120 * @signal_fence: pointer to the fence object of the signal CS (used by wait
1121 * CS only).
1122 * @finish_work: workqueue object to run when CS is completed by H/W.
1123 * @work_tdr: delayed work node for TDR.
1124 * @mirror_node : node in device mirror list of command submissions.
1125 * @debugfs_list: node in debugfs list of command submissions.
1126 * @sequence: the sequence number of this CS.
1127 * @type: CS_TYPE_*.
1128 * @submitted: true if CS was submitted to H/W.
1129 * @completed: true if CS was completed by device.
1130 * @timedout : true if CS was timedout.
1131 * @tdr_active: true if TDR was activated for this CS (to prevent
1132 * double TDR activation).
1133 * @aborted: true if CS was aborted due to some device error.
1134 * @timestamp: true if a timestmap must be captured upon completion
1136 struct hl_cs {
1137 u16 *jobs_in_queue_cnt;
1138 struct hl_ctx *ctx;
1139 struct list_head job_list;
1140 spinlock_t job_lock;
1141 struct kref refcount;
1142 struct hl_fence *fence;
1143 struct hl_fence *signal_fence;
1144 struct work_struct finish_work;
1145 struct delayed_work work_tdr;
1146 struct list_head mirror_node;
1147 struct list_head debugfs_list;
1148 u64 sequence;
1149 enum hl_cs_type type;
1150 u8 submitted;
1151 u8 completed;
1152 u8 timedout;
1153 u8 tdr_active;
1154 u8 aborted;
1155 u8 timestamp;
1159 * struct hl_cs_job - command submission job.
1160 * @cs_node: the node to hang on the CS jobs list.
1161 * @cs: the CS this job belongs to.
1162 * @user_cb: the CB we got from the user.
1163 * @patched_cb: in case of patching, this is internal CB which is submitted on
1164 * the queue instead of the CB we got from the IOCTL.
1165 * @finish_work: workqueue object to run when job is completed.
1166 * @userptr_list: linked-list of userptr mappings that belong to this job and
1167 * wait for completion.
1168 * @debugfs_list: node in debugfs list of command submission jobs.
1169 * @refcount: reference counter for usage of the CS job.
1170 * @queue_type: the type of the H/W queue this job is submitted to.
1171 * @id: the id of this job inside a CS.
1172 * @hw_queue_id: the id of the H/W queue this job is submitted to.
1173 * @user_cb_size: the actual size of the CB we got from the user.
1174 * @job_cb_size: the actual size of the CB that we put on the queue.
1175 * @is_kernel_allocated_cb: true if the CB handle we got from the user holds a
1176 * handle to a kernel-allocated CB object, false
1177 * otherwise (SRAM/DRAM/host address).
1178 * @contains_dma_pkt: whether the JOB contains at least one DMA packet. This
1179 * info is needed later, when adding the 2xMSG_PROT at the
1180 * end of the JOB, to know which barriers to put in the
1181 * MSG_PROT packets. Relevant only for GAUDI as GOYA doesn't
1182 * have streams so the engine can't be busy by another
1183 * stream.
1185 struct hl_cs_job {
1186 struct list_head cs_node;
1187 struct hl_cs *cs;
1188 struct hl_cb *user_cb;
1189 struct hl_cb *patched_cb;
1190 struct work_struct finish_work;
1191 struct list_head userptr_list;
1192 struct list_head debugfs_list;
1193 struct kref refcount;
1194 enum hl_queue_type queue_type;
1195 u32 id;
1196 u32 hw_queue_id;
1197 u32 user_cb_size;
1198 u32 job_cb_size;
1199 u8 is_kernel_allocated_cb;
1200 u8 contains_dma_pkt;
1204 * struct hl_cs_parser - command submission parser properties.
1205 * @user_cb: the CB we got from the user.
1206 * @patched_cb: in case of patching, this is internal CB which is submitted on
1207 * the queue instead of the CB we got from the IOCTL.
1208 * @job_userptr_list: linked-list of userptr mappings that belong to the related
1209 * job and wait for completion.
1210 * @cs_sequence: the sequence number of the related CS.
1211 * @queue_type: the type of the H/W queue this job is submitted to.
1212 * @ctx_id: the ID of the context the related CS belongs to.
1213 * @hw_queue_id: the id of the H/W queue this job is submitted to.
1214 * @user_cb_size: the actual size of the CB we got from the user.
1215 * @patched_cb_size: the size of the CB after parsing.
1216 * @job_id: the id of the related job inside the related CS.
1217 * @is_kernel_allocated_cb: true if the CB handle we got from the user holds a
1218 * handle to a kernel-allocated CB object, false
1219 * otherwise (SRAM/DRAM/host address).
1220 * @contains_dma_pkt: whether the JOB contains at least one DMA packet. This
1221 * info is needed later, when adding the 2xMSG_PROT at the
1222 * end of the JOB, to know which barriers to put in the
1223 * MSG_PROT packets. Relevant only for GAUDI as GOYA doesn't
1224 * have streams so the engine can't be busy by another
1225 * stream.
1227 struct hl_cs_parser {
1228 struct hl_cb *user_cb;
1229 struct hl_cb *patched_cb;
1230 struct list_head *job_userptr_list;
1231 u64 cs_sequence;
1232 enum hl_queue_type queue_type;
1233 u32 ctx_id;
1234 u32 hw_queue_id;
1235 u32 user_cb_size;
1236 u32 patched_cb_size;
1237 u8 job_id;
1238 u8 is_kernel_allocated_cb;
1239 u8 contains_dma_pkt;
1243 * MEMORY STRUCTURE
1247 * struct hl_vm_hash_node - hash element from virtual address to virtual
1248 * memory area descriptor (hl_vm_phys_pg_list or
1249 * hl_userptr).
1250 * @node: node to hang on the hash table in context object.
1251 * @vaddr: key virtual address.
1252 * @ptr: value pointer (hl_vm_phys_pg_list or hl_userptr).
1254 struct hl_vm_hash_node {
1255 struct hlist_node node;
1256 u64 vaddr;
1257 void *ptr;
1261 * struct hl_vm_phys_pg_pack - physical page pack.
1262 * @vm_type: describes the type of the virtual area descriptor.
1263 * @pages: the physical page array.
1264 * @npages: num physical pages in the pack.
1265 * @total_size: total size of all the pages in this list.
1266 * @mapping_cnt: number of shared mappings.
1267 * @asid: the context related to this list.
1268 * @page_size: size of each page in the pack.
1269 * @flags: HL_MEM_* flags related to this list.
1270 * @handle: the provided handle related to this list.
1271 * @offset: offset from the first page.
1272 * @contiguous: is contiguous physical memory.
1273 * @created_from_userptr: is product of host virtual address.
1275 struct hl_vm_phys_pg_pack {
1276 enum vm_type_t vm_type; /* must be first */
1277 u64 *pages;
1278 u64 npages;
1279 u64 total_size;
1280 atomic_t mapping_cnt;
1281 u32 asid;
1282 u32 page_size;
1283 u32 flags;
1284 u32 handle;
1285 u32 offset;
1286 u8 contiguous;
1287 u8 created_from_userptr;
1291 * struct hl_vm_va_block - virtual range block information.
1292 * @node: node to hang on the virtual range list in context object.
1293 * @start: virtual range start address.
1294 * @end: virtual range end address.
1295 * @size: virtual range size.
1297 struct hl_vm_va_block {
1298 struct list_head node;
1299 u64 start;
1300 u64 end;
1301 u64 size;
1305 * struct hl_vm - virtual memory manager for MMU.
1306 * @dram_pg_pool: pool for DRAM physical pages of 2MB.
1307 * @dram_pg_pool_refcount: reference counter for the pool usage.
1308 * @idr_lock: protects the phys_pg_list_handles.
1309 * @phys_pg_pack_handles: idr to hold all device allocations handles.
1310 * @init_done: whether initialization was done. We need this because VM
1311 * initialization might be skipped during device initialization.
1313 struct hl_vm {
1314 struct gen_pool *dram_pg_pool;
1315 struct kref dram_pg_pool_refcount;
1316 spinlock_t idr_lock;
1317 struct idr phys_pg_pack_handles;
1318 u8 init_done;
1323 * DEBUG, PROFILING STRUCTURE
1327 * struct hl_debug_params - Coresight debug parameters.
1328 * @input: pointer to component specific input parameters.
1329 * @output: pointer to component specific output parameters.
1330 * @output_size: size of output buffer.
1331 * @reg_idx: relevant register ID.
1332 * @op: component operation to execute.
1333 * @enable: true if to enable component debugging, false otherwise.
1335 struct hl_debug_params {
1336 void *input;
1337 void *output;
1338 u32 output_size;
1339 u32 reg_idx;
1340 u32 op;
1341 bool enable;
1345 * FILE PRIVATE STRUCTURE
1349 * struct hl_fpriv - process information stored in FD private data.
1350 * @hdev: habanalabs device structure.
1351 * @filp: pointer to the given file structure.
1352 * @taskpid: current process ID.
1353 * @ctx: current executing context. TODO: remove for multiple ctx per process
1354 * @ctx_mgr: context manager to handle multiple context for this FD.
1355 * @cb_mgr: command buffer manager to handle multiple buffers for this FD.
1356 * @debugfs_list: list of relevant ASIC debugfs.
1357 * @dev_node: node in the device list of file private data
1358 * @refcount: number of related contexts.
1359 * @restore_phase_mutex: lock for context switch and restore phase.
1360 * @is_control: true for control device, false otherwise
1362 struct hl_fpriv {
1363 struct hl_device *hdev;
1364 struct file *filp;
1365 struct pid *taskpid;
1366 struct hl_ctx *ctx;
1367 struct hl_ctx_mgr ctx_mgr;
1368 struct hl_cb_mgr cb_mgr;
1369 struct list_head debugfs_list;
1370 struct list_head dev_node;
1371 struct kref refcount;
1372 struct mutex restore_phase_mutex;
1373 u8 is_control;
1378 * DebugFS
1382 * struct hl_info_list - debugfs file ops.
1383 * @name: file name.
1384 * @show: function to output information.
1385 * @write: function to write to the file.
1387 struct hl_info_list {
1388 const char *name;
1389 int (*show)(struct seq_file *s, void *data);
1390 ssize_t (*write)(struct file *file, const char __user *buf,
1391 size_t count, loff_t *f_pos);
1395 * struct hl_debugfs_entry - debugfs dentry wrapper.
1396 * @dent: base debugfs entry structure.
1397 * @info_ent: dentry realted ops.
1398 * @dev_entry: ASIC specific debugfs manager.
1400 struct hl_debugfs_entry {
1401 struct dentry *dent;
1402 const struct hl_info_list *info_ent;
1403 struct hl_dbg_device_entry *dev_entry;
1407 * struct hl_dbg_device_entry - ASIC specific debugfs manager.
1408 * @root: root dentry.
1409 * @hdev: habanalabs device structure.
1410 * @entry_arr: array of available hl_debugfs_entry.
1411 * @file_list: list of available debugfs files.
1412 * @file_mutex: protects file_list.
1413 * @cb_list: list of available CBs.
1414 * @cb_spinlock: protects cb_list.
1415 * @cs_list: list of available CSs.
1416 * @cs_spinlock: protects cs_list.
1417 * @cs_job_list: list of available CB jobs.
1418 * @cs_job_spinlock: protects cs_job_list.
1419 * @userptr_list: list of available userptrs (virtual memory chunk descriptor).
1420 * @userptr_spinlock: protects userptr_list.
1421 * @ctx_mem_hash_list: list of available contexts with MMU mappings.
1422 * @ctx_mem_hash_spinlock: protects cb_list.
1423 * @addr: next address to read/write from/to in read/write32.
1424 * @mmu_addr: next virtual address to translate to physical address in mmu_show.
1425 * @mmu_asid: ASID to use while translating in mmu_show.
1426 * @i2c_bus: generic u8 debugfs file for bus value to use in i2c_data_read.
1427 * @i2c_bus: generic u8 debugfs file for address value to use in i2c_data_read.
1428 * @i2c_bus: generic u8 debugfs file for register value to use in i2c_data_read.
1430 struct hl_dbg_device_entry {
1431 struct dentry *root;
1432 struct hl_device *hdev;
1433 struct hl_debugfs_entry *entry_arr;
1434 struct list_head file_list;
1435 struct mutex file_mutex;
1436 struct list_head cb_list;
1437 spinlock_t cb_spinlock;
1438 struct list_head cs_list;
1439 spinlock_t cs_spinlock;
1440 struct list_head cs_job_list;
1441 spinlock_t cs_job_spinlock;
1442 struct list_head userptr_list;
1443 spinlock_t userptr_spinlock;
1444 struct list_head ctx_mem_hash_list;
1445 spinlock_t ctx_mem_hash_spinlock;
1446 u64 addr;
1447 u64 mmu_addr;
1448 u32 mmu_asid;
1449 u8 i2c_bus;
1450 u8 i2c_addr;
1451 u8 i2c_reg;
1456 * DEVICES
1459 #define HL_STR_MAX 32
1461 #define HL_DEV_STS_MAX (HL_DEVICE_STATUS_NEEDS_RESET + 1)
1463 /* Theoretical limit only. A single host can only contain up to 4 or 8 PCIe
1464 * x16 cards. In extreme cases, there are hosts that can accommodate 16 cards.
1466 #define HL_MAX_MINORS 256
1469 * Registers read & write functions.
1472 u32 hl_rreg(struct hl_device *hdev, u32 reg);
1473 void hl_wreg(struct hl_device *hdev, u32 reg, u32 val);
1475 #define RREG32(reg) hdev->asic_funcs->rreg(hdev, (reg))
1476 #define WREG32(reg, v) hdev->asic_funcs->wreg(hdev, (reg), (v))
1477 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
1478 hdev->asic_funcs->rreg(hdev, (reg)))
1480 #define WREG32_P(reg, val, mask) \
1481 do { \
1482 u32 tmp_ = RREG32(reg); \
1483 tmp_ &= (mask); \
1484 tmp_ |= ((val) & ~(mask)); \
1485 WREG32(reg, tmp_); \
1486 } while (0)
1487 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1488 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1490 #define RMWREG32(reg, val, mask) \
1491 do { \
1492 u32 tmp_ = RREG32(reg); \
1493 tmp_ &= ~(mask); \
1494 tmp_ |= ((val) << __ffs(mask)); \
1495 WREG32(reg, tmp_); \
1496 } while (0)
1498 #define RREG32_MASK(reg, mask) ((RREG32(reg) & mask) >> __ffs(mask))
1500 #define REG_FIELD_SHIFT(reg, field) reg##_##field##_SHIFT
1501 #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK
1502 #define WREG32_FIELD(reg, offset, field, val) \
1503 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & \
1504 ~REG_FIELD_MASK(reg, field)) | \
1505 (val) << REG_FIELD_SHIFT(reg, field))
1507 /* Timeout should be longer when working with simulator but cap the
1508 * increased timeout to some maximum
1510 #define hl_poll_timeout(hdev, addr, val, cond, sleep_us, timeout_us) \
1511 ({ \
1512 ktime_t __timeout; \
1513 if (hdev->pdev) \
1514 __timeout = ktime_add_us(ktime_get(), timeout_us); \
1515 else \
1516 __timeout = ktime_add_us(ktime_get(),\
1517 min((u64)(timeout_us * 10), \
1518 (u64) HL_SIM_MAX_TIMEOUT_US)); \
1519 might_sleep_if(sleep_us); \
1520 for (;;) { \
1521 (val) = RREG32(addr); \
1522 if (cond) \
1523 break; \
1524 if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \
1525 (val) = RREG32(addr); \
1526 break; \
1528 if (sleep_us) \
1529 usleep_range((sleep_us >> 2) + 1, sleep_us); \
1531 (cond) ? 0 : -ETIMEDOUT; \
1535 * address in this macro points always to a memory location in the
1536 * host's (server's) memory. That location is updated asynchronously
1537 * either by the direct access of the device or by another core.
1539 * To work both in LE and BE architectures, we need to distinguish between the
1540 * two states (device or another core updates the memory location). Therefore,
1541 * if mem_written_by_device is true, the host memory being polled will be
1542 * updated directly by the device. If false, the host memory being polled will
1543 * be updated by host CPU. Required so host knows whether or not the memory
1544 * might need to be byte-swapped before returning value to caller.
1546 #define hl_poll_timeout_memory(hdev, addr, val, cond, sleep_us, timeout_us, \
1547 mem_written_by_device) \
1548 ({ \
1549 ktime_t __timeout; \
1550 if (hdev->pdev) \
1551 __timeout = ktime_add_us(ktime_get(), timeout_us); \
1552 else \
1553 __timeout = ktime_add_us(ktime_get(),\
1554 min((u64)(timeout_us * 10), \
1555 (u64) HL_SIM_MAX_TIMEOUT_US)); \
1556 might_sleep_if(sleep_us); \
1557 for (;;) { \
1558 /* Verify we read updates done by other cores or by device */ \
1559 mb(); \
1560 (val) = *((u32 *)(addr)); \
1561 if (mem_written_by_device) \
1562 (val) = le32_to_cpu(*(__le32 *) &(val)); \
1563 if (cond) \
1564 break; \
1565 if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \
1566 (val) = *((u32 *)(addr)); \
1567 if (mem_written_by_device) \
1568 (val) = le32_to_cpu(*(__le32 *) &(val)); \
1569 break; \
1571 if (sleep_us) \
1572 usleep_range((sleep_us >> 2) + 1, sleep_us); \
1574 (cond) ? 0 : -ETIMEDOUT; \
1577 #define hl_poll_timeout_device_memory(hdev, addr, val, cond, sleep_us, \
1578 timeout_us) \
1579 ({ \
1580 ktime_t __timeout; \
1581 if (hdev->pdev) \
1582 __timeout = ktime_add_us(ktime_get(), timeout_us); \
1583 else \
1584 __timeout = ktime_add_us(ktime_get(),\
1585 min((u64)(timeout_us * 10), \
1586 (u64) HL_SIM_MAX_TIMEOUT_US)); \
1587 might_sleep_if(sleep_us); \
1588 for (;;) { \
1589 (val) = readl(addr); \
1590 if (cond) \
1591 break; \
1592 if (timeout_us && ktime_compare(ktime_get(), __timeout) > 0) { \
1593 (val) = readl(addr); \
1594 break; \
1596 if (sleep_us) \
1597 usleep_range((sleep_us >> 2) + 1, sleep_us); \
1599 (cond) ? 0 : -ETIMEDOUT; \
1602 struct hwmon_chip_info;
1605 * struct hl_device_reset_work - reset workqueue task wrapper.
1606 * @wq: work queue for device reset procedure.
1607 * @reset_work: reset work to be done.
1608 * @hdev: habanalabs device structure.
1610 struct hl_device_reset_work {
1611 struct workqueue_struct *wq;
1612 struct delayed_work reset_work;
1613 struct hl_device *hdev;
1617 * struct hl_device_idle_busy_ts - used for calculating device utilization rate.
1618 * @idle_to_busy_ts: timestamp where device changed from idle to busy.
1619 * @busy_to_idle_ts: timestamp where device changed from busy to idle.
1621 struct hl_device_idle_busy_ts {
1622 ktime_t idle_to_busy_ts;
1623 ktime_t busy_to_idle_ts;
1627 * struct hr_mmu_hop_addrs - used for holding per-device host-resident mmu hop
1628 * information.
1629 * @virt_addr: the virtual address of the hop.
1630 * @phys-addr: the physical address of the hop (used by the device-mmu).
1631 * @shadow_addr: The shadow of the hop used by the driver for walking the hops.
1633 struct hr_mmu_hop_addrs {
1634 u64 virt_addr;
1635 u64 phys_addr;
1636 u64 shadow_addr;
1640 * struct hl_mmu_hr_pgt_priv - used for holding per-device mmu host-resident
1641 * page-table internal information.
1642 * @mmu_pgt_pool: pool of page tables used by MMU for allocating hops.
1643 * @mmu_shadow_hop0: shadow array of hop0 tables.
1645 struct hl_mmu_hr_priv {
1646 struct gen_pool *mmu_pgt_pool;
1647 struct hr_mmu_hop_addrs *mmu_shadow_hop0;
1651 * struct hl_mmu_dr_pgt_priv - used for holding per-device mmu device-resident
1652 * page-table internal information.
1653 * @mmu_pgt_pool: pool of page tables used by MMU for allocating hops.
1654 * @mmu_shadow_hop0: shadow array of hop0 tables.
1656 struct hl_mmu_dr_priv {
1657 struct gen_pool *mmu_pgt_pool;
1658 void *mmu_shadow_hop0;
1662 * struct hl_mmu_priv - used for holding per-device mmu internal information.
1663 * @dr: information on the device-resident MMU, when exists.
1664 * @hr: information on the host-resident MMU, when exists.
1666 struct hl_mmu_priv {
1667 struct hl_mmu_dr_priv dr;
1668 struct hl_mmu_hr_priv hr;
1672 * struct hl_mmu_per_hop_info - A structure describing one TLB HOP and its entry
1673 * that was created in order to translate a virtual address to a
1674 * physical one.
1675 * @hop_addr: The address of the hop.
1676 * @hop_pte_addr: The address of the hop entry.
1677 * @hop_pte_val: The value in the hop entry.
1679 struct hl_mmu_per_hop_info {
1680 u64 hop_addr;
1681 u64 hop_pte_addr;
1682 u64 hop_pte_val;
1686 * struct hl_mmu_hop_info - A structure describing the TLB hops and their
1687 * hop-entries that were created in order to translate a virtual address to a
1688 * physical one.
1689 * @hop_info: Array holding the per-hop information used for the translation.
1690 * @used_hops: The number of hops used for the translation.
1692 struct hl_mmu_hop_info {
1693 struct hl_mmu_per_hop_info hop_info[MMU_ARCH_5_HOPS];
1694 u32 used_hops;
1698 * struct hl_mmu_funcs - Device related MMU functions.
1699 * @init: initialize the MMU module.
1700 * @fini: release the MMU module.
1701 * @ctx_init: Initialize a context for using the MMU module.
1702 * @ctx_fini: disable a ctx from using the mmu module.
1703 * @map: maps a virtual address to physical address for a context.
1704 * @unmap: unmap a virtual address of a context.
1705 * @flush: flush all writes from all cores to reach device MMU.
1706 * @swap_out: marks all mapping of the given context as swapped out.
1707 * @swap_in: marks all mapping of the given context as swapped in.
1708 * @get_tlb_info: returns the list of hops and hop-entries used that were
1709 * created in order to translate the giver virtual address to a
1710 * physical one.
1712 struct hl_mmu_funcs {
1713 int (*init)(struct hl_device *hdev);
1714 void (*fini)(struct hl_device *hdev);
1715 int (*ctx_init)(struct hl_ctx *ctx);
1716 void (*ctx_fini)(struct hl_ctx *ctx);
1717 int (*map)(struct hl_ctx *ctx,
1718 u64 virt_addr, u64 phys_addr, u32 page_size,
1719 bool is_dram_addr);
1720 int (*unmap)(struct hl_ctx *ctx,
1721 u64 virt_addr, bool is_dram_addr);
1722 void (*flush)(struct hl_ctx *ctx);
1723 void (*swap_out)(struct hl_ctx *ctx);
1724 void (*swap_in)(struct hl_ctx *ctx);
1725 int (*get_tlb_info)(struct hl_ctx *ctx,
1726 u64 virt_addr, struct hl_mmu_hop_info *hops);
1730 * struct hl_device - habanalabs device structure.
1731 * @pdev: pointer to PCI device, can be NULL in case of simulator device.
1732 * @pcie_bar_phys: array of available PCIe bars physical addresses.
1733 * (required only for PCI address match mode)
1734 * @pcie_bar: array of available PCIe bars virtual addresses.
1735 * @rmmio: configuration area address on SRAM.
1736 * @cdev: related char device.
1737 * @cdev_ctrl: char device for control operations only (INFO IOCTL)
1738 * @dev: related kernel basic device structure.
1739 * @dev_ctrl: related kernel device structure for the control device
1740 * @work_freq: delayed work to lower device frequency if possible.
1741 * @work_heartbeat: delayed work for CPU-CP is-alive check.
1742 * @device_reset_work: delayed work which performs hard reset
1743 * @asic_name: ASIC specific name.
1744 * @asic_type: ASIC specific type.
1745 * @completion_queue: array of hl_cq.
1746 * @cq_wq: work queues of completion queues for executing work in process
1747 * context.
1748 * @eq_wq: work queue of event queue for executing work in process context.
1749 * @kernel_ctx: Kernel driver context structure.
1750 * @kernel_queues: array of hl_hw_queue.
1751 * @cs_mirror_list: CS mirror list for TDR.
1752 * @cs_mirror_lock: protects cs_mirror_list.
1753 * @kernel_cb_mgr: command buffer manager for creating/destroying/handling CGs.
1754 * @event_queue: event queue for IRQ from CPU-CP.
1755 * @dma_pool: DMA pool for small allocations.
1756 * @cpu_accessible_dma_mem: Host <-> CPU-CP shared memory CPU address.
1757 * @cpu_accessible_dma_address: Host <-> CPU-CP shared memory DMA address.
1758 * @cpu_accessible_dma_pool: Host <-> CPU-CP shared memory pool.
1759 * @asid_bitmap: holds used/available ASIDs.
1760 * @asid_mutex: protects asid_bitmap.
1761 * @send_cpu_message_lock: enforces only one message in Host <-> CPU-CP queue.
1762 * @debug_lock: protects critical section of setting debug mode for device
1763 * @asic_prop: ASIC specific immutable properties.
1764 * @asic_funcs: ASIC specific functions.
1765 * @asic_specific: ASIC specific information to use only from ASIC files.
1766 * @vm: virtual memory manager for MMU.
1767 * @mmu_cache_lock: protects MMU cache invalidation as it can serve one context.
1768 * @hwmon_dev: H/W monitor device.
1769 * @pm_mng_profile: current power management profile.
1770 * @hl_chip_info: ASIC's sensors information.
1771 * @device_status_description: device status description.
1772 * @hl_debugfs: device's debugfs manager.
1773 * @cb_pool: list of preallocated CBs.
1774 * @cb_pool_lock: protects the CB pool.
1775 * @internal_cb_pool_virt_addr: internal command buffer pool virtual address.
1776 * @internal_cb_pool_dma_addr: internal command buffer pool dma address.
1777 * @internal_cb_pool: internal command buffer memory pool.
1778 * @internal_cb_va_base: internal cb pool mmu virtual address base
1779 * @fpriv_list: list of file private data structures. Each structure is created
1780 * when a user opens the device
1781 * @fpriv_list_lock: protects the fpriv_list
1782 * @compute_ctx: current compute context executing.
1783 * @idle_busy_ts_arr: array to hold time stamps of transitions from idle to busy
1784 * and vice-versa
1785 * @aggregated_cs_counters: aggregated cs counters among all contexts
1786 * @mmu_priv: device-specific MMU data.
1787 * @mmu_func: device-related MMU functions.
1788 * @dram_used_mem: current DRAM memory consumption.
1789 * @timeout_jiffies: device CS timeout value.
1790 * @max_power: the max power of the device, as configured by the sysadmin. This
1791 * value is saved so in case of hard-reset, the driver will restore
1792 * this value and update the F/W after the re-initialization
1793 * @clock_gating_mask: is clock gating enabled. bitmask that represents the
1794 * different engines. See debugfs-driver-habanalabs for
1795 * details.
1796 * @in_reset: is device in reset flow.
1797 * @curr_pll_profile: current PLL profile.
1798 * @card_type: Various ASICs have several card types. This indicates the card
1799 * type of the current device.
1800 * @cs_active_cnt: number of active command submissions on this device (active
1801 * means already in H/W queues)
1802 * @major: habanalabs kernel driver major.
1803 * @high_pll: high PLL profile frequency.
1804 * @soft_reset_cnt: number of soft reset since the driver was loaded.
1805 * @hard_reset_cnt: number of hard reset since the driver was loaded.
1806 * @idle_busy_ts_idx: index of current entry in idle_busy_ts_arr
1807 * @clk_throttling_reason: bitmask represents the current clk throttling reasons
1808 * @id: device minor.
1809 * @id_control: minor of the control device
1810 * @cpu_pci_msb_addr: 50-bit extension bits for the device CPU's 40-bit
1811 * addresses.
1812 * @disabled: is device disabled.
1813 * @late_init_done: is late init stage was done during initialization.
1814 * @hwmon_initialized: is H/W monitor sensors was initialized.
1815 * @hard_reset_pending: is there a hard reset work pending.
1816 * @heartbeat: is heartbeat sanity check towards CPU-CP enabled.
1817 * @reset_on_lockup: true if a reset should be done in case of stuck CS, false
1818 * otherwise.
1819 * @dram_default_page_mapping: is DRAM default page mapping enabled.
1820 * @memory_scrub: true to perform device memory scrub in various locations,
1821 * such as context-switch, context close, page free, etc.
1822 * @pmmu_huge_range: is a different virtual addresses range used for PMMU with
1823 * huge pages.
1824 * @init_done: is the initialization of the device done.
1825 * @device_cpu_disabled: is the device CPU disabled (due to timeouts)
1826 * @dma_mask: the dma mask that was set for this device
1827 * @in_debug: is device under debug. This, together with fpriv_list, enforces
1828 * that only a single user is configuring the debug infrastructure.
1829 * @power9_64bit_dma_enable: true to enable 64-bit DMA mask support. Relevant
1830 * only to POWER9 machines.
1831 * @cdev_sysfs_created: were char devices and sysfs nodes created.
1832 * @stop_on_err: true if engines should stop on error.
1833 * @supports_sync_stream: is sync stream supported.
1834 * @sync_stream_queue_idx: helper index for sync stream queues initialization.
1835 * @collective_mon_idx: helper index for collective initialization
1836 * @supports_coresight: is CoreSight supported.
1837 * @supports_soft_reset: is soft reset supported.
1838 * @supports_cb_mapping: is mapping a CB to the device's MMU supported.
1839 * @needs_reset: true if reset_on_lockup is false and device should be reset
1840 * due to lockup.
1841 * @process_kill_trial_cnt: number of trials reset thread tried killing
1842 * user processes
1843 * @device_fini_pending: true if device_fini was called and might be
1844 * waiting for the reset thread to finish
1846 struct hl_device {
1847 struct pci_dev *pdev;
1848 u64 pcie_bar_phys[HL_PCI_NUM_BARS];
1849 void __iomem *pcie_bar[HL_PCI_NUM_BARS];
1850 void __iomem *rmmio;
1851 struct cdev cdev;
1852 struct cdev cdev_ctrl;
1853 struct device *dev;
1854 struct device *dev_ctrl;
1855 struct delayed_work work_freq;
1856 struct delayed_work work_heartbeat;
1857 struct hl_device_reset_work device_reset_work;
1858 char asic_name[HL_STR_MAX];
1859 char status[HL_DEV_STS_MAX][HL_STR_MAX];
1860 enum hl_asic_type asic_type;
1861 struct hl_cq *completion_queue;
1862 struct workqueue_struct **cq_wq;
1863 struct workqueue_struct *eq_wq;
1864 struct hl_ctx *kernel_ctx;
1865 struct hl_hw_queue *kernel_queues;
1866 struct list_head cs_mirror_list;
1867 spinlock_t cs_mirror_lock;
1868 struct hl_cb_mgr kernel_cb_mgr;
1869 struct hl_eq event_queue;
1870 struct dma_pool *dma_pool;
1871 void *cpu_accessible_dma_mem;
1872 dma_addr_t cpu_accessible_dma_address;
1873 struct gen_pool *cpu_accessible_dma_pool;
1874 unsigned long *asid_bitmap;
1875 struct mutex asid_mutex;
1876 struct mutex send_cpu_message_lock;
1877 struct mutex debug_lock;
1878 struct asic_fixed_properties asic_prop;
1879 const struct hl_asic_funcs *asic_funcs;
1880 void *asic_specific;
1881 struct hl_vm vm;
1882 struct mutex mmu_cache_lock;
1883 struct device *hwmon_dev;
1884 enum hl_pm_mng_profile pm_mng_profile;
1885 struct hwmon_chip_info *hl_chip_info;
1887 struct hl_dbg_device_entry hl_debugfs;
1889 struct list_head cb_pool;
1890 spinlock_t cb_pool_lock;
1892 void *internal_cb_pool_virt_addr;
1893 dma_addr_t internal_cb_pool_dma_addr;
1894 struct gen_pool *internal_cb_pool;
1895 u64 internal_cb_va_base;
1897 struct list_head fpriv_list;
1898 struct mutex fpriv_list_lock;
1900 struct hl_ctx *compute_ctx;
1902 struct hl_device_idle_busy_ts *idle_busy_ts_arr;
1904 struct hl_cs_counters_atomic aggregated_cs_counters;
1906 struct hl_mmu_priv mmu_priv;
1907 struct hl_mmu_funcs mmu_func[MMU_NUM_PGT_LOCATIONS];
1909 atomic64_t dram_used_mem;
1910 u64 timeout_jiffies;
1911 u64 max_power;
1912 u64 clock_gating_mask;
1913 atomic_t in_reset;
1914 enum hl_pll_frequency curr_pll_profile;
1915 enum cpucp_card_types card_type;
1916 int cs_active_cnt;
1917 u32 major;
1918 u32 high_pll;
1919 u32 soft_reset_cnt;
1920 u32 hard_reset_cnt;
1921 u32 idle_busy_ts_idx;
1922 u32 clk_throttling_reason;
1923 u16 id;
1924 u16 id_control;
1925 u16 cpu_pci_msb_addr;
1926 u8 disabled;
1927 u8 late_init_done;
1928 u8 hwmon_initialized;
1929 u8 hard_reset_pending;
1930 u8 heartbeat;
1931 u8 reset_on_lockup;
1932 u8 dram_default_page_mapping;
1933 u8 memory_scrub;
1934 u8 pmmu_huge_range;
1935 u8 init_done;
1936 u8 device_cpu_disabled;
1937 u8 dma_mask;
1938 u8 in_debug;
1939 u8 power9_64bit_dma_enable;
1940 u8 cdev_sysfs_created;
1941 u8 stop_on_err;
1942 u8 supports_sync_stream;
1943 u8 sync_stream_queue_idx;
1944 u8 collective_mon_idx;
1945 u8 supports_coresight;
1946 u8 supports_soft_reset;
1947 u8 supports_cb_mapping;
1948 u8 needs_reset;
1949 u8 process_kill_trial_cnt;
1950 u8 device_fini_pending;
1952 /* Parameters for bring-up */
1953 u64 nic_ports_mask;
1954 u64 fw_loading;
1955 u8 mmu_enable;
1956 u8 mmu_huge_page_opt;
1957 u8 cpu_enable;
1958 u8 reset_pcilink;
1959 u8 cpu_queues_enable;
1960 u8 pldm;
1961 u8 axi_drain;
1962 u8 sram_scrambler_enable;
1963 u8 dram_scrambler_enable;
1964 u8 hard_reset_on_fw_events;
1965 u8 bmc_enable;
1966 u8 rl_enable;
1967 u8 reset_on_preboot_fail;
1972 * IOCTLs
1976 * typedef hl_ioctl_t - typedef for ioctl function in the driver
1977 * @hpriv: pointer to the FD's private data, which contains state of
1978 * user process
1979 * @data: pointer to the input/output arguments structure of the IOCTL
1981 * Return: 0 for success, negative value for error
1983 typedef int hl_ioctl_t(struct hl_fpriv *hpriv, void *data);
1986 * struct hl_ioctl_desc - describes an IOCTL entry of the driver.
1987 * @cmd: the IOCTL code as created by the kernel macros.
1988 * @func: pointer to the driver's function that should be called for this IOCTL.
1990 struct hl_ioctl_desc {
1991 unsigned int cmd;
1992 hl_ioctl_t *func;
1997 * Kernel module functions that can be accessed by entire module
2001 * hl_mem_area_inside_range() - Checks whether address+size are inside a range.
2002 * @address: The start address of the area we want to validate.
2003 * @size: The size in bytes of the area we want to validate.
2004 * @range_start_address: The start address of the valid range.
2005 * @range_end_address: The end address of the valid range.
2007 * Return: true if the area is inside the valid range, false otherwise.
2009 static inline bool hl_mem_area_inside_range(u64 address, u64 size,
2010 u64 range_start_address, u64 range_end_address)
2012 u64 end_address = address + size;
2014 if ((address >= range_start_address) &&
2015 (end_address <= range_end_address) &&
2016 (end_address > address))
2017 return true;
2019 return false;
2023 * hl_mem_area_crosses_range() - Checks whether address+size crossing a range.
2024 * @address: The start address of the area we want to validate.
2025 * @size: The size in bytes of the area we want to validate.
2026 * @range_start_address: The start address of the valid range.
2027 * @range_end_address: The end address of the valid range.
2029 * Return: true if the area overlaps part or all of the valid range,
2030 * false otherwise.
2032 static inline bool hl_mem_area_crosses_range(u64 address, u32 size,
2033 u64 range_start_address, u64 range_end_address)
2035 u64 end_address = address + size;
2037 if ((address >= range_start_address) &&
2038 (address < range_end_address))
2039 return true;
2041 if ((end_address >= range_start_address) &&
2042 (end_address < range_end_address))
2043 return true;
2045 if ((address < range_start_address) &&
2046 (end_address >= range_end_address))
2047 return true;
2049 return false;
2052 int hl_device_open(struct inode *inode, struct file *filp);
2053 int hl_device_open_ctrl(struct inode *inode, struct file *filp);
2054 bool hl_device_operational(struct hl_device *hdev,
2055 enum hl_device_status *status);
2056 enum hl_device_status hl_device_status(struct hl_device *hdev);
2057 int hl_device_set_debug_mode(struct hl_device *hdev, bool enable);
2058 int create_hdev(struct hl_device **dev, struct pci_dev *pdev,
2059 enum hl_asic_type asic_type, int minor);
2060 void destroy_hdev(struct hl_device *hdev);
2061 int hl_hw_queues_create(struct hl_device *hdev);
2062 void hl_hw_queues_destroy(struct hl_device *hdev);
2063 int hl_hw_queue_send_cb_no_cmpl(struct hl_device *hdev, u32 hw_queue_id,
2064 u32 cb_size, u64 cb_ptr);
2065 int hl_hw_queue_schedule_cs(struct hl_cs *cs);
2066 u32 hl_hw_queue_add_ptr(u32 ptr, u16 val);
2067 void hl_hw_queue_inc_ci_kernel(struct hl_device *hdev, u32 hw_queue_id);
2068 void hl_int_hw_queue_update_ci(struct hl_cs *cs);
2069 void hl_hw_queue_reset(struct hl_device *hdev, bool hard_reset);
2071 #define hl_queue_inc_ptr(p) hl_hw_queue_add_ptr(p, 1)
2072 #define hl_pi_2_offset(pi) ((pi) & (HL_QUEUE_LENGTH - 1))
2074 int hl_cq_init(struct hl_device *hdev, struct hl_cq *q, u32 hw_queue_id);
2075 void hl_cq_fini(struct hl_device *hdev, struct hl_cq *q);
2076 int hl_eq_init(struct hl_device *hdev, struct hl_eq *q);
2077 void hl_eq_fini(struct hl_device *hdev, struct hl_eq *q);
2078 void hl_cq_reset(struct hl_device *hdev, struct hl_cq *q);
2079 void hl_eq_reset(struct hl_device *hdev, struct hl_eq *q);
2080 irqreturn_t hl_irq_handler_cq(int irq, void *arg);
2081 irqreturn_t hl_irq_handler_eq(int irq, void *arg);
2082 u32 hl_cq_inc_ptr(u32 ptr);
2084 int hl_asid_init(struct hl_device *hdev);
2085 void hl_asid_fini(struct hl_device *hdev);
2086 unsigned long hl_asid_alloc(struct hl_device *hdev);
2087 void hl_asid_free(struct hl_device *hdev, unsigned long asid);
2089 int hl_ctx_create(struct hl_device *hdev, struct hl_fpriv *hpriv);
2090 void hl_ctx_free(struct hl_device *hdev, struct hl_ctx *ctx);
2091 int hl_ctx_init(struct hl_device *hdev, struct hl_ctx *ctx, bool is_kernel_ctx);
2092 void hl_ctx_do_release(struct kref *ref);
2093 void hl_ctx_get(struct hl_device *hdev, struct hl_ctx *ctx);
2094 int hl_ctx_put(struct hl_ctx *ctx);
2095 struct hl_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq);
2096 void hl_ctx_mgr_init(struct hl_ctx_mgr *mgr);
2097 void hl_ctx_mgr_fini(struct hl_device *hdev, struct hl_ctx_mgr *mgr);
2099 int hl_device_init(struct hl_device *hdev, struct class *hclass);
2100 void hl_device_fini(struct hl_device *hdev);
2101 int hl_device_suspend(struct hl_device *hdev);
2102 int hl_device_resume(struct hl_device *hdev);
2103 int hl_device_reset(struct hl_device *hdev, bool hard_reset,
2104 bool from_hard_reset_thread);
2105 void hl_hpriv_get(struct hl_fpriv *hpriv);
2106 void hl_hpriv_put(struct hl_fpriv *hpriv);
2107 int hl_device_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq);
2108 uint32_t hl_device_utilization(struct hl_device *hdev, uint32_t period_ms);
2110 int hl_build_hwmon_channel_info(struct hl_device *hdev,
2111 struct cpucp_sensor *sensors_arr);
2113 int hl_sysfs_init(struct hl_device *hdev);
2114 void hl_sysfs_fini(struct hl_device *hdev);
2116 int hl_hwmon_init(struct hl_device *hdev);
2117 void hl_hwmon_fini(struct hl_device *hdev);
2119 int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr,
2120 struct hl_ctx *ctx, u32 cb_size, bool internal_cb,
2121 bool map_cb, u64 *handle);
2122 int hl_cb_destroy(struct hl_device *hdev, struct hl_cb_mgr *mgr, u64 cb_handle);
2123 int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma);
2124 struct hl_cb *hl_cb_get(struct hl_device *hdev, struct hl_cb_mgr *mgr,
2125 u32 handle);
2126 void hl_cb_put(struct hl_cb *cb);
2127 void hl_cb_mgr_init(struct hl_cb_mgr *mgr);
2128 void hl_cb_mgr_fini(struct hl_device *hdev, struct hl_cb_mgr *mgr);
2129 struct hl_cb *hl_cb_kernel_create(struct hl_device *hdev, u32 cb_size,
2130 bool internal_cb);
2131 int hl_cb_pool_init(struct hl_device *hdev);
2132 int hl_cb_pool_fini(struct hl_device *hdev);
2133 int hl_cb_va_pool_init(struct hl_ctx *ctx);
2134 void hl_cb_va_pool_fini(struct hl_ctx *ctx);
2136 void hl_cs_rollback_all(struct hl_device *hdev);
2137 struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev,
2138 enum hl_queue_type queue_type, bool is_kernel_allocated_cb);
2139 void hl_sob_reset_error(struct kref *ref);
2140 int hl_gen_sob_mask(u16 sob_base, u8 sob_mask, u8 *mask);
2141 void hl_fence_put(struct hl_fence *fence);
2142 void hl_fence_get(struct hl_fence *fence);
2143 void cs_get(struct hl_cs *cs);
2145 void goya_set_asic_funcs(struct hl_device *hdev);
2146 void gaudi_set_asic_funcs(struct hl_device *hdev);
2148 int hl_vm_ctx_init(struct hl_ctx *ctx);
2149 void hl_vm_ctx_fini(struct hl_ctx *ctx);
2151 int hl_vm_init(struct hl_device *hdev);
2152 void hl_vm_fini(struct hl_device *hdev);
2154 u64 hl_reserve_va_block(struct hl_device *hdev, struct hl_ctx *ctx,
2155 enum hl_va_range_type type, u32 size, u32 alignment);
2156 int hl_unreserve_va_block(struct hl_device *hdev, struct hl_ctx *ctx,
2157 u64 start_addr, u64 size);
2158 int hl_pin_host_memory(struct hl_device *hdev, u64 addr, u64 size,
2159 struct hl_userptr *userptr);
2160 void hl_unpin_host_memory(struct hl_device *hdev, struct hl_userptr *userptr);
2161 void hl_userptr_delete_list(struct hl_device *hdev,
2162 struct list_head *userptr_list);
2163 bool hl_userptr_is_pinned(struct hl_device *hdev, u64 addr, u32 size,
2164 struct list_head *userptr_list,
2165 struct hl_userptr **userptr);
2167 int hl_mmu_init(struct hl_device *hdev);
2168 void hl_mmu_fini(struct hl_device *hdev);
2169 int hl_mmu_ctx_init(struct hl_ctx *ctx);
2170 void hl_mmu_ctx_fini(struct hl_ctx *ctx);
2171 int hl_mmu_map_page(struct hl_ctx *ctx, u64 virt_addr, u64 phys_addr,
2172 u32 page_size, bool flush_pte);
2173 int hl_mmu_unmap_page(struct hl_ctx *ctx, u64 virt_addr, u32 page_size,
2174 bool flush_pte);
2175 int hl_mmu_map_contiguous(struct hl_ctx *ctx, u64 virt_addr,
2176 u64 phys_addr, u32 size);
2177 int hl_mmu_unmap_contiguous(struct hl_ctx *ctx, u64 virt_addr, u32 size);
2178 void hl_mmu_swap_out(struct hl_ctx *ctx);
2179 void hl_mmu_swap_in(struct hl_ctx *ctx);
2180 int hl_mmu_if_set_funcs(struct hl_device *hdev);
2181 void hl_mmu_v1_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu);
2182 int hl_mmu_va_to_pa(struct hl_ctx *ctx, u64 virt_addr, u64 *phys_addr);
2183 int hl_mmu_get_tlb_info(struct hl_ctx *ctx, u64 virt_addr,
2184 struct hl_mmu_hop_info *hops);
2186 int hl_fw_load_fw_to_device(struct hl_device *hdev, const char *fw_name,
2187 void __iomem *dst, u32 src_offset, u32 size);
2188 int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode);
2189 int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg,
2190 u16 len, u32 timeout, u64 *result);
2191 int hl_fw_unmask_irq(struct hl_device *hdev, u16 event_type);
2192 int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr,
2193 size_t irq_arr_size);
2194 int hl_fw_test_cpu_queue(struct hl_device *hdev);
2195 void *hl_fw_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
2196 dma_addr_t *dma_handle);
2197 void hl_fw_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
2198 void *vaddr);
2199 int hl_fw_send_heartbeat(struct hl_device *hdev);
2200 int hl_fw_cpucp_info_get(struct hl_device *hdev,
2201 u32 cpu_security_boot_status_reg);
2202 int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size);
2203 int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev,
2204 struct hl_info_pci_counters *counters);
2205 int hl_fw_cpucp_total_energy_get(struct hl_device *hdev,
2206 u64 *total_energy);
2207 int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, u16 pll_index,
2208 u16 *pll_freq_arr);
2209 int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg,
2210 u32 msg_to_cpu_reg, u32 cpu_msg_status_reg,
2211 u32 cpu_security_boot_status_reg, u32 boot_err0_reg,
2212 bool skip_bmc, u32 cpu_timeout, u32 boot_fit_timeout);
2213 int hl_fw_read_preboot_status(struct hl_device *hdev, u32 cpu_boot_status_reg,
2214 u32 cpu_security_boot_status_reg, u32 boot_err0_reg,
2215 u32 timeout);
2217 int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3],
2218 bool is_wc[3]);
2219 int hl_pci_iatu_write(struct hl_device *hdev, u32 addr, u32 data);
2220 int hl_pci_set_inbound_region(struct hl_device *hdev, u8 region,
2221 struct hl_inbound_pci_region *pci_region);
2222 int hl_pci_set_outbound_region(struct hl_device *hdev,
2223 struct hl_outbound_pci_region *pci_region);
2224 int hl_pci_init(struct hl_device *hdev);
2225 void hl_pci_fini(struct hl_device *hdev);
2227 long hl_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr);
2228 void hl_set_frequency(struct hl_device *hdev, u32 pll_index, u64 freq);
2229 int hl_get_temperature(struct hl_device *hdev,
2230 int sensor_index, u32 attr, long *value);
2231 int hl_set_temperature(struct hl_device *hdev,
2232 int sensor_index, u32 attr, long value);
2233 int hl_get_voltage(struct hl_device *hdev,
2234 int sensor_index, u32 attr, long *value);
2235 int hl_get_current(struct hl_device *hdev,
2236 int sensor_index, u32 attr, long *value);
2237 int hl_get_fan_speed(struct hl_device *hdev,
2238 int sensor_index, u32 attr, long *value);
2239 int hl_get_pwm_info(struct hl_device *hdev,
2240 int sensor_index, u32 attr, long *value);
2241 void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
2242 long value);
2243 u64 hl_get_max_power(struct hl_device *hdev);
2244 void hl_set_max_power(struct hl_device *hdev);
2245 int hl_set_voltage(struct hl_device *hdev,
2246 int sensor_index, u32 attr, long value);
2247 int hl_set_current(struct hl_device *hdev,
2248 int sensor_index, u32 attr, long value);
2250 #ifdef CONFIG_DEBUG_FS
2252 void hl_debugfs_init(void);
2253 void hl_debugfs_fini(void);
2254 void hl_debugfs_add_device(struct hl_device *hdev);
2255 void hl_debugfs_remove_device(struct hl_device *hdev);
2256 void hl_debugfs_add_file(struct hl_fpriv *hpriv);
2257 void hl_debugfs_remove_file(struct hl_fpriv *hpriv);
2258 void hl_debugfs_add_cb(struct hl_cb *cb);
2259 void hl_debugfs_remove_cb(struct hl_cb *cb);
2260 void hl_debugfs_add_cs(struct hl_cs *cs);
2261 void hl_debugfs_remove_cs(struct hl_cs *cs);
2262 void hl_debugfs_add_job(struct hl_device *hdev, struct hl_cs_job *job);
2263 void hl_debugfs_remove_job(struct hl_device *hdev, struct hl_cs_job *job);
2264 void hl_debugfs_add_userptr(struct hl_device *hdev, struct hl_userptr *userptr);
2265 void hl_debugfs_remove_userptr(struct hl_device *hdev,
2266 struct hl_userptr *userptr);
2267 void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx);
2268 void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev, struct hl_ctx *ctx);
2270 #else
2272 static inline void __init hl_debugfs_init(void)
2276 static inline void hl_debugfs_fini(void)
2280 static inline void hl_debugfs_add_device(struct hl_device *hdev)
2284 static inline void hl_debugfs_remove_device(struct hl_device *hdev)
2288 static inline void hl_debugfs_add_file(struct hl_fpriv *hpriv)
2292 static inline void hl_debugfs_remove_file(struct hl_fpriv *hpriv)
2296 static inline void hl_debugfs_add_cb(struct hl_cb *cb)
2300 static inline void hl_debugfs_remove_cb(struct hl_cb *cb)
2304 static inline void hl_debugfs_add_cs(struct hl_cs *cs)
2308 static inline void hl_debugfs_remove_cs(struct hl_cs *cs)
2312 static inline void hl_debugfs_add_job(struct hl_device *hdev,
2313 struct hl_cs_job *job)
2317 static inline void hl_debugfs_remove_job(struct hl_device *hdev,
2318 struct hl_cs_job *job)
2322 static inline void hl_debugfs_add_userptr(struct hl_device *hdev,
2323 struct hl_userptr *userptr)
2327 static inline void hl_debugfs_remove_userptr(struct hl_device *hdev,
2328 struct hl_userptr *userptr)
2332 static inline void hl_debugfs_add_ctx_mem_hash(struct hl_device *hdev,
2333 struct hl_ctx *ctx)
2337 static inline void hl_debugfs_remove_ctx_mem_hash(struct hl_device *hdev,
2338 struct hl_ctx *ctx)
2342 #endif
2344 /* IOCTLs */
2345 long hl_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
2346 long hl_ioctl_control(struct file *filep, unsigned int cmd, unsigned long arg);
2347 int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data);
2348 int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data);
2349 int hl_cs_wait_ioctl(struct hl_fpriv *hpriv, void *data);
2350 int hl_mem_ioctl(struct hl_fpriv *hpriv, void *data);
2352 #endif /* HABANALABSP_H_ */