drivers/misc/mei/hw-me.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2012-2020, Intel Corporation. All rights reserved.
   4  * Intel Management Engine Interface (Intel MEI) Linux driver
   5  */
   6
   7 #ifndef _MEI_INTERFACE_H_
   8 #define _MEI_INTERFACE_H_
   9
  10 #include <linux/irqreturn.h>
  11 #include <linux/pci.h>
  12 #include <linux/mei.h>
  13
  14 #include "mei_dev.h"
  15 #include "client.h"
  16
  17 /*
  18  * mei_cfg - mei device configuration
  19  *
  20  * @fw_status: FW status
  21  * @quirk_probe: device exclusion quirk
  22  * @kind: MEI head kind
  23  * @dma_size: device DMA buffers size
  24  * @fw_ver_supported: is fw version retrievable from FW
  25  * @hw_trc_supported: does the hw support trc register
  26  */
  27 struct mei_cfg {
  28         const struct mei_fw_status fw_status;
  29         bool (*quirk_probe)(const struct pci_dev *pdev);
  30         const char *kind;
  31         size_t dma_size[DMA_DSCR_NUM];
  32         u32 fw_ver_supported:1;
  33         u32 hw_trc_supported:1;
  34 };
  35
  36
  37 #define MEI_PCI_DEVICE(dev, cfg) \
  38         .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
  39         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
  40         .driver_data = (kernel_ulong_t)(cfg),
  41
  42 #define MEI_ME_RPM_TIMEOUT    500 /* ms */
  43
  44 /**
  45  * struct mei_me_hw - me hw specific data
  46  *
  47  * @cfg: per device generation config and ops
  48  * @mem_addr: io memory address
  49  * @irq: irq number
  50  * @pg_state: power gating state
  51  * @d0i3_supported: di03 support
  52  * @hbuf_depth: depth of hardware host/write buffer in slots
  53  * @read_fws: read FW status register handler
  54  */
  55 struct mei_me_hw {
  56         const struct mei_cfg *cfg;
  57         void __iomem *mem_addr;
  58         int irq;
  59         enum mei_pg_state pg_state;
  60         bool d0i3_supported;
  61         u8 hbuf_depth;
  62         int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
  63 };
  64
  65 #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
  66
  67 /**
  68  * enum mei_cfg_idx - indices to platform specific configurations.
  69  *
  70  * Note: has to be synchronized with mei_cfg_list[]
  71  *
  72  * @MEI_ME_UNDEF_CFG:      Lower sentinel.
  73  * @MEI_ME_ICH_CFG:        I/O Controller Hub legacy devices.
  74  * @MEI_ME_ICH10_CFG:      I/O Controller Hub platforms Gen10
  75  * @MEI_ME_PCH6_CFG:       Platform Controller Hub platforms (Gen6).
  76  * @MEI_ME_PCH7_CFG:       Platform Controller Hub platforms (Gen7).
  77  * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations
  78  *                         with quirk for Node Manager exclusion.
  79  * @MEI_ME_PCH8_CFG:       Platform Controller Hub Gen8 and newer
  80  *                         client platforms.
  81  * @MEI_ME_PCH8_ITOUCH_CFG:Platform Controller Hub Gen8 and newer
  82  *                         client platforms (iTouch).
  83  * @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer
  84  *                         servers platforms with quirk for
  85  *                         SPS firmware exclusion.
  86  * @MEI_ME_PCH12_CFG:      Platform Controller Hub Gen12 and newer
  87  * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0
  88  *                         servers platforms with quirk for
  89  *                         SPS firmware exclusion.
  90  * @MEI_ME_PCH12_SPS_CFG:  Platform Controller Hub Gen12 5.0 and newer
  91  *                         servers platforms with quirk for
  92  *                         SPS firmware exclusion.
  93  * @MEI_ME_PCH15_CFG:      Platform Controller Hub Gen15 and newer
  94  * @MEI_ME_PCH15_SPS_CFG:  Platform Controller Hub Gen15 and newer
  95  *                         servers platforms with quirk for
  96  *                         SPS firmware exclusion.
  97  * @MEI_ME_NUM_CFG:        Upper Sentinel.
  98  */
  99 enum mei_cfg_idx {
 100         MEI_ME_UNDEF_CFG,
 101         MEI_ME_ICH_CFG,
 102         MEI_ME_ICH10_CFG,
 103         MEI_ME_PCH6_CFG,
 104         MEI_ME_PCH7_CFG,
 105         MEI_ME_PCH_CPT_PBG_CFG,
 106         MEI_ME_PCH8_CFG,
 107         MEI_ME_PCH8_ITOUCH_CFG,
 108         MEI_ME_PCH8_SPS_4_CFG,
 109         MEI_ME_PCH12_CFG,
 110         MEI_ME_PCH12_SPS_4_CFG,
 111         MEI_ME_PCH12_SPS_CFG,
 112         MEI_ME_PCH12_SPS_ITOUCH_CFG,
 113         MEI_ME_PCH15_CFG,
 114         MEI_ME_PCH15_SPS_CFG,
 115         MEI_ME_NUM_CFG,
 116 };
 117
 118 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
 119
 120 struct mei_device *mei_me_dev_init(struct device *parent,
 121                                    const struct mei_cfg *cfg);
 122
 123 int mei_me_pg_enter_sync(struct mei_device *dev);
 124 int mei_me_pg_exit_sync(struct mei_device *dev);
 125
 126 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
 127 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
 128
 129 #endif /* _MEI_INTERFACE_H_ */