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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / mmc / host / meson-mx-sdhc-mmc.c
blob7cd9c0ec2fcfe97cd42c0458d9d6f32a67953545
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Amlogic Meson6/Meson8/Meson8b/Meson8m2 SDHC MMC host controller driver.
4 *
5 * Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/iopoll.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/regmap.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/types.h>
20
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
25
26 #include "meson-mx-sdhc.h"
27
28 #define MESON_SDHC_NUM_BULK_CLKS 4
29 #define MESON_SDHC_MAX_BLK_SIZE 512
30 #define MESON_SDHC_NUM_TUNING_TRIES 10
31
32 #define MESON_SDHC_WAIT_CMD_READY_SLEEP_US 1
33 #define MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US 100000
34 #define MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US 1
35 #define MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US 200
36
37 struct meson_mx_sdhc_data {
38 void (*init_hw)(struct mmc_host *mmc);
39 void (*set_pdma)(struct mmc_host *mmc);
40 void (*wait_before_send)(struct mmc_host *mmc);
41 bool hardware_flush_all_cmds;
42 };
43
44 struct meson_mx_sdhc_host {
45 struct mmc_host *mmc;
46
47 struct mmc_request *mrq;
48 struct mmc_command *cmd;
49 int error;
50
51 struct regmap *regmap;
52
53 struct clk *pclk;
54 struct clk *sd_clk;
55 struct clk_bulk_data bulk_clks[MESON_SDHC_NUM_BULK_CLKS];
56 bool bulk_clks_enabled;
57
58 const struct meson_mx_sdhc_data *platform;
59 };
60
61 static const struct regmap_config meson_mx_sdhc_regmap_config = {
62 .reg_bits = 8,
63 .val_bits = 32,
64 .reg_stride = 4,
65 .max_register = MESON_SDHC_CLK2,
66 };
67
68 static void meson_mx_sdhc_hw_reset(struct mmc_host *mmc)
69 {
70 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
71
72 regmap_write(host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_MAIN_CTRL |
73 MESON_SDHC_SRST_RXFIFO | MESON_SDHC_SRST_TXFIFO |
74 MESON_SDHC_SRST_DPHY_RX | MESON_SDHC_SRST_DPHY_TX |
75 MESON_SDHC_SRST_DMA_IF);
76 usleep_range(10, 100);
77
78 regmap_write(host->regmap, MESON_SDHC_SRST, 0);
79 usleep_range(10, 100);
80 }
81
82 static void meson_mx_sdhc_clear_fifo(struct mmc_host *mmc)
83 {
84 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
85 u32 stat;
86
87 regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
88 if (!FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) &&
89 !FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat))
90 return;
91
92 regmap_write(host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_RXFIFO |
93 MESON_SDHC_SRST_TXFIFO | MESON_SDHC_SRST_MAIN_CTRL);
94 udelay(5);
95
96 regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
97 if (FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) ||
98 FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat))
99 dev_warn(mmc_dev(host->mmc),
100 "Failed to clear FIFOs, RX: %lu, TX: %lu\n",
101 FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat),
102 FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat));
103 }
104
105 static void meson_mx_sdhc_wait_cmd_ready(struct mmc_host *mmc)
106 {
107 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
108 u32 stat, esta;
109 int ret;
110
111 ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT, stat,
112 !(stat & MESON_SDHC_STAT_CMD_BUSY),
113 MESON_SDHC_WAIT_CMD_READY_SLEEP_US,
114 MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US);
115 if (ret) {
116 dev_warn(mmc_dev(mmc),
117 "Failed to poll for CMD_BUSY while processing CMD%d\n",
118 host->cmd->opcode);
119 meson_mx_sdhc_hw_reset(mmc);
120 }
121
122 ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, esta,
123 !(esta & MESON_SDHC_ESTA_11_13),
124 MESON_SDHC_WAIT_CMD_READY_SLEEP_US,
125 MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US);
126 if (ret) {
127 dev_warn(mmc_dev(mmc),
128 "Failed to poll for ESTA[13:11] while processing CMD%d\n",
129 host->cmd->opcode);
130 meson_mx_sdhc_hw_reset(mmc);
131 }
132 }
133
134 static void meson_mx_sdhc_start_cmd(struct mmc_host *mmc,
135 struct mmc_command *cmd)
136 {
137 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
138 u32 ictl, send;
139 int pack_len;
140
141 host->cmd = cmd;
142
143 ictl = MESON_SDHC_ICTL_DATA_TIMEOUT | MESON_SDHC_ICTL_DATA_ERR_CRC |
144 MESON_SDHC_ICTL_RXFIFO_FULL | MESON_SDHC_ICTL_TXFIFO_EMPTY |
145 MESON_SDHC_ICTL_RESP_TIMEOUT | MESON_SDHC_ICTL_RESP_ERR_CRC;
146
147 send = FIELD_PREP(MESON_SDHC_SEND_CMD_INDEX, cmd->opcode);
148
149 if (cmd->data) {
150 send |= MESON_SDHC_SEND_CMD_HAS_DATA;
151 send |= FIELD_PREP(MESON_SDHC_SEND_TOTAL_PACK,
152 cmd->data->blocks - 1);
153
154 if (cmd->data->blksz < MESON_SDHC_MAX_BLK_SIZE)
155 pack_len = cmd->data->blksz;
156 else
157 pack_len = 0;
158
159 if (cmd->data->flags & MMC_DATA_WRITE)
160 send |= MESON_SDHC_SEND_DATA_DIR;
161
162 /*
163 * If command with no data, just wait response done
164 * interrupt(int[0]), and if command with data transfer, just
165 * wait dma done interrupt(int[11]), don't need care about
166 * dat0 busy or not.
167 */
168 if (host->platform->hardware_flush_all_cmds ||
169 cmd->data->flags & MMC_DATA_WRITE)
170 /* hardware flush: */
171 ictl |= MESON_SDHC_ICTL_DMA_DONE;
172 else
173 /* software flush: */
174 ictl |= MESON_SDHC_ICTL_DATA_XFER_OK;
175 } else {
176 pack_len = 0;
177
178 ictl |= MESON_SDHC_ICTL_RESP_OK;
179 }
180
181 if (cmd->opcode == MMC_STOP_TRANSMISSION)
182 send |= MESON_SDHC_SEND_DATA_STOP;
183
184 if (cmd->flags & MMC_RSP_PRESENT)
185 send |= MESON_SDHC_SEND_CMD_HAS_RESP;
186
187 if (cmd->flags & MMC_RSP_136) {
188 send |= MESON_SDHC_SEND_RESP_LEN;
189 send |= MESON_SDHC_SEND_RESP_NO_CRC;
190 }
191
192 if (!(cmd->flags & MMC_RSP_CRC))
193 send |= MESON_SDHC_SEND_RESP_NO_CRC;
194
195 if (cmd->flags & MMC_RSP_BUSY)
196 send |= MESON_SDHC_SEND_R1B;
197
198 /* enable the new IRQs and mask all pending ones */
199 regmap_write(host->regmap, MESON_SDHC_ICTL, ictl);
200 regmap_write(host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS);
201
202 regmap_write(host->regmap, MESON_SDHC_ARGU, cmd->arg);
203
204 regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
205 MESON_SDHC_CTRL_PACK_LEN,
206 FIELD_PREP(MESON_SDHC_CTRL_PACK_LEN, pack_len));
207
208 if (cmd->data)
209 regmap_write(host->regmap, MESON_SDHC_ADDR,
210 sg_dma_address(cmd->data->sg));
211
212 meson_mx_sdhc_wait_cmd_ready(mmc);
213
214 if (cmd->data)
215 host->platform->set_pdma(mmc);
216
217 if (host->platform->wait_before_send)
218 host->platform->wait_before_send(mmc);
219
220 regmap_write(host->regmap, MESON_SDHC_SEND, send);
221 }
222
223 static void meson_mx_sdhc_disable_clks(struct mmc_host *mmc)
224 {
225 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
226
227 if (!host->bulk_clks_enabled)
228 return;
229
230 clk_bulk_disable_unprepare(MESON_SDHC_NUM_BULK_CLKS, host->bulk_clks);
231
232 host->bulk_clks_enabled = false;
233 }
234
235 static int meson_mx_sdhc_enable_clks(struct mmc_host *mmc)
236 {
237 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
238 int ret;
239
240 if (host->bulk_clks_enabled)
241 return 0;
242
243 ret = clk_bulk_prepare_enable(MESON_SDHC_NUM_BULK_CLKS,
244 host->bulk_clks);
245 if (ret)
246 return ret;
247
248 host->bulk_clks_enabled = true;
249
250 return 0;
251 }
252
253 static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)
254 {
255 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
256 u32 rx_clk_phase;
257 int ret;
258
259 meson_mx_sdhc_disable_clks(mmc);
260
261 if (ios->clock) {
262 ret = clk_set_rate(host->sd_clk, ios->clock);
263 if (ret) {
264 dev_warn(mmc_dev(mmc),
265 "Failed to set MMC clock to %uHz: %d\n",
266 ios->clock, host->error);
267 return ret;
268 }
269
270 ret = meson_mx_sdhc_enable_clks(mmc);
271 if (ret)
272 return ret;
273
274 mmc->actual_clock = clk_get_rate(host->sd_clk);
275
276 /*
277 * according to Amlogic the following latching points are
278 * selected with empirical values, there is no (known) formula
279 * to calculate these.
280 */
281 if (mmc->actual_clock > 100000000) {
282 rx_clk_phase = 1;
283 } else if (mmc->actual_clock > 45000000) {
284 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
285 rx_clk_phase = 15;
286 else
287 rx_clk_phase = 11;
288 } else if (mmc->actual_clock >= 25000000) {
289 rx_clk_phase = 15;
290 } else if (mmc->actual_clock > 5000000) {
291 rx_clk_phase = 23;
292 } else if (mmc->actual_clock > 1000000) {
293 rx_clk_phase = 55;
294 } else {
295 rx_clk_phase = 1061;
296 }
297
298 regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
299 MESON_SDHC_CLK2_RX_CLK_PHASE,
300 FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
301 rx_clk_phase));
302 } else {
303 mmc->actual_clock = 0;
304 }
305
306 return 0;
307 }
308
309 static void meson_mx_sdhc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
310 {
311 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
312 unsigned short vdd = ios->vdd;
313
314 switch (ios->power_mode) {
315 case MMC_POWER_OFF:
316 vdd = 0;
317 fallthrough;
318
319 case MMC_POWER_UP:
320 if (!IS_ERR(mmc->supply.vmmc)) {
321 host->error = mmc_regulator_set_ocr(mmc,
322 mmc->supply.vmmc,
323 vdd);
324 if (host->error)
325 return;
326 }
327
328 break;
329
330 case MMC_POWER_ON:
331 break;
332 }
333
334 host->error = meson_mx_sdhc_set_clk(mmc, ios);
335 if (host->error)
336 return;
337
338 switch (ios->bus_width) {
339 case MMC_BUS_WIDTH_1:
340 regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
341 MESON_SDHC_CTRL_DAT_TYPE,
342 FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 0));
343 break;
344
345 case MMC_BUS_WIDTH_4:
346 regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
347 MESON_SDHC_CTRL_DAT_TYPE,
348 FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 1));
349 break;
350
351 case MMC_BUS_WIDTH_8:
352 regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
353 MESON_SDHC_CTRL_DAT_TYPE,
354 FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 2));
355 break;
356
357 default:
358 dev_err(mmc_dev(mmc), "unsupported bus width: %d\n",
359 ios->bus_width);
360 host->error = -EINVAL;
361 return;
362 }
363 }
364
365 static int meson_mx_sdhc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq)
366 {
367 struct mmc_data *data = mrq->data;
368 int dma_len;
369
370 if (!data)
371 return 0;
372
373 dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
374 mmc_get_dma_dir(data));
375 if (dma_len <= 0) {
376 dev_err(mmc_dev(mmc), "dma_map_sg failed\n");
377 return -ENOMEM;
378 }
379
380 return 0;
381 }
382
383 static void meson_mx_sdhc_request(struct mmc_host *mmc, struct mmc_request *mrq)
384 {
385 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
386 struct mmc_command *cmd = mrq->cmd;
387
388 if (!host->error)
389 host->error = meson_mx_sdhc_map_dma(mmc, mrq);
390
391 if (host->error) {
392 cmd->error = host->error;
393 mmc_request_done(mmc, mrq);
394 return;
395 }
396
397 host->mrq = mrq;
398
399 meson_mx_sdhc_start_cmd(mmc, mrq->cmd);
400 }
401
402 static int meson_mx_sdhc_card_busy(struct mmc_host *mmc)
403 {
404 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
405 u32 stat;
406
407 regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
408 return FIELD_GET(MESON_SDHC_STAT_DAT3_0, stat) == 0;
409 }
410
411 static bool meson_mx_sdhc_tuning_point_matches(struct mmc_host *mmc,
412 u32 opcode)
413 {
414 unsigned int i, num_matches = 0;
415 int ret;
416
417 for (i = 0; i < MESON_SDHC_NUM_TUNING_TRIES; i++) {
418 ret = mmc_send_tuning(mmc, opcode, NULL);
419 if (!ret)
420 num_matches++;
421 }
422
423 return num_matches == MESON_SDHC_NUM_TUNING_TRIES;
424 }
425
426 static int meson_mx_sdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
427 {
428 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
429 int div, start, len, best_start, best_len;
430 int curr_phase, old_phase, new_phase;
431 u32 val;
432
433 len = 0;
434 start = 0;
435 best_len = 0;
436
437 regmap_read(host->regmap, MESON_SDHC_CLK2, &val);
438 old_phase = FIELD_GET(MESON_SDHC_CLK2_RX_CLK_PHASE, val);
439
440 regmap_read(host->regmap, MESON_SDHC_CLKC, &val);
441 div = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val);
442
443 for (curr_phase = 0; curr_phase <= div; curr_phase++) {
444 regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
445 MESON_SDHC_CLK2_RX_CLK_PHASE,
446 FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
447 curr_phase));
448
449 if (meson_mx_sdhc_tuning_point_matches(mmc, opcode)) {
450 if (!len) {
451 start = curr_phase;
452
453 dev_dbg(mmc_dev(mmc),
454 "New RX phase window starts at %u\n",
455 start);
456 }
457
458 len++;
459 } else {
460 if (len > best_len) {
461 best_start = start;
462 best_len = len;
463
464 dev_dbg(mmc_dev(mmc),
465 "New best RX phase window: %u - %u\n",
466 best_start, best_start + best_len);
467 }
468
469 /* reset the current window */
470 len = 0;
471 }
472 }
473
474 if (len > best_len)
475 /* the last window is the best (or possibly only) window */
476 new_phase = start + (len / 2);
477 else if (best_len)
478 /* there was a better window than the last */
479 new_phase = best_start + (best_len / 2);
480 else
481 /* no window was found at all, reset to the original phase */
482 new_phase = old_phase;
483
484 regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
485 MESON_SDHC_CLK2_RX_CLK_PHASE,
486 FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
487 new_phase));
488
489 if (!len && !best_len)
490 return -EIO;
491
492 dev_dbg(mmc_dev(mmc), "Tuned RX clock phase to %u\n", new_phase);
493
494 return 0;
495 }
496
497 static const struct mmc_host_ops meson_mx_sdhc_ops = {
498 .hw_reset = meson_mx_sdhc_hw_reset,
499 .request = meson_mx_sdhc_request,
500 .set_ios = meson_mx_sdhc_set_ios,
501 .card_busy = meson_mx_sdhc_card_busy,
502 .execute_tuning = meson_mx_sdhc_execute_tuning,
503 .get_cd = mmc_gpio_get_cd,
504 .get_ro = mmc_gpio_get_ro,
505 };
506
507 static void meson_mx_sdhc_request_done(struct meson_mx_sdhc_host *host)
508 {
509 struct mmc_request *mrq = host->mrq;
510 struct mmc_host *mmc = host->mmc;
511
512 /* disable interrupts and mask all pending ones */
513 regmap_update_bits(host->regmap, MESON_SDHC_ICTL,
514 MESON_SDHC_ICTL_ALL_IRQS, 0);
515 regmap_update_bits(host->regmap, MESON_SDHC_ISTA,
516 MESON_SDHC_ISTA_ALL_IRQS, MESON_SDHC_ISTA_ALL_IRQS);
517
518 host->mrq = NULL;
519 host->cmd = NULL;
520
521 mmc_request_done(mmc, mrq);
522 }
523
524 static u32 meson_mx_sdhc_read_response(struct meson_mx_sdhc_host *host, u8 idx)
525 {
526 u32 val;
527
528 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
529 MESON_SDHC_PDMA_DMA_MODE, 0);
530
531 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
532 MESON_SDHC_PDMA_PIO_RDRESP,
533 FIELD_PREP(MESON_SDHC_PDMA_PIO_RDRESP, idx));
534
535 regmap_read(host->regmap, MESON_SDHC_ARGU, &val);
536
537 return val;
538 }
539
540 static irqreturn_t meson_mx_sdhc_irq(int irq, void *data)
541 {
542 struct meson_mx_sdhc_host *host = data;
543 struct mmc_command *cmd = host->cmd;
544 u32 ictl, ista;
545
546 regmap_read(host->regmap, MESON_SDHC_ICTL, &ictl);
547 regmap_read(host->regmap, MESON_SDHC_ISTA, &ista);
548
549 if (!(ictl & ista))
550 return IRQ_NONE;
551
552 if (ista & MESON_SDHC_ISTA_RXFIFO_FULL ||
553 ista & MESON_SDHC_ISTA_TXFIFO_EMPTY)
554 cmd->error = -EIO;
555 else if (ista & MESON_SDHC_ISTA_RESP_ERR_CRC)
556 cmd->error = -EILSEQ;
557 else if (ista & MESON_SDHC_ISTA_RESP_TIMEOUT)
558 cmd->error = -ETIMEDOUT;
559
560 if (cmd->data) {
561 if (ista & MESON_SDHC_ISTA_DATA_ERR_CRC)
562 cmd->data->error = -EILSEQ;
563 else if (ista & MESON_SDHC_ISTA_DATA_TIMEOUT)
564 cmd->data->error = -ETIMEDOUT;
565 }
566
567 if (cmd->error || (cmd->data && cmd->data->error))
568 dev_dbg(mmc_dev(host->mmc), "CMD%d error, ISTA: 0x%08x\n",
569 cmd->opcode, ista);
570
571 return IRQ_WAKE_THREAD;
572 }
573
574 static irqreturn_t meson_mx_sdhc_irq_thread(int irq, void *irq_data)
575 {
576 struct meson_mx_sdhc_host *host = irq_data;
577 struct mmc_command *cmd;
578 u32 val;
579
580 cmd = host->cmd;
581 if (WARN_ON(!cmd))
582 return IRQ_HANDLED;
583
584 if (cmd->data && !cmd->data->error) {
585 if (!host->platform->hardware_flush_all_cmds &&
586 cmd->data->flags & MMC_DATA_READ) {
587 meson_mx_sdhc_wait_cmd_ready(host->mmc);
588
589 /*
590 * If MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH was
591 * previously 0x1 then it has to be set to 0x3. If it
592 * was 0x0 before then it has to be set to 0x2. Without
593 * this reading SD cards sometimes transfers garbage,
594 * which results in cards not being detected due to:
595 * unrecognised SCR structure version <random number>
596 */
597 val = FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
598 2);
599 regmap_update_bits(host->regmap, MESON_SDHC_PDMA, val,
600 val);
601 }
602
603 dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg,
604 cmd->data->sg_len, mmc_get_dma_dir(cmd->data));
605
606 cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks;
607 }
608
609 meson_mx_sdhc_wait_cmd_ready(host->mmc);
610
611 if (cmd->flags & MMC_RSP_136) {
612 cmd->resp[0] = meson_mx_sdhc_read_response(host, 4);
613 cmd->resp[1] = meson_mx_sdhc_read_response(host, 3);
614 cmd->resp[2] = meson_mx_sdhc_read_response(host, 2);
615 cmd->resp[3] = meson_mx_sdhc_read_response(host, 1);
616 } else {
617 cmd->resp[0] = meson_mx_sdhc_read_response(host, 0);
618 }
619
620 if (cmd->error == -EIO || cmd->error == -ETIMEDOUT)
621 meson_mx_sdhc_hw_reset(host->mmc);
622 else if (cmd->data)
623 /*
624 * Clear the FIFOs after completing data transfers to prevent
625 * corrupting data on write access. It's not clear why this is
626 * needed (for reads and writes), but it mimics what the BSP
627 * kernel did.
628 */
629 meson_mx_sdhc_clear_fifo(host->mmc);
630
631 meson_mx_sdhc_request_done(host);
632
633 return IRQ_HANDLED;
634 }
635
636 static void meson_mx_sdhc_init_hw_meson8(struct mmc_host *mmc)
637 {
638 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
639
640 regmap_write(host->regmap, MESON_SDHC_MISC,
641 FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 7) |
642 FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) |
643 FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2));
644
645 regmap_write(host->regmap, MESON_SDHC_ENHC,
646 FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 63) |
647 MESON_SDHC_ENHC_MESON6_DMA_WR_RESP |
648 FIELD_PREP(MESON_SDHC_ENHC_MESON6_RX_TIMEOUT, 255) |
649 FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12));
650 };
651
652 static void meson_mx_sdhc_set_pdma_meson8(struct mmc_host *mmc)
653 {
654 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
655
656 if (host->cmd->data->flags & MMC_DATA_WRITE)
657 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
658 MESON_SDHC_PDMA_DMA_MODE |
659 MESON_SDHC_PDMA_RD_BURST |
660 MESON_SDHC_PDMA_TXFIFO_FILL,
661 MESON_SDHC_PDMA_DMA_MODE |
662 FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 31) |
663 MESON_SDHC_PDMA_TXFIFO_FILL);
664 else
665 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
666 MESON_SDHC_PDMA_DMA_MODE |
667 MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
668 MESON_SDHC_PDMA_DMA_MODE |
669 FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
670 1));
671
672 if (host->cmd->data->flags & MMC_DATA_WRITE)
673 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
674 MESON_SDHC_PDMA_RD_BURST,
675 FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15));
676 }
677
678 static void meson_mx_sdhc_wait_before_send_meson8(struct mmc_host *mmc)
679 {
680 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
681 u32 val;
682 int ret;
683
684 ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, val,
685 val == 0,
686 MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US,
687 MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US);
688 if (ret)
689 dev_warn(mmc_dev(mmc),
690 "Failed to wait for ESTA to clear: 0x%08x\n", val);
691
692 if (host->cmd->data && host->cmd->data->flags & MMC_DATA_WRITE) {
693 ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT,
694 val, val & MESON_SDHC_STAT_TXFIFO_CNT,
695 MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US,
696 MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US);
697 if (ret)
698 dev_warn(mmc_dev(mmc),
699 "Failed to wait for TX FIFO to fill\n");
700 }
701 }
702
703 static void meson_mx_sdhc_init_hw_meson8m2(struct mmc_host *mmc)
704 {
705 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
706
707 regmap_write(host->regmap, MESON_SDHC_MISC,
708 FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 6) |
709 FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) |
710 FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2));
711
712 regmap_write(host->regmap, MESON_SDHC_ENHC,
713 FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 64) |
714 FIELD_PREP(MESON_SDHC_ENHC_MESON8M2_DEBUG, 1) |
715 MESON_SDHC_ENHC_MESON8M2_WRRSP_MODE |
716 FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12));
717 }
718
719 static void meson_mx_sdhc_set_pdma_meson8m2(struct mmc_host *mmc)
720 {
721 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
722
723 regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
724 MESON_SDHC_PDMA_DMA_MODE, MESON_SDHC_PDMA_DMA_MODE);
725 }
726
727 static void meson_mx_sdhc_init_hw(struct mmc_host *mmc)
728 {
729 struct meson_mx_sdhc_host *host = mmc_priv(mmc);
730
731 meson_mx_sdhc_hw_reset(mmc);
732
733 regmap_write(host->regmap, MESON_SDHC_CTRL,
734 FIELD_PREP(MESON_SDHC_CTRL_RX_PERIOD, 0xf) |
735 FIELD_PREP(MESON_SDHC_CTRL_RX_TIMEOUT, 0x7f) |
736 FIELD_PREP(MESON_SDHC_CTRL_RX_ENDIAN, 0x7) |
737 FIELD_PREP(MESON_SDHC_CTRL_TX_ENDIAN, 0x7));
738
739 /*
740 * start with a valid divider and enable the memory (un-setting
741 * MESON_SDHC_CLKC_MEM_PWR_OFF).
742 */
743 regmap_write(host->regmap, MESON_SDHC_CLKC, MESON_SDHC_CLKC_CLK_DIV);
744
745 regmap_write(host->regmap, MESON_SDHC_CLK2,
746 FIELD_PREP(MESON_SDHC_CLK2_SD_CLK_PHASE, 1));
747
748 regmap_write(host->regmap, MESON_SDHC_PDMA,
749 MESON_SDHC_PDMA_DMA_URGENT |
750 FIELD_PREP(MESON_SDHC_PDMA_WR_BURST, 7) |
751 FIELD_PREP(MESON_SDHC_PDMA_TXFIFO_TH, 49) |
752 FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15) |
753 FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_TH, 7));
754
755 /* some initialization bits depend on the SoC: */
756 host->platform->init_hw(mmc);
757
758 /* disable and mask all interrupts: */
759 regmap_write(host->regmap, MESON_SDHC_ICTL, 0);
760 regmap_write(host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS);
761 }
762
763 static int meson_mx_sdhc_probe(struct platform_device *pdev)
764 {
765 struct device *dev = &pdev->dev;
766 struct meson_mx_sdhc_host *host;
767 struct mmc_host *mmc;
768 void __iomem *base;
769 int ret, irq;
770
771 mmc = mmc_alloc_host(sizeof(*host), dev);
772 if (!mmc)
773 return -ENOMEM;
774
775 ret = devm_add_action_or_reset(dev, (void(*)(void *))mmc_free_host,
776 mmc);
777 if (ret) {
778 dev_err(dev, "Failed to register mmc_free_host action\n");
779 return ret;
780 }
781
782 host = mmc_priv(mmc);
783 host->mmc = mmc;
784
785 platform_set_drvdata(pdev, host);
786
787 host->platform = device_get_match_data(dev);
788 if (!host->platform)
789 return -EINVAL;
790
791 base = devm_platform_ioremap_resource(pdev, 0);
792 if (IS_ERR(base))
793 return PTR_ERR(base);
794
795 host->regmap = devm_regmap_init_mmio(dev, base,
796 &meson_mx_sdhc_regmap_config);
797 if (IS_ERR(host->regmap))
798 return PTR_ERR(host->regmap);
799
800 host->pclk = devm_clk_get(dev, "pclk");
801 if (IS_ERR(host->pclk))
802 return PTR_ERR(host->pclk);
803
804 /* accessing any register requires the module clock to be enabled: */
805 ret = clk_prepare_enable(host->pclk);
806 if (ret) {
807 dev_err(dev, "Failed to enable 'pclk' clock\n");
808 return ret;
809 }
810
811 meson_mx_sdhc_init_hw(mmc);
812
813 ret = meson_mx_sdhc_register_clkc(dev, base, host->bulk_clks);
814 if (ret)
815 goto err_disable_pclk;
816
817 host->sd_clk = host->bulk_clks[1].clk;
818
819 /* Get regulators and the supported OCR mask */
820 ret = mmc_regulator_get_supply(mmc);
821 if (ret)
822 goto err_disable_pclk;
823
824 mmc->max_req_size = SZ_128K;
825 mmc->max_seg_size = mmc->max_req_size;
826 mmc->max_blk_count = FIELD_GET(MESON_SDHC_SEND_TOTAL_PACK, ~0);
827 mmc->max_blk_size = MESON_SDHC_MAX_BLK_SIZE;
828 mmc->max_busy_timeout = 30 * MSEC_PER_SEC;
829 mmc->f_min = clk_round_rate(host->sd_clk, 1);
830 mmc->f_max = clk_round_rate(host->sd_clk, ULONG_MAX);
831 mmc->max_current_180 = 300;
832 mmc->max_current_330 = 300;
833 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_HW_RESET;
834 mmc->ops = &meson_mx_sdhc_ops;
835
836 ret = mmc_of_parse(mmc);
837 if (ret)
838 goto err_disable_pclk;
839
840 irq = platform_get_irq(pdev, 0);
841 ret = devm_request_threaded_irq(dev, irq, meson_mx_sdhc_irq,
842 meson_mx_sdhc_irq_thread, IRQF_ONESHOT,
843 NULL, host);
844 if (ret)
845 goto err_disable_pclk;
846
847 ret = mmc_add_host(mmc);
848 if (ret)
849 goto err_disable_pclk;
850
851 return 0;
852
853 err_disable_pclk:
854 clk_disable_unprepare(host->pclk);
855 return ret;
856 }
857
858 static int meson_mx_sdhc_remove(struct platform_device *pdev)
859 {
860 struct meson_mx_sdhc_host *host = platform_get_drvdata(pdev);
861
862 mmc_remove_host(host->mmc);
863
864 meson_mx_sdhc_disable_clks(host->mmc);
865
866 clk_disable_unprepare(host->pclk);
867
868 return 0;
869 }
870
871 static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8 = {
872 .init_hw = meson_mx_sdhc_init_hw_meson8,
873 .set_pdma = meson_mx_sdhc_set_pdma_meson8,
874 .wait_before_send = meson_mx_sdhc_wait_before_send_meson8,
875 .hardware_flush_all_cmds = false,
876 };
877
878 static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8m2 = {
879 .init_hw = meson_mx_sdhc_init_hw_meson8m2,
880 .set_pdma = meson_mx_sdhc_set_pdma_meson8m2,
881 .hardware_flush_all_cmds = true,
882 };
883
884 static const struct of_device_id meson_mx_sdhc_of_match[] = {
885 {
886 .compatible = "amlogic,meson8-sdhc",
887 .data = &meson_mx_sdhc_data_meson8
888 },
889 {
890 .compatible = "amlogic,meson8b-sdhc",
891 .data = &meson_mx_sdhc_data_meson8
892 },
893 {
894 .compatible = "amlogic,meson8m2-sdhc",
895 .data = &meson_mx_sdhc_data_meson8m2
896 },
897 { /* sentinel */ }
898 };
899 MODULE_DEVICE_TABLE(of, meson_mx_sdhc_of_match);
900
901 static struct platform_driver meson_mx_sdhc_driver = {
902 .probe = meson_mx_sdhc_probe,
903 .remove = meson_mx_sdhc_remove,
904 .driver = {
905 .name = "meson-mx-sdhc",
906 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
907 .of_match_table = of_match_ptr(meson_mx_sdhc_of_match),
908 },
909 };
910
911 module_platform_driver(meson_mx_sdhc_driver);
912
913 MODULE_DESCRIPTION("Meson6, Meson8, Meson8b and Meson8m2 SDHC Host Driver");
914 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
915 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support