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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / mmc / host / rtsx_pci_sdmmc.c
blobe6f5bbce5685e332d07211cdfa3de55e69b5db3e
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Realtek PCI-Express SD/MMC Card Interface driver
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */
9
10 #include <linux/module.h>
11 #include <linux/slab.h>
12 #include <linux/highmem.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/workqueue.h>
16 #include <linux/mmc/host.h>
17 #include <linux/mmc/mmc.h>
18 #include <linux/mmc/sd.h>
19 #include <linux/mmc/sdio.h>
20 #include <linux/mmc/card.h>
21 #include <linux/rtsx_pci.h>
22 #include <asm/unaligned.h>
23 #include <linux/pm_runtime.h>
24
25 struct realtek_pci_sdmmc {
26 struct platform_device *pdev;
27 struct rtsx_pcr *pcr;
28 struct mmc_host *mmc;
29 struct mmc_request *mrq;
30 #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
31
32 struct work_struct work;
33 struct mutex host_mutex;
34
35 u8 ssc_depth;
36 unsigned int clock;
37 bool vpclk;
38 bool double_clk;
39 bool eject;
40 bool initial_mode;
41 int power_state;
42 #define SDMMC_POWER_ON 1
43 #define SDMMC_POWER_OFF 0
44
45 int sg_count;
46 s32 cookie;
47 int cookie_sg_count;
48 bool using_cookie;
49 };
50
51 static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios);
52
53 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
54 {
55 return &(host->pdev->dev);
56 }
57
58 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
59 {
60 rtsx_pci_write_register(host->pcr, CARD_STOP,
61 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
62 }
63
64 #ifdef DEBUG
65 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
66 {
67 u16 len = end - start + 1;
68 int i;
69 u8 data[8];
70
71 for (i = 0; i < len; i += 8) {
72 int j;
73 int n = min(8, len - i);
74
75 memset(&data, 0, sizeof(data));
76 for (j = 0; j < n; j++)
77 rtsx_pci_read_register(host->pcr, start + i + j,
78 data + j);
79 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
80 start + i, n, data);
81 }
82 }
83
84 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
85 {
86 dump_reg_range(host, 0xFDA0, 0xFDB3);
87 dump_reg_range(host, 0xFD52, 0xFD69);
88 }
89 #else
90 #define sd_print_debug_regs(host)
91 #endif /* DEBUG */
92
93 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
94 {
95 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
96 }
97
98 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
99 {
100 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
101 SD_CMD_START | cmd->opcode);
102 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
103 }
104
105 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
106 {
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
109 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
111 }
112
113 static int sd_response_type(struct mmc_command *cmd)
114 {
115 switch (mmc_resp_type(cmd)) {
116 case MMC_RSP_NONE:
117 return SD_RSP_TYPE_R0;
118 case MMC_RSP_R1:
119 return SD_RSP_TYPE_R1;
120 case MMC_RSP_R1_NO_CRC:
121 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
122 case MMC_RSP_R1B:
123 return SD_RSP_TYPE_R1b;
124 case MMC_RSP_R2:
125 return SD_RSP_TYPE_R2;
126 case MMC_RSP_R3:
127 return SD_RSP_TYPE_R3;
128 default:
129 return -EINVAL;
130 }
131 }
132
133 static int sd_status_index(int resp_type)
134 {
135 if (resp_type == SD_RSP_TYPE_R0)
136 return 0;
137 else if (resp_type == SD_RSP_TYPE_R2)
138 return 16;
139
140 return 5;
141 }
142 /*
143 * sd_pre_dma_transfer - do dma_map_sg() or using cookie
144 *
145 * @pre: if called in pre_req()
146 * return:
147 * 0 - do dma_map_sg()
148 * 1 - using cookie
149 */
150 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
151 struct mmc_data *data, bool pre)
152 {
153 struct rtsx_pcr *pcr = host->pcr;
154 int read = data->flags & MMC_DATA_READ;
155 int count = 0;
156 int using_cookie = 0;
157
158 if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
159 dev_err(sdmmc_dev(host),
160 "error: data->host_cookie = %d, host->cookie = %d\n",
161 data->host_cookie, host->cookie);
162 data->host_cookie = 0;
163 }
164
165 if (pre || data->host_cookie != host->cookie) {
166 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
167 } else {
168 count = host->cookie_sg_count;
169 using_cookie = 1;
170 }
171
172 if (pre) {
173 host->cookie_sg_count = count;
174 if (++host->cookie < 0)
175 host->cookie = 1;
176 data->host_cookie = host->cookie;
177 } else {
178 host->sg_count = count;
179 }
180
181 return using_cookie;
182 }
183
184 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
185 {
186 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
187 struct mmc_data *data = mrq->data;
188
189 if (data->host_cookie) {
190 dev_err(sdmmc_dev(host),
191 "error: reset data->host_cookie = %d\n",
192 data->host_cookie);
193 data->host_cookie = 0;
194 }
195
196 sd_pre_dma_transfer(host, data, true);
197 dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
198 }
199
200 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
201 int err)
202 {
203 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
204 struct rtsx_pcr *pcr = host->pcr;
205 struct mmc_data *data = mrq->data;
206 int read = data->flags & MMC_DATA_READ;
207
208 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
209 data->host_cookie = 0;
210 }
211
212 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
213 struct mmc_command *cmd)
214 {
215 struct rtsx_pcr *pcr = host->pcr;
216 u8 cmd_idx = (u8)cmd->opcode;
217 u32 arg = cmd->arg;
218 int err = 0;
219 int timeout = 100;
220 int i;
221 u8 *ptr;
222 int rsp_type;
223 int stat_idx;
224 bool clock_toggled = false;
225
226 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
227 __func__, cmd_idx, arg);
228
229 rsp_type = sd_response_type(cmd);
230 if (rsp_type < 0)
231 goto out;
232
233 stat_idx = sd_status_index(rsp_type);
234
235 if (rsp_type == SD_RSP_TYPE_R1b)
236 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
237
238 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
239 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
240 0xFF, SD_CLK_TOGGLE_EN);
241 if (err < 0)
242 goto out;
243
244 clock_toggled = true;
245 }
246
247 rtsx_pci_init_cmd(pcr);
248 sd_cmd_set_sd_cmd(pcr, cmd);
249 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
250 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
251 0x01, PINGPONG_BUFFER);
252 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
253 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
254 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
255 SD_TRANSFER_END | SD_STAT_IDLE,
256 SD_TRANSFER_END | SD_STAT_IDLE);
257
258 if (rsp_type == SD_RSP_TYPE_R2) {
259 /* Read data from ping-pong buffer */
260 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
261 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
262 } else if (rsp_type != SD_RSP_TYPE_R0) {
263 /* Read data from SD_CMDx registers */
264 for (i = SD_CMD0; i <= SD_CMD4; i++)
265 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
266 }
267
268 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
269
270 err = rtsx_pci_send_cmd(pcr, timeout);
271 if (err < 0) {
272 sd_print_debug_regs(host);
273 sd_clear_error(host);
274 dev_dbg(sdmmc_dev(host),
275 "rtsx_pci_send_cmd error (err = %d)\n", err);
276 goto out;
277 }
278
279 if (rsp_type == SD_RSP_TYPE_R0) {
280 err = 0;
281 goto out;
282 }
283
284 /* Eliminate returned value of CHECK_REG_CMD */
285 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
286
287 /* Check (Start,Transmission) bit of Response */
288 if ((ptr[0] & 0xC0) != 0) {
289 err = -EILSEQ;
290 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
291 goto out;
292 }
293
294 /* Check CRC7 */
295 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
296 if (ptr[stat_idx] & SD_CRC7_ERR) {
297 err = -EILSEQ;
298 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
299 goto out;
300 }
301 }
302
303 if (rsp_type == SD_RSP_TYPE_R2) {
304 /*
305 * The controller offloads the last byte {CRC-7, end bit 1'b1}
306 * of response type R2. Assign dummy CRC, 0, and end bit to the
307 * byte(ptr[16], goes into the LSB of resp[3] later).
308 */
309 ptr[16] = 1;
310
311 for (i = 0; i < 4; i++) {
312 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
313 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
314 i, cmd->resp[i]);
315 }
316 } else {
317 cmd->resp[0] = get_unaligned_be32(ptr + 1);
318 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
319 cmd->resp[0]);
320 }
321
322 out:
323 cmd->error = err;
324
325 if (err && clock_toggled)
326 rtsx_pci_write_register(pcr, SD_BUS_STAT,
327 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
328 }
329
330 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
331 u16 byte_cnt, u8 *buf, int buf_len, int timeout)
332 {
333 struct rtsx_pcr *pcr = host->pcr;
334 int err;
335 u8 trans_mode;
336
337 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
338 __func__, cmd->opcode, cmd->arg);
339
340 if (!buf)
341 buf_len = 0;
342
343 if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
344 trans_mode = SD_TM_AUTO_TUNING;
345 else
346 trans_mode = SD_TM_NORMAL_READ;
347
348 rtsx_pci_init_cmd(pcr);
349 sd_cmd_set_sd_cmd(pcr, cmd);
350 sd_cmd_set_data_len(pcr, 1, byte_cnt);
351 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
352 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
353 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
354 if (trans_mode != SD_TM_AUTO_TUNING)
355 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
356 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
357
358 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
359 0xFF, trans_mode | SD_TRANSFER_START);
360 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
361 SD_TRANSFER_END, SD_TRANSFER_END);
362
363 err = rtsx_pci_send_cmd(pcr, timeout);
364 if (err < 0) {
365 sd_print_debug_regs(host);
366 dev_dbg(sdmmc_dev(host),
367 "rtsx_pci_send_cmd fail (err = %d)\n", err);
368 return err;
369 }
370
371 if (buf && buf_len) {
372 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
373 if (err < 0) {
374 dev_dbg(sdmmc_dev(host),
375 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
376 return err;
377 }
378 }
379
380 return 0;
381 }
382
383 static int sd_write_data(struct realtek_pci_sdmmc *host,
384 struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
385 int timeout)
386 {
387 struct rtsx_pcr *pcr = host->pcr;
388 int err;
389
390 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
391 __func__, cmd->opcode, cmd->arg);
392
393 if (!buf)
394 buf_len = 0;
395
396 sd_send_cmd_get_rsp(host, cmd);
397 if (cmd->error)
398 return cmd->error;
399
400 if (buf && buf_len) {
401 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
402 if (err < 0) {
403 dev_dbg(sdmmc_dev(host),
404 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
405 return err;
406 }
407 }
408
409 rtsx_pci_init_cmd(pcr);
410 sd_cmd_set_data_len(pcr, 1, byte_cnt);
411 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
412 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
413 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
414 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
415 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
416 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
417 SD_TRANSFER_END, SD_TRANSFER_END);
418
419 err = rtsx_pci_send_cmd(pcr, timeout);
420 if (err < 0) {
421 sd_print_debug_regs(host);
422 dev_dbg(sdmmc_dev(host),
423 "rtsx_pci_send_cmd fail (err = %d)\n", err);
424 return err;
425 }
426
427 return 0;
428 }
429
430 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
431 struct mmc_request *mrq)
432 {
433 struct rtsx_pcr *pcr = host->pcr;
434 struct mmc_host *mmc = host->mmc;
435 struct mmc_card *card = mmc->card;
436 struct mmc_command *cmd = mrq->cmd;
437 struct mmc_data *data = mrq->data;
438 int uhs = mmc_card_uhs(card);
439 u8 cfg2 = 0;
440 int err;
441 int resp_type;
442 size_t data_len = data->blksz * data->blocks;
443
444 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
445 __func__, cmd->opcode, cmd->arg);
446
447 resp_type = sd_response_type(cmd);
448 if (resp_type < 0)
449 return resp_type;
450
451 if (!uhs)
452 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
453
454 rtsx_pci_init_cmd(pcr);
455 sd_cmd_set_sd_cmd(pcr, cmd);
456 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
457 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
458 DMA_DONE_INT, DMA_DONE_INT);
459 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
460 0xFF, (u8)(data_len >> 24));
461 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
462 0xFF, (u8)(data_len >> 16));
463 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
464 0xFF, (u8)(data_len >> 8));
465 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
466 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
467 0x03 | DMA_PACK_SIZE_MASK,
468 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
469 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
470 0x01, RING_BUFFER);
471 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
472 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
473 SD_TRANSFER_START | SD_TM_AUTO_READ_2);
474 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
475 SD_TRANSFER_END, SD_TRANSFER_END);
476 rtsx_pci_send_cmd_no_wait(pcr);
477
478 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
479 if (err < 0) {
480 sd_print_debug_regs(host);
481 sd_clear_error(host);
482 return err;
483 }
484
485 return 0;
486 }
487
488 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
489 struct mmc_request *mrq)
490 {
491 struct rtsx_pcr *pcr = host->pcr;
492 struct mmc_host *mmc = host->mmc;
493 struct mmc_card *card = mmc->card;
494 struct mmc_command *cmd = mrq->cmd;
495 struct mmc_data *data = mrq->data;
496 int uhs = mmc_card_uhs(card);
497 u8 cfg2;
498 int err;
499 size_t data_len = data->blksz * data->blocks;
500
501 sd_send_cmd_get_rsp(host, cmd);
502 if (cmd->error)
503 return cmd->error;
504
505 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
506 __func__, cmd->opcode, cmd->arg);
507
508 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
509 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
510
511 if (!uhs)
512 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
513
514 rtsx_pci_init_cmd(pcr);
515 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
516 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
517 DMA_DONE_INT, DMA_DONE_INT);
518 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
519 0xFF, (u8)(data_len >> 24));
520 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
521 0xFF, (u8)(data_len >> 16));
522 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
523 0xFF, (u8)(data_len >> 8));
524 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
525 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
526 0x03 | DMA_PACK_SIZE_MASK,
527 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
528 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
529 0x01, RING_BUFFER);
530 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
531 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
532 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
533 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
534 SD_TRANSFER_END, SD_TRANSFER_END);
535 rtsx_pci_send_cmd_no_wait(pcr);
536 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
537 if (err < 0) {
538 sd_clear_error(host);
539 return err;
540 }
541
542 return 0;
543 }
544
545 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
546 {
547 struct mmc_data *data = mrq->data;
548
549 if (host->sg_count < 0) {
550 data->error = host->sg_count;
551 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
552 __func__, host->sg_count);
553 return data->error;
554 }
555
556 if (data->flags & MMC_DATA_READ)
557 return sd_read_long_data(host, mrq);
558
559 return sd_write_long_data(host, mrq);
560 }
561
562 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
563 {
564 rtsx_pci_write_register(host->pcr, SD_CFG1,
565 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
566 }
567
568 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
569 {
570 rtsx_pci_write_register(host->pcr, SD_CFG1,
571 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
572 }
573
574 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
575 struct mmc_request *mrq)
576 {
577 struct mmc_command *cmd = mrq->cmd;
578 struct mmc_data *data = mrq->data;
579 u8 *buf;
580
581 buf = kzalloc(data->blksz, GFP_NOIO);
582 if (!buf) {
583 cmd->error = -ENOMEM;
584 return;
585 }
586
587 if (data->flags & MMC_DATA_READ) {
588 if (host->initial_mode)
589 sd_disable_initial_mode(host);
590
591 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
592 data->blksz, 200);
593
594 if (host->initial_mode)
595 sd_enable_initial_mode(host);
596
597 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
598 } else {
599 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
600
601 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
602 data->blksz, 200);
603 }
604
605 kfree(buf);
606 }
607
608 static int sd_change_phase(struct realtek_pci_sdmmc *host,
609 u8 sample_point, bool rx)
610 {
611 struct rtsx_pcr *pcr = host->pcr;
612 u16 SD_VP_CTL = 0;
613 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
614 __func__, rx ? "RX" : "TX", sample_point);
615
616 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
617 if (rx) {
618 SD_VP_CTL = SD_VPRX_CTL;
619 rtsx_pci_write_register(pcr, SD_VPRX_CTL,
620 PHASE_SELECT_MASK, sample_point);
621 } else {
622 SD_VP_CTL = SD_VPTX_CTL;
623 rtsx_pci_write_register(pcr, SD_VPTX_CTL,
624 PHASE_SELECT_MASK, sample_point);
625 }
626 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
627 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
628 PHASE_NOT_RESET);
629 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
630 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
631
632 return 0;
633 }
634
635 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
636 {
637 bit %= RTSX_PHASE_MAX;
638 return phase_map & (1 << bit);
639 }
640
641 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
642 {
643 int i;
644
645 for (i = 0; i < RTSX_PHASE_MAX; i++) {
646 if (test_phase_bit(phase_map, start_bit + i) == 0)
647 return i;
648 }
649 return RTSX_PHASE_MAX;
650 }
651
652 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
653 {
654 int start = 0, len = 0;
655 int start_final = 0, len_final = 0;
656 u8 final_phase = 0xFF;
657
658 if (phase_map == 0) {
659 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
660 return final_phase;
661 }
662
663 while (start < RTSX_PHASE_MAX) {
664 len = sd_get_phase_len(phase_map, start);
665 if (len_final < len) {
666 start_final = start;
667 len_final = len;
668 }
669 start += len ? len : 1;
670 }
671
672 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
673 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
674 phase_map, len_final, final_phase);
675
676 return final_phase;
677 }
678
679 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
680 {
681 int i;
682 u8 val = 0;
683
684 for (i = 0; i < 100; i++) {
685 rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
686 if (val & SD_DATA_IDLE)
687 return;
688
689 udelay(100);
690 }
691 }
692
693 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
694 u8 opcode, u8 sample_point)
695 {
696 int err;
697 struct mmc_command cmd = {};
698 struct rtsx_pcr *pcr = host->pcr;
699
700 sd_change_phase(host, sample_point, true);
701
702 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
703 SD_RSP_80CLK_TIMEOUT_EN);
704
705 cmd.opcode = opcode;
706 err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
707 if (err < 0) {
708 /* Wait till SD DATA IDLE */
709 sd_wait_data_idle(host);
710 sd_clear_error(host);
711 rtsx_pci_write_register(pcr, SD_CFG3,
712 SD_RSP_80CLK_TIMEOUT_EN, 0);
713 return err;
714 }
715
716 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
717 return 0;
718 }
719
720 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
721 u8 opcode, u32 *phase_map)
722 {
723 int err, i;
724 u32 raw_phase_map = 0;
725
726 for (i = 0; i < RTSX_PHASE_MAX; i++) {
727 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
728 if (err == 0)
729 raw_phase_map |= 1 << i;
730 }
731
732 if (phase_map)
733 *phase_map = raw_phase_map;
734
735 return 0;
736 }
737
738 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
739 {
740 int err, i;
741 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
742 u8 final_phase;
743
744 for (i = 0; i < RX_TUNING_CNT; i++) {
745 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
746 if (err < 0)
747 return err;
748
749 if (raw_phase_map[i] == 0)
750 break;
751 }
752
753 phase_map = 0xFFFFFFFF;
754 for (i = 0; i < RX_TUNING_CNT; i++) {
755 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
756 i, raw_phase_map[i]);
757 phase_map &= raw_phase_map[i];
758 }
759 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
760
761 if (phase_map) {
762 final_phase = sd_search_final_phase(host, phase_map);
763 if (final_phase == 0xFF)
764 return -EINVAL;
765
766 err = sd_change_phase(host, final_phase, true);
767 if (err < 0)
768 return err;
769 } else {
770 return -EINVAL;
771 }
772
773 return 0;
774 }
775
776 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
777 struct mmc_data *data)
778 {
779 return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
780 }
781
782 static inline int sd_rw_cmd(struct mmc_command *cmd)
783 {
784 return mmc_op_multi(cmd->opcode) ||
785 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
786 (cmd->opcode == MMC_WRITE_BLOCK);
787 }
788
789 static void sd_request(struct work_struct *work)
790 {
791 struct realtek_pci_sdmmc *host = container_of(work,
792 struct realtek_pci_sdmmc, work);
793 struct rtsx_pcr *pcr = host->pcr;
794
795 struct mmc_host *mmc = host->mmc;
796 struct mmc_request *mrq = host->mrq;
797 struct mmc_command *cmd = mrq->cmd;
798 struct mmc_data *data = mrq->data;
799
800 unsigned int data_size = 0;
801 int err;
802
803 if (host->eject || !sd_get_cd_int(host)) {
804 cmd->error = -ENOMEDIUM;
805 goto finish;
806 }
807
808 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
809 if (err) {
810 cmd->error = err;
811 goto finish;
812 }
813
814 mutex_lock(&pcr->pcr_mutex);
815
816 rtsx_pci_start_run(pcr);
817
818 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
819 host->initial_mode, host->double_clk, host->vpclk);
820 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
821 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
822 CARD_SHARE_MASK, CARD_SHARE_48_SD);
823
824 mutex_lock(&host->host_mutex);
825 host->mrq = mrq;
826 mutex_unlock(&host->host_mutex);
827
828 if (mrq->data)
829 data_size = data->blocks * data->blksz;
830
831 if (!data_size) {
832 sd_send_cmd_get_rsp(host, cmd);
833 } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
834 cmd->error = sd_rw_multi(host, mrq);
835 if (!host->using_cookie)
836 sdmmc_post_req(host->mmc, host->mrq, 0);
837
838 if (mmc_op_multi(cmd->opcode) && mrq->stop)
839 sd_send_cmd_get_rsp(host, mrq->stop);
840 } else {
841 sd_normal_rw(host, mrq);
842 }
843
844 if (mrq->data) {
845 if (cmd->error || data->error)
846 data->bytes_xfered = 0;
847 else
848 data->bytes_xfered = data->blocks * data->blksz;
849 }
850
851 mutex_unlock(&pcr->pcr_mutex);
852
853 finish:
854 if (cmd->error) {
855 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
856 cmd->opcode, cmd->arg, cmd->error);
857 }
858
859 mutex_lock(&host->host_mutex);
860 host->mrq = NULL;
861 mutex_unlock(&host->host_mutex);
862
863 mmc_request_done(mmc, mrq);
864 }
865
866 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
867 {
868 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
869 struct mmc_data *data = mrq->data;
870
871 mutex_lock(&host->host_mutex);
872 host->mrq = mrq;
873 mutex_unlock(&host->host_mutex);
874
875 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
876 host->using_cookie = sd_pre_dma_transfer(host, data, false);
877
878 schedule_work(&host->work);
879 }
880
881 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
882 unsigned char bus_width)
883 {
884 int err = 0;
885 u8 width[] = {
886 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
887 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
888 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
889 };
890
891 if (bus_width <= MMC_BUS_WIDTH_8)
892 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
893 0x03, width[bus_width]);
894
895 return err;
896 }
897
898 static int sd_power_on(struct realtek_pci_sdmmc *host)
899 {
900 struct rtsx_pcr *pcr = host->pcr;
901 struct mmc_host *mmc = host->mmc;
902 int err;
903 u32 val;
904 u8 test_mode;
905
906 if (host->power_state == SDMMC_POWER_ON)
907 return 0;
908
909 rtsx_pci_init_cmd(pcr);
910 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
911 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
912 CARD_SHARE_MASK, CARD_SHARE_48_SD);
913 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
914 SD_CLK_EN, SD_CLK_EN);
915 err = rtsx_pci_send_cmd(pcr, 100);
916 if (err < 0)
917 return err;
918
919 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
920 if (err < 0)
921 return err;
922
923 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
924 if (err < 0)
925 return err;
926
927 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
928 if (err < 0)
929 return err;
930
931 if (PCI_PID(pcr) == PID_5261) {
932 /*
933 * If test mode is set switch to SD Express mandatorily,
934 * this is only for factory testing.
935 */
936 rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode);
937 if (test_mode & RTS5261_FW_EXPRESS_TEST_MASK) {
938 sdmmc_init_sd_express(mmc, NULL);
939 return 0;
940 }
941 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
942 mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V;
943 /*
944 * HW read wp status when resuming from S3/S4,
945 * and then picks SD legacy interface if it's set
946 * in read-only mode.
947 */
948 val = rtsx_pci_readl(pcr, RTSX_BIPR);
949 if (val & SD_WRITE_PROTECT) {
950 pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS;
951 mmc->caps2 &= ~(MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V);
952 }
953 }
954
955 host->power_state = SDMMC_POWER_ON;
956 return 0;
957 }
958
959 static int sd_power_off(struct realtek_pci_sdmmc *host)
960 {
961 struct rtsx_pcr *pcr = host->pcr;
962 int err;
963
964 host->power_state = SDMMC_POWER_OFF;
965
966 rtsx_pci_init_cmd(pcr);
967
968 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
969 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
970
971 err = rtsx_pci_send_cmd(pcr, 100);
972 if (err < 0)
973 return err;
974
975 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
976 if (err < 0)
977 return err;
978
979 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
980 }
981
982 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
983 unsigned char power_mode)
984 {
985 int err;
986
987 if (power_mode == MMC_POWER_OFF)
988 err = sd_power_off(host);
989 else
990 err = sd_power_on(host);
991
992 return err;
993 }
994
995 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
996 {
997 struct rtsx_pcr *pcr = host->pcr;
998 int err = 0;
999
1000 rtsx_pci_init_cmd(pcr);
1001
1002 switch (timing) {
1003 case MMC_TIMING_UHS_SDR104:
1004 case MMC_TIMING_UHS_SDR50:
1005 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1006 0x0C | SD_ASYNC_FIFO_NOT_RST,
1007 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
1008 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1009 CLK_LOW_FREQ, CLK_LOW_FREQ);
1010 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1011 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1012 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1013 break;
1014
1015 case MMC_TIMING_MMC_DDR52:
1016 case MMC_TIMING_UHS_DDR50:
1017 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1018 0x0C | SD_ASYNC_FIFO_NOT_RST,
1019 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1020 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1021 CLK_LOW_FREQ, CLK_LOW_FREQ);
1022 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1023 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1025 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1026 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1027 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1028 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1029 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1030 break;
1031
1032 case MMC_TIMING_MMC_HS:
1033 case MMC_TIMING_SD_HS:
1034 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1035 0x0C, SD_20_MODE);
1036 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1037 CLK_LOW_FREQ, CLK_LOW_FREQ);
1038 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1039 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1040 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1041 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1042 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1043 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1044 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1045 break;
1046
1047 default:
1048 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1049 SD_CFG1, 0x0C, SD_20_MODE);
1050 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1051 CLK_LOW_FREQ, CLK_LOW_FREQ);
1052 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1053 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1054 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1055 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1056 SD_PUSH_POINT_CTL, 0xFF, 0);
1057 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1058 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1059 break;
1060 }
1061
1062 err = rtsx_pci_send_cmd(pcr, 100);
1063
1064 return err;
1065 }
1066
1067 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1068 {
1069 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1070 struct rtsx_pcr *pcr = host->pcr;
1071
1072 if (host->eject)
1073 return;
1074
1075 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1076 return;
1077
1078 mutex_lock(&pcr->pcr_mutex);
1079
1080 rtsx_pci_start_run(pcr);
1081
1082 sd_set_bus_width(host, ios->bus_width);
1083 sd_set_power_mode(host, ios->power_mode);
1084 sd_set_timing(host, ios->timing);
1085
1086 host->vpclk = false;
1087 host->double_clk = true;
1088
1089 switch (ios->timing) {
1090 case MMC_TIMING_UHS_SDR104:
1091 case MMC_TIMING_UHS_SDR50:
1092 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1093 host->vpclk = true;
1094 host->double_clk = false;
1095 break;
1096 case MMC_TIMING_MMC_DDR52:
1097 case MMC_TIMING_UHS_DDR50:
1098 case MMC_TIMING_UHS_SDR25:
1099 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1100 break;
1101 default:
1102 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1103 break;
1104 }
1105
1106 host->initial_mode = (ios->clock <= 1000000) ? true : false;
1107
1108 host->clock = ios->clock;
1109 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1110 host->initial_mode, host->double_clk, host->vpclk);
1111
1112 mutex_unlock(&pcr->pcr_mutex);
1113 }
1114
1115 static int sdmmc_get_ro(struct mmc_host *mmc)
1116 {
1117 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1118 struct rtsx_pcr *pcr = host->pcr;
1119 int ro = 0;
1120 u32 val;
1121
1122 if (host->eject)
1123 return -ENOMEDIUM;
1124
1125 mutex_lock(&pcr->pcr_mutex);
1126
1127 rtsx_pci_start_run(pcr);
1128
1129 /* Check SD mechanical write-protect switch */
1130 val = rtsx_pci_readl(pcr, RTSX_BIPR);
1131 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1132 if (val & SD_WRITE_PROTECT)
1133 ro = 1;
1134
1135 mutex_unlock(&pcr->pcr_mutex);
1136
1137 return ro;
1138 }
1139
1140 static int sdmmc_get_cd(struct mmc_host *mmc)
1141 {
1142 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1143 struct rtsx_pcr *pcr = host->pcr;
1144 int cd = 0;
1145 u32 val;
1146
1147 if (host->eject)
1148 return cd;
1149
1150 mutex_lock(&pcr->pcr_mutex);
1151
1152 rtsx_pci_start_run(pcr);
1153
1154 /* Check SD card detect */
1155 val = rtsx_pci_card_exist(pcr);
1156 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1157 if (val & SD_EXIST)
1158 cd = 1;
1159
1160 mutex_unlock(&pcr->pcr_mutex);
1161
1162 return cd;
1163 }
1164
1165 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1166 {
1167 struct rtsx_pcr *pcr = host->pcr;
1168 int err;
1169 u8 stat;
1170
1171 /* Reference to Signal Voltage Switch Sequence in SD spec.
1172 * Wait for a period of time so that the card can drive SD_CMD and
1173 * SD_DAT[3:0] to low after sending back CMD11 response.
1174 */
1175 mdelay(1);
1176
1177 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1178 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1179 * abort the voltage switch sequence;
1180 */
1181 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1182 if (err < 0)
1183 return err;
1184
1185 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1186 SD_DAT1_STATUS | SD_DAT0_STATUS))
1187 return -EINVAL;
1188
1189 /* Stop toggle SD clock */
1190 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1191 0xFF, SD_CLK_FORCE_STOP);
1192 if (err < 0)
1193 return err;
1194
1195 return 0;
1196 }
1197
1198 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1199 {
1200 struct rtsx_pcr *pcr = host->pcr;
1201 int err;
1202 u8 stat, mask, val;
1203
1204 /* Wait 1.8V output of voltage regulator in card stable */
1205 msleep(50);
1206
1207 /* Toggle SD clock again */
1208 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1209 if (err < 0)
1210 return err;
1211
1212 /* Wait for a period of time so that the card can drive
1213 * SD_DAT[3:0] to high at 1.8V
1214 */
1215 msleep(20);
1216
1217 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1218 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1219 if (err < 0)
1220 return err;
1221
1222 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1223 SD_DAT1_STATUS | SD_DAT0_STATUS;
1224 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1225 SD_DAT1_STATUS | SD_DAT0_STATUS;
1226 if ((stat & mask) != val) {
1227 dev_dbg(sdmmc_dev(host),
1228 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1229 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1230 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1231 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1232 return -EINVAL;
1233 }
1234
1235 return 0;
1236 }
1237
1238 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1239 {
1240 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1241 struct rtsx_pcr *pcr = host->pcr;
1242 int err = 0;
1243 u8 voltage;
1244
1245 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1246 __func__, ios->signal_voltage);
1247
1248 if (host->eject)
1249 return -ENOMEDIUM;
1250
1251 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1252 if (err)
1253 return err;
1254
1255 mutex_lock(&pcr->pcr_mutex);
1256
1257 rtsx_pci_start_run(pcr);
1258
1259 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1260 voltage = OUTPUT_3V3;
1261 else
1262 voltage = OUTPUT_1V8;
1263
1264 if (voltage == OUTPUT_1V8) {
1265 err = sd_wait_voltage_stable_1(host);
1266 if (err < 0)
1267 goto out;
1268 }
1269
1270 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1271 if (err < 0)
1272 goto out;
1273
1274 if (voltage == OUTPUT_1V8) {
1275 err = sd_wait_voltage_stable_2(host);
1276 if (err < 0)
1277 goto out;
1278 }
1279
1280 out:
1281 /* Stop toggle SD clock in idle */
1282 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1283 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1284
1285 mutex_unlock(&pcr->pcr_mutex);
1286
1287 return err;
1288 }
1289
1290 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1291 {
1292 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1293 struct rtsx_pcr *pcr = host->pcr;
1294 int err = 0;
1295
1296 if (host->eject)
1297 return -ENOMEDIUM;
1298
1299 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1300 if (err)
1301 return err;
1302
1303 mutex_lock(&pcr->pcr_mutex);
1304
1305 rtsx_pci_start_run(pcr);
1306
1307 /* Set initial TX phase */
1308 switch (mmc->ios.timing) {
1309 case MMC_TIMING_UHS_SDR104:
1310 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1311 break;
1312
1313 case MMC_TIMING_UHS_SDR50:
1314 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1315 break;
1316
1317 case MMC_TIMING_UHS_DDR50:
1318 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1319 break;
1320
1321 default:
1322 err = 0;
1323 }
1324
1325 if (err)
1326 goto out;
1327
1328 /* Tuning RX phase */
1329 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1330 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1331 err = sd_tuning_rx(host, opcode);
1332 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1333 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1334
1335 out:
1336 mutex_unlock(&pcr->pcr_mutex);
1337
1338 return err;
1339 }
1340
1341 static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
1342 {
1343 u32 relink_time;
1344 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1345 struct rtsx_pcr *pcr = host->pcr;
1346
1347 /* Set relink_time for changing to PCIe card */
1348 relink_time = 0x8FFF;
1349
1350 rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time);
1351 rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8);
1352 rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16);
1353
1354 rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80);
1355 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
1356 RTS5261_LDO1_OCP_THD_MASK,
1357 pcr->option.sd_800mA_ocp_thd);
1358
1359 if (pcr->ops->disable_auto_blink)
1360 pcr->ops->disable_auto_blink(pcr);
1361
1362 /* For PCIe/NVMe mode can't enter delink issue */
1363 pcr->hw_param.interrupt_en &= ~(SD_INT_EN);
1364 rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en);
1365
1366 rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
1367 RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN);
1368 rtsx_pci_write_register(pcr, RTS5261_FW_CFG0,
1369 RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS);
1370 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1371 RTS5261_MCU_CLOCK_GATING, RTS5261_MCU_CLOCK_GATING);
1372 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1373 RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK
1374 | RTS5261_DRIVER_ENABLE_FW,
1375 RTS5261_MCU_CLOCK_SEL_16M | RTS5261_DRIVER_ENABLE_FW);
1376 host->eject = true;
1377 return 0;
1378 }
1379
1380 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1381 .pre_req = sdmmc_pre_req,
1382 .post_req = sdmmc_post_req,
1383 .request = sdmmc_request,
1384 .set_ios = sdmmc_set_ios,
1385 .get_ro = sdmmc_get_ro,
1386 .get_cd = sdmmc_get_cd,
1387 .start_signal_voltage_switch = sdmmc_switch_voltage,
1388 .execute_tuning = sdmmc_execute_tuning,
1389 .init_sd_express = sdmmc_init_sd_express,
1390 };
1391
1392 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1393 {
1394 struct mmc_host *mmc = host->mmc;
1395 struct rtsx_pcr *pcr = host->pcr;
1396
1397 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1398
1399 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1400 mmc->caps |= MMC_CAP_UHS_SDR50;
1401 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1402 mmc->caps |= MMC_CAP_UHS_SDR104;
1403 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1404 mmc->caps |= MMC_CAP_UHS_DDR50;
1405 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1406 mmc->caps |= MMC_CAP_1_8V_DDR;
1407 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1408 mmc->caps |= MMC_CAP_8_BIT_DATA;
1409 if (pcr->extra_caps & EXTRA_CAPS_NO_MMC)
1410 mmc->caps2 |= MMC_CAP2_NO_MMC;
1411 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
1412 mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V;
1413 }
1414
1415 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1416 {
1417 struct mmc_host *mmc = host->mmc;
1418 struct rtsx_pcr *pcr = host->pcr;
1419
1420 mmc->f_min = 250000;
1421 mmc->f_max = 208000000;
1422 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1423 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1424 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1425 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1426 if (pcr->rtd3_en)
1427 mmc->caps = mmc->caps | MMC_CAP_AGGRESSIVE_PM;
1428 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1429 mmc->max_current_330 = 400;
1430 mmc->max_current_180 = 800;
1431 mmc->ops = &realtek_pci_sdmmc_ops;
1432
1433 init_extra_caps(host);
1434
1435 mmc->max_segs = 256;
1436 mmc->max_seg_size = 65536;
1437 mmc->max_blk_size = 512;
1438 mmc->max_blk_count = 65535;
1439 mmc->max_req_size = 524288;
1440 }
1441
1442 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1443 {
1444 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1445
1446 host->cookie = -1;
1447 mmc_detect_change(host->mmc, 0);
1448 }
1449
1450 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1451 {
1452 struct mmc_host *mmc;
1453 struct realtek_pci_sdmmc *host;
1454 struct rtsx_pcr *pcr;
1455 struct pcr_handle *handle = pdev->dev.platform_data;
1456
1457 if (!handle)
1458 return -ENXIO;
1459
1460 pcr = handle->pcr;
1461 if (!pcr)
1462 return -ENXIO;
1463
1464 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1465
1466 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1467 if (!mmc)
1468 return -ENOMEM;
1469
1470 host = mmc_priv(mmc);
1471 host->pcr = pcr;
1472 host->mmc = mmc;
1473 host->pdev = pdev;
1474 host->cookie = -1;
1475 host->power_state = SDMMC_POWER_OFF;
1476 INIT_WORK(&host->work, sd_request);
1477 platform_set_drvdata(pdev, host);
1478 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1479 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1480
1481 mutex_init(&host->host_mutex);
1482
1483 realtek_init_host(host);
1484
1485 if (pcr->rtd3_en) {
1486 pm_runtime_set_autosuspend_delay(&pdev->dev, 5000);
1487 pm_runtime_use_autosuspend(&pdev->dev);
1488 pm_runtime_enable(&pdev->dev);
1489 }
1490
1491
1492 mmc_add_host(mmc);
1493
1494 return 0;
1495 }
1496
1497 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1498 {
1499 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1500 struct rtsx_pcr *pcr;
1501 struct mmc_host *mmc;
1502
1503 if (!host)
1504 return 0;
1505
1506 pcr = host->pcr;
1507 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1508 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1509 mmc = host->mmc;
1510
1511 if (pcr->rtd3_en) {
1512 pm_runtime_dont_use_autosuspend(&pdev->dev);
1513 pm_runtime_disable(&pdev->dev);
1514 }
1515
1516 cancel_work_sync(&host->work);
1517
1518 mutex_lock(&host->host_mutex);
1519 if (host->mrq) {
1520 dev_dbg(&(pdev->dev),
1521 "%s: Controller removed during transfer\n",
1522 mmc_hostname(mmc));
1523
1524 rtsx_pci_complete_unfinished_transfer(pcr);
1525
1526 host->mrq->cmd->error = -ENOMEDIUM;
1527 if (host->mrq->stop)
1528 host->mrq->stop->error = -ENOMEDIUM;
1529 mmc_request_done(mmc, host->mrq);
1530 }
1531 mutex_unlock(&host->host_mutex);
1532
1533 mmc_remove_host(mmc);
1534 host->eject = true;
1535
1536 flush_work(&host->work);
1537
1538 mmc_free_host(mmc);
1539
1540 dev_dbg(&(pdev->dev),
1541 ": Realtek PCI-E SDMMC controller has been removed\n");
1542
1543 return 0;
1544 }
1545
1546 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1547 {
1548 .name = DRV_NAME_RTSX_PCI_SDMMC,
1549 }, {
1550 /* sentinel */
1551 }
1552 };
1553 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1554
1555 static struct platform_driver rtsx_pci_sdmmc_driver = {
1556 .probe = rtsx_pci_sdmmc_drv_probe,
1557 .remove = rtsx_pci_sdmmc_drv_remove,
1558 .id_table = rtsx_pci_sdmmc_ids,
1559 .driver = {
1560 .name = DRV_NAME_RTSX_PCI_SDMMC,
1561 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1562 },
1563 };
1564 module_platform_driver(rtsx_pci_sdmmc_driver);
1565
1566 MODULE_LICENSE("GPL");
1567 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1568 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
Linux with added FPC-III support