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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / mmc / host / s3cmci.c
bloba33a7823c265565249002c62f6d7ee8e3ba5488d
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
4 *
5 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
6 *
7 * Current driver maintained by Ben Dooks and Simtec Electronics
8 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
9 */
10
11 #include <linux/module.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/clk.h>
15 #include <linux/mmc/host.h>
16 #include <linux/platform_device.h>
17 #include <linux/cpufreq.h>
18 #include <linux/debugfs.h>
19 #include <linux/seq_file.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/io.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/mmc/slot-gpio.h>
27 #include <linux/platform_data/mmc-s3cmci.h>
28
29 #include "s3cmci.h"
30
31 #define DRIVER_NAME "s3c-mci"
32
33 #define S3C2410_SDICON (0x00)
34 #define S3C2410_SDIPRE (0x04)
35 #define S3C2410_SDICMDARG (0x08)
36 #define S3C2410_SDICMDCON (0x0C)
37 #define S3C2410_SDICMDSTAT (0x10)
38 #define S3C2410_SDIRSP0 (0x14)
39 #define S3C2410_SDIRSP1 (0x18)
40 #define S3C2410_SDIRSP2 (0x1C)
41 #define S3C2410_SDIRSP3 (0x20)
42 #define S3C2410_SDITIMER (0x24)
43 #define S3C2410_SDIBSIZE (0x28)
44 #define S3C2410_SDIDCON (0x2C)
45 #define S3C2410_SDIDCNT (0x30)
46 #define S3C2410_SDIDSTA (0x34)
47 #define S3C2410_SDIFSTA (0x38)
48
49 #define S3C2410_SDIDATA (0x3C)
50 #define S3C2410_SDIIMSK (0x40)
51
52 #define S3C2440_SDIDATA (0x40)
53 #define S3C2440_SDIIMSK (0x3C)
54
55 #define S3C2440_SDICON_SDRESET (1 << 8)
56 #define S3C2410_SDICON_SDIOIRQ (1 << 3)
57 #define S3C2410_SDICON_FIFORESET (1 << 1)
58 #define S3C2410_SDICON_CLOCKTYPE (1 << 0)
59
60 #define S3C2410_SDICMDCON_LONGRSP (1 << 10)
61 #define S3C2410_SDICMDCON_WAITRSP (1 << 9)
62 #define S3C2410_SDICMDCON_CMDSTART (1 << 8)
63 #define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
64 #define S3C2410_SDICMDCON_INDEX (0x3f)
65
66 #define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
67 #define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
68 #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
69 #define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
70
71 #define S3C2440_SDIDCON_DS_WORD (2 << 22)
72 #define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
73 #define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
74 #define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
75 #define S3C2410_SDIDCON_WIDEBUS (1 << 16)
76 #define S3C2410_SDIDCON_DMAEN (1 << 15)
77 #define S3C2410_SDIDCON_STOP (1 << 14)
78 #define S3C2440_SDIDCON_DATSTART (1 << 14)
79
80 #define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
81 #define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
82
83 #define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
84
85 #define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9)
86 #define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
87 #define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
88 #define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
89 #define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
90 #define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
91 #define S3C2410_SDIDSTA_TXDATAON (1 << 1)
92 #define S3C2410_SDIDSTA_RXDATAON (1 << 0)
93
94 #define S3C2440_SDIFSTA_FIFORESET (1 << 16)
95 #define S3C2440_SDIFSTA_FIFOFAIL (3 << 14)
96 #define S3C2410_SDIFSTA_TFDET (1 << 13)
97 #define S3C2410_SDIFSTA_RFDET (1 << 12)
98 #define S3C2410_SDIFSTA_COUNTMASK (0x7f)
99
100 #define S3C2410_SDIIMSK_RESPONSECRC (1 << 17)
101 #define S3C2410_SDIIMSK_CMDSENT (1 << 16)
102 #define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15)
103 #define S3C2410_SDIIMSK_RESPONSEND (1 << 14)
104 #define S3C2410_SDIIMSK_SDIOIRQ (1 << 12)
105 #define S3C2410_SDIIMSK_FIFOFAIL (1 << 11)
106 #define S3C2410_SDIIMSK_CRCSTATUS (1 << 10)
107 #define S3C2410_SDIIMSK_DATACRC (1 << 9)
108 #define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8)
109 #define S3C2410_SDIIMSK_DATAFINISH (1 << 7)
110 #define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4)
111 #define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2)
112 #define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0)
113
114 enum dbg_channels {
115 dbg_err = (1 << 0),
116 dbg_debug = (1 << 1),
117 dbg_info = (1 << 2),
118 dbg_irq = (1 << 3),
119 dbg_sg = (1 << 4),
120 dbg_dma = (1 << 5),
121 dbg_pio = (1 << 6),
122 dbg_fail = (1 << 7),
123 dbg_conf = (1 << 8),
124 };
125
126 static const int dbgmap_err = dbg_fail;
127 static const int dbgmap_info = dbg_info | dbg_conf;
128 static const int dbgmap_debug = dbg_err | dbg_debug;
129
130 #define dbg(host, channels, args...) \
131 do { \
132 if (dbgmap_err & channels) \
133 dev_err(&host->pdev->dev, args); \
134 else if (dbgmap_info & channels) \
135 dev_info(&host->pdev->dev, args); \
136 else if (dbgmap_debug & channels) \
137 dev_dbg(&host->pdev->dev, args); \
138 } while (0)
139
140 static void finalize_request(struct s3cmci_host *host);
141 static void s3cmci_send_request(struct mmc_host *mmc);
142 static void s3cmci_reset(struct s3cmci_host *host);
143
144 #ifdef CONFIG_MMC_DEBUG
145
146 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
147 {
148 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer;
149 u32 datcon, datcnt, datsta, fsta;
150
151 con = readl(host->base + S3C2410_SDICON);
152 pre = readl(host->base + S3C2410_SDIPRE);
153 cmdarg = readl(host->base + S3C2410_SDICMDARG);
154 cmdcon = readl(host->base + S3C2410_SDICMDCON);
155 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
156 r0 = readl(host->base + S3C2410_SDIRSP0);
157 r1 = readl(host->base + S3C2410_SDIRSP1);
158 r2 = readl(host->base + S3C2410_SDIRSP2);
159 r3 = readl(host->base + S3C2410_SDIRSP3);
160 timer = readl(host->base + S3C2410_SDITIMER);
161 datcon = readl(host->base + S3C2410_SDIDCON);
162 datcnt = readl(host->base + S3C2410_SDIDCNT);
163 datsta = readl(host->base + S3C2410_SDIDSTA);
164 fsta = readl(host->base + S3C2410_SDIFSTA);
165
166 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
167 prefix, con, pre, timer);
168
169 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
170 prefix, cmdcon, cmdarg, cmdsta);
171
172 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
173 " DSTA:[%08x] DCNT:[%08x]\n",
174 prefix, datcon, fsta, datsta, datcnt);
175
176 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
177 " R2:[%08x] R3:[%08x]\n",
178 prefix, r0, r1, r2, r3);
179 }
180
181 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
182 int stop)
183 {
184 snprintf(host->dbgmsg_cmd, 300,
185 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
186 host->ccnt, (stop ? " (STOP)" : ""),
187 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
188
189 if (cmd->data) {
190 snprintf(host->dbgmsg_dat, 300,
191 "#%u bsize:%u blocks:%u bytes:%u",
192 host->dcnt, cmd->data->blksz,
193 cmd->data->blocks,
194 cmd->data->blocks * cmd->data->blksz);
195 } else {
196 host->dbgmsg_dat[0] = '\0';
197 }
198 }
199
200 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
201 int fail)
202 {
203 unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
204
205 if (!cmd)
206 return;
207
208 if (cmd->error == 0) {
209 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
210 host->dbgmsg_cmd, cmd->resp[0]);
211 } else {
212 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
213 cmd->error, host->dbgmsg_cmd, host->status);
214 }
215
216 if (!cmd->data)
217 return;
218
219 if (cmd->data->error == 0) {
220 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
221 } else {
222 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
223 cmd->data->error, host->dbgmsg_dat,
224 readl(host->base + S3C2410_SDIDCNT));
225 }
226 }
227 #else
228 static void dbg_dumpcmd(struct s3cmci_host *host,
229 struct mmc_command *cmd, int fail) { }
230
231 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
232 int stop) { }
233
234 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
235
236 #endif /* CONFIG_MMC_DEBUG */
237
238 /**
239 * s3cmci_host_usedma - return whether the host is using dma or pio
240 * @host: The host state
241 *
242 * Return true if the host is using DMA to transfer data, else false
243 * to use PIO mode. Will return static data depending on the driver
244 * configuration.
245 */
246 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
247 {
248 #ifdef CONFIG_MMC_S3C_PIO
249 return false;
250 #else /* CONFIG_MMC_S3C_DMA */
251 return true;
252 #endif
253 }
254
255 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
256 {
257 u32 newmask;
258
259 newmask = readl(host->base + host->sdiimsk);
260 newmask |= imask;
261
262 writel(newmask, host->base + host->sdiimsk);
263
264 return newmask;
265 }
266
267 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
268 {
269 u32 newmask;
270
271 newmask = readl(host->base + host->sdiimsk);
272 newmask &= ~imask;
273
274 writel(newmask, host->base + host->sdiimsk);
275
276 return newmask;
277 }
278
279 static inline void clear_imask(struct s3cmci_host *host)
280 {
281 u32 mask = readl(host->base + host->sdiimsk);
282
283 /* preserve the SDIO IRQ mask state */
284 mask &= S3C2410_SDIIMSK_SDIOIRQ;
285 writel(mask, host->base + host->sdiimsk);
286 }
287
288 /**
289 * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
290 * @host: The host to check.
291 *
292 * Test to see if the SDIO interrupt is being signalled in case the
293 * controller has failed to re-detect a card interrupt. Read GPE8 and
294 * see if it is low and if so, signal a SDIO interrupt.
295 *
296 * This is currently called if a request is finished (we assume that the
297 * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
298 * already being indicated.
299 */
300 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
301 {
302 if (host->sdio_irqen) {
303 if (host->pdata->bus[3] &&
304 gpiod_get_value(host->pdata->bus[3]) == 0) {
305 pr_debug("%s: signalling irq\n", __func__);
306 mmc_signal_sdio_irq(host->mmc);
307 }
308 }
309 }
310
311 static inline int get_data_buffer(struct s3cmci_host *host,
312 u32 *bytes, u32 **pointer)
313 {
314 struct scatterlist *sg;
315
316 if (host->pio_active == XFER_NONE)
317 return -EINVAL;
318
319 if ((!host->mrq) || (!host->mrq->data))
320 return -EINVAL;
321
322 if (host->pio_sgptr >= host->mrq->data->sg_len) {
323 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
324 host->pio_sgptr, host->mrq->data->sg_len);
325 return -EBUSY;
326 }
327 sg = &host->mrq->data->sg[host->pio_sgptr];
328
329 *bytes = sg->length;
330 *pointer = sg_virt(sg);
331
332 host->pio_sgptr++;
333
334 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
335 host->pio_sgptr, host->mrq->data->sg_len);
336
337 return 0;
338 }
339
340 static inline u32 fifo_count(struct s3cmci_host *host)
341 {
342 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
343
344 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
345 return fifostat;
346 }
347
348 static inline u32 fifo_free(struct s3cmci_host *host)
349 {
350 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
351
352 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
353 return 63 - fifostat;
354 }
355
356 /**
357 * s3cmci_enable_irq - enable IRQ, after having disabled it.
358 * @host: The device state.
359 * @more: True if more IRQs are expected from transfer.
360 *
361 * Enable the main IRQ if needed after it has been disabled.
362 *
363 * The IRQ can be one of the following states:
364 * - disabled during IDLE
365 * - disabled whilst processing data
366 * - enabled during transfer
367 * - enabled whilst awaiting SDIO interrupt detection
368 */
369 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
370 {
371 unsigned long flags;
372 bool enable = false;
373
374 local_irq_save(flags);
375
376 host->irq_enabled = more;
377 host->irq_disabled = false;
378
379 enable = more | host->sdio_irqen;
380
381 if (host->irq_state != enable) {
382 host->irq_state = enable;
383
384 if (enable)
385 enable_irq(host->irq);
386 else
387 disable_irq(host->irq);
388 }
389
390 local_irq_restore(flags);
391 }
392
393 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
394 {
395 unsigned long flags;
396
397 local_irq_save(flags);
398
399 /* pr_debug("%s: transfer %d\n", __func__, transfer); */
400
401 host->irq_disabled = transfer;
402
403 if (transfer && host->irq_state) {
404 host->irq_state = false;
405 disable_irq(host->irq);
406 }
407
408 local_irq_restore(flags);
409 }
410
411 static void do_pio_read(struct s3cmci_host *host)
412 {
413 int res;
414 u32 fifo;
415 u32 *ptr;
416 u32 fifo_words;
417 void __iomem *from_ptr;
418
419 /* write real prescaler to host, it might be set slow to fix */
420 writel(host->prescaler, host->base + S3C2410_SDIPRE);
421
422 from_ptr = host->base + host->sdidata;
423
424 while ((fifo = fifo_count(host))) {
425 if (!host->pio_bytes) {
426 res = get_data_buffer(host, &host->pio_bytes,
427 &host->pio_ptr);
428 if (res) {
429 host->pio_active = XFER_NONE;
430 host->complete_what = COMPLETION_FINALIZE;
431
432 dbg(host, dbg_pio, "pio_read(): "
433 "complete (no more data).\n");
434 return;
435 }
436
437 dbg(host, dbg_pio,
438 "pio_read(): new target: [%i]@[%p]\n",
439 host->pio_bytes, host->pio_ptr);
440 }
441
442 dbg(host, dbg_pio,
443 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
444 fifo, host->pio_bytes,
445 readl(host->base + S3C2410_SDIDCNT));
446
447 /* If we have reached the end of the block, we can
448 * read a word and get 1 to 3 bytes. If we in the
449 * middle of the block, we have to read full words,
450 * otherwise we will write garbage, so round down to
451 * an even multiple of 4. */
452 if (fifo >= host->pio_bytes)
453 fifo = host->pio_bytes;
454 else
455 fifo -= fifo & 3;
456
457 host->pio_bytes -= fifo;
458 host->pio_count += fifo;
459
460 fifo_words = fifo >> 2;
461 ptr = host->pio_ptr;
462 while (fifo_words--)
463 *ptr++ = readl(from_ptr);
464 host->pio_ptr = ptr;
465
466 if (fifo & 3) {
467 u32 n = fifo & 3;
468 u32 data = readl(from_ptr);
469 u8 *p = (u8 *)host->pio_ptr;
470
471 while (n--) {
472 *p++ = data;
473 data >>= 8;
474 }
475 }
476 }
477
478 if (!host->pio_bytes) {
479 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
480 if (res) {
481 dbg(host, dbg_pio,
482 "pio_read(): complete (no more buffers).\n");
483 host->pio_active = XFER_NONE;
484 host->complete_what = COMPLETION_FINALIZE;
485
486 return;
487 }
488 }
489
490 enable_imask(host,
491 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
492 }
493
494 static void do_pio_write(struct s3cmci_host *host)
495 {
496 void __iomem *to_ptr;
497 int res;
498 u32 fifo;
499 u32 *ptr;
500
501 to_ptr = host->base + host->sdidata;
502
503 while ((fifo = fifo_free(host)) > 3) {
504 if (!host->pio_bytes) {
505 res = get_data_buffer(host, &host->pio_bytes,
506 &host->pio_ptr);
507 if (res) {
508 dbg(host, dbg_pio,
509 "pio_write(): complete (no more data).\n");
510 host->pio_active = XFER_NONE;
511
512 return;
513 }
514
515 dbg(host, dbg_pio,
516 "pio_write(): new source: [%i]@[%p]\n",
517 host->pio_bytes, host->pio_ptr);
518
519 }
520
521 /* If we have reached the end of the block, we have to
522 * write exactly the remaining number of bytes. If we
523 * in the middle of the block, we have to write full
524 * words, so round down to an even multiple of 4. */
525 if (fifo >= host->pio_bytes)
526 fifo = host->pio_bytes;
527 else
528 fifo -= fifo & 3;
529
530 host->pio_bytes -= fifo;
531 host->pio_count += fifo;
532
533 fifo = (fifo + 3) >> 2;
534 ptr = host->pio_ptr;
535 while (fifo--)
536 writel(*ptr++, to_ptr);
537 host->pio_ptr = ptr;
538 }
539
540 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
541 }
542
543 static void pio_tasklet(unsigned long data)
544 {
545 struct s3cmci_host *host = (struct s3cmci_host *) data;
546
547 s3cmci_disable_irq(host, true);
548
549 if (host->pio_active == XFER_WRITE)
550 do_pio_write(host);
551
552 if (host->pio_active == XFER_READ)
553 do_pio_read(host);
554
555 if (host->complete_what == COMPLETION_FINALIZE) {
556 clear_imask(host);
557 if (host->pio_active != XFER_NONE) {
558 dbg(host, dbg_err, "unfinished %s "
559 "- pio_count:[%u] pio_bytes:[%u]\n",
560 (host->pio_active == XFER_READ) ? "read" : "write",
561 host->pio_count, host->pio_bytes);
562
563 if (host->mrq->data)
564 host->mrq->data->error = -EINVAL;
565 }
566
567 s3cmci_enable_irq(host, false);
568 finalize_request(host);
569 } else
570 s3cmci_enable_irq(host, true);
571 }
572
573 /*
574 * ISR for SDI Interface IRQ
575 * Communication between driver and ISR works as follows:
576 * host->mrq points to current request
577 * host->complete_what Indicates when the request is considered done
578 * COMPLETION_CMDSENT when the command was sent
579 * COMPLETION_RSPFIN when a response was received
580 * COMPLETION_XFERFINISH when the data transfer is finished
581 * COMPLETION_XFERFINISH_RSPFIN both of the above.
582 * host->complete_request is the completion-object the driver waits for
583 *
584 * 1) Driver sets up host->mrq and host->complete_what
585 * 2) Driver prepares the transfer
586 * 3) Driver enables interrupts
587 * 4) Driver starts transfer
588 * 5) Driver waits for host->complete_rquest
589 * 6) ISR checks for request status (errors and success)
590 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
591 * 7) ISR completes host->complete_request
592 * 8) ISR disables interrupts
593 * 9) Driver wakes up and takes care of the request
594 *
595 * Note: "->error"-fields are expected to be set to 0 before the request
596 * was issued by mmc.c - therefore they are only set, when an error
597 * contition comes up
598 */
599
600 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
601 {
602 struct s3cmci_host *host = dev_id;
603 struct mmc_command *cmd;
604 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
605 u32 mci_cclear = 0, mci_dclear;
606 unsigned long iflags;
607
608 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
609 mci_imsk = readl(host->base + host->sdiimsk);
610
611 if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
612 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
613 mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
614 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
615
616 mmc_signal_sdio_irq(host->mmc);
617 return IRQ_HANDLED;
618 }
619 }
620
621 spin_lock_irqsave(&host->complete_lock, iflags);
622
623 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
624 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
625 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
626 mci_dclear = 0;
627
628 if ((host->complete_what == COMPLETION_NONE) ||
629 (host->complete_what == COMPLETION_FINALIZE)) {
630 host->status = "nothing to complete";
631 clear_imask(host);
632 goto irq_out;
633 }
634
635 if (!host->mrq) {
636 host->status = "no active mrq";
637 clear_imask(host);
638 goto irq_out;
639 }
640
641 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
642
643 if (!cmd) {
644 host->status = "no active cmd";
645 clear_imask(host);
646 goto irq_out;
647 }
648
649 if (!s3cmci_host_usedma(host)) {
650 if ((host->pio_active == XFER_WRITE) &&
651 (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
652
653 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
654 tasklet_schedule(&host->pio_tasklet);
655 host->status = "pio tx";
656 }
657
658 if ((host->pio_active == XFER_READ) &&
659 (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
660
661 disable_imask(host,
662 S3C2410_SDIIMSK_RXFIFOHALF |
663 S3C2410_SDIIMSK_RXFIFOLAST);
664
665 tasklet_schedule(&host->pio_tasklet);
666 host->status = "pio rx";
667 }
668 }
669
670 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
671 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
672 cmd->error = -ETIMEDOUT;
673 host->status = "error: command timeout";
674 goto fail_transfer;
675 }
676
677 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
678 if (host->complete_what == COMPLETION_CMDSENT) {
679 host->status = "ok: command sent";
680 goto close_transfer;
681 }
682
683 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
684 }
685
686 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
687 if (cmd->flags & MMC_RSP_CRC) {
688 if (host->mrq->cmd->flags & MMC_RSP_136) {
689 dbg(host, dbg_irq,
690 "fixup: ignore CRC fail with long rsp\n");
691 } else {
692 /* note, we used to fail the transfer
693 * here, but it seems that this is just
694 * the hardware getting it wrong.
695 *
696 * cmd->error = -EILSEQ;
697 * host->status = "error: bad command crc";
698 * goto fail_transfer;
699 */
700 }
701 }
702
703 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
704 }
705
706 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
707 if (host->complete_what == COMPLETION_RSPFIN) {
708 host->status = "ok: command response received";
709 goto close_transfer;
710 }
711
712 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
713 host->complete_what = COMPLETION_XFERFINISH;
714
715 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
716 }
717
718 /* errors handled after this point are only relevant
719 when a data transfer is in progress */
720
721 if (!cmd->data)
722 goto clear_status_bits;
723
724 /* Check for FIFO failure */
725 if (host->is2440) {
726 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
727 dbg(host, dbg_err, "FIFO failure\n");
728 host->mrq->data->error = -EILSEQ;
729 host->status = "error: 2440 fifo failure";
730 goto fail_transfer;
731 }
732 } else {
733 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
734 dbg(host, dbg_err, "FIFO failure\n");
735 cmd->data->error = -EILSEQ;
736 host->status = "error: fifo failure";
737 goto fail_transfer;
738 }
739 }
740
741 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
742 dbg(host, dbg_err, "bad data crc (outgoing)\n");
743 cmd->data->error = -EILSEQ;
744 host->status = "error: bad data crc (outgoing)";
745 goto fail_transfer;
746 }
747
748 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
749 dbg(host, dbg_err, "bad data crc (incoming)\n");
750 cmd->data->error = -EILSEQ;
751 host->status = "error: bad data crc (incoming)";
752 goto fail_transfer;
753 }
754
755 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
756 dbg(host, dbg_err, "data timeout\n");
757 cmd->data->error = -ETIMEDOUT;
758 host->status = "error: data timeout";
759 goto fail_transfer;
760 }
761
762 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
763 if (host->complete_what == COMPLETION_XFERFINISH) {
764 host->status = "ok: data transfer completed";
765 goto close_transfer;
766 }
767
768 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
769 host->complete_what = COMPLETION_RSPFIN;
770
771 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
772 }
773
774 clear_status_bits:
775 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
776 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
777
778 goto irq_out;
779
780 fail_transfer:
781 host->pio_active = XFER_NONE;
782
783 close_transfer:
784 host->complete_what = COMPLETION_FINALIZE;
785
786 clear_imask(host);
787 tasklet_schedule(&host->pio_tasklet);
788
789 goto irq_out;
790
791 irq_out:
792 dbg(host, dbg_irq,
793 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
794 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
795
796 spin_unlock_irqrestore(&host->complete_lock, iflags);
797 return IRQ_HANDLED;
798
799 }
800
801 static void s3cmci_dma_done_callback(void *arg)
802 {
803 struct s3cmci_host *host = arg;
804 unsigned long iflags;
805
806 BUG_ON(!host->mrq);
807 BUG_ON(!host->mrq->data);
808
809 spin_lock_irqsave(&host->complete_lock, iflags);
810
811 dbg(host, dbg_dma, "DMA FINISHED\n");
812
813 host->dma_complete = 1;
814 host->complete_what = COMPLETION_FINALIZE;
815
816 tasklet_schedule(&host->pio_tasklet);
817 spin_unlock_irqrestore(&host->complete_lock, iflags);
818
819 }
820
821 static void finalize_request(struct s3cmci_host *host)
822 {
823 struct mmc_request *mrq = host->mrq;
824 struct mmc_command *cmd;
825 int debug_as_failure = 0;
826
827 if (host->complete_what != COMPLETION_FINALIZE)
828 return;
829
830 if (!mrq)
831 return;
832 cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
833
834 if (cmd->data && (cmd->error == 0) &&
835 (cmd->data->error == 0)) {
836 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
837 dbg(host, dbg_dma, "DMA Missing (%d)!\n",
838 host->dma_complete);
839 return;
840 }
841 }
842
843 /* Read response from controller. */
844 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
845 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
846 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
847 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
848
849 writel(host->prescaler, host->base + S3C2410_SDIPRE);
850
851 if (cmd->error)
852 debug_as_failure = 1;
853
854 if (cmd->data && cmd->data->error)
855 debug_as_failure = 1;
856
857 dbg_dumpcmd(host, cmd, debug_as_failure);
858
859 /* Cleanup controller */
860 writel(0, host->base + S3C2410_SDICMDARG);
861 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
862 writel(0, host->base + S3C2410_SDICMDCON);
863 clear_imask(host);
864
865 if (cmd->data && cmd->error)
866 cmd->data->error = cmd->error;
867
868 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
869 host->cmd_is_stop = 1;
870 s3cmci_send_request(host->mmc);
871 return;
872 }
873
874 /* If we have no data transfer we are finished here */
875 if (!mrq->data)
876 goto request_done;
877
878 /* Calculate the amout of bytes transfer if there was no error */
879 if (mrq->data->error == 0) {
880 mrq->data->bytes_xfered =
881 (mrq->data->blocks * mrq->data->blksz);
882 } else {
883 mrq->data->bytes_xfered = 0;
884 }
885
886 /* If we had an error while transferring data we flush the
887 * DMA channel and the fifo to clear out any garbage. */
888 if (mrq->data->error != 0) {
889 if (s3cmci_host_usedma(host))
890 dmaengine_terminate_all(host->dma);
891
892 if (host->is2440) {
893 /* Clear failure register and reset fifo. */
894 writel(S3C2440_SDIFSTA_FIFORESET |
895 S3C2440_SDIFSTA_FIFOFAIL,
896 host->base + S3C2410_SDIFSTA);
897 } else {
898 u32 mci_con;
899
900 /* reset fifo */
901 mci_con = readl(host->base + S3C2410_SDICON);
902 mci_con |= S3C2410_SDICON_FIFORESET;
903
904 writel(mci_con, host->base + S3C2410_SDICON);
905 }
906 }
907
908 request_done:
909 host->complete_what = COMPLETION_NONE;
910 host->mrq = NULL;
911
912 s3cmci_check_sdio_irq(host);
913 mmc_request_done(host->mmc, mrq);
914 }
915
916 static void s3cmci_send_command(struct s3cmci_host *host,
917 struct mmc_command *cmd)
918 {
919 u32 ccon, imsk;
920
921 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
922 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
923 S3C2410_SDIIMSK_RESPONSECRC;
924
925 enable_imask(host, imsk);
926
927 if (cmd->data)
928 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
929 else if (cmd->flags & MMC_RSP_PRESENT)
930 host->complete_what = COMPLETION_RSPFIN;
931 else
932 host->complete_what = COMPLETION_CMDSENT;
933
934 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
935
936 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
937 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
938
939 if (cmd->flags & MMC_RSP_PRESENT)
940 ccon |= S3C2410_SDICMDCON_WAITRSP;
941
942 if (cmd->flags & MMC_RSP_136)
943 ccon |= S3C2410_SDICMDCON_LONGRSP;
944
945 writel(ccon, host->base + S3C2410_SDICMDCON);
946 }
947
948 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
949 {
950 u32 dcon, imsk, stoptries = 3;
951
952 if ((data->blksz & 3) != 0) {
953 /* We cannot deal with unaligned blocks with more than
954 * one block being transferred. */
955
956 if (data->blocks > 1) {
957 pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
958 __func__, data->blksz);
959 return -EINVAL;
960 }
961 }
962
963 while (readl(host->base + S3C2410_SDIDSTA) &
964 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
965
966 dbg(host, dbg_err,
967 "mci_setup_data() transfer stillin progress.\n");
968
969 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
970 s3cmci_reset(host);
971
972 if ((stoptries--) == 0) {
973 dbg_dumpregs(host, "DRF");
974 return -EINVAL;
975 }
976 }
977
978 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
979
980 if (s3cmci_host_usedma(host))
981 dcon |= S3C2410_SDIDCON_DMAEN;
982
983 if (host->bus_width == MMC_BUS_WIDTH_4)
984 dcon |= S3C2410_SDIDCON_WIDEBUS;
985
986 dcon |= S3C2410_SDIDCON_BLOCKMODE;
987
988 if (data->flags & MMC_DATA_WRITE) {
989 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
990 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
991 }
992
993 if (data->flags & MMC_DATA_READ) {
994 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
995 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
996 }
997
998 if (host->is2440) {
999 dcon |= S3C2440_SDIDCON_DS_WORD;
1000 dcon |= S3C2440_SDIDCON_DATSTART;
1001 }
1002
1003 writel(dcon, host->base + S3C2410_SDIDCON);
1004
1005 /* write BSIZE register */
1006
1007 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1008
1009 /* add to IMASK register */
1010 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1011 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1012
1013 enable_imask(host, imsk);
1014
1015 /* write TIMER register */
1016
1017 if (host->is2440) {
1018 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1019 } else {
1020 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1021
1022 /* FIX: set slow clock to prevent timeouts on read */
1023 if (data->flags & MMC_DATA_READ)
1024 writel(0xFF, host->base + S3C2410_SDIPRE);
1025 }
1026
1027 return 0;
1028 }
1029
1030 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1031
1032 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1033 {
1034 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1035
1036 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1037
1038 host->pio_sgptr = 0;
1039 host->pio_bytes = 0;
1040 host->pio_count = 0;
1041 host->pio_active = rw ? XFER_WRITE : XFER_READ;
1042
1043 if (rw) {
1044 do_pio_write(host);
1045 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1046 } else {
1047 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1048 | S3C2410_SDIIMSK_RXFIFOLAST);
1049 }
1050
1051 return 0;
1052 }
1053
1054 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1055 {
1056 int rw = data->flags & MMC_DATA_WRITE;
1057 struct dma_async_tx_descriptor *desc;
1058 struct dma_slave_config conf = {
1059 .src_addr = host->mem->start + host->sdidata,
1060 .dst_addr = host->mem->start + host->sdidata,
1061 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1062 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1063 };
1064
1065 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1066
1067 /* Restore prescaler value */
1068 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1069
1070 if (!rw)
1071 conf.direction = DMA_DEV_TO_MEM;
1072 else
1073 conf.direction = DMA_MEM_TO_DEV;
1074
1075 dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1076 mmc_get_dma_dir(data));
1077
1078 dmaengine_slave_config(host->dma, &conf);
1079 desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1080 conf.direction,
1081 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1082 if (!desc)
1083 goto unmap_exit;
1084 desc->callback = s3cmci_dma_done_callback;
1085 desc->callback_param = host;
1086 dmaengine_submit(desc);
1087 dma_async_issue_pending(host->dma);
1088
1089 return 0;
1090
1091 unmap_exit:
1092 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1093 mmc_get_dma_dir(data));
1094 return -ENOMEM;
1095 }
1096
1097 static void s3cmci_send_request(struct mmc_host *mmc)
1098 {
1099 struct s3cmci_host *host = mmc_priv(mmc);
1100 struct mmc_request *mrq = host->mrq;
1101 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1102
1103 host->ccnt++;
1104 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1105
1106 /* Clear command, data and fifo status registers
1107 Fifo clear only necessary on 2440, but doesn't hurt on 2410
1108 */
1109 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1110 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1111 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1112
1113 if (cmd->data) {
1114 int res = s3cmci_setup_data(host, cmd->data);
1115
1116 host->dcnt++;
1117
1118 if (res) {
1119 dbg(host, dbg_err, "setup data error %d\n", res);
1120 cmd->error = res;
1121 cmd->data->error = res;
1122
1123 mmc_request_done(mmc, mrq);
1124 return;
1125 }
1126
1127 if (s3cmci_host_usedma(host))
1128 res = s3cmci_prepare_dma(host, cmd->data);
1129 else
1130 res = s3cmci_prepare_pio(host, cmd->data);
1131
1132 if (res) {
1133 dbg(host, dbg_err, "data prepare error %d\n", res);
1134 cmd->error = res;
1135 cmd->data->error = res;
1136
1137 mmc_request_done(mmc, mrq);
1138 return;
1139 }
1140 }
1141
1142 /* Send command */
1143 s3cmci_send_command(host, cmd);
1144
1145 /* Enable Interrupt */
1146 s3cmci_enable_irq(host, true);
1147 }
1148
1149 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1150 {
1151 struct s3cmci_host *host = mmc_priv(mmc);
1152
1153 host->status = "mmc request";
1154 host->cmd_is_stop = 0;
1155 host->mrq = mrq;
1156
1157 if (mmc_gpio_get_cd(mmc) == 0) {
1158 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1159 host->mrq->cmd->error = -ENOMEDIUM;
1160 mmc_request_done(mmc, mrq);
1161 } else
1162 s3cmci_send_request(mmc);
1163 }
1164
1165 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1166 {
1167 u32 mci_psc;
1168
1169 /* Set clock */
1170 for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1171 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1172
1173 if (host->real_rate <= ios->clock)
1174 break;
1175 }
1176
1177 if (mci_psc > 255)
1178 mci_psc = 255;
1179
1180 host->prescaler = mci_psc;
1181 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1182
1183 /* If requested clock is 0, real_rate will be 0, too */
1184 if (ios->clock == 0)
1185 host->real_rate = 0;
1186 }
1187
1188 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1189 {
1190 struct s3cmci_host *host = mmc_priv(mmc);
1191 u32 mci_con;
1192
1193 /* Set the power state */
1194
1195 mci_con = readl(host->base + S3C2410_SDICON);
1196
1197 switch (ios->power_mode) {
1198 case MMC_POWER_ON:
1199 case MMC_POWER_UP:
1200 if (!host->is2440)
1201 mci_con |= S3C2410_SDICON_FIFORESET;
1202 break;
1203
1204 case MMC_POWER_OFF:
1205 default:
1206 if (host->is2440)
1207 mci_con |= S3C2440_SDICON_SDRESET;
1208 break;
1209 }
1210
1211 if (host->pdata->set_power)
1212 host->pdata->set_power(ios->power_mode, ios->vdd);
1213
1214 s3cmci_set_clk(host, ios);
1215
1216 /* Set CLOCK_ENABLE */
1217 if (ios->clock)
1218 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1219 else
1220 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1221
1222 writel(mci_con, host->base + S3C2410_SDICON);
1223
1224 if ((ios->power_mode == MMC_POWER_ON) ||
1225 (ios->power_mode == MMC_POWER_UP)) {
1226 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1227 host->real_rate/1000, ios->clock/1000);
1228 } else {
1229 dbg(host, dbg_conf, "powered down.\n");
1230 }
1231
1232 host->bus_width = ios->bus_width;
1233 }
1234
1235 static void s3cmci_reset(struct s3cmci_host *host)
1236 {
1237 u32 con = readl(host->base + S3C2410_SDICON);
1238
1239 con |= S3C2440_SDICON_SDRESET;
1240 writel(con, host->base + S3C2410_SDICON);
1241 }
1242
1243 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1244 {
1245 struct s3cmci_host *host = mmc_priv(mmc);
1246 unsigned long flags;
1247 u32 con;
1248
1249 local_irq_save(flags);
1250
1251 con = readl(host->base + S3C2410_SDICON);
1252 host->sdio_irqen = enable;
1253
1254 if (enable == host->sdio_irqen)
1255 goto same_state;
1256
1257 if (enable) {
1258 con |= S3C2410_SDICON_SDIOIRQ;
1259 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1260
1261 if (!host->irq_state && !host->irq_disabled) {
1262 host->irq_state = true;
1263 enable_irq(host->irq);
1264 }
1265 } else {
1266 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1267 con &= ~S3C2410_SDICON_SDIOIRQ;
1268
1269 if (!host->irq_enabled && host->irq_state) {
1270 disable_irq_nosync(host->irq);
1271 host->irq_state = false;
1272 }
1273 }
1274
1275 writel(con, host->base + S3C2410_SDICON);
1276
1277 same_state:
1278 local_irq_restore(flags);
1279
1280 s3cmci_check_sdio_irq(host);
1281 }
1282
1283 static const struct mmc_host_ops s3cmci_ops = {
1284 .request = s3cmci_request,
1285 .set_ios = s3cmci_set_ios,
1286 .get_ro = mmc_gpio_get_ro,
1287 .get_cd = mmc_gpio_get_cd,
1288 .enable_sdio_irq = s3cmci_enable_sdio_irq,
1289 };
1290
1291 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1292
1293 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1294 unsigned long val, void *data)
1295 {
1296 struct s3cmci_host *host;
1297 struct mmc_host *mmc;
1298 unsigned long newclk;
1299 unsigned long flags;
1300
1301 host = container_of(nb, struct s3cmci_host, freq_transition);
1302 newclk = clk_get_rate(host->clk);
1303 mmc = host->mmc;
1304
1305 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1306 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1307 spin_lock_irqsave(&mmc->lock, flags);
1308
1309 host->clk_rate = newclk;
1310
1311 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1312 mmc->ios.clock != 0)
1313 s3cmci_set_clk(host, &mmc->ios);
1314
1315 spin_unlock_irqrestore(&mmc->lock, flags);
1316 }
1317
1318 return 0;
1319 }
1320
1321 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1322 {
1323 host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1324
1325 return cpufreq_register_notifier(&host->freq_transition,
1326 CPUFREQ_TRANSITION_NOTIFIER);
1327 }
1328
1329 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1330 {
1331 cpufreq_unregister_notifier(&host->freq_transition,
1332 CPUFREQ_TRANSITION_NOTIFIER);
1333 }
1334
1335 #else
1336 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1337 {
1338 return 0;
1339 }
1340
1341 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1342 {
1343 }
1344 #endif
1345
1346
1347 #ifdef CONFIG_DEBUG_FS
1348
1349 static int s3cmci_state_show(struct seq_file *seq, void *v)
1350 {
1351 struct s3cmci_host *host = seq->private;
1352
1353 seq_printf(seq, "Register base = 0x%p\n", host->base);
1354 seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1355 seq_printf(seq, "Prescale = %d\n", host->prescaler);
1356 seq_printf(seq, "is2440 = %d\n", host->is2440);
1357 seq_printf(seq, "IRQ = %d\n", host->irq);
1358 seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1359 seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1360 seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1361 seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1362 seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1363 seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1364 seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1365
1366 return 0;
1367 }
1368
1369 DEFINE_SHOW_ATTRIBUTE(s3cmci_state);
1370
1371 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1372
1373 struct s3cmci_reg {
1374 unsigned short addr;
1375 unsigned char *name;
1376 };
1377
1378 static const struct s3cmci_reg debug_regs[] = {
1379 DBG_REG(CON),
1380 DBG_REG(PRE),
1381 DBG_REG(CMDARG),
1382 DBG_REG(CMDCON),
1383 DBG_REG(CMDSTAT),
1384 DBG_REG(RSP0),
1385 DBG_REG(RSP1),
1386 DBG_REG(RSP2),
1387 DBG_REG(RSP3),
1388 DBG_REG(TIMER),
1389 DBG_REG(BSIZE),
1390 DBG_REG(DCON),
1391 DBG_REG(DCNT),
1392 DBG_REG(DSTA),
1393 DBG_REG(FSTA),
1394 {}
1395 };
1396
1397 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1398 {
1399 struct s3cmci_host *host = seq->private;
1400 const struct s3cmci_reg *rptr = debug_regs;
1401
1402 for (; rptr->name; rptr++)
1403 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1404 readl(host->base + rptr->addr));
1405
1406 seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1407
1408 return 0;
1409 }
1410
1411 DEFINE_SHOW_ATTRIBUTE(s3cmci_regs);
1412
1413 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1414 {
1415 struct device *dev = &host->pdev->dev;
1416 struct dentry *root;
1417
1418 root = debugfs_create_dir(dev_name(dev), NULL);
1419 host->debug_root = root;
1420
1421 debugfs_create_file("state", 0444, root, host, &s3cmci_state_fops);
1422 debugfs_create_file("regs", 0444, root, host, &s3cmci_regs_fops);
1423 }
1424
1425 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1426 {
1427 debugfs_remove_recursive(host->debug_root);
1428 }
1429
1430 #else
1431 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1432 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1433
1434 #endif /* CONFIG_DEBUG_FS */
1435
1436 static int s3cmci_probe_pdata(struct s3cmci_host *host)
1437 {
1438 struct platform_device *pdev = host->pdev;
1439 struct mmc_host *mmc = host->mmc;
1440 struct s3c24xx_mci_pdata *pdata;
1441 int i, ret;
1442
1443 host->is2440 = platform_get_device_id(pdev)->driver_data;
1444 pdata = pdev->dev.platform_data;
1445 if (!pdata) {
1446 dev_err(&pdev->dev, "need platform data");
1447 return -ENXIO;
1448 }
1449
1450 for (i = 0; i < 6; i++) {
1451 pdata->bus[i] = devm_gpiod_get_index(&pdev->dev, "bus", i,
1452 GPIOD_OUT_LOW);
1453 if (IS_ERR(pdata->bus[i])) {
1454 dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1455 return PTR_ERR(pdata->bus[i]);
1456 }
1457 }
1458
1459 if (pdata->no_wprotect)
1460 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1461
1462 if (pdata->no_detect)
1463 mmc->caps |= MMC_CAP_NEEDS_POLL;
1464
1465 if (pdata->wprotect_invert)
1466 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1467
1468 /* If we get -ENOENT we have no card detect GPIO line */
1469 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
1470 if (ret != -ENOENT) {
1471 dev_err(&pdev->dev, "error requesting GPIO for CD %d\n",
1472 ret);
1473 return ret;
1474 }
1475
1476 ret = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
1477 if (ret != -ENOENT) {
1478 dev_err(&pdev->dev, "error requesting GPIO for WP %d\n",
1479 ret);
1480 return ret;
1481 }
1482
1483 return 0;
1484 }
1485
1486 static int s3cmci_probe_dt(struct s3cmci_host *host)
1487 {
1488 struct platform_device *pdev = host->pdev;
1489 struct s3c24xx_mci_pdata *pdata;
1490 struct mmc_host *mmc = host->mmc;
1491 int ret;
1492
1493 host->is2440 = (long) of_device_get_match_data(&pdev->dev);
1494
1495 ret = mmc_of_parse(mmc);
1496 if (ret)
1497 return ret;
1498
1499 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1500 if (!pdata)
1501 return -ENOMEM;
1502
1503 pdev->dev.platform_data = pdata;
1504
1505 return 0;
1506 }
1507
1508 static int s3cmci_probe(struct platform_device *pdev)
1509 {
1510 struct s3cmci_host *host;
1511 struct mmc_host *mmc;
1512 int ret;
1513
1514 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1515 if (!mmc) {
1516 ret = -ENOMEM;
1517 goto probe_out;
1518 }
1519
1520 host = mmc_priv(mmc);
1521 host->mmc = mmc;
1522 host->pdev = pdev;
1523
1524 if (pdev->dev.of_node)
1525 ret = s3cmci_probe_dt(host);
1526 else
1527 ret = s3cmci_probe_pdata(host);
1528
1529 if (ret)
1530 goto probe_free_host;
1531
1532 host->pdata = pdev->dev.platform_data;
1533
1534 spin_lock_init(&host->complete_lock);
1535 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1536
1537 if (host->is2440) {
1538 host->sdiimsk = S3C2440_SDIIMSK;
1539 host->sdidata = S3C2440_SDIDATA;
1540 host->clk_div = 1;
1541 } else {
1542 host->sdiimsk = S3C2410_SDIIMSK;
1543 host->sdidata = S3C2410_SDIDATA;
1544 host->clk_div = 2;
1545 }
1546
1547 host->complete_what = COMPLETION_NONE;
1548 host->pio_active = XFER_NONE;
1549
1550 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1551 if (!host->mem) {
1552 dev_err(&pdev->dev,
1553 "failed to get io memory region resource.\n");
1554
1555 ret = -ENOENT;
1556 goto probe_free_host;
1557 }
1558
1559 host->mem = request_mem_region(host->mem->start,
1560 resource_size(host->mem), pdev->name);
1561
1562 if (!host->mem) {
1563 dev_err(&pdev->dev, "failed to request io memory region.\n");
1564 ret = -ENOENT;
1565 goto probe_free_host;
1566 }
1567
1568 host->base = ioremap(host->mem->start, resource_size(host->mem));
1569 if (!host->base) {
1570 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1571 ret = -EINVAL;
1572 goto probe_free_mem_region;
1573 }
1574
1575 host->irq = platform_get_irq(pdev, 0);
1576 if (host->irq <= 0) {
1577 ret = -EINVAL;
1578 goto probe_iounmap;
1579 }
1580
1581 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1582 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1583 ret = -ENOENT;
1584 goto probe_iounmap;
1585 }
1586
1587 /* We get spurious interrupts even when we have set the IMSK
1588 * register to ignore everything, so use disable_irq() to make
1589 * ensure we don't lock the system with un-serviceable requests. */
1590
1591 disable_irq(host->irq);
1592 host->irq_state = false;
1593
1594 /* Depending on the dma state, get a DMA channel to use. */
1595
1596 if (s3cmci_host_usedma(host)) {
1597 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1598 ret = PTR_ERR_OR_ZERO(host->dma);
1599 if (ret) {
1600 dev_err(&pdev->dev, "cannot get DMA channel.\n");
1601 goto probe_free_irq;
1602 }
1603 }
1604
1605 host->clk = clk_get(&pdev->dev, "sdi");
1606 if (IS_ERR(host->clk)) {
1607 dev_err(&pdev->dev, "failed to find clock source.\n");
1608 ret = PTR_ERR(host->clk);
1609 host->clk = NULL;
1610 goto probe_free_dma;
1611 }
1612
1613 ret = clk_prepare_enable(host->clk);
1614 if (ret) {
1615 dev_err(&pdev->dev, "failed to enable clock source.\n");
1616 goto clk_free;
1617 }
1618
1619 host->clk_rate = clk_get_rate(host->clk);
1620
1621 mmc->ops = &s3cmci_ops;
1622 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1623 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1624 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1625 #else
1626 mmc->caps = MMC_CAP_4_BIT_DATA;
1627 #endif
1628 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1629 mmc->f_max = host->clk_rate / host->clk_div;
1630
1631 if (host->pdata->ocr_avail)
1632 mmc->ocr_avail = host->pdata->ocr_avail;
1633
1634 mmc->max_blk_count = 4095;
1635 mmc->max_blk_size = 4095;
1636 mmc->max_req_size = 4095 * 512;
1637 mmc->max_seg_size = mmc->max_req_size;
1638
1639 mmc->max_segs = 128;
1640
1641 dbg(host, dbg_debug,
1642 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1643 (host->is2440?"2440":""),
1644 host->base, host->irq, host->irq_cd, host->dma);
1645
1646 ret = s3cmci_cpufreq_register(host);
1647 if (ret) {
1648 dev_err(&pdev->dev, "failed to register cpufreq\n");
1649 goto free_dmabuf;
1650 }
1651
1652 ret = mmc_add_host(mmc);
1653 if (ret) {
1654 dev_err(&pdev->dev, "failed to add mmc host.\n");
1655 goto free_cpufreq;
1656 }
1657
1658 s3cmci_debugfs_attach(host);
1659
1660 platform_set_drvdata(pdev, mmc);
1661 dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1662 s3cmci_host_usedma(host) ? "dma" : "pio",
1663 mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1664
1665 return 0;
1666
1667 free_cpufreq:
1668 s3cmci_cpufreq_deregister(host);
1669
1670 free_dmabuf:
1671 clk_disable_unprepare(host->clk);
1672
1673 clk_free:
1674 clk_put(host->clk);
1675
1676 probe_free_dma:
1677 if (s3cmci_host_usedma(host))
1678 dma_release_channel(host->dma);
1679
1680 probe_free_irq:
1681 free_irq(host->irq, host);
1682
1683 probe_iounmap:
1684 iounmap(host->base);
1685
1686 probe_free_mem_region:
1687 release_mem_region(host->mem->start, resource_size(host->mem));
1688
1689 probe_free_host:
1690 mmc_free_host(mmc);
1691
1692 probe_out:
1693 return ret;
1694 }
1695
1696 static void s3cmci_shutdown(struct platform_device *pdev)
1697 {
1698 struct mmc_host *mmc = platform_get_drvdata(pdev);
1699 struct s3cmci_host *host = mmc_priv(mmc);
1700
1701 if (host->irq_cd >= 0)
1702 free_irq(host->irq_cd, host);
1703
1704 s3cmci_debugfs_remove(host);
1705 s3cmci_cpufreq_deregister(host);
1706 mmc_remove_host(mmc);
1707 clk_disable_unprepare(host->clk);
1708 }
1709
1710 static int s3cmci_remove(struct platform_device *pdev)
1711 {
1712 struct mmc_host *mmc = platform_get_drvdata(pdev);
1713 struct s3cmci_host *host = mmc_priv(mmc);
1714
1715 s3cmci_shutdown(pdev);
1716
1717 clk_put(host->clk);
1718
1719 tasklet_disable(&host->pio_tasklet);
1720
1721 if (s3cmci_host_usedma(host))
1722 dma_release_channel(host->dma);
1723
1724 free_irq(host->irq, host);
1725
1726 iounmap(host->base);
1727 release_mem_region(host->mem->start, resource_size(host->mem));
1728
1729 mmc_free_host(mmc);
1730 return 0;
1731 }
1732
1733 static const struct of_device_id s3cmci_dt_match[] = {
1734 {
1735 .compatible = "samsung,s3c2410-sdi",
1736 .data = (void *)0,
1737 },
1738 {
1739 .compatible = "samsung,s3c2412-sdi",
1740 .data = (void *)1,
1741 },
1742 {
1743 .compatible = "samsung,s3c2440-sdi",
1744 .data = (void *)1,
1745 },
1746 { /* sentinel */ },
1747 };
1748 MODULE_DEVICE_TABLE(of, s3cmci_dt_match);
1749
1750 static const struct platform_device_id s3cmci_driver_ids[] = {
1751 {
1752 .name = "s3c2410-sdi",
1753 .driver_data = 0,
1754 }, {
1755 .name = "s3c2412-sdi",
1756 .driver_data = 1,
1757 }, {
1758 .name = "s3c2440-sdi",
1759 .driver_data = 1,
1760 },
1761 { }
1762 };
1763
1764 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1765
1766 static struct platform_driver s3cmci_driver = {
1767 .driver = {
1768 .name = "s3c-sdi",
1769 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1770 .of_match_table = s3cmci_dt_match,
1771 },
1772 .id_table = s3cmci_driver_ids,
1773 .probe = s3cmci_probe,
1774 .remove = s3cmci_remove,
1775 .shutdown = s3cmci_shutdown,
1776 };
1777
1778 module_platform_driver(s3cmci_driver);
1779
1780 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1781 MODULE_LICENSE("GPL v2");
1782 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
Linux with added FPC-III support