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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-pci-gli.c
blobb85edd62e7f08c00c1e22e8e10689e231134e802
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019 Genesys Logic, Inc.
4 *
5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
6 *
7 * Version: v0.9.0 (2019-08-08)
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/pci.h>
13 #include <linux/mmc/mmc.h>
14 #include <linux/delay.h>
15 #include "sdhci.h"
16 #include "sdhci-pci.h"
17 #include "cqhci.h"
18
19 /* Genesys Logic extra registers */
20 #define SDHCI_GLI_9750_WT 0x800
21 #define SDHCI_GLI_9750_WT_EN BIT(0)
22 #define GLI_9750_WT_EN_ON 0x1
23 #define GLI_9750_WT_EN_OFF 0x0
24
25 #define SDHCI_GLI_9750_DRIVING 0x860
26 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0)
27 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26)
28 #define GLI_9750_DRIVING_1_VALUE 0xFFF
29 #define GLI_9750_DRIVING_2_VALUE 0x3
30 #define SDHCI_GLI_9750_SEL_1 BIT(29)
31 #define SDHCI_GLI_9750_SEL_2 BIT(31)
32 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))
33
34 #define SDHCI_GLI_9750_PLL 0x864
35 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)
36 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)
37 #define SDHCI_GLI_9750_PLL_DIR BIT(15)
38 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)
39 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)
40 #define GLI_9750_PLL_TX2_INV_VALUE 0x1
41 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0
42 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)
43 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31)
44
45 #define SDHCI_GLI_9750_PLLSSC 0x86C
46 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)
47
48 #define SDHCI_GLI_9750_SW_CTRL 0x874
49 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)
50 #define GLI_9750_SW_CTRL_4_VALUE 0x3
51
52 #define SDHCI_GLI_9750_MISC 0x878
53 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2)
54 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3)
55 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4)
56 #define GLI_9750_MISC_TX1_INV_VALUE 0x0
57 #define GLI_9750_MISC_RX_INV_ON 0x1
58 #define GLI_9750_MISC_RX_INV_OFF 0x0
59 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
60 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5
61
62 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540
63 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)
64 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1
65 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0
66 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16)
67 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19)
68 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1
69 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2
70
71 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544
72 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0)
73 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1
74
75 #define SDHCI_GLI_9763E_CTRL_HS400 0x7
76
77 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C
78 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8)
79
80 #define PCIE_GLI_9763E_VHS 0x884
81 #define GLI_9763E_VHS_REV GENMASK(19, 16)
82 #define GLI_9763E_VHS_REV_R 0x0
83 #define GLI_9763E_VHS_REV_M 0x1
84 #define GLI_9763E_VHS_REV_W 0x2
85 #define PCIE_GLI_9763E_MB 0x888
86 #define GLI_9763E_MB_CMDQ_OFF BIT(19)
87 #define PCIE_GLI_9763E_SCR 0x8E0
88 #define GLI_9763E_SCR_AXI_REQ BIT(9)
89
90 #define PCIE_GLI_9763E_MMC_CTRL 0x960
91 #define GLI_9763E_HS400_SLOW BIT(3)
92
93 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200
94 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
95 SDHCI_TRNS_BLK_CNT_EN | \
96 SDHCI_TRNS_DMA)
97
98 #define PCI_GLI_9755_WT 0x800
99 #define PCI_GLI_9755_WT_EN BIT(0)
100 #define GLI_9755_WT_EN_ON 0x1
101 #define GLI_9755_WT_EN_OFF 0x0
102
103 #define PCI_GLI_9755_PECONF 0x44
104 #define PCI_GLI_9755_LFCLK GENMASK(14, 12)
105 #define PCI_GLI_9755_DMACLK BIT(29)
106
107 #define PCI_GLI_9755_PLL 0x64
108 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)
109 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)
110 #define PCI_GLI_9755_PLL_DIR BIT(15)
111 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)
112 #define PCI_GLI_9755_PLLSSC_EN BIT(31)
113
114 #define PCI_GLI_9755_PLLSSC 0x68
115 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)
116
117 #define GLI_MAX_TUNING_LOOP 40
118
119 /* Genesys Logic chipset */
120 static inline void gl9750_wt_on(struct sdhci_host *host)
121 {
122 u32 wt_value;
123 u32 wt_enable;
124
125 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
126 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
127
128 if (wt_enable == GLI_9750_WT_EN_ON)
129 return;
130
131 wt_value &= ~SDHCI_GLI_9750_WT_EN;
132 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
133
134 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
135 }
136
137 static inline void gl9750_wt_off(struct sdhci_host *host)
138 {
139 u32 wt_value;
140 u32 wt_enable;
141
142 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
143 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
144
145 if (wt_enable == GLI_9750_WT_EN_OFF)
146 return;
147
148 wt_value &= ~SDHCI_GLI_9750_WT_EN;
149 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
150
151 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
152 }
153
154 static void gli_set_9750(struct sdhci_host *host)
155 {
156 u32 driving_value;
157 u32 pll_value;
158 u32 sw_ctrl_value;
159 u32 misc_value;
160 u32 parameter_value;
161 u32 control_value;
162 u16 ctrl2;
163
164 gl9750_wt_on(host);
165
166 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
167 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
168 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
169 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
170 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
171 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
172
173 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
174 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
175 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
176 GLI_9750_DRIVING_1_VALUE);
177 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
178 GLI_9750_DRIVING_2_VALUE);
179 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
180 driving_value |= SDHCI_GLI_9750_SEL_2;
181 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
182
183 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
184 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
185 GLI_9750_SW_CTRL_4_VALUE);
186 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
187
188 /* reset the tuning flow after reinit and before starting tuning */
189 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
190 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
191 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
192 GLI_9750_PLL_TX2_INV_VALUE);
193 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
194 GLI_9750_PLL_TX2_DLY_VALUE);
195
196 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
197 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
198 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
199 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
200 GLI_9750_MISC_TX1_INV_VALUE);
201 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
202 GLI_9750_MISC_RX_INV_VALUE);
203 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
204 GLI_9750_MISC_TX1_DLY_VALUE);
205
206 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
207 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
208 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
209
210 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
211 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
212 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
213 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
214 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
215 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
216
217 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
218 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
219
220 /* disable tuned clk */
221 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
222 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
223 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
224
225 /* enable tuning parameters control */
226 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
227 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
228 GLI_9750_TUNING_CONTROL_EN_ON);
229 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
230
231 /* write tuning parameters */
232 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
233
234 /* disable tuning parameters control */
235 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
236 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
237 GLI_9750_TUNING_CONTROL_EN_OFF);
238 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
239
240 /* clear tuned clk */
241 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
242 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
243 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
244
245 gl9750_wt_off(host);
246 }
247
248 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
249 {
250 u32 misc_value;
251
252 gl9750_wt_on(host);
253
254 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
255 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
256 if (b) {
257 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
258 GLI_9750_MISC_RX_INV_ON);
259 } else {
260 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
261 GLI_9750_MISC_RX_INV_OFF);
262 }
263 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
264
265 gl9750_wt_off(host);
266 }
267
268 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
269 {
270 int i;
271 int rx_inv;
272
273 for (rx_inv = 0; rx_inv < 2; rx_inv++) {
274 gli_set_9750_rx_inv(host, !!rx_inv);
275 sdhci_start_tuning(host);
276
277 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
278 u16 ctrl;
279
280 sdhci_send_tuning(host, opcode);
281
282 if (!host->tuning_done) {
283 sdhci_abort_tuning(host, opcode);
284 break;
285 }
286
287 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
288 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
289 if (ctrl & SDHCI_CTRL_TUNED_CLK)
290 return 0; /* Success! */
291 break;
292 }
293 }
294 }
295 if (!host->tuning_done) {
296 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
297 mmc_hostname(host->mmc));
298 return -ETIMEDOUT;
299 }
300
301 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
302 mmc_hostname(host->mmc));
303 sdhci_reset_tuning(host);
304
305 return -EAGAIN;
306 }
307
308 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
309 {
310 host->mmc->retune_period = 0;
311 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
312 host->mmc->retune_period = host->tuning_count;
313
314 gli_set_9750(host);
315 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
316 sdhci_end_tuning(host);
317
318 return 0;
319 }
320
321 static void gl9750_disable_ssc_pll(struct sdhci_host *host)
322 {
323 u32 pll;
324
325 gl9750_wt_on(host);
326 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
327 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
328 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
329 gl9750_wt_off(host);
330 }
331
332 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
333 {
334 u32 pll;
335
336 gl9750_wt_on(host);
337 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
338 pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
339 SDHCI_GLI_9750_PLL_PDIV |
340 SDHCI_GLI_9750_PLL_DIR);
341 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
342 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
343 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
344 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
345 gl9750_wt_off(host);
346
347 /* wait for pll stable */
348 mdelay(1);
349 }
350
351 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
352 {
353 u32 pll;
354 u32 ssc;
355
356 gl9750_wt_on(host);
357 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
358 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
359 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
360 SDHCI_GLI_9750_PLLSSC_EN);
361 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
362 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
363 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
364 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
365 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
366 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
367 gl9750_wt_off(host);
368 }
369
370 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
371 {
372 /* set pll to 205MHz and enable ssc */
373 gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7);
374 gl9750_set_pll(host, 0x1, 0x246, 0x0);
375 }
376
377 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
378 {
379 struct mmc_ios *ios = &host->mmc->ios;
380 u16 clk;
381
382 host->mmc->actual_clock = 0;
383
384 gl9750_disable_ssc_pll(host);
385 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
386
387 if (clock == 0)
388 return;
389
390 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
391 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
392 host->mmc->actual_clock = 205000000;
393 gl9750_set_ssc_pll_205mhz(host);
394 }
395
396 sdhci_enable_clk(host, clk);
397 }
398
399 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
400 {
401 int ret;
402
403 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
404 PCI_IRQ_MSI | PCI_IRQ_MSIX);
405 if (ret < 0) {
406 pr_warn("%s: enable PCI MSI failed, error=%d\n",
407 mmc_hostname(slot->host->mmc), ret);
408 return;
409 }
410
411 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
412 }
413
414 static inline void gl9755_wt_on(struct pci_dev *pdev)
415 {
416 u32 wt_value;
417 u32 wt_enable;
418
419 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
420 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
421
422 if (wt_enable == GLI_9755_WT_EN_ON)
423 return;
424
425 wt_value &= ~PCI_GLI_9755_WT_EN;
426 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
427
428 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
429 }
430
431 static inline void gl9755_wt_off(struct pci_dev *pdev)
432 {
433 u32 wt_value;
434 u32 wt_enable;
435
436 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
437 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
438
439 if (wt_enable == GLI_9755_WT_EN_OFF)
440 return;
441
442 wt_value &= ~PCI_GLI_9755_WT_EN;
443 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
444
445 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
446 }
447
448 static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
449 {
450 u32 pll;
451
452 gl9755_wt_on(pdev);
453 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
454 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
455 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
456 gl9755_wt_off(pdev);
457 }
458
459 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
460 {
461 u32 pll;
462
463 gl9755_wt_on(pdev);
464 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
465 pll &= ~(PCI_GLI_9755_PLL_LDIV |
466 PCI_GLI_9755_PLL_PDIV |
467 PCI_GLI_9755_PLL_DIR);
468 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
469 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
470 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
471 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
472 gl9755_wt_off(pdev);
473
474 /* wait for pll stable */
475 mdelay(1);
476 }
477
478 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
479 {
480 u32 pll;
481 u32 ssc;
482
483 gl9755_wt_on(pdev);
484 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
485 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
486 pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
487 PCI_GLI_9755_PLLSSC_EN);
488 ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
489 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
490 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
491 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
492 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
493 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
494 gl9755_wt_off(pdev);
495 }
496
497 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
498 {
499 /* set pll to 205MHz and enable ssc */
500 gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7);
501 gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
502 }
503
504 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
505 {
506 struct sdhci_pci_slot *slot = sdhci_priv(host);
507 struct mmc_ios *ios = &host->mmc->ios;
508 struct pci_dev *pdev;
509 u16 clk;
510
511 pdev = slot->chip->pdev;
512 host->mmc->actual_clock = 0;
513
514 gl9755_disable_ssc_pll(pdev);
515 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
516
517 if (clock == 0)
518 return;
519
520 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
521 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
522 host->mmc->actual_clock = 205000000;
523 gl9755_set_ssc_pll_205mhz(pdev);
524 }
525
526 sdhci_enable_clk(host, clk);
527 }
528
529 static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
530 {
531 struct pci_dev *pdev = slot->chip->pdev;
532 u32 value;
533
534 gl9755_wt_on(pdev);
535
536 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
537 value &= ~PCI_GLI_9755_LFCLK;
538 value &= ~PCI_GLI_9755_DMACLK;
539 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
540
541 gl9755_wt_off(pdev);
542 }
543
544 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
545 {
546 struct sdhci_host *host = slot->host;
547
548 gli_pcie_enable_msi(slot);
549 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
550 sdhci_enable_v4_mode(host);
551
552 return 0;
553 }
554
555 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
556 {
557 struct sdhci_host *host = slot->host;
558
559 gl9755_hw_setting(slot);
560 gli_pcie_enable_msi(slot);
561 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
562 sdhci_enable_v4_mode(host);
563
564 return 0;
565 }
566
567 static void sdhci_gli_voltage_switch(struct sdhci_host *host)
568 {
569 /*
570 * According to Section 3.6.1 signal voltage switch procedure in
571 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
572 * follows:
573 * (6) Set 1.8V Signal Enable in the Host Control 2 register.
574 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
575 * period.
576 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
577 * step (12).
578 *
579 * Wait 5ms after set 1.8V signal enable in Host Control 2 register
580 * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
581 */
582 usleep_range(5000, 5500);
583 }
584
585 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
586 {
587 sdhci_reset(host, mask);
588 gli_set_9750(host);
589 }
590
591 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
592 {
593 u32 value;
594
595 value = readl(host->ioaddr + reg);
596 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
597 value |= 0xc8;
598
599 return value;
600 }
601
602 #ifdef CONFIG_PM_SLEEP
603 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
604 {
605 struct sdhci_pci_slot *slot = chip->slots[0];
606
607 pci_free_irq_vectors(slot->chip->pdev);
608 gli_pcie_enable_msi(slot);
609
610 return sdhci_pci_resume_host(chip);
611 }
612
613 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip)
614 {
615 struct sdhci_pci_slot *slot = chip->slots[0];
616 int ret;
617
618 ret = sdhci_pci_gli_resume(chip);
619 if (ret)
620 return ret;
621
622 return cqhci_resume(slot->host->mmc);
623 }
624
625 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip)
626 {
627 struct sdhci_pci_slot *slot = chip->slots[0];
628 int ret;
629
630 ret = cqhci_suspend(slot->host->mmc);
631 if (ret)
632 return ret;
633
634 return sdhci_suspend_host(slot->host);
635 }
636 #endif
637
638 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
639 struct mmc_ios *ios)
640 {
641 struct sdhci_host *host = mmc_priv(mmc);
642 u32 val;
643
644 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
645 if (ios->enhanced_strobe)
646 val |= SDHCI_GLI_9763E_HS400_ES_BIT;
647 else
648 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
649
650 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
651 }
652
653 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
654 unsigned int timing)
655 {
656 u16 ctrl_2;
657
658 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
659 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
660 if (timing == MMC_TIMING_MMC_HS200)
661 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
662 else if (timing == MMC_TIMING_MMC_HS)
663 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
664 else if (timing == MMC_TIMING_MMC_DDR52)
665 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
666 else if (timing == MMC_TIMING_MMC_HS400)
667 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
668
669 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
670 }
671
672 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
673 {
674 sdhci_dumpregs(mmc_priv(mmc));
675 }
676
677 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
678 {
679 struct cqhci_host *cq_host = mmc->cqe_private;
680 u32 value;
681
682 value = cqhci_readl(cq_host, CQHCI_CFG);
683 value |= CQHCI_ENABLE;
684 cqhci_writel(cq_host, value, CQHCI_CFG);
685 }
686
687 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
688 {
689 struct sdhci_host *host = mmc_priv(mmc);
690
691 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
692 sdhci_cqe_enable(mmc);
693 }
694
695 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
696 {
697 int cmd_error = 0;
698 int data_error = 0;
699
700 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
701 return intmask;
702
703 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
704
705 return 0;
706 }
707
708 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
709 {
710 struct sdhci_host *host = mmc_priv(mmc);
711 struct cqhci_host *cq_host = mmc->cqe_private;
712 u32 value;
713
714 value = cqhci_readl(cq_host, CQHCI_CFG);
715 value &= ~CQHCI_ENABLE;
716 cqhci_writel(cq_host, value, CQHCI_CFG);
717 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
718 }
719
720 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
721 .enable = sdhci_gl9763e_cqe_enable,
722 .disable = sdhci_cqe_disable,
723 .dumpregs = sdhci_gl9763e_dumpregs,
724 .pre_enable = sdhci_gl9763e_cqe_pre_enable,
725 .post_disable = sdhci_gl9763e_cqe_post_disable,
726 };
727
728 static int gl9763e_add_host(struct sdhci_pci_slot *slot)
729 {
730 struct device *dev = &slot->chip->pdev->dev;
731 struct sdhci_host *host = slot->host;
732 struct cqhci_host *cq_host;
733 bool dma64;
734 int ret;
735
736 ret = sdhci_setup_host(host);
737 if (ret)
738 return ret;
739
740 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
741 if (!cq_host) {
742 ret = -ENOMEM;
743 goto cleanup;
744 }
745
746 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
747 cq_host->ops = &sdhci_gl9763e_cqhci_ops;
748
749 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
750 if (dma64)
751 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
752
753 ret = cqhci_init(cq_host, host->mmc, dma64);
754 if (ret)
755 goto cleanup;
756
757 ret = __sdhci_add_host(host);
758 if (ret)
759 goto cleanup;
760
761 return 0;
762
763 cleanup:
764 sdhci_cleanup_host(host);
765 return ret;
766 }
767
768 static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask)
769 {
770 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
771 host->mmc->cqe_private)
772 cqhci_deactivate(host->mmc);
773 sdhci_reset(host, mask);
774 }
775
776 static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
777 {
778 struct pci_dev *pdev = slot->chip->pdev;
779 u32 value;
780
781 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
782 value &= ~GLI_9763E_VHS_REV;
783 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
784 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
785
786 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
787 value |= GLI_9763E_SCR_AXI_REQ;
788 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
789
790 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
791 value &= ~GLI_9763E_HS400_SLOW;
792 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
793
794 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
795 value &= ~GLI_9763E_VHS_REV;
796 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
797 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
798 }
799
800 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
801 {
802 struct pci_dev *pdev = slot->chip->pdev;
803 struct sdhci_host *host = slot->host;
804 u32 value;
805
806 host->mmc->caps |= MMC_CAP_8_BIT_DATA |
807 MMC_CAP_1_8V_DDR |
808 MMC_CAP_NONREMOVABLE;
809 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
810 MMC_CAP2_HS400_1_8V |
811 MMC_CAP2_HS400_ES |
812 MMC_CAP2_NO_SDIO |
813 MMC_CAP2_NO_SD;
814
815 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
816 if (!(value & GLI_9763E_MB_CMDQ_OFF))
817 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
818
819 gli_pcie_enable_msi(slot);
820 host->mmc_host_ops.hs400_enhanced_strobe =
821 gl9763e_hs400_enhanced_strobe;
822 gli_set_gl9763e(slot);
823 sdhci_enable_v4_mode(host);
824
825 return 0;
826 }
827
828 static const struct sdhci_ops sdhci_gl9755_ops = {
829 .set_clock = sdhci_gl9755_set_clock,
830 .enable_dma = sdhci_pci_enable_dma,
831 .set_bus_width = sdhci_set_bus_width,
832 .reset = sdhci_reset,
833 .set_uhs_signaling = sdhci_set_uhs_signaling,
834 .voltage_switch = sdhci_gli_voltage_switch,
835 };
836
837 const struct sdhci_pci_fixes sdhci_gl9755 = {
838 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
839 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
840 .probe_slot = gli_probe_slot_gl9755,
841 .ops = &sdhci_gl9755_ops,
842 #ifdef CONFIG_PM_SLEEP
843 .resume = sdhci_pci_gli_resume,
844 #endif
845 };
846
847 static const struct sdhci_ops sdhci_gl9750_ops = {
848 .read_l = sdhci_gl9750_readl,
849 .set_clock = sdhci_gl9750_set_clock,
850 .enable_dma = sdhci_pci_enable_dma,
851 .set_bus_width = sdhci_set_bus_width,
852 .reset = sdhci_gl9750_reset,
853 .set_uhs_signaling = sdhci_set_uhs_signaling,
854 .voltage_switch = sdhci_gli_voltage_switch,
855 .platform_execute_tuning = gl9750_execute_tuning,
856 };
857
858 const struct sdhci_pci_fixes sdhci_gl9750 = {
859 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
860 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
861 .probe_slot = gli_probe_slot_gl9750,
862 .ops = &sdhci_gl9750_ops,
863 #ifdef CONFIG_PM_SLEEP
864 .resume = sdhci_pci_gli_resume,
865 #endif
866 };
867
868 static const struct sdhci_ops sdhci_gl9763e_ops = {
869 .set_clock = sdhci_set_clock,
870 .enable_dma = sdhci_pci_enable_dma,
871 .set_bus_width = sdhci_set_bus_width,
872 .reset = sdhci_gl9763e_reset,
873 .set_uhs_signaling = sdhci_set_gl9763e_signaling,
874 .voltage_switch = sdhci_gli_voltage_switch,
875 .irq = sdhci_gl9763e_cqhci_irq,
876 };
877
878 const struct sdhci_pci_fixes sdhci_gl9763e = {
879 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
880 .probe_slot = gli_probe_slot_gl9763e,
881 .ops = &sdhci_gl9763e_ops,
882 #ifdef CONFIG_PM_SLEEP
883 .resume = sdhci_cqhci_gli_resume,
884 .suspend = sdhci_cqhci_gli_suspend,
885 #endif
886 .add_host = gl9763e_add_host,
887 };
Linux with added FPC-III support