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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / mmc / host / sunxi-mmc.c
blob6310693f2ac06d2145d8e951afb13923eb6fa6c8
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for sunxi SD/MMC host controllers
4 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
5 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
6 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
7 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
8 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
9 * (C) Copyright 2017 Sootech SA
10 */
11
12 #include <linux/clk.h>
13 #include <linux/clk/sunxi-ng.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/err.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/mmc/card.h>
22 #include <linux/mmc/core.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/mmc/sd.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/module.h>
29 #include <linux/mod_devicetable.h>
30 #include <linux/of_address.h>
31 #include <linux/of_platform.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/reset.h>
36 #include <linux/scatterlist.h>
37 #include <linux/slab.h>
38 #include <linux/spinlock.h>
39
40 /* register offset definitions */
41 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
42 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
43 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
44 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
45 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
46 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
47 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */
48 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
49 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
50 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
51 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
52 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
53 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
54 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
55 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
56 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */
57 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
58 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
59 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
60 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
61 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
62 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
63 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
64 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
65 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
66 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
67 #define SDXC_REG_CHDA (0x90)
68 #define SDXC_REG_CBDA (0x94)
69
70 /* New registers introduced in A64 */
71 #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */
72 #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */
73 #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */
74 #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */
75 #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */
76
77 #define mmc_readl(host, reg) \
78 readl((host)->reg_base + SDXC_##reg)
79 #define mmc_writel(host, reg, value) \
80 writel((value), (host)->reg_base + SDXC_##reg)
81
82 /* global control register bits */
83 #define SDXC_SOFT_RESET BIT(0)
84 #define SDXC_FIFO_RESET BIT(1)
85 #define SDXC_DMA_RESET BIT(2)
86 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
87 #define SDXC_DMA_ENABLE_BIT BIT(5)
88 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
89 #define SDXC_POSEDGE_LATCH_DATA BIT(9)
90 #define SDXC_DDR_MODE BIT(10)
91 #define SDXC_MEMORY_ACCESS_DONE BIT(29)
92 #define SDXC_ACCESS_DONE_DIRECT BIT(30)
93 #define SDXC_ACCESS_BY_AHB BIT(31)
94 #define SDXC_ACCESS_BY_DMA (0 << 31)
95 #define SDXC_HARDWARE_RESET \
96 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
97
98 /* clock control bits */
99 #define SDXC_MASK_DATA0 BIT(31)
100 #define SDXC_CARD_CLOCK_ON BIT(16)
101 #define SDXC_LOW_POWER_ON BIT(17)
102
103 /* bus width */
104 #define SDXC_WIDTH1 0
105 #define SDXC_WIDTH4 1
106 #define SDXC_WIDTH8 2
107
108 /* smc command bits */
109 #define SDXC_RESP_EXPIRE BIT(6)
110 #define SDXC_LONG_RESPONSE BIT(7)
111 #define SDXC_CHECK_RESPONSE_CRC BIT(8)
112 #define SDXC_DATA_EXPIRE BIT(9)
113 #define SDXC_WRITE BIT(10)
114 #define SDXC_SEQUENCE_MODE BIT(11)
115 #define SDXC_SEND_AUTO_STOP BIT(12)
116 #define SDXC_WAIT_PRE_OVER BIT(13)
117 #define SDXC_STOP_ABORT_CMD BIT(14)
118 #define SDXC_SEND_INIT_SEQUENCE BIT(15)
119 #define SDXC_UPCLK_ONLY BIT(21)
120 #define SDXC_READ_CEATA_DEV BIT(22)
121 #define SDXC_CCS_EXPIRE BIT(23)
122 #define SDXC_ENABLE_BIT_BOOT BIT(24)
123 #define SDXC_ALT_BOOT_OPTIONS BIT(25)
124 #define SDXC_BOOT_ACK_EXPIRE BIT(26)
125 #define SDXC_BOOT_ABORT BIT(27)
126 #define SDXC_VOLTAGE_SWITCH BIT(28)
127 #define SDXC_USE_HOLD_REGISTER BIT(29)
128 #define SDXC_START BIT(31)
129
130 /* interrupt bits */
131 #define SDXC_RESP_ERROR BIT(1)
132 #define SDXC_COMMAND_DONE BIT(2)
133 #define SDXC_DATA_OVER BIT(3)
134 #define SDXC_TX_DATA_REQUEST BIT(4)
135 #define SDXC_RX_DATA_REQUEST BIT(5)
136 #define SDXC_RESP_CRC_ERROR BIT(6)
137 #define SDXC_DATA_CRC_ERROR BIT(7)
138 #define SDXC_RESP_TIMEOUT BIT(8)
139 #define SDXC_DATA_TIMEOUT BIT(9)
140 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
141 #define SDXC_FIFO_RUN_ERROR BIT(11)
142 #define SDXC_HARD_WARE_LOCKED BIT(12)
143 #define SDXC_START_BIT_ERROR BIT(13)
144 #define SDXC_AUTO_COMMAND_DONE BIT(14)
145 #define SDXC_END_BIT_ERROR BIT(15)
146 #define SDXC_SDIO_INTERRUPT BIT(16)
147 #define SDXC_CARD_INSERT BIT(30)
148 #define SDXC_CARD_REMOVE BIT(31)
149 #define SDXC_INTERRUPT_ERROR_BIT \
150 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
151 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
152 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
153 #define SDXC_INTERRUPT_DONE_BIT \
154 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
155 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
156
157 /* status */
158 #define SDXC_RXWL_FLAG BIT(0)
159 #define SDXC_TXWL_FLAG BIT(1)
160 #define SDXC_FIFO_EMPTY BIT(2)
161 #define SDXC_FIFO_FULL BIT(3)
162 #define SDXC_CARD_PRESENT BIT(8)
163 #define SDXC_CARD_DATA_BUSY BIT(9)
164 #define SDXC_DATA_FSM_BUSY BIT(10)
165 #define SDXC_DMA_REQUEST BIT(31)
166 #define SDXC_FIFO_SIZE 16
167
168 /* Function select */
169 #define SDXC_CEATA_ON (0xceaa << 16)
170 #define SDXC_SEND_IRQ_RESPONSE BIT(0)
171 #define SDXC_SDIO_READ_WAIT BIT(1)
172 #define SDXC_ABORT_READ_DATA BIT(2)
173 #define SDXC_SEND_CCSD BIT(8)
174 #define SDXC_SEND_AUTO_STOPCCSD BIT(9)
175 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
176
177 /* IDMA controller bus mod bit field */
178 #define SDXC_IDMAC_SOFT_RESET BIT(0)
179 #define SDXC_IDMAC_FIX_BURST BIT(1)
180 #define SDXC_IDMAC_IDMA_ON BIT(7)
181 #define SDXC_IDMAC_REFETCH_DES BIT(31)
182
183 /* IDMA status bit field */
184 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
185 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
186 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
187 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
188 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
189 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
190 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
191 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
192 #define SDXC_IDMAC_IDLE (0 << 13)
193 #define SDXC_IDMAC_SUSPEND (1 << 13)
194 #define SDXC_IDMAC_DESC_READ (2 << 13)
195 #define SDXC_IDMAC_DESC_CHECK (3 << 13)
196 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
197 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
198 #define SDXC_IDMAC_READ (6 << 13)
199 #define SDXC_IDMAC_WRITE (7 << 13)
200 #define SDXC_IDMAC_DESC_CLOSE (8 << 13)
201
202 /*
203 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
204 * Bits 0-12: buf1 size
205 * Bits 13-25: buf2 size
206 * Bits 26-31: not used
207 * Since we only ever set buf1 size, we can simply store it directly.
208 */
209 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
210 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
211 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
212 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
213 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
214 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
215 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
216
217 #define SDXC_CLK_400K 0
218 #define SDXC_CLK_25M 1
219 #define SDXC_CLK_50M 2
220 #define SDXC_CLK_50M_DDR 3
221 #define SDXC_CLK_50M_DDR_8BIT 4
222
223 #define SDXC_2X_TIMING_MODE BIT(31)
224
225 #define SDXC_CAL_START BIT(15)
226 #define SDXC_CAL_DONE BIT(14)
227 #define SDXC_CAL_DL_SHIFT 8
228 #define SDXC_CAL_DL_SW_EN BIT(7)
229 #define SDXC_CAL_DL_SW_SHIFT 0
230 #define SDXC_CAL_DL_MASK 0x3f
231
232 #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/
233
234 struct sunxi_mmc_clk_delay {
235 u32 output;
236 u32 sample;
237 };
238
239 struct sunxi_idma_des {
240 __le32 config;
241 __le32 buf_size;
242 __le32 buf_addr_ptr1;
243 __le32 buf_addr_ptr2;
244 };
245
246 struct sunxi_mmc_cfg {
247 u32 idma_des_size_bits;
248 const struct sunxi_mmc_clk_delay *clk_delays;
249
250 /* does the IP block support autocalibration? */
251 bool can_calibrate;
252
253 /* Does DATA0 needs to be masked while the clock is updated */
254 bool mask_data0;
255
256 /*
257 * hardware only supports new timing mode, either due to lack of
258 * a mode switch in the clock controller, or the mmc controller
259 * is permanently configured in the new timing mode, without the
260 * NTSR mode switch.
261 */
262 bool needs_new_timings;
263
264 /* clock hardware can switch between old and new timing modes */
265 bool ccu_has_timings_switch;
266 };
267
268 struct sunxi_mmc_host {
269 struct device *dev;
270 struct mmc_host *mmc;
271 struct reset_control *reset;
272 const struct sunxi_mmc_cfg *cfg;
273
274 /* IO mapping base */
275 void __iomem *reg_base;
276
277 /* clock management */
278 struct clk *clk_ahb;
279 struct clk *clk_mmc;
280 struct clk *clk_sample;
281 struct clk *clk_output;
282
283 /* irq */
284 spinlock_t lock;
285 int irq;
286 u32 int_sum;
287 u32 sdio_imask;
288
289 /* dma */
290 dma_addr_t sg_dma;
291 void *sg_cpu;
292 bool wait_dma;
293
294 struct mmc_request *mrq;
295 struct mmc_request *manual_stop_mrq;
296 int ferror;
297
298 /* vqmmc */
299 bool vqmmc_enabled;
300
301 /* timings */
302 bool use_new_timings;
303 };
304
305 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
306 {
307 unsigned long expire = jiffies + msecs_to_jiffies(250);
308 u32 rval;
309
310 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
311 do {
312 rval = mmc_readl(host, REG_GCTRL);
313 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
314
315 if (rval & SDXC_HARDWARE_RESET) {
316 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
317 return -EIO;
318 }
319
320 return 0;
321 }
322
323 static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
324 {
325 u32 rval;
326
327 if (sunxi_mmc_reset_host(host))
328 return -EIO;
329
330 /*
331 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
332 *
333 * TODO: sun9i has a larger FIFO and supports higher trigger values
334 */
335 mmc_writel(host, REG_FTRGL, 0x20070008);
336 /* Maximum timeout value */
337 mmc_writel(host, REG_TMOUT, 0xffffffff);
338 /* Unmask SDIO interrupt if needed */
339 mmc_writel(host, REG_IMASK, host->sdio_imask);
340 /* Clear all pending interrupts */
341 mmc_writel(host, REG_RINTR, 0xffffffff);
342 /* Debug register? undocumented */
343 mmc_writel(host, REG_DBGC, 0xdeb);
344 /* Enable CEATA support */
345 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
346 /* Set DMA descriptor list base address */
347 mmc_writel(host, REG_DLBA, host->sg_dma);
348
349 rval = mmc_readl(host, REG_GCTRL);
350 rval |= SDXC_INTERRUPT_ENABLE_BIT;
351 /* Undocumented, but found in Allwinner code */
352 rval &= ~SDXC_ACCESS_DONE_DIRECT;
353 mmc_writel(host, REG_GCTRL, rval);
354
355 return 0;
356 }
357
358 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
359 struct mmc_data *data)
360 {
361 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
362 dma_addr_t next_desc = host->sg_dma;
363 int i, max_len = (1 << host->cfg->idma_des_size_bits);
364
365 for (i = 0; i < data->sg_len; i++) {
366 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
367 SDXC_IDMAC_DES0_OWN |
368 SDXC_IDMAC_DES0_DIC);
369
370 if (data->sg[i].length == max_len)
371 pdes[i].buf_size = 0; /* 0 == max_len */
372 else
373 pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
374
375 next_desc += sizeof(struct sunxi_idma_des);
376 pdes[i].buf_addr_ptr1 =
377 cpu_to_le32(sg_dma_address(&data->sg[i]));
378 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
379 }
380
381 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
382 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
383 SDXC_IDMAC_DES0_ER);
384 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
385 pdes[i - 1].buf_addr_ptr2 = 0;
386
387 /*
388 * Avoid the io-store starting the idmac hitting io-mem before the
389 * descriptors hit the main-mem.
390 */
391 wmb();
392 }
393
394 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
395 struct mmc_data *data)
396 {
397 u32 i, dma_len;
398 struct scatterlist *sg;
399
400 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
401 mmc_get_dma_dir(data));
402 if (dma_len == 0) {
403 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
404 return -ENOMEM;
405 }
406
407 for_each_sg(data->sg, sg, data->sg_len, i) {
408 if (sg->offset & 3 || sg->length & 3) {
409 dev_err(mmc_dev(host->mmc),
410 "unaligned scatterlist: os %x length %d\n",
411 sg->offset, sg->length);
412 return -EINVAL;
413 }
414 }
415
416 return 0;
417 }
418
419 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
420 struct mmc_data *data)
421 {
422 u32 rval;
423
424 sunxi_mmc_init_idma_des(host, data);
425
426 rval = mmc_readl(host, REG_GCTRL);
427 rval |= SDXC_DMA_ENABLE_BIT;
428 mmc_writel(host, REG_GCTRL, rval);
429 rval |= SDXC_DMA_RESET;
430 mmc_writel(host, REG_GCTRL, rval);
431
432 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
433
434 if (!(data->flags & MMC_DATA_WRITE))
435 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
436
437 mmc_writel(host, REG_DMAC,
438 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
439 }
440
441 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
442 struct mmc_request *req)
443 {
444 u32 arg, cmd_val, ri;
445 unsigned long expire = jiffies + msecs_to_jiffies(1000);
446
447 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
448 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
449
450 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
451 cmd_val |= SD_IO_RW_DIRECT;
452 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
453 ((req->cmd->arg >> 28) & 0x7);
454 } else {
455 cmd_val |= MMC_STOP_TRANSMISSION;
456 arg = 0;
457 }
458
459 mmc_writel(host, REG_CARG, arg);
460 mmc_writel(host, REG_CMDR, cmd_val);
461
462 do {
463 ri = mmc_readl(host, REG_RINTR);
464 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
465 time_before(jiffies, expire));
466
467 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
468 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
469 if (req->stop)
470 req->stop->resp[0] = -ETIMEDOUT;
471 } else {
472 if (req->stop)
473 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
474 }
475
476 mmc_writel(host, REG_RINTR, 0xffff);
477 }
478
479 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
480 {
481 struct mmc_command *cmd = host->mrq->cmd;
482 struct mmc_data *data = host->mrq->data;
483
484 /* For some cmds timeout is normal with sd/mmc cards */
485 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
486 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
487 cmd->opcode == SD_IO_RW_DIRECT))
488 return;
489
490 dev_dbg(mmc_dev(host->mmc),
491 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
492 host->mmc->index, cmd->opcode,
493 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
494 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
495 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
496 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
497 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
498 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
499 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
500 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
501 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
502 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
503 );
504 }
505
506 /* Called in interrupt context! */
507 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
508 {
509 struct mmc_request *mrq = host->mrq;
510 struct mmc_data *data = mrq->data;
511 u32 rval;
512
513 mmc_writel(host, REG_IMASK, host->sdio_imask);
514 mmc_writel(host, REG_IDIE, 0);
515
516 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
517 sunxi_mmc_dump_errinfo(host);
518 mrq->cmd->error = -ETIMEDOUT;
519
520 if (data) {
521 data->error = -ETIMEDOUT;
522 host->manual_stop_mrq = mrq;
523 }
524
525 if (mrq->stop)
526 mrq->stop->error = -ETIMEDOUT;
527 } else {
528 if (mrq->cmd->flags & MMC_RSP_136) {
529 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
530 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
531 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
532 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
533 } else {
534 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
535 }
536
537 if (data)
538 data->bytes_xfered = data->blocks * data->blksz;
539 }
540
541 if (data) {
542 mmc_writel(host, REG_IDST, 0x337);
543 mmc_writel(host, REG_DMAC, 0);
544 rval = mmc_readl(host, REG_GCTRL);
545 rval |= SDXC_DMA_RESET;
546 mmc_writel(host, REG_GCTRL, rval);
547 rval &= ~SDXC_DMA_ENABLE_BIT;
548 mmc_writel(host, REG_GCTRL, rval);
549 rval |= SDXC_FIFO_RESET;
550 mmc_writel(host, REG_GCTRL, rval);
551 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
552 mmc_get_dma_dir(data));
553 }
554
555 mmc_writel(host, REG_RINTR, 0xffff);
556
557 host->mrq = NULL;
558 host->int_sum = 0;
559 host->wait_dma = false;
560
561 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
562 }
563
564 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
565 {
566 struct sunxi_mmc_host *host = dev_id;
567 struct mmc_request *mrq;
568 u32 msk_int, idma_int;
569 bool finalize = false;
570 bool sdio_int = false;
571 irqreturn_t ret = IRQ_HANDLED;
572
573 spin_lock(&host->lock);
574
575 idma_int = mmc_readl(host, REG_IDST);
576 msk_int = mmc_readl(host, REG_MISTA);
577
578 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
579 host->mrq, msk_int, idma_int);
580
581 mrq = host->mrq;
582 if (mrq) {
583 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
584 host->wait_dma = false;
585
586 host->int_sum |= msk_int;
587
588 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
589 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
590 !(host->int_sum & SDXC_COMMAND_DONE))
591 mmc_writel(host, REG_IMASK,
592 host->sdio_imask | SDXC_COMMAND_DONE);
593 /* Don't wait for dma on error */
594 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
595 finalize = true;
596 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
597 !host->wait_dma)
598 finalize = true;
599 }
600
601 if (msk_int & SDXC_SDIO_INTERRUPT)
602 sdio_int = true;
603
604 mmc_writel(host, REG_RINTR, msk_int);
605 mmc_writel(host, REG_IDST, idma_int);
606
607 if (finalize)
608 ret = sunxi_mmc_finalize_request(host);
609
610 spin_unlock(&host->lock);
611
612 if (finalize && ret == IRQ_HANDLED)
613 mmc_request_done(host->mmc, mrq);
614
615 if (sdio_int)
616 mmc_signal_sdio_irq(host->mmc);
617
618 return ret;
619 }
620
621 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
622 {
623 struct sunxi_mmc_host *host = dev_id;
624 struct mmc_request *mrq;
625 unsigned long iflags;
626
627 spin_lock_irqsave(&host->lock, iflags);
628 mrq = host->manual_stop_mrq;
629 spin_unlock_irqrestore(&host->lock, iflags);
630
631 if (!mrq) {
632 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
633 return IRQ_HANDLED;
634 }
635
636 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
637
638 /*
639 * We will never have more than one outstanding request,
640 * and we do not complete the request until after
641 * we've cleared host->manual_stop_mrq so we do not need to
642 * spin lock this function.
643 * Additionally we have wait states within this function
644 * so having it in a lock is a very bad idea.
645 */
646 sunxi_mmc_send_manual_stop(host, mrq);
647
648 spin_lock_irqsave(&host->lock, iflags);
649 host->manual_stop_mrq = NULL;
650 spin_unlock_irqrestore(&host->lock, iflags);
651
652 mmc_request_done(host->mmc, mrq);
653
654 return IRQ_HANDLED;
655 }
656
657 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
658 {
659 unsigned long expire = jiffies + msecs_to_jiffies(750);
660 u32 rval;
661
662 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
663 oclk_en ? "en" : "dis");
664
665 rval = mmc_readl(host, REG_CLKCR);
666 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
667
668 if (oclk_en)
669 rval |= SDXC_CARD_CLOCK_ON;
670 if (host->cfg->mask_data0)
671 rval |= SDXC_MASK_DATA0;
672
673 mmc_writel(host, REG_CLKCR, rval);
674
675 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
676 mmc_writel(host, REG_CMDR, rval);
677
678 do {
679 rval = mmc_readl(host, REG_CMDR);
680 } while (time_before(jiffies, expire) && (rval & SDXC_START));
681
682 /* clear irq status bits set by the command */
683 mmc_writel(host, REG_RINTR,
684 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
685
686 if (rval & SDXC_START) {
687 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
688 return -EIO;
689 }
690
691 if (host->cfg->mask_data0) {
692 rval = mmc_readl(host, REG_CLKCR);
693 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
694 }
695
696 return 0;
697 }
698
699 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
700 {
701 if (!host->cfg->can_calibrate)
702 return 0;
703
704 /*
705 * FIXME:
706 * This is not clear how the calibration is supposed to work
707 * yet. The best rate have been obtained by simply setting the
708 * delay to 0, as Allwinner does in its BSP.
709 *
710 * The only mode that doesn't have such a delay is HS400, that
711 * is in itself a TODO.
712 */
713 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
714
715 return 0;
716 }
717
718 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
719 struct mmc_ios *ios, u32 rate)
720 {
721 int index;
722
723 /* clk controller delays not used under new timings mode */
724 if (host->use_new_timings)
725 return 0;
726
727 /* some old controllers don't support delays */
728 if (!host->cfg->clk_delays)
729 return 0;
730
731 /* determine delays */
732 if (rate <= 400000) {
733 index = SDXC_CLK_400K;
734 } else if (rate <= 25000000) {
735 index = SDXC_CLK_25M;
736 } else if (rate <= 52000000) {
737 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
738 ios->timing != MMC_TIMING_MMC_DDR52) {
739 index = SDXC_CLK_50M;
740 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
741 index = SDXC_CLK_50M_DDR_8BIT;
742 } else {
743 index = SDXC_CLK_50M_DDR;
744 }
745 } else {
746 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
747 return -EINVAL;
748 }
749
750 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
751 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
752
753 return 0;
754 }
755
756 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
757 struct mmc_ios *ios)
758 {
759 struct mmc_host *mmc = host->mmc;
760 long rate;
761 u32 rval, clock = ios->clock, div = 1;
762 int ret;
763
764 ret = sunxi_mmc_oclk_onoff(host, 0);
765 if (ret)
766 return ret;
767
768 /* Our clock is gated now */
769 mmc->actual_clock = 0;
770
771 if (!ios->clock)
772 return 0;
773
774 /*
775 * Under the old timing mode, 8 bit DDR requires the module
776 * clock to be double the card clock. Under the new timing
777 * mode, all DDR modes require a doubled module clock.
778 *
779 * We currently only support the standard MMC DDR52 mode.
780 * This block should be updated once support for other DDR
781 * modes is added.
782 */
783 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
784 (host->use_new_timings ||
785 ios->bus_width == MMC_BUS_WIDTH_8)) {
786 div = 2;
787 clock <<= 1;
788 }
789
790 if (host->use_new_timings && host->cfg->ccu_has_timings_switch) {
791 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
792 if (ret) {
793 dev_err(mmc_dev(mmc),
794 "error setting new timing mode\n");
795 return ret;
796 }
797 }
798
799 rate = clk_round_rate(host->clk_mmc, clock);
800 if (rate < 0) {
801 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
802 clock, rate);
803 return rate;
804 }
805 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
806 clock, rate);
807
808 /* setting clock rate */
809 ret = clk_set_rate(host->clk_mmc, rate);
810 if (ret) {
811 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
812 rate, ret);
813 return ret;
814 }
815
816 /* set internal divider */
817 rval = mmc_readl(host, REG_CLKCR);
818 rval &= ~0xff;
819 rval |= div - 1;
820 mmc_writel(host, REG_CLKCR, rval);
821
822 /* update card clock rate to account for internal divider */
823 rate /= div;
824
825 /*
826 * Configure the controller to use the new timing mode if needed.
827 * On controllers that only support the new timing mode, such as
828 * the eMMC controller on the A64, this register does not exist,
829 * and any writes to it are ignored.
830 */
831 if (host->use_new_timings) {
832 /* Don't touch the delay bits */
833 rval = mmc_readl(host, REG_SD_NTSR);
834 rval |= SDXC_2X_TIMING_MODE;
835 mmc_writel(host, REG_SD_NTSR, rval);
836 }
837
838 /* sunxi_mmc_clk_set_phase expects the actual card clock rate */
839 ret = sunxi_mmc_clk_set_phase(host, ios, rate);
840 if (ret)
841 return ret;
842
843 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
844 if (ret)
845 return ret;
846
847 /*
848 * FIXME:
849 *
850 * In HS400 we'll also need to calibrate the data strobe
851 * signal. This should only happen on the MMC2 controller (at
852 * least on the A64).
853 */
854
855 ret = sunxi_mmc_oclk_onoff(host, 1);
856 if (ret)
857 return ret;
858
859 /* And we just enabled our clock back */
860 mmc->actual_clock = rate;
861
862 return 0;
863 }
864
865 static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host,
866 unsigned char width)
867 {
868 switch (width) {
869 case MMC_BUS_WIDTH_1:
870 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
871 break;
872 case MMC_BUS_WIDTH_4:
873 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
874 break;
875 case MMC_BUS_WIDTH_8:
876 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
877 break;
878 }
879 }
880
881 static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios)
882 {
883 u32 rval;
884
885 /* set ddr mode */
886 rval = mmc_readl(host, REG_GCTRL);
887 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
888 ios->timing == MMC_TIMING_MMC_DDR52)
889 rval |= SDXC_DDR_MODE;
890 else
891 rval &= ~SDXC_DDR_MODE;
892 mmc_writel(host, REG_GCTRL, rval);
893
894 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
895 /* Android code had a usleep_range(50000, 55000); here */
896 }
897
898 static void sunxi_mmc_card_power(struct sunxi_mmc_host *host,
899 struct mmc_ios *ios)
900 {
901 struct mmc_host *mmc = host->mmc;
902
903 switch (ios->power_mode) {
904 case MMC_POWER_UP:
905 dev_dbg(mmc_dev(mmc), "Powering card up\n");
906
907 if (!IS_ERR(mmc->supply.vmmc)) {
908 host->ferror = mmc_regulator_set_ocr(mmc,
909 mmc->supply.vmmc,
910 ios->vdd);
911 if (host->ferror)
912 return;
913 }
914
915 if (!IS_ERR(mmc->supply.vqmmc)) {
916 host->ferror = regulator_enable(mmc->supply.vqmmc);
917 if (host->ferror) {
918 dev_err(mmc_dev(mmc),
919 "failed to enable vqmmc\n");
920 return;
921 }
922 host->vqmmc_enabled = true;
923 }
924 break;
925
926 case MMC_POWER_OFF:
927 dev_dbg(mmc_dev(mmc), "Powering card off\n");
928
929 if (!IS_ERR(mmc->supply.vmmc))
930 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
931
932 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
933 regulator_disable(mmc->supply.vqmmc);
934
935 host->vqmmc_enabled = false;
936 break;
937
938 default:
939 dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n");
940 break;
941 }
942 }
943
944 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
945 {
946 struct sunxi_mmc_host *host = mmc_priv(mmc);
947
948 sunxi_mmc_card_power(host, ios);
949 sunxi_mmc_set_bus_width(host, ios->bus_width);
950 sunxi_mmc_set_clk(host, ios);
951 }
952
953 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
954 {
955 int ret;
956
957 /* vqmmc regulator is available */
958 if (!IS_ERR(mmc->supply.vqmmc)) {
959 ret = mmc_regulator_set_vqmmc(mmc, ios);
960 return ret < 0 ? ret : 0;
961 }
962
963 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
964 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
965 return 0;
966
967 return -EINVAL;
968 }
969
970 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
971 {
972 struct sunxi_mmc_host *host = mmc_priv(mmc);
973 unsigned long flags;
974 u32 imask;
975
976 if (enable)
977 pm_runtime_get_noresume(host->dev);
978
979 spin_lock_irqsave(&host->lock, flags);
980
981 imask = mmc_readl(host, REG_IMASK);
982 if (enable) {
983 host->sdio_imask = SDXC_SDIO_INTERRUPT;
984 imask |= SDXC_SDIO_INTERRUPT;
985 } else {
986 host->sdio_imask = 0;
987 imask &= ~SDXC_SDIO_INTERRUPT;
988 }
989 mmc_writel(host, REG_IMASK, imask);
990 spin_unlock_irqrestore(&host->lock, flags);
991
992 if (!enable)
993 pm_runtime_put_noidle(host->mmc->parent);
994 }
995
996 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
997 {
998 struct sunxi_mmc_host *host = mmc_priv(mmc);
999 mmc_writel(host, REG_HWRST, 0);
1000 udelay(10);
1001 mmc_writel(host, REG_HWRST, 1);
1002 udelay(300);
1003 }
1004
1005 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
1006 {
1007 struct sunxi_mmc_host *host = mmc_priv(mmc);
1008 struct mmc_command *cmd = mrq->cmd;
1009 struct mmc_data *data = mrq->data;
1010 unsigned long iflags;
1011 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
1012 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
1013 bool wait_dma = host->wait_dma;
1014 int ret;
1015
1016 /* Check for set_ios errors (should never happen) */
1017 if (host->ferror) {
1018 mrq->cmd->error = host->ferror;
1019 mmc_request_done(mmc, mrq);
1020 return;
1021 }
1022
1023 if (data) {
1024 ret = sunxi_mmc_map_dma(host, data);
1025 if (ret < 0) {
1026 dev_err(mmc_dev(mmc), "map DMA failed\n");
1027 cmd->error = ret;
1028 data->error = ret;
1029 mmc_request_done(mmc, mrq);
1030 return;
1031 }
1032 }
1033
1034 if (cmd->opcode == MMC_GO_IDLE_STATE) {
1035 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
1036 imask |= SDXC_COMMAND_DONE;
1037 }
1038
1039 if (cmd->flags & MMC_RSP_PRESENT) {
1040 cmd_val |= SDXC_RESP_EXPIRE;
1041 if (cmd->flags & MMC_RSP_136)
1042 cmd_val |= SDXC_LONG_RESPONSE;
1043 if (cmd->flags & MMC_RSP_CRC)
1044 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
1045
1046 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
1047 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
1048
1049 if (cmd->data->stop) {
1050 imask |= SDXC_AUTO_COMMAND_DONE;
1051 cmd_val |= SDXC_SEND_AUTO_STOP;
1052 } else {
1053 imask |= SDXC_DATA_OVER;
1054 }
1055
1056 if (cmd->data->flags & MMC_DATA_WRITE)
1057 cmd_val |= SDXC_WRITE;
1058 else
1059 wait_dma = true;
1060 } else {
1061 imask |= SDXC_COMMAND_DONE;
1062 }
1063 } else {
1064 imask |= SDXC_COMMAND_DONE;
1065 }
1066
1067 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
1068 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
1069 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
1070
1071 spin_lock_irqsave(&host->lock, iflags);
1072
1073 if (host->mrq || host->manual_stop_mrq) {
1074 spin_unlock_irqrestore(&host->lock, iflags);
1075
1076 if (data)
1077 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1078 mmc_get_dma_dir(data));
1079
1080 dev_err(mmc_dev(mmc), "request already pending\n");
1081 mrq->cmd->error = -EBUSY;
1082 mmc_request_done(mmc, mrq);
1083 return;
1084 }
1085
1086 if (data) {
1087 mmc_writel(host, REG_BLKSZ, data->blksz);
1088 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
1089 sunxi_mmc_start_dma(host, data);
1090 }
1091
1092 host->mrq = mrq;
1093 host->wait_dma = wait_dma;
1094 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
1095 mmc_writel(host, REG_CARG, cmd->arg);
1096 mmc_writel(host, REG_CMDR, cmd_val);
1097
1098 spin_unlock_irqrestore(&host->lock, iflags);
1099 }
1100
1101 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
1102 {
1103 struct sunxi_mmc_host *host = mmc_priv(mmc);
1104
1105 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
1106 }
1107
1108 static const struct mmc_host_ops sunxi_mmc_ops = {
1109 .request = sunxi_mmc_request,
1110 .set_ios = sunxi_mmc_set_ios,
1111 .get_ro = mmc_gpio_get_ro,
1112 .get_cd = mmc_gpio_get_cd,
1113 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
1114 .start_signal_voltage_switch = sunxi_mmc_volt_switch,
1115 .hw_reset = sunxi_mmc_hw_reset,
1116 .card_busy = sunxi_mmc_card_busy,
1117 };
1118
1119 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
1120 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1121 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1122 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
1123 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
1124 /* Value from A83T "new timing mode". Works but might not be right. */
1125 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
1126 };
1127
1128 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
1129 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1130 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1131 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
1132 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
1133 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
1134 };
1135
1136 static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
1137 .idma_des_size_bits = 13,
1138 .clk_delays = NULL,
1139 .can_calibrate = false,
1140 };
1141
1142 static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
1143 .idma_des_size_bits = 16,
1144 .clk_delays = NULL,
1145 .can_calibrate = false,
1146 };
1147
1148 static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
1149 .idma_des_size_bits = 16,
1150 .clk_delays = sunxi_mmc_clk_delays,
1151 .can_calibrate = false,
1152 };
1153
1154 static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = {
1155 .idma_des_size_bits = 16,
1156 .clk_delays = sunxi_mmc_clk_delays,
1157 .can_calibrate = false,
1158 .ccu_has_timings_switch = true,
1159 };
1160
1161 static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1162 .idma_des_size_bits = 16,
1163 .clk_delays = sun9i_mmc_clk_delays,
1164 .can_calibrate = false,
1165 };
1166
1167 static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
1168 .idma_des_size_bits = 16,
1169 .clk_delays = NULL,
1170 .can_calibrate = true,
1171 .mask_data0 = true,
1172 .needs_new_timings = true,
1173 };
1174
1175 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
1176 .idma_des_size_bits = 13,
1177 .clk_delays = NULL,
1178 .can_calibrate = true,
1179 .needs_new_timings = true,
1180 };
1181
1182 static const struct of_device_id sunxi_mmc_of_match[] = {
1183 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1184 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
1185 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
1186 { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg },
1187 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
1188 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
1189 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
1190 { /* sentinel */ }
1191 };
1192 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1193
1194 static int sunxi_mmc_enable(struct sunxi_mmc_host *host)
1195 {
1196 int ret;
1197
1198 if (!IS_ERR(host->reset)) {
1199 ret = reset_control_reset(host->reset);
1200 if (ret) {
1201 dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n",
1202 ret);
1203 return ret;
1204 }
1205 }
1206
1207 ret = clk_prepare_enable(host->clk_ahb);
1208 if (ret) {
1209 dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret);
1210 goto error_assert_reset;
1211 }
1212
1213 ret = clk_prepare_enable(host->clk_mmc);
1214 if (ret) {
1215 dev_err(host->dev, "Enable mmc clk err %d\n", ret);
1216 goto error_disable_clk_ahb;
1217 }
1218
1219 ret = clk_prepare_enable(host->clk_output);
1220 if (ret) {
1221 dev_err(host->dev, "Enable output clk err %d\n", ret);
1222 goto error_disable_clk_mmc;
1223 }
1224
1225 ret = clk_prepare_enable(host->clk_sample);
1226 if (ret) {
1227 dev_err(host->dev, "Enable sample clk err %d\n", ret);
1228 goto error_disable_clk_output;
1229 }
1230
1231 /*
1232 * Sometimes the controller asserts the irq on boot for some reason,
1233 * make sure the controller is in a sane state before enabling irqs.
1234 */
1235 ret = sunxi_mmc_reset_host(host);
1236 if (ret)
1237 goto error_disable_clk_sample;
1238
1239 return 0;
1240
1241 error_disable_clk_sample:
1242 clk_disable_unprepare(host->clk_sample);
1243 error_disable_clk_output:
1244 clk_disable_unprepare(host->clk_output);
1245 error_disable_clk_mmc:
1246 clk_disable_unprepare(host->clk_mmc);
1247 error_disable_clk_ahb:
1248 clk_disable_unprepare(host->clk_ahb);
1249 error_assert_reset:
1250 if (!IS_ERR(host->reset))
1251 reset_control_assert(host->reset);
1252 return ret;
1253 }
1254
1255 static void sunxi_mmc_disable(struct sunxi_mmc_host *host)
1256 {
1257 sunxi_mmc_reset_host(host);
1258
1259 clk_disable_unprepare(host->clk_sample);
1260 clk_disable_unprepare(host->clk_output);
1261 clk_disable_unprepare(host->clk_mmc);
1262 clk_disable_unprepare(host->clk_ahb);
1263
1264 if (!IS_ERR(host->reset))
1265 reset_control_assert(host->reset);
1266 }
1267
1268 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1269 struct platform_device *pdev)
1270 {
1271 int ret;
1272
1273 host->cfg = of_device_get_match_data(&pdev->dev);
1274 if (!host->cfg)
1275 return -EINVAL;
1276
1277 ret = mmc_regulator_get_supply(host->mmc);
1278 if (ret)
1279 return ret;
1280
1281 host->reg_base = devm_platform_ioremap_resource(pdev, 0);
1282 if (IS_ERR(host->reg_base))
1283 return PTR_ERR(host->reg_base);
1284
1285 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1286 if (IS_ERR(host->clk_ahb)) {
1287 dev_err(&pdev->dev, "Could not get ahb clock\n");
1288 return PTR_ERR(host->clk_ahb);
1289 }
1290
1291 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1292 if (IS_ERR(host->clk_mmc)) {
1293 dev_err(&pdev->dev, "Could not get mmc clock\n");
1294 return PTR_ERR(host->clk_mmc);
1295 }
1296
1297 if (host->cfg->clk_delays) {
1298 host->clk_output = devm_clk_get(&pdev->dev, "output");
1299 if (IS_ERR(host->clk_output)) {
1300 dev_err(&pdev->dev, "Could not get output clock\n");
1301 return PTR_ERR(host->clk_output);
1302 }
1303
1304 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1305 if (IS_ERR(host->clk_sample)) {
1306 dev_err(&pdev->dev, "Could not get sample clock\n");
1307 return PTR_ERR(host->clk_sample);
1308 }
1309 }
1310
1311 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1312 "ahb");
1313 if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1314 return PTR_ERR(host->reset);
1315
1316 ret = sunxi_mmc_enable(host);
1317 if (ret)
1318 return ret;
1319
1320 host->irq = platform_get_irq(pdev, 0);
1321 if (host->irq <= 0) {
1322 ret = -EINVAL;
1323 goto error_disable_mmc;
1324 }
1325
1326 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1327 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1328
1329 error_disable_mmc:
1330 sunxi_mmc_disable(host);
1331 return ret;
1332 }
1333
1334 static int sunxi_mmc_probe(struct platform_device *pdev)
1335 {
1336 struct sunxi_mmc_host *host;
1337 struct mmc_host *mmc;
1338 int ret;
1339
1340 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1341 if (!mmc) {
1342 dev_err(&pdev->dev, "mmc alloc host failed\n");
1343 return -ENOMEM;
1344 }
1345 platform_set_drvdata(pdev, mmc);
1346
1347 host = mmc_priv(mmc);
1348 host->dev = &pdev->dev;
1349 host->mmc = mmc;
1350 spin_lock_init(&host->lock);
1351
1352 ret = sunxi_mmc_resource_request(host, pdev);
1353 if (ret)
1354 goto error_free_host;
1355
1356 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1357 &host->sg_dma, GFP_KERNEL);
1358 if (!host->sg_cpu) {
1359 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1360 ret = -ENOMEM;
1361 goto error_free_host;
1362 }
1363
1364 if (host->cfg->ccu_has_timings_switch) {
1365 /*
1366 * Supports both old and new timing modes.
1367 * Try setting the clk to new timing mode.
1368 */
1369 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
1370
1371 /* And check the result */
1372 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc);
1373 if (ret < 0) {
1374 /*
1375 * For whatever reason we were not able to get
1376 * the current active mode. Default to old mode.
1377 */
1378 dev_warn(&pdev->dev, "MMC clk timing mode unknown\n");
1379 host->use_new_timings = false;
1380 } else {
1381 host->use_new_timings = !!ret;
1382 }
1383 } else if (host->cfg->needs_new_timings) {
1384 /* Supports new timing mode only */
1385 host->use_new_timings = true;
1386 }
1387
1388 mmc->ops = &sunxi_mmc_ops;
1389 mmc->max_blk_count = 8192;
1390 mmc->max_blk_size = 4096;
1391 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1392 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
1393 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
1394 /* 400kHz ~ 52MHz */
1395 mmc->f_min = 400000;
1396 mmc->f_max = 52000000;
1397 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1398 MMC_CAP_SDIO_IRQ;
1399
1400 /*
1401 * Some H5 devices do not have signal traces precise enough to
1402 * use HS DDR mode for their eMMC chips.
1403 *
1404 * We still enable HS DDR modes for all the other controller
1405 * variants that support them.
1406 */
1407 if ((host->cfg->clk_delays || host->use_new_timings) &&
1408 !of_device_is_compatible(pdev->dev.of_node,
1409 "allwinner,sun50i-h5-emmc"))
1410 mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1411
1412 ret = mmc_of_parse(mmc);
1413 if (ret)
1414 goto error_free_dma;
1415
1416 /*
1417 * If we don't support delay chains in the SoC, we can't use any
1418 * of the higher speed modes. Mask them out in case the device
1419 * tree specifies the properties for them, which gets added to
1420 * the caps by mmc_of_parse() above.
1421 */
1422 if (!(host->cfg->clk_delays || host->use_new_timings)) {
1423 mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR |
1424 MMC_CAP_1_2V_DDR | MMC_CAP_UHS);
1425 mmc->caps2 &= ~MMC_CAP2_HS200;
1426 }
1427
1428 /* TODO: This driver doesn't support HS400 mode yet */
1429 mmc->caps2 &= ~MMC_CAP2_HS400;
1430
1431 ret = sunxi_mmc_init_host(host);
1432 if (ret)
1433 goto error_free_dma;
1434
1435 pm_runtime_set_active(&pdev->dev);
1436 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1437 pm_runtime_use_autosuspend(&pdev->dev);
1438 pm_runtime_enable(&pdev->dev);
1439
1440 ret = mmc_add_host(mmc);
1441 if (ret)
1442 goto error_free_dma;
1443
1444 dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n",
1445 mmc->max_req_size >> 10,
1446 host->use_new_timings ? ", uses new timings mode" : "");
1447
1448 return 0;
1449
1450 error_free_dma:
1451 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1452 error_free_host:
1453 mmc_free_host(mmc);
1454 return ret;
1455 }
1456
1457 static int sunxi_mmc_remove(struct platform_device *pdev)
1458 {
1459 struct mmc_host *mmc = platform_get_drvdata(pdev);
1460 struct sunxi_mmc_host *host = mmc_priv(mmc);
1461
1462 mmc_remove_host(mmc);
1463 pm_runtime_force_suspend(&pdev->dev);
1464 disable_irq(host->irq);
1465 sunxi_mmc_disable(host);
1466 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1467 mmc_free_host(mmc);
1468
1469 return 0;
1470 }
1471
1472 #ifdef CONFIG_PM
1473 static int sunxi_mmc_runtime_resume(struct device *dev)
1474 {
1475 struct mmc_host *mmc = dev_get_drvdata(dev);
1476 struct sunxi_mmc_host *host = mmc_priv(mmc);
1477 int ret;
1478
1479 ret = sunxi_mmc_enable(host);
1480 if (ret)
1481 return ret;
1482
1483 sunxi_mmc_init_host(host);
1484 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width);
1485 sunxi_mmc_set_clk(host, &mmc->ios);
1486 enable_irq(host->irq);
1487
1488 return 0;
1489 }
1490
1491 static int sunxi_mmc_runtime_suspend(struct device *dev)
1492 {
1493 struct mmc_host *mmc = dev_get_drvdata(dev);
1494 struct sunxi_mmc_host *host = mmc_priv(mmc);
1495
1496 /*
1497 * When clocks are off, it's possible receiving
1498 * fake interrupts, which will stall the system.
1499 * Disabling the irq will prevent this.
1500 */
1501 disable_irq(host->irq);
1502 sunxi_mmc_reset_host(host);
1503 sunxi_mmc_disable(host);
1504
1505 return 0;
1506 }
1507 #endif
1508
1509 static const struct dev_pm_ops sunxi_mmc_pm_ops = {
1510 SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,
1511 sunxi_mmc_runtime_resume,
1512 NULL)
1513 };
1514
1515 static struct platform_driver sunxi_mmc_driver = {
1516 .driver = {
1517 .name = "sunxi-mmc",
1518 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1519 .of_match_table = sunxi_mmc_of_match,
1520 .pm = &sunxi_mmc_pm_ops,
1521 },
1522 .probe = sunxi_mmc_probe,
1523 .remove = sunxi_mmc_remove,
1524 };
1525 module_platform_driver(sunxi_mmc_driver);
1526
1527 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1528 MODULE_LICENSE("GPL v2");
1529 MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>");
1530 MODULE_ALIAS("platform:sunxi-mmc");
Linux with added FPC-III support