1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (C) 2017-2018 Socionext Inc.
4 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 #include <linux/bitfield.h>
7 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/mfd/tmio.h>
12 #include <linux/mmc/host.h>
13 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
22 #define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16)
23 #define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10)
24 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop
25 #define UNIPHIER_SD_CC_EXT_MODE 0x1b0
26 #define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1)
27 #define UNIPHIER_SD_HOST_MODE 0x1c8
28 #define UNIPHIER_SD_VOLT 0x1e4
29 #define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0)
30 #define UNIPHIER_SD_VOLT_OFF 0
31 #define UNIPHIER_SD_VOLT_330 1 // 3.3V signal
32 #define UNIPHIER_SD_VOLT_180 2 // 1.8V signal
33 #define UNIPHIER_SD_DMA_MODE 0x410
34 #define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16)
35 #define UNIPHIER_SD_DMA_MODE_DIR_TO_DEV 0
36 #define UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1
37 #define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4)
38 #define UNIPHIER_SD_DMA_MODE_WIDTH_8 0
39 #define UNIPHIER_SD_DMA_MODE_WIDTH_16 1
40 #define UNIPHIER_SD_DMA_MODE_WIDTH_32 2
41 #define UNIPHIER_SD_DMA_MODE_WIDTH_64 3
42 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed
43 #define UNIPHIER_SD_DMA_CTL 0x414
44 #define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared)
45 #define UNIPHIER_SD_DMA_RST 0x418
46 #define UNIPHIER_SD_DMA_RST_CH1 BIT(9)
47 #define UNIPHIER_SD_DMA_RST_CH0 BIT(8)
48 #define UNIPHIER_SD_DMA_ADDR_L 0x440
49 #define UNIPHIER_SD_DMA_ADDR_H 0x444
52 * IP is extended to support various features: built-in DMA engine,
53 * 1/1024 divisor, etc.
55 #define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0)
56 /* RX channel of the built-in DMA controller is broken (Pro5) */
57 #define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1)
59 struct uniphier_sd_priv
{
60 struct tmio_mmc_data tmio_data
;
61 struct pinctrl
*pinctrl
;
62 struct pinctrl_state
*pinstate_uhs
;
64 struct reset_control
*rst
;
65 struct reset_control
*rst_br
;
66 struct reset_control
*rst_hw
;
67 struct dma_chan
*chan
;
68 enum dma_data_direction dma_dir
;
69 unsigned long clk_rate
;
73 static void *uniphier_sd_priv(struct tmio_mmc_host
*host
)
75 return container_of(host
->pdata
, struct uniphier_sd_priv
, tmio_data
);
78 static void uniphier_sd_dma_endisable(struct tmio_mmc_host
*host
, int enable
)
80 sd_ctrl_write16(host
, CTL_DMA_ENABLE
, enable
? DMA_ENABLE_DMASDRW
: 0);
83 /* external DMA engine */
84 static void uniphier_sd_external_dma_issue(unsigned long arg
)
86 struct tmio_mmc_host
*host
= (void *)arg
;
87 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
89 uniphier_sd_dma_endisable(host
, 1);
90 dma_async_issue_pending(priv
->chan
);
93 static void uniphier_sd_external_dma_callback(void *param
,
94 const struct dmaengine_result
*result
)
96 struct tmio_mmc_host
*host
= param
;
97 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
100 dma_unmap_sg(mmc_dev(host
->mmc
), host
->sg_ptr
, host
->sg_len
,
103 spin_lock_irqsave(&host
->lock
, flags
);
105 if (result
->result
== DMA_TRANS_NOERROR
) {
107 * When the external DMA engine is enabled, strangely enough,
108 * the DATAEND flag can be asserted even if the DMA engine has
109 * not been kicked yet. Enable the TMIO_STAT_DATAEND irq only
110 * after we make sure the DMA engine finishes the transfer,
111 * hence, in this callback.
113 tmio_mmc_enable_mmc_irqs(host
, TMIO_STAT_DATAEND
);
115 host
->data
->error
= -ETIMEDOUT
;
116 tmio_mmc_do_data_irq(host
);
119 spin_unlock_irqrestore(&host
->lock
, flags
);
122 static void uniphier_sd_external_dma_start(struct tmio_mmc_host
*host
,
123 struct mmc_data
*data
)
125 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
126 enum dma_transfer_direction dma_tx_dir
;
127 struct dma_async_tx_descriptor
*desc
;
134 if (data
->flags
& MMC_DATA_READ
) {
135 priv
->dma_dir
= DMA_FROM_DEVICE
;
136 dma_tx_dir
= DMA_DEV_TO_MEM
;
138 priv
->dma_dir
= DMA_TO_DEVICE
;
139 dma_tx_dir
= DMA_MEM_TO_DEV
;
142 sg_len
= dma_map_sg(mmc_dev(host
->mmc
), host
->sg_ptr
, host
->sg_len
,
147 desc
= dmaengine_prep_slave_sg(priv
->chan
, host
->sg_ptr
, sg_len
,
148 dma_tx_dir
, DMA_CTRL_ACK
);
152 desc
->callback_result
= uniphier_sd_external_dma_callback
;
153 desc
->callback_param
= host
;
155 cookie
= dmaengine_submit(desc
);
164 dma_unmap_sg(mmc_dev(host
->mmc
), host
->sg_ptr
, host
->sg_len
,
167 uniphier_sd_dma_endisable(host
, 0);
170 static void uniphier_sd_external_dma_enable(struct tmio_mmc_host
*host
,
175 static void uniphier_sd_external_dma_request(struct tmio_mmc_host
*host
,
176 struct tmio_mmc_data
*pdata
)
178 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
179 struct dma_chan
*chan
;
181 chan
= dma_request_chan(mmc_dev(host
->mmc
), "rx-tx");
183 dev_warn(mmc_dev(host
->mmc
),
184 "failed to request DMA channel. falling back to PIO\n");
185 return; /* just use PIO even for -EPROBE_DEFER */
188 /* this driver uses a single channel for both RX an TX */
190 host
->chan_rx
= chan
;
191 host
->chan_tx
= chan
;
193 tasklet_init(&host
->dma_issue
, uniphier_sd_external_dma_issue
,
194 (unsigned long)host
);
197 static void uniphier_sd_external_dma_release(struct tmio_mmc_host
*host
)
199 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
202 dma_release_channel(priv
->chan
);
205 static void uniphier_sd_external_dma_abort(struct tmio_mmc_host
*host
)
207 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
209 uniphier_sd_dma_endisable(host
, 0);
212 dmaengine_terminate_sync(priv
->chan
);
215 static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host
*host
)
217 uniphier_sd_dma_endisable(host
, 0);
219 tmio_mmc_do_data_irq(host
);
222 static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops
= {
223 .start
= uniphier_sd_external_dma_start
,
224 .enable
= uniphier_sd_external_dma_enable
,
225 .request
= uniphier_sd_external_dma_request
,
226 .release
= uniphier_sd_external_dma_release
,
227 .abort
= uniphier_sd_external_dma_abort
,
228 .dataend
= uniphier_sd_external_dma_dataend
,
231 static void uniphier_sd_internal_dma_issue(unsigned long arg
)
233 struct tmio_mmc_host
*host
= (void *)arg
;
236 spin_lock_irqsave(&host
->lock
, flags
);
237 tmio_mmc_enable_mmc_irqs(host
, TMIO_STAT_DATAEND
);
238 spin_unlock_irqrestore(&host
->lock
, flags
);
240 uniphier_sd_dma_endisable(host
, 1);
241 writel(UNIPHIER_SD_DMA_CTL_START
, host
->ctl
+ UNIPHIER_SD_DMA_CTL
);
244 static void uniphier_sd_internal_dma_start(struct tmio_mmc_host
*host
,
245 struct mmc_data
*data
)
247 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
248 struct scatterlist
*sg
= host
->sg_ptr
;
250 unsigned int dma_mode_dir
;
254 if ((data
->flags
& MMC_DATA_READ
) && !host
->chan_rx
)
257 if (WARN_ON(host
->sg_len
!= 1))
260 if (!IS_ALIGNED(sg
->offset
, 8))
263 if (data
->flags
& MMC_DATA_READ
) {
264 priv
->dma_dir
= DMA_FROM_DEVICE
;
265 dma_mode_dir
= UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV
;
267 priv
->dma_dir
= DMA_TO_DEVICE
;
268 dma_mode_dir
= UNIPHIER_SD_DMA_MODE_DIR_TO_DEV
;
271 sg_len
= dma_map_sg(mmc_dev(host
->mmc
), sg
, 1, priv
->dma_dir
);
275 dma_mode
= FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK
, dma_mode_dir
);
276 dma_mode
|= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK
,
277 UNIPHIER_SD_DMA_MODE_WIDTH_64
);
278 dma_mode
|= UNIPHIER_SD_DMA_MODE_ADDR_INC
;
280 writel(dma_mode
, host
->ctl
+ UNIPHIER_SD_DMA_MODE
);
282 dma_addr
= sg_dma_address(data
->sg
);
283 writel(lower_32_bits(dma_addr
), host
->ctl
+ UNIPHIER_SD_DMA_ADDR_L
);
284 writel(upper_32_bits(dma_addr
), host
->ctl
+ UNIPHIER_SD_DMA_ADDR_H
);
290 uniphier_sd_dma_endisable(host
, 0);
293 static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host
*host
,
298 static void uniphier_sd_internal_dma_request(struct tmio_mmc_host
*host
,
299 struct tmio_mmc_data
*pdata
)
301 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
304 * Due to a hardware bug, Pro5 cannot use DMA for RX.
305 * We can still use DMA for TX, but PIO for RX.
307 if (!(priv
->caps
& UNIPHIER_SD_CAP_BROKEN_DMA_RX
))
308 host
->chan_rx
= (void *)0xdeadbeaf;
310 host
->chan_tx
= (void *)0xdeadbeaf;
312 tasklet_init(&host
->dma_issue
, uniphier_sd_internal_dma_issue
,
313 (unsigned long)host
);
316 static void uniphier_sd_internal_dma_release(struct tmio_mmc_host
*host
)
318 /* Each value is set to zero to assume "disabling" each DMA */
319 host
->chan_rx
= NULL
;
320 host
->chan_tx
= NULL
;
323 static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host
*host
)
327 uniphier_sd_dma_endisable(host
, 0);
329 tmp
= readl(host
->ctl
+ UNIPHIER_SD_DMA_RST
);
330 tmp
&= ~(UNIPHIER_SD_DMA_RST_CH1
| UNIPHIER_SD_DMA_RST_CH0
);
331 writel(tmp
, host
->ctl
+ UNIPHIER_SD_DMA_RST
);
333 tmp
|= UNIPHIER_SD_DMA_RST_CH1
| UNIPHIER_SD_DMA_RST_CH0
;
334 writel(tmp
, host
->ctl
+ UNIPHIER_SD_DMA_RST
);
337 static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host
*host
)
339 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
341 uniphier_sd_dma_endisable(host
, 0);
342 dma_unmap_sg(mmc_dev(host
->mmc
), host
->sg_ptr
, 1, priv
->dma_dir
);
344 tmio_mmc_do_data_irq(host
);
347 static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops
= {
348 .start
= uniphier_sd_internal_dma_start
,
349 .enable
= uniphier_sd_internal_dma_enable
,
350 .request
= uniphier_sd_internal_dma_request
,
351 .release
= uniphier_sd_internal_dma_release
,
352 .abort
= uniphier_sd_internal_dma_abort
,
353 .dataend
= uniphier_sd_internal_dma_dataend
,
356 static int uniphier_sd_clk_enable(struct tmio_mmc_host
*host
)
358 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
359 struct mmc_host
*mmc
= host
->mmc
;
362 ret
= clk_prepare_enable(priv
->clk
);
366 ret
= clk_set_rate(priv
->clk
, ULONG_MAX
);
370 priv
->clk_rate
= clk_get_rate(priv
->clk
);
372 /* If max-frequency property is set, use it. */
374 mmc
->f_max
= priv
->clk_rate
;
377 * 1/512 is the finest divisor in the original IP. Newer versions
378 * also supports 1/1024 divisor. (UniPhier-specific extension)
380 if (priv
->caps
& UNIPHIER_SD_CAP_EXTENDED_IP
)
381 mmc
->f_min
= priv
->clk_rate
/ 1024;
383 mmc
->f_min
= priv
->clk_rate
/ 512;
385 ret
= reset_control_deassert(priv
->rst
);
389 ret
= reset_control_deassert(priv
->rst_br
);
396 reset_control_assert(priv
->rst
);
398 clk_disable_unprepare(priv
->clk
);
403 static void uniphier_sd_clk_disable(struct tmio_mmc_host
*host
)
405 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
407 reset_control_assert(priv
->rst_br
);
408 reset_control_assert(priv
->rst
);
409 clk_disable_unprepare(priv
->clk
);
412 static void uniphier_sd_hw_reset(struct mmc_host
*mmc
)
414 struct tmio_mmc_host
*host
= mmc_priv(mmc
);
415 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
417 reset_control_assert(priv
->rst_hw
);
418 /* For eMMC, minimum is 1us but give it 9us for good measure */
420 reset_control_deassert(priv
->rst_hw
);
421 /* For eMMC, minimum is 200us but give it 300us for good measure */
422 usleep_range(300, 1000);
425 static void uniphier_sd_set_clock(struct tmio_mmc_host
*host
,
428 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
429 unsigned long divisor
;
432 tmp
= readl(host
->ctl
+ (CTL_SD_CARD_CLK_CTL
<< 1));
434 /* stop the clock before changing its rate to avoid a glitch signal */
435 tmp
&= ~CLK_CTL_SCLKEN
;
436 writel(tmp
, host
->ctl
+ (CTL_SD_CARD_CLK_CTL
<< 1));
441 tmp
&= ~UNIPHIER_SD_CLK_CTL_DIV1024
;
442 tmp
&= ~UNIPHIER_SD_CLK_CTL_DIV1
;
443 tmp
&= ~CLK_CTL_DIV_MASK
;
445 divisor
= priv
->clk_rate
/ clock
;
448 * In the original IP, bit[7:0] represents the divisor.
449 * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2
451 * The IP does not define a way to achieve 1/1. For UniPhier variants,
452 * bit10 is used for 1/1. Newer versions of UniPhier variants use
456 tmp
|= UNIPHIER_SD_CLK_CTL_DIV1
;
457 else if (priv
->caps
& UNIPHIER_SD_CAP_EXTENDED_IP
&& divisor
> 512)
458 tmp
|= UNIPHIER_SD_CLK_CTL_DIV1024
;
460 tmp
|= roundup_pow_of_two(divisor
) >> 2;
462 writel(tmp
, host
->ctl
+ (CTL_SD_CARD_CLK_CTL
<< 1));
464 tmp
|= CLK_CTL_SCLKEN
;
465 writel(tmp
, host
->ctl
+ (CTL_SD_CARD_CLK_CTL
<< 1));
468 static void uniphier_sd_host_init(struct tmio_mmc_host
*host
)
470 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
474 * Connected to 32bit AXI.
475 * This register holds settings for SoC-specific internal bus
476 * connection. What is worse, the register spec was changed,
477 * breaking the backward compatibility. Write an appropriate
478 * value depending on a flag associated with a compatible string.
480 if (priv
->caps
& UNIPHIER_SD_CAP_EXTENDED_IP
)
485 writel(val
, host
->ctl
+ UNIPHIER_SD_HOST_MODE
);
489 * If supported, the controller can automatically
490 * enable/disable the clock line to the card.
492 if (priv
->caps
& UNIPHIER_SD_CAP_EXTENDED_IP
)
493 val
|= UNIPHIER_SD_CLKCTL_OFFEN
;
495 writel(val
, host
->ctl
+ (CTL_SD_CARD_CLK_CTL
<< 1));
498 static int uniphier_sd_start_signal_voltage_switch(struct mmc_host
*mmc
,
501 struct tmio_mmc_host
*host
= mmc_priv(mmc
);
502 struct uniphier_sd_priv
*priv
= uniphier_sd_priv(host
);
503 struct pinctrl_state
*pinstate
= NULL
;
506 switch (ios
->signal_voltage
) {
507 case MMC_SIGNAL_VOLTAGE_330
:
508 val
= UNIPHIER_SD_VOLT_330
;
510 case MMC_SIGNAL_VOLTAGE_180
:
511 val
= UNIPHIER_SD_VOLT_180
;
512 pinstate
= priv
->pinstate_uhs
;
518 tmp
= readl(host
->ctl
+ UNIPHIER_SD_VOLT
);
519 tmp
&= ~UNIPHIER_SD_VOLT_MASK
;
520 tmp
|= FIELD_PREP(UNIPHIER_SD_VOLT_MASK
, val
);
521 writel(tmp
, host
->ctl
+ UNIPHIER_SD_VOLT
);
524 pinctrl_select_state(priv
->pinctrl
, pinstate
);
526 pinctrl_select_default_state(mmc_dev(mmc
));
531 static int uniphier_sd_uhs_init(struct tmio_mmc_host
*host
,
532 struct uniphier_sd_priv
*priv
)
534 priv
->pinctrl
= devm_pinctrl_get(mmc_dev(host
->mmc
));
535 if (IS_ERR(priv
->pinctrl
))
536 return PTR_ERR(priv
->pinctrl
);
538 priv
->pinstate_uhs
= pinctrl_lookup_state(priv
->pinctrl
, "uhs");
539 if (IS_ERR(priv
->pinstate_uhs
))
540 return PTR_ERR(priv
->pinstate_uhs
);
542 host
->ops
.start_signal_voltage_switch
=
543 uniphier_sd_start_signal_voltage_switch
;
548 static int uniphier_sd_probe(struct platform_device
*pdev
)
550 struct device
*dev
= &pdev
->dev
;
551 struct uniphier_sd_priv
*priv
;
552 struct tmio_mmc_data
*tmio_data
;
553 struct tmio_mmc_host
*host
;
556 irq
= platform_get_irq(pdev
, 0);
560 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
564 priv
->caps
= (unsigned long)of_device_get_match_data(dev
);
566 priv
->clk
= devm_clk_get(dev
, NULL
);
567 if (IS_ERR(priv
->clk
)) {
568 dev_err(dev
, "failed to get clock\n");
569 return PTR_ERR(priv
->clk
);
572 priv
->rst
= devm_reset_control_get_shared(dev
, "host");
573 if (IS_ERR(priv
->rst
)) {
574 dev_err(dev
, "failed to get host reset\n");
575 return PTR_ERR(priv
->rst
);
578 /* old version has one more reset */
579 if (!(priv
->caps
& UNIPHIER_SD_CAP_EXTENDED_IP
)) {
580 priv
->rst_br
= devm_reset_control_get_shared(dev
, "bridge");
581 if (IS_ERR(priv
->rst_br
)) {
582 dev_err(dev
, "failed to get bridge reset\n");
583 return PTR_ERR(priv
->rst_br
);
587 tmio_data
= &priv
->tmio_data
;
588 tmio_data
->flags
|= TMIO_MMC_32BIT_DATA_PORT
;
589 tmio_data
->flags
|= TMIO_MMC_USE_BUSY_TIMEOUT
;
591 host
= tmio_mmc_host_alloc(pdev
, tmio_data
);
593 return PTR_ERR(host
);
595 if (host
->mmc
->caps
& MMC_CAP_HW_RESET
) {
596 priv
->rst_hw
= devm_reset_control_get_exclusive(dev
, "hw");
597 if (IS_ERR(priv
->rst_hw
)) {
598 dev_err(dev
, "failed to get hw reset\n");
599 ret
= PTR_ERR(priv
->rst_hw
);
602 host
->ops
.hw_reset
= uniphier_sd_hw_reset
;
605 if (host
->mmc
->caps
& MMC_CAP_UHS
) {
606 ret
= uniphier_sd_uhs_init(host
, priv
);
609 "failed to setup UHS (error %d). Disabling UHS.",
611 host
->mmc
->caps
&= ~MMC_CAP_UHS
;
615 if (priv
->caps
& UNIPHIER_SD_CAP_EXTENDED_IP
)
616 host
->dma_ops
= &uniphier_sd_internal_dma_ops
;
618 host
->dma_ops
= &uniphier_sd_external_dma_ops
;
621 host
->clk_enable
= uniphier_sd_clk_enable
;
622 host
->clk_disable
= uniphier_sd_clk_disable
;
623 host
->set_clock
= uniphier_sd_set_clock
;
625 ret
= uniphier_sd_clk_enable(host
);
629 uniphier_sd_host_init(host
);
631 tmio_data
->ocr_mask
= MMC_VDD_32_33
| MMC_VDD_33_34
;
632 if (host
->mmc
->caps
& MMC_CAP_UHS
)
633 tmio_data
->ocr_mask
|= MMC_VDD_165_195
;
635 tmio_data
->max_segs
= 1;
636 tmio_data
->max_blk_count
= U16_MAX
;
638 ret
= tmio_mmc_host_probe(host
);
642 ret
= devm_request_irq(dev
, irq
, tmio_mmc_irq
, IRQF_SHARED
,
643 dev_name(dev
), host
);
650 tmio_mmc_host_remove(host
);
652 tmio_mmc_host_free(host
);
657 static int uniphier_sd_remove(struct platform_device
*pdev
)
659 struct tmio_mmc_host
*host
= platform_get_drvdata(pdev
);
661 tmio_mmc_host_remove(host
);
662 uniphier_sd_clk_disable(host
);
667 static const struct of_device_id uniphier_sd_match
[] = {
669 .compatible
= "socionext,uniphier-sd-v2.91",
672 .compatible
= "socionext,uniphier-sd-v3.1",
673 .data
= (void *)(UNIPHIER_SD_CAP_EXTENDED_IP
|
674 UNIPHIER_SD_CAP_BROKEN_DMA_RX
),
677 .compatible
= "socionext,uniphier-sd-v3.1.1",
678 .data
= (void *)UNIPHIER_SD_CAP_EXTENDED_IP
,
682 MODULE_DEVICE_TABLE(of
, uniphier_sd_match
);
684 static struct platform_driver uniphier_sd_driver
= {
685 .probe
= uniphier_sd_probe
,
686 .remove
= uniphier_sd_remove
,
688 .name
= "uniphier-sd",
689 .probe_type
= PROBE_PREFER_ASYNCHRONOUS
,
690 .of_match_table
= uniphier_sd_match
,
693 module_platform_driver(uniphier_sd_driver
);
695 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
696 MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver");
697 MODULE_LICENSE("GPL v2");