1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2014 Renesas Electronics Europe Ltd.
4 * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dmaengine.h>
12 #include <linux/highmem.h>
13 #include <linux/interrupt.h>
15 #include <linux/log2.h>
16 #include <linux/mmc/host.h>
17 #include <linux/mmc/mmc.h>
18 #include <linux/mmc/sd.h>
19 #include <linux/mmc/sdio.h>
20 #include <linux/module.h>
21 #include <linux/pagemap.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/platform_device.h>
24 #include <linux/scatterlist.h>
25 #include <linux/string.h>
26 #include <linux/time.h>
27 #include <linux/virtio.h>
28 #include <linux/workqueue.h>
30 #define USDHI6_SD_CMD 0x0000
31 #define USDHI6_SD_PORT_SEL 0x0004
32 #define USDHI6_SD_ARG 0x0008
33 #define USDHI6_SD_STOP 0x0010
34 #define USDHI6_SD_SECCNT 0x0014
35 #define USDHI6_SD_RSP10 0x0018
36 #define USDHI6_SD_RSP32 0x0020
37 #define USDHI6_SD_RSP54 0x0028
38 #define USDHI6_SD_RSP76 0x0030
39 #define USDHI6_SD_INFO1 0x0038
40 #define USDHI6_SD_INFO2 0x003c
41 #define USDHI6_SD_INFO1_MASK 0x0040
42 #define USDHI6_SD_INFO2_MASK 0x0044
43 #define USDHI6_SD_CLK_CTRL 0x0048
44 #define USDHI6_SD_SIZE 0x004c
45 #define USDHI6_SD_OPTION 0x0050
46 #define USDHI6_SD_ERR_STS1 0x0058
47 #define USDHI6_SD_ERR_STS2 0x005c
48 #define USDHI6_SD_BUF0 0x0060
49 #define USDHI6_SDIO_MODE 0x0068
50 #define USDHI6_SDIO_INFO1 0x006c
51 #define USDHI6_SDIO_INFO1_MASK 0x0070
52 #define USDHI6_CC_EXT_MODE 0x01b0
53 #define USDHI6_SOFT_RST 0x01c0
54 #define USDHI6_VERSION 0x01c4
55 #define USDHI6_HOST_MODE 0x01c8
56 #define USDHI6_SDIF_MODE 0x01cc
58 #define USDHI6_SD_CMD_APP 0x0040
59 #define USDHI6_SD_CMD_MODE_RSP_AUTO 0x0000
60 #define USDHI6_SD_CMD_MODE_RSP_NONE 0x0300
61 #define USDHI6_SD_CMD_MODE_RSP_R1 0x0400 /* Also R5, R6, R7 */
62 #define USDHI6_SD_CMD_MODE_RSP_R1B 0x0500 /* R1b */
63 #define USDHI6_SD_CMD_MODE_RSP_R2 0x0600
64 #define USDHI6_SD_CMD_MODE_RSP_R3 0x0700 /* Also R4 */
65 #define USDHI6_SD_CMD_DATA 0x0800
66 #define USDHI6_SD_CMD_READ 0x1000
67 #define USDHI6_SD_CMD_MULTI 0x2000
68 #define USDHI6_SD_CMD_CMD12_AUTO_OFF 0x4000
70 #define USDHI6_CC_EXT_MODE_SDRW BIT(1)
72 #define USDHI6_SD_INFO1_RSP_END BIT(0)
73 #define USDHI6_SD_INFO1_ACCESS_END BIT(2)
74 #define USDHI6_SD_INFO1_CARD_OUT BIT(3)
75 #define USDHI6_SD_INFO1_CARD_IN BIT(4)
76 #define USDHI6_SD_INFO1_CD BIT(5)
77 #define USDHI6_SD_INFO1_WP BIT(7)
78 #define USDHI6_SD_INFO1_D3_CARD_OUT BIT(8)
79 #define USDHI6_SD_INFO1_D3_CARD_IN BIT(9)
81 #define USDHI6_SD_INFO2_CMD_ERR BIT(0)
82 #define USDHI6_SD_INFO2_CRC_ERR BIT(1)
83 #define USDHI6_SD_INFO2_END_ERR BIT(2)
84 #define USDHI6_SD_INFO2_TOUT BIT(3)
85 #define USDHI6_SD_INFO2_IWA_ERR BIT(4)
86 #define USDHI6_SD_INFO2_IRA_ERR BIT(5)
87 #define USDHI6_SD_INFO2_RSP_TOUT BIT(6)
88 #define USDHI6_SD_INFO2_SDDAT0 BIT(7)
89 #define USDHI6_SD_INFO2_BRE BIT(8)
90 #define USDHI6_SD_INFO2_BWE BIT(9)
91 #define USDHI6_SD_INFO2_SCLKDIVEN BIT(13)
92 #define USDHI6_SD_INFO2_CBSY BIT(14)
93 #define USDHI6_SD_INFO2_ILA BIT(15)
95 #define USDHI6_SD_INFO1_CARD_INSERT (USDHI6_SD_INFO1_CARD_IN | USDHI6_SD_INFO1_D3_CARD_IN)
96 #define USDHI6_SD_INFO1_CARD_EJECT (USDHI6_SD_INFO1_CARD_OUT | USDHI6_SD_INFO1_D3_CARD_OUT)
97 #define USDHI6_SD_INFO1_CARD (USDHI6_SD_INFO1_CARD_INSERT | USDHI6_SD_INFO1_CARD_EJECT)
98 #define USDHI6_SD_INFO1_CARD_CD (USDHI6_SD_INFO1_CARD_IN | USDHI6_SD_INFO1_CARD_OUT)
100 #define USDHI6_SD_INFO2_ERR (USDHI6_SD_INFO2_CMD_ERR | \
101 USDHI6_SD_INFO2_CRC_ERR | USDHI6_SD_INFO2_END_ERR | \
102 USDHI6_SD_INFO2_TOUT | USDHI6_SD_INFO2_IWA_ERR | \
103 USDHI6_SD_INFO2_IRA_ERR | USDHI6_SD_INFO2_RSP_TOUT | \
106 #define USDHI6_SD_INFO1_IRQ (USDHI6_SD_INFO1_RSP_END | USDHI6_SD_INFO1_ACCESS_END | \
107 USDHI6_SD_INFO1_CARD)
109 #define USDHI6_SD_INFO2_IRQ (USDHI6_SD_INFO2_ERR | USDHI6_SD_INFO2_BRE | \
110 USDHI6_SD_INFO2_BWE | 0x0800 | USDHI6_SD_INFO2_ILA)
112 #define USDHI6_SD_CLK_CTRL_SCLKEN BIT(8)
114 #define USDHI6_SD_STOP_STP BIT(0)
115 #define USDHI6_SD_STOP_SEC BIT(8)
117 #define USDHI6_SDIO_INFO1_IOIRQ BIT(0)
118 #define USDHI6_SDIO_INFO1_EXPUB52 BIT(14)
119 #define USDHI6_SDIO_INFO1_EXWT BIT(15)
121 #define USDHI6_SD_ERR_STS1_CRC_NO_ERROR BIT(13)
123 #define USDHI6_SOFT_RST_RESERVED (BIT(1) | BIT(2))
124 #define USDHI6_SOFT_RST_RESET BIT(0)
126 #define USDHI6_SD_OPTION_TIMEOUT_SHIFT 4
127 #define USDHI6_SD_OPTION_TIMEOUT_MASK (0xf << USDHI6_SD_OPTION_TIMEOUT_SHIFT)
128 #define USDHI6_SD_OPTION_WIDTH_1 BIT(15)
130 #define USDHI6_SD_PORT_SEL_PORTS_SHIFT 8
132 #define USDHI6_SD_CLK_CTRL_DIV_MASK 0xff
134 #define USDHI6_SDIO_INFO1_IRQ (USDHI6_SDIO_INFO1_IOIRQ | 3 | \
135 USDHI6_SDIO_INFO1_EXPUB52 | USDHI6_SDIO_INFO1_EXWT)
137 #define USDHI6_MIN_DMA 64
139 #define USDHI6_REQ_TIMEOUT_MS 4000
141 enum usdhi6_wait_for
{
142 USDHI6_WAIT_FOR_REQUEST
,
144 USDHI6_WAIT_FOR_MREAD
,
145 USDHI6_WAIT_FOR_MWRITE
,
146 USDHI6_WAIT_FOR_READ
,
147 USDHI6_WAIT_FOR_WRITE
,
148 USDHI6_WAIT_FOR_DATA_END
,
149 USDHI6_WAIT_FOR_STOP
,
155 void *mapped
; /* mapped page */
159 struct mmc_host
*mmc
;
160 struct mmc_request
*mrq
;
164 /* SG memory handling */
166 /* Common for multiple and single block requests */
167 struct usdhi6_page pg
; /* current page from an SG */
168 void *blk_page
; /* either a mapped page, or the bounce buffer */
169 size_t offset
; /* offset within a page, including sg->offset */
171 /* Blocks, crossing a page boundary */
173 struct usdhi6_page head_pg
;
175 /* A bounce buffer for unaligned blocks or blocks, crossing a page boundary */
176 struct scatterlist bounce_sg
;
179 /* Multiple block requests only */
180 struct scatterlist
*sg
; /* current SG segment */
181 int page_idx
; /* page index within an SG segment */
183 enum usdhi6_wait_for wait
;
193 /* Timeout handling */
194 struct delayed_work timeout_work
;
195 unsigned long timeout
;
198 struct dma_chan
*chan_rx
;
199 struct dma_chan
*chan_tx
;
203 struct pinctrl
*pinctrl
;
204 struct pinctrl_state
*pins_uhs
;
209 static void usdhi6_write(struct usdhi6_host
*host
, u32 reg
, u32 data
)
211 iowrite32(data
, host
->base
+ reg
);
212 dev_vdbg(mmc_dev(host
->mmc
), "%s(0x%p + 0x%x) = 0x%x\n", __func__
,
213 host
->base
, reg
, data
);
216 static void usdhi6_write16(struct usdhi6_host
*host
, u32 reg
, u16 data
)
218 iowrite16(data
, host
->base
+ reg
);
219 dev_vdbg(mmc_dev(host
->mmc
), "%s(0x%p + 0x%x) = 0x%x\n", __func__
,
220 host
->base
, reg
, data
);
223 static u32
usdhi6_read(struct usdhi6_host
*host
, u32 reg
)
225 u32 data
= ioread32(host
->base
+ reg
);
226 dev_vdbg(mmc_dev(host
->mmc
), "%s(0x%p + 0x%x) = 0x%x\n", __func__
,
227 host
->base
, reg
, data
);
231 static u16
usdhi6_read16(struct usdhi6_host
*host
, u32 reg
)
233 u16 data
= ioread16(host
->base
+ reg
);
234 dev_vdbg(mmc_dev(host
->mmc
), "%s(0x%p + 0x%x) = 0x%x\n", __func__
,
235 host
->base
, reg
, data
);
239 static void usdhi6_irq_enable(struct usdhi6_host
*host
, u32 info1
, u32 info2
)
241 host
->status_mask
= USDHI6_SD_INFO1_IRQ
& ~info1
;
242 host
->status2_mask
= USDHI6_SD_INFO2_IRQ
& ~info2
;
243 usdhi6_write(host
, USDHI6_SD_INFO1_MASK
, host
->status_mask
);
244 usdhi6_write(host
, USDHI6_SD_INFO2_MASK
, host
->status2_mask
);
247 static void usdhi6_wait_for_resp(struct usdhi6_host
*host
)
249 usdhi6_irq_enable(host
, USDHI6_SD_INFO1_RSP_END
|
250 USDHI6_SD_INFO1_ACCESS_END
| USDHI6_SD_INFO1_CARD_CD
,
251 USDHI6_SD_INFO2_ERR
);
254 static void usdhi6_wait_for_brwe(struct usdhi6_host
*host
, bool read
)
256 usdhi6_irq_enable(host
, USDHI6_SD_INFO1_ACCESS_END
|
257 USDHI6_SD_INFO1_CARD_CD
, USDHI6_SD_INFO2_ERR
|
258 (read
? USDHI6_SD_INFO2_BRE
: USDHI6_SD_INFO2_BWE
));
261 static void usdhi6_only_cd(struct usdhi6_host
*host
)
263 /* Mask all except card hotplug */
264 usdhi6_irq_enable(host
, USDHI6_SD_INFO1_CARD_CD
, 0);
267 static void usdhi6_mask_all(struct usdhi6_host
*host
)
269 usdhi6_irq_enable(host
, 0, 0);
272 static int usdhi6_error_code(struct usdhi6_host
*host
)
276 usdhi6_write(host
, USDHI6_SD_STOP
, USDHI6_SD_STOP_STP
);
279 (USDHI6_SD_INFO2_RSP_TOUT
| USDHI6_SD_INFO2_TOUT
)) {
280 u32 rsp54
= usdhi6_read(host
, USDHI6_SD_RSP54
);
281 int opc
= host
->mrq
? host
->mrq
->cmd
->opcode
: -1;
283 err
= usdhi6_read(host
, USDHI6_SD_ERR_STS2
);
284 /* Response timeout is often normal, don't spam the log */
285 if (host
->wait
== USDHI6_WAIT_FOR_CMD
)
286 dev_dbg(mmc_dev(host
->mmc
),
287 "T-out sts 0x%x, resp 0x%x, state %u, CMD%d\n",
288 err
, rsp54
, host
->wait
, opc
);
290 dev_warn(mmc_dev(host
->mmc
),
291 "T-out sts 0x%x, resp 0x%x, state %u, CMD%d\n",
292 err
, rsp54
, host
->wait
, opc
);
296 err
= usdhi6_read(host
, USDHI6_SD_ERR_STS1
);
297 if (err
!= USDHI6_SD_ERR_STS1_CRC_NO_ERROR
)
298 dev_warn(mmc_dev(host
->mmc
), "Err sts 0x%x, state %u, CMD%d\n",
299 err
, host
->wait
, host
->mrq
? host
->mrq
->cmd
->opcode
: -1);
300 if (host
->io_error
& USDHI6_SD_INFO2_ILA
)
306 /* Scatter-Gather management */
309 * In PIO mode we have to map each page separately, using kmap(). That way
310 * adjacent pages are mapped to non-adjacent virtual addresses. That's why we
311 * have to use a bounce buffer for blocks, crossing page boundaries. Such blocks
312 * have been observed with an SDIO WiFi card (b43 driver).
314 static void usdhi6_blk_bounce(struct usdhi6_host
*host
,
315 struct scatterlist
*sg
)
317 struct mmc_data
*data
= host
->mrq
->data
;
318 size_t blk_head
= host
->head_len
;
320 dev_dbg(mmc_dev(host
->mmc
), "%s(): CMD%u of %u SG: %ux%u @ 0x%x\n",
321 __func__
, host
->mrq
->cmd
->opcode
, data
->sg_len
,
322 data
->blksz
, data
->blocks
, sg
->offset
);
324 host
->head_pg
.page
= host
->pg
.page
;
325 host
->head_pg
.mapped
= host
->pg
.mapped
;
326 host
->pg
.page
= nth_page(host
->pg
.page
, 1);
327 host
->pg
.mapped
= kmap(host
->pg
.page
);
329 host
->blk_page
= host
->bounce_buf
;
332 if (data
->flags
& MMC_DATA_READ
)
335 memcpy(host
->bounce_buf
, host
->head_pg
.mapped
+ PAGE_SIZE
- blk_head
,
337 memcpy(host
->bounce_buf
+ blk_head
, host
->pg
.mapped
,
338 data
->blksz
- blk_head
);
341 /* Only called for multiple block IO */
342 static void usdhi6_sg_prep(struct usdhi6_host
*host
)
344 struct mmc_request
*mrq
= host
->mrq
;
345 struct mmc_data
*data
= mrq
->data
;
347 usdhi6_write(host
, USDHI6_SD_SECCNT
, data
->blocks
);
350 /* TODO: if we always map, this is redundant */
351 host
->offset
= host
->sg
->offset
;
354 /* Map the first page in an SG segment: common for multiple and single block IO */
355 static void *usdhi6_sg_map(struct usdhi6_host
*host
)
357 struct mmc_data
*data
= host
->mrq
->data
;
358 struct scatterlist
*sg
= data
->sg_len
> 1 ? host
->sg
: data
->sg
;
359 size_t head
= PAGE_SIZE
- sg
->offset
;
360 size_t blk_head
= head
% data
->blksz
;
362 WARN(host
->pg
.page
, "%p not properly unmapped!\n", host
->pg
.page
);
363 if (WARN(sg_dma_len(sg
) % data
->blksz
,
364 "SG size %u isn't a multiple of block size %u\n",
365 sg_dma_len(sg
), data
->blksz
))
368 host
->pg
.page
= sg_page(sg
);
369 host
->pg
.mapped
= kmap(host
->pg
.page
);
370 host
->offset
= sg
->offset
;
373 * Block size must be a power of 2 for multi-block transfers,
374 * therefore blk_head is equal for all pages in this SG
376 host
->head_len
= blk_head
;
378 if (head
< data
->blksz
)
380 * The first block in the SG crosses a page boundary.
381 * Max blksz = 512, so blocks can only span 2 pages
383 usdhi6_blk_bounce(host
, sg
);
385 host
->blk_page
= host
->pg
.mapped
;
387 dev_dbg(mmc_dev(host
->mmc
), "Mapped %p (%lx) at %p + %u for CMD%u @ 0x%p\n",
388 host
->pg
.page
, page_to_pfn(host
->pg
.page
), host
->pg
.mapped
,
389 sg
->offset
, host
->mrq
->cmd
->opcode
, host
->mrq
);
391 return host
->blk_page
+ host
->offset
;
394 /* Unmap the current page: common for multiple and single block IO */
395 static void usdhi6_sg_unmap(struct usdhi6_host
*host
, bool force
)
397 struct mmc_data
*data
= host
->mrq
->data
;
398 struct page
*page
= host
->head_pg
.page
;
401 /* Previous block was cross-page boundary */
402 struct scatterlist
*sg
= data
->sg_len
> 1 ?
404 size_t blk_head
= host
->head_len
;
406 if (!data
->error
&& data
->flags
& MMC_DATA_READ
) {
407 memcpy(host
->head_pg
.mapped
+ PAGE_SIZE
- blk_head
,
408 host
->bounce_buf
, blk_head
);
409 memcpy(host
->pg
.mapped
, host
->bounce_buf
+ blk_head
,
410 data
->blksz
- blk_head
);
413 flush_dcache_page(page
);
416 host
->head_pg
.page
= NULL
;
418 if (!force
&& sg_dma_len(sg
) + sg
->offset
>
419 (host
->page_idx
<< PAGE_SHIFT
) + data
->blksz
- blk_head
)
420 /* More blocks in this SG, don't unmap the next page */
424 page
= host
->pg
.page
;
428 flush_dcache_page(page
);
431 host
->pg
.page
= NULL
;
434 /* Called from MMC_WRITE_MULTIPLE_BLOCK or MMC_READ_MULTIPLE_BLOCK */
435 static void usdhi6_sg_advance(struct usdhi6_host
*host
)
437 struct mmc_data
*data
= host
->mrq
->data
;
440 /* New offset: set at the end of the previous block */
441 if (host
->head_pg
.page
) {
442 /* Finished a cross-page block, jump to the new page */
444 host
->offset
= data
->blksz
- host
->head_len
;
445 host
->blk_page
= host
->pg
.mapped
;
446 usdhi6_sg_unmap(host
, false);
448 host
->offset
+= data
->blksz
;
449 /* The completed block didn't cross a page boundary */
450 if (host
->offset
== PAGE_SIZE
) {
451 /* If required, we'll map the page below */
458 * Now host->blk_page + host->offset point at the end of our last block
459 * and host->page_idx is the index of the page, in which our new block
463 done
= (host
->page_idx
<< PAGE_SHIFT
) + host
->offset
;
464 total
= host
->sg
->offset
+ sg_dma_len(host
->sg
);
466 dev_dbg(mmc_dev(host
->mmc
), "%s(): %zu of %zu @ %zu\n", __func__
,
467 done
, total
, host
->offset
);
469 if (done
< total
&& host
->offset
) {
470 /* More blocks in this page */
471 if (host
->offset
+ data
->blksz
> PAGE_SIZE
)
472 /* We approached at a block, that spans 2 pages */
473 usdhi6_blk_bounce(host
, host
->sg
);
478 /* Finished current page or an SG segment */
479 usdhi6_sg_unmap(host
, false);
483 * End of an SG segment or the complete SG: jump to the next
484 * segment, we'll map it later in usdhi6_blk_read() or
487 struct scatterlist
*next
= sg_next(host
->sg
);
492 host
->wait
= USDHI6_WAIT_FOR_DATA_END
;
495 if (WARN(next
&& sg_dma_len(next
) % data
->blksz
,
496 "SG size %u isn't a multiple of block size %u\n",
497 sg_dma_len(next
), data
->blksz
))
498 data
->error
= -EINVAL
;
503 /* We cannot get here after crossing a page border */
505 /* Next page in the same SG */
506 host
->pg
.page
= nth_page(sg_page(host
->sg
), host
->page_idx
);
507 host
->pg
.mapped
= kmap(host
->pg
.page
);
508 host
->blk_page
= host
->pg
.mapped
;
510 dev_dbg(mmc_dev(host
->mmc
), "Mapped %p (%lx) at %p for CMD%u @ 0x%p\n",
511 host
->pg
.page
, page_to_pfn(host
->pg
.page
), host
->pg
.mapped
,
512 host
->mrq
->cmd
->opcode
, host
->mrq
);
517 static void usdhi6_dma_release(struct usdhi6_host
*host
)
519 host
->dma_active
= false;
521 struct dma_chan
*chan
= host
->chan_tx
;
522 host
->chan_tx
= NULL
;
523 dma_release_channel(chan
);
526 struct dma_chan
*chan
= host
->chan_rx
;
527 host
->chan_rx
= NULL
;
528 dma_release_channel(chan
);
532 static void usdhi6_dma_stop_unmap(struct usdhi6_host
*host
)
534 struct mmc_data
*data
= host
->mrq
->data
;
536 if (!host
->dma_active
)
539 usdhi6_write(host
, USDHI6_CC_EXT_MODE
, 0);
540 host
->dma_active
= false;
542 if (data
->flags
& MMC_DATA_READ
)
543 dma_unmap_sg(host
->chan_rx
->device
->dev
, data
->sg
,
544 data
->sg_len
, DMA_FROM_DEVICE
);
546 dma_unmap_sg(host
->chan_tx
->device
->dev
, data
->sg
,
547 data
->sg_len
, DMA_TO_DEVICE
);
550 static void usdhi6_dma_complete(void *arg
)
552 struct usdhi6_host
*host
= arg
;
553 struct mmc_request
*mrq
= host
->mrq
;
555 if (WARN(!mrq
|| !mrq
->data
, "%s: NULL data in DMA completion for %p!\n",
556 dev_name(mmc_dev(host
->mmc
)), mrq
))
559 dev_dbg(mmc_dev(host
->mmc
), "%s(): CMD%u DMA completed\n", __func__
,
562 usdhi6_dma_stop_unmap(host
);
563 usdhi6_wait_for_brwe(host
, mrq
->data
->flags
& MMC_DATA_READ
);
566 static int usdhi6_dma_setup(struct usdhi6_host
*host
, struct dma_chan
*chan
,
567 enum dma_transfer_direction dir
)
569 struct mmc_data
*data
= host
->mrq
->data
;
570 struct scatterlist
*sg
= data
->sg
;
571 struct dma_async_tx_descriptor
*desc
= NULL
;
572 dma_cookie_t cookie
= -EINVAL
;
573 enum dma_data_direction data_dir
;
578 data_dir
= DMA_TO_DEVICE
;
581 data_dir
= DMA_FROM_DEVICE
;
587 ret
= dma_map_sg(chan
->device
->dev
, sg
, data
->sg_len
, data_dir
);
589 host
->dma_active
= true;
590 desc
= dmaengine_prep_slave_sg(chan
, sg
, ret
, dir
,
591 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
595 desc
->callback
= usdhi6_dma_complete
;
596 desc
->callback_param
= host
;
597 cookie
= dmaengine_submit(desc
);
600 dev_dbg(mmc_dev(host
->mmc
), "%s(): mapped %d -> %d, cookie %d @ %p\n",
601 __func__
, data
->sg_len
, ret
, cookie
, desc
);
604 /* DMA failed, fall back to PIO */
607 usdhi6_dma_release(host
);
608 dev_warn(mmc_dev(host
->mmc
),
609 "DMA failed: %d, falling back to PIO\n", ret
);
615 static int usdhi6_dma_start(struct usdhi6_host
*host
)
617 if (!host
->chan_rx
|| !host
->chan_tx
)
620 if (host
->mrq
->data
->flags
& MMC_DATA_READ
)
621 return usdhi6_dma_setup(host
, host
->chan_rx
, DMA_DEV_TO_MEM
);
623 return usdhi6_dma_setup(host
, host
->chan_tx
, DMA_MEM_TO_DEV
);
626 static void usdhi6_dma_kill(struct usdhi6_host
*host
)
628 struct mmc_data
*data
= host
->mrq
->data
;
630 dev_dbg(mmc_dev(host
->mmc
), "%s(): SG of %u: %ux%u\n",
631 __func__
, data
->sg_len
, data
->blocks
, data
->blksz
);
633 if (data
->flags
& MMC_DATA_READ
)
634 dmaengine_terminate_all(host
->chan_rx
);
636 dmaengine_terminate_all(host
->chan_tx
);
639 static void usdhi6_dma_check_error(struct usdhi6_host
*host
)
641 struct mmc_data
*data
= host
->mrq
->data
;
643 dev_dbg(mmc_dev(host
->mmc
), "%s(): IO error %d, status 0x%x\n",
644 __func__
, host
->io_error
, usdhi6_read(host
, USDHI6_SD_INFO1
));
646 if (host
->io_error
) {
647 data
->error
= usdhi6_error_code(host
);
648 data
->bytes_xfered
= 0;
649 usdhi6_dma_kill(host
);
650 usdhi6_dma_release(host
);
651 dev_warn(mmc_dev(host
->mmc
),
652 "DMA failed: %d, falling back to PIO\n", data
->error
);
657 * The datasheet tells us to check a response from the card, whereas
658 * responses only come after the command phase, not after the data
659 * phase. Let's check anyway.
661 if (host
->irq_status
& USDHI6_SD_INFO1_RSP_END
)
662 dev_warn(mmc_dev(host
->mmc
), "Unexpected response received!\n");
665 static void usdhi6_dma_kick(struct usdhi6_host
*host
)
667 if (host
->mrq
->data
->flags
& MMC_DATA_READ
)
668 dma_async_issue_pending(host
->chan_rx
);
670 dma_async_issue_pending(host
->chan_tx
);
673 static void usdhi6_dma_request(struct usdhi6_host
*host
, phys_addr_t start
)
675 struct dma_slave_config cfg
= {
676 .src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
,
677 .dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
,
681 host
->chan_tx
= dma_request_chan(mmc_dev(host
->mmc
), "tx");
682 dev_dbg(mmc_dev(host
->mmc
), "%s: TX: got channel %p\n", __func__
,
685 if (IS_ERR(host
->chan_tx
)) {
686 host
->chan_tx
= NULL
;
690 cfg
.direction
= DMA_MEM_TO_DEV
;
691 cfg
.dst_addr
= start
+ USDHI6_SD_BUF0
;
692 cfg
.dst_maxburst
= 128; /* 128 words * 4 bytes = 512 bytes */
694 ret
= dmaengine_slave_config(host
->chan_tx
, &cfg
);
698 host
->chan_rx
= dma_request_chan(mmc_dev(host
->mmc
), "rx");
699 dev_dbg(mmc_dev(host
->mmc
), "%s: RX: got channel %p\n", __func__
,
702 if (IS_ERR(host
->chan_rx
)) {
703 host
->chan_rx
= NULL
;
707 cfg
.direction
= DMA_DEV_TO_MEM
;
708 cfg
.src_addr
= cfg
.dst_addr
;
709 cfg
.src_maxburst
= 128; /* 128 words * 4 bytes = 512 bytes */
711 ret
= dmaengine_slave_config(host
->chan_rx
, &cfg
);
718 dma_release_channel(host
->chan_rx
);
719 host
->chan_rx
= NULL
;
721 dma_release_channel(host
->chan_tx
);
722 host
->chan_tx
= NULL
;
727 static void usdhi6_clk_set(struct usdhi6_host
*host
, struct mmc_ios
*ios
)
729 unsigned long rate
= ios
->clock
;
733 for (i
= 1000; i
; i
--) {
734 if (usdhi6_read(host
, USDHI6_SD_INFO2
) & USDHI6_SD_INFO2_SCLKDIVEN
)
736 usleep_range(10, 100);
740 dev_err(mmc_dev(host
->mmc
), "SD bus busy, clock set aborted\n");
744 val
= usdhi6_read(host
, USDHI6_SD_CLK_CTRL
) & ~USDHI6_SD_CLK_CTRL_DIV_MASK
;
747 unsigned long new_rate
;
749 if (host
->imclk
<= rate
) {
750 if (ios
->timing
!= MMC_TIMING_UHS_DDR50
) {
751 /* Cannot have 1-to-1 clock in DDR mode */
752 new_rate
= host
->imclk
;
755 new_rate
= host
->imclk
/ 2;
759 roundup_pow_of_two(DIV_ROUND_UP(host
->imclk
, rate
));
761 new_rate
= host
->imclk
/ div
;
764 if (host
->rate
== new_rate
)
767 host
->rate
= new_rate
;
769 dev_dbg(mmc_dev(host
->mmc
), "target %lu, div %u, set %lu\n",
770 rate
, (val
& 0xff) << 2, new_rate
);
774 * if old or new rate is equal to input rate, have to switch the clock
775 * off before changing and on after
777 if (host
->imclk
== rate
|| host
->imclk
== host
->rate
|| !rate
)
778 usdhi6_write(host
, USDHI6_SD_CLK_CTRL
,
779 val
& ~USDHI6_SD_CLK_CTRL_SCLKEN
);
786 usdhi6_write(host
, USDHI6_SD_CLK_CTRL
, val
);
788 if (host
->imclk
== rate
|| host
->imclk
== host
->rate
||
789 !(val
& USDHI6_SD_CLK_CTRL_SCLKEN
))
790 usdhi6_write(host
, USDHI6_SD_CLK_CTRL
,
791 val
| USDHI6_SD_CLK_CTRL_SCLKEN
);
794 static void usdhi6_set_power(struct usdhi6_host
*host
, struct mmc_ios
*ios
)
796 struct mmc_host
*mmc
= host
->mmc
;
798 if (!IS_ERR(mmc
->supply
.vmmc
))
799 /* Errors ignored... */
800 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
,
801 ios
->power_mode
? ios
->vdd
: 0);
804 static int usdhi6_reset(struct usdhi6_host
*host
)
808 usdhi6_write(host
, USDHI6_SOFT_RST
, USDHI6_SOFT_RST_RESERVED
);
810 usdhi6_write(host
, USDHI6_SOFT_RST
, USDHI6_SOFT_RST_RESERVED
| USDHI6_SOFT_RST_RESET
);
811 for (i
= 1000; i
; i
--)
812 if (usdhi6_read(host
, USDHI6_SOFT_RST
) & USDHI6_SOFT_RST_RESET
)
815 return i
? 0 : -ETIMEDOUT
;
818 static void usdhi6_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
820 struct usdhi6_host
*host
= mmc_priv(mmc
);
824 dev_dbg(mmc_dev(mmc
), "%uHz, OCR: %u, power %u, bus-width %u, timing %u\n",
825 ios
->clock
, ios
->vdd
, ios
->power_mode
, ios
->bus_width
, ios
->timing
);
827 switch (ios
->power_mode
) {
829 usdhi6_set_power(host
, ios
);
830 usdhi6_only_cd(host
);
834 * We only also touch USDHI6_SD_OPTION from .request(), which
835 * cannot race with MMC_POWER_UP
837 ret
= usdhi6_reset(host
);
839 dev_err(mmc_dev(mmc
), "Cannot reset the interface!\n");
841 usdhi6_set_power(host
, ios
);
842 usdhi6_only_cd(host
);
846 option
= usdhi6_read(host
, USDHI6_SD_OPTION
);
848 * The eMMC standard only allows 4 or 8 bits in the DDR mode,
849 * the same probably holds for SD cards. We check here anyway,
850 * since the datasheet explicitly requires 4 bits for DDR.
852 if (ios
->bus_width
== MMC_BUS_WIDTH_1
) {
853 if (ios
->timing
== MMC_TIMING_UHS_DDR50
)
854 dev_err(mmc_dev(mmc
),
855 "4 bits are required for DDR\n");
856 option
|= USDHI6_SD_OPTION_WIDTH_1
;
859 option
&= ~USDHI6_SD_OPTION_WIDTH_1
;
860 mode
= ios
->timing
== MMC_TIMING_UHS_DDR50
;
862 usdhi6_write(host
, USDHI6_SD_OPTION
, option
);
863 usdhi6_write(host
, USDHI6_SDIF_MODE
, mode
);
867 if (host
->rate
!= ios
->clock
)
868 usdhi6_clk_set(host
, ios
);
871 /* This is data timeout. Response timeout is fixed to 640 clock cycles */
872 static void usdhi6_timeout_set(struct usdhi6_host
*host
)
874 struct mmc_request
*mrq
= host
->mrq
;
879 ticks
= host
->rate
/ 1000 * mrq
->cmd
->busy_timeout
;
881 ticks
= host
->rate
/ 1000000 * (mrq
->data
->timeout_ns
/ 1000) +
882 mrq
->data
->timeout_clks
;
884 if (!ticks
|| ticks
> 1 << 27)
887 else if (ticks
< 1 << 13)
891 val
= order_base_2(ticks
) - 13;
893 dev_dbg(mmc_dev(host
->mmc
), "Set %s timeout %lu ticks @ %lu Hz\n",
894 mrq
->data
? "data" : "cmd", ticks
, host
->rate
);
896 /* Timeout Counter mask: 0xf0 */
897 usdhi6_write(host
, USDHI6_SD_OPTION
, (val
<< USDHI6_SD_OPTION_TIMEOUT_SHIFT
) |
898 (usdhi6_read(host
, USDHI6_SD_OPTION
) & ~USDHI6_SD_OPTION_TIMEOUT_MASK
));
901 static void usdhi6_request_done(struct usdhi6_host
*host
)
903 struct mmc_request
*mrq
= host
->mrq
;
904 struct mmc_data
*data
= mrq
->data
;
906 if (WARN(host
->pg
.page
|| host
->head_pg
.page
,
907 "Page %p or %p not unmapped: wait %u, CMD%d(%c) @ +0x%zx %ux%u in SG%u!\n",
908 host
->pg
.page
, host
->head_pg
.page
, host
->wait
, mrq
->cmd
->opcode
,
909 data
? (data
->flags
& MMC_DATA_READ
? 'R' : 'W') : '-',
910 data
? host
->offset
: 0, data
? data
->blocks
: 0,
911 data
? data
->blksz
: 0, data
? data
->sg_len
: 0))
912 usdhi6_sg_unmap(host
, true);
914 if (mrq
->cmd
->error
||
915 (data
&& data
->error
) ||
916 (mrq
->stop
&& mrq
->stop
->error
))
917 dev_dbg(mmc_dev(host
->mmc
), "%s(CMD%d: %ux%u): err %d %d %d\n",
918 __func__
, mrq
->cmd
->opcode
, data
? data
->blocks
: 0,
919 data
? data
->blksz
: 0,
921 data
? data
->error
: 1,
922 mrq
->stop
? mrq
->stop
->error
: 1);
925 usdhi6_write(host
, USDHI6_CC_EXT_MODE
, 0);
926 host
->wait
= USDHI6_WAIT_FOR_REQUEST
;
929 mmc_request_done(host
->mmc
, mrq
);
932 static int usdhi6_cmd_flags(struct usdhi6_host
*host
)
934 struct mmc_request
*mrq
= host
->mrq
;
935 struct mmc_command
*cmd
= mrq
->cmd
;
936 u16 opc
= cmd
->opcode
;
939 host
->app_cmd
= false;
940 opc
|= USDHI6_SD_CMD_APP
;
944 opc
|= USDHI6_SD_CMD_DATA
;
946 if (mrq
->data
->flags
& MMC_DATA_READ
)
947 opc
|= USDHI6_SD_CMD_READ
;
949 if (cmd
->opcode
== MMC_READ_MULTIPLE_BLOCK
||
950 cmd
->opcode
== MMC_WRITE_MULTIPLE_BLOCK
||
951 (cmd
->opcode
== SD_IO_RW_EXTENDED
&&
952 mrq
->data
->blocks
> 1)) {
953 opc
|= USDHI6_SD_CMD_MULTI
;
955 opc
|= USDHI6_SD_CMD_CMD12_AUTO_OFF
;
958 switch (mmc_resp_type(cmd
)) {
960 opc
|= USDHI6_SD_CMD_MODE_RSP_NONE
;
963 opc
|= USDHI6_SD_CMD_MODE_RSP_R1
;
966 opc
|= USDHI6_SD_CMD_MODE_RSP_R1B
;
969 opc
|= USDHI6_SD_CMD_MODE_RSP_R2
;
972 opc
|= USDHI6_SD_CMD_MODE_RSP_R3
;
975 dev_warn(mmc_dev(host
->mmc
),
976 "Unknown response type %d\n",
985 static int usdhi6_rq_start(struct usdhi6_host
*host
)
987 struct mmc_request
*mrq
= host
->mrq
;
988 struct mmc_command
*cmd
= mrq
->cmd
;
989 struct mmc_data
*data
= mrq
->data
;
990 int opc
= usdhi6_cmd_flags(host
);
996 for (i
= 1000; i
; i
--) {
997 if (!(usdhi6_read(host
, USDHI6_SD_INFO2
) & USDHI6_SD_INFO2_CBSY
))
999 usleep_range(10, 100);
1003 dev_dbg(mmc_dev(host
->mmc
), "Command active, request aborted\n");
1013 if (cmd
->opcode
== SD_IO_RW_EXTENDED
&& data
->blocks
> 1) {
1014 switch (data
->blksz
) {
1027 } else if ((cmd
->opcode
== MMC_READ_MULTIPLE_BLOCK
||
1028 cmd
->opcode
== MMC_WRITE_MULTIPLE_BLOCK
) &&
1029 data
->blksz
!= 512) {
1034 dev_warn(mmc_dev(host
->mmc
), "%s(): %u blocks of %u bytes\n",
1035 __func__
, data
->blocks
, data
->blksz
);
1039 if (cmd
->opcode
== MMC_READ_MULTIPLE_BLOCK
||
1040 cmd
->opcode
== MMC_WRITE_MULTIPLE_BLOCK
||
1041 (cmd
->opcode
== SD_IO_RW_EXTENDED
&&
1043 usdhi6_sg_prep(host
);
1045 usdhi6_write(host
, USDHI6_SD_SIZE
, data
->blksz
);
1047 if ((data
->blksz
>= USDHI6_MIN_DMA
||
1048 data
->blocks
> 1) &&
1050 data
->sg
->offset
% 4))
1051 dev_dbg(mmc_dev(host
->mmc
),
1052 "Bad SG of %u: %ux%u @ %u\n", data
->sg_len
,
1053 data
->blksz
, data
->blocks
, data
->sg
->offset
);
1055 /* Enable DMA for USDHI6_MIN_DMA bytes or more */
1056 use_dma
= data
->blksz
>= USDHI6_MIN_DMA
&&
1057 !(data
->blksz
% 4) &&
1058 usdhi6_dma_start(host
) >= DMA_MIN_COOKIE
;
1061 usdhi6_write(host
, USDHI6_CC_EXT_MODE
, USDHI6_CC_EXT_MODE_SDRW
);
1063 dev_dbg(mmc_dev(host
->mmc
),
1064 "%s(): request opcode %u, %u blocks of %u bytes in %u segments, %s %s @+0x%x%s\n",
1065 __func__
, cmd
->opcode
, data
->blocks
, data
->blksz
,
1066 data
->sg_len
, use_dma
? "DMA" : "PIO",
1067 data
->flags
& MMC_DATA_READ
? "read" : "write",
1068 data
->sg
->offset
, mrq
->stop
? " + stop" : "");
1070 dev_dbg(mmc_dev(host
->mmc
), "%s(): request opcode %u\n",
1071 __func__
, cmd
->opcode
);
1074 /* We have to get a command completion interrupt with DMA too */
1075 usdhi6_wait_for_resp(host
);
1077 host
->wait
= USDHI6_WAIT_FOR_CMD
;
1078 schedule_delayed_work(&host
->timeout_work
, host
->timeout
);
1080 /* SEC bit is required to enable block counting by the core */
1081 usdhi6_write(host
, USDHI6_SD_STOP
,
1082 data
&& data
->blocks
> 1 ? USDHI6_SD_STOP_SEC
: 0);
1083 usdhi6_write(host
, USDHI6_SD_ARG
, cmd
->arg
);
1085 /* Kick command execution */
1086 usdhi6_write(host
, USDHI6_SD_CMD
, opc
);
1091 static void usdhi6_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1093 struct usdhi6_host
*host
= mmc_priv(mmc
);
1096 cancel_delayed_work_sync(&host
->timeout_work
);
1101 usdhi6_timeout_set(host
);
1102 ret
= usdhi6_rq_start(host
);
1104 mrq
->cmd
->error
= ret
;
1105 usdhi6_request_done(host
);
1109 static int usdhi6_get_cd(struct mmc_host
*mmc
)
1111 struct usdhi6_host
*host
= mmc_priv(mmc
);
1112 /* Read is atomic, no need to lock */
1113 u32 status
= usdhi6_read(host
, USDHI6_SD_INFO1
) & USDHI6_SD_INFO1_CD
;
1116 * level status.CD CD_ACTIVE_HIGH card present
1122 return !status
^ !(mmc
->caps2
& MMC_CAP2_CD_ACTIVE_HIGH
);
1125 static int usdhi6_get_ro(struct mmc_host
*mmc
)
1127 struct usdhi6_host
*host
= mmc_priv(mmc
);
1128 /* No locking as above */
1129 u32 status
= usdhi6_read(host
, USDHI6_SD_INFO1
) & USDHI6_SD_INFO1_WP
;
1132 * level status.WP RO_ACTIVE_HIGH card read-only
1138 return !status
^ !(mmc
->caps2
& MMC_CAP2_RO_ACTIVE_HIGH
);
1141 static void usdhi6_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1143 struct usdhi6_host
*host
= mmc_priv(mmc
);
1145 dev_dbg(mmc_dev(mmc
), "%s(): %sable\n", __func__
, enable
? "en" : "dis");
1148 host
->sdio_mask
= USDHI6_SDIO_INFO1_IRQ
& ~USDHI6_SDIO_INFO1_IOIRQ
;
1149 usdhi6_write(host
, USDHI6_SDIO_INFO1_MASK
, host
->sdio_mask
);
1150 usdhi6_write(host
, USDHI6_SDIO_MODE
, 1);
1152 usdhi6_write(host
, USDHI6_SDIO_MODE
, 0);
1153 usdhi6_write(host
, USDHI6_SDIO_INFO1_MASK
, USDHI6_SDIO_INFO1_IRQ
);
1154 host
->sdio_mask
= USDHI6_SDIO_INFO1_IRQ
;
1158 static int usdhi6_set_pinstates(struct usdhi6_host
*host
, int voltage
)
1160 if (IS_ERR(host
->pins_uhs
))
1164 case MMC_SIGNAL_VOLTAGE_180
:
1165 case MMC_SIGNAL_VOLTAGE_120
:
1166 return pinctrl_select_state(host
->pinctrl
,
1170 return pinctrl_select_default_state(mmc_dev(host
->mmc
));
1174 static int usdhi6_sig_volt_switch(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1178 ret
= mmc_regulator_set_vqmmc(mmc
, ios
);
1182 ret
= usdhi6_set_pinstates(mmc_priv(mmc
), ios
->signal_voltage
);
1184 dev_warn_once(mmc_dev(mmc
),
1185 "Failed to set pinstate err=%d\n", ret
);
1189 static const struct mmc_host_ops usdhi6_ops
= {
1190 .request
= usdhi6_request
,
1191 .set_ios
= usdhi6_set_ios
,
1192 .get_cd
= usdhi6_get_cd
,
1193 .get_ro
= usdhi6_get_ro
,
1194 .enable_sdio_irq
= usdhi6_enable_sdio_irq
,
1195 .start_signal_voltage_switch
= usdhi6_sig_volt_switch
,
1198 /* State machine handlers */
1200 static void usdhi6_resp_cmd12(struct usdhi6_host
*host
)
1202 struct mmc_command
*cmd
= host
->mrq
->stop
;
1203 cmd
->resp
[0] = usdhi6_read(host
, USDHI6_SD_RSP10
);
1206 static void usdhi6_resp_read(struct usdhi6_host
*host
)
1208 struct mmc_command
*cmd
= host
->mrq
->cmd
;
1209 u32
*rsp
= cmd
->resp
, tmp
= 0;
1218 * resp[0] = r[127..96]
1219 * resp[1] = r[95..64]
1220 * resp[2] = r[63..32]
1221 * resp[3] = r[31..0]
1223 * resp[0] = r[39..8]
1226 if (mmc_resp_type(cmd
) == MMC_RSP_NONE
)
1229 if (!(host
->irq_status
& USDHI6_SD_INFO1_RSP_END
)) {
1230 dev_err(mmc_dev(host
->mmc
),
1231 "CMD%d: response expected but is missing!\n", cmd
->opcode
);
1235 if (mmc_resp_type(cmd
) & MMC_RSP_136
)
1236 for (i
= 0; i
< 4; i
++) {
1238 rsp
[3 - i
] = tmp
>> 24;
1239 tmp
= usdhi6_read(host
, USDHI6_SD_RSP10
+ i
* 8);
1240 rsp
[3 - i
] |= tmp
<< 8;
1242 else if (cmd
->opcode
== MMC_READ_MULTIPLE_BLOCK
||
1243 cmd
->opcode
== MMC_WRITE_MULTIPLE_BLOCK
)
1244 /* Read RSP54 to avoid conflict with auto CMD12 */
1245 rsp
[0] = usdhi6_read(host
, USDHI6_SD_RSP54
);
1247 rsp
[0] = usdhi6_read(host
, USDHI6_SD_RSP10
);
1249 dev_dbg(mmc_dev(host
->mmc
), "Response 0x%x\n", rsp
[0]);
1252 static int usdhi6_blk_read(struct usdhi6_host
*host
)
1254 struct mmc_data
*data
= host
->mrq
->data
;
1258 if (host
->io_error
) {
1259 data
->error
= usdhi6_error_code(host
);
1263 if (host
->pg
.page
) {
1264 p
= host
->blk_page
+ host
->offset
;
1266 p
= usdhi6_sg_map(host
);
1268 data
->error
= -ENOMEM
;
1273 for (i
= 0; i
< data
->blksz
/ 4; i
++, p
++)
1274 *p
= usdhi6_read(host
, USDHI6_SD_BUF0
);
1276 rest
= data
->blksz
% 4;
1277 for (i
= 0; i
< (rest
+ 1) / 2; i
++) {
1278 u16 d
= usdhi6_read16(host
, USDHI6_SD_BUF0
);
1279 ((u8
*)p
)[2 * i
] = ((u8
*)&d
)[0];
1281 ((u8
*)p
)[2 * i
+ 1] = ((u8
*)&d
)[1];
1287 dev_dbg(mmc_dev(host
->mmc
), "%s(): %d\n", __func__
, data
->error
);
1288 host
->wait
= USDHI6_WAIT_FOR_REQUEST
;
1292 static int usdhi6_blk_write(struct usdhi6_host
*host
)
1294 struct mmc_data
*data
= host
->mrq
->data
;
1298 if (host
->io_error
) {
1299 data
->error
= usdhi6_error_code(host
);
1303 if (host
->pg
.page
) {
1304 p
= host
->blk_page
+ host
->offset
;
1306 p
= usdhi6_sg_map(host
);
1308 data
->error
= -ENOMEM
;
1313 for (i
= 0; i
< data
->blksz
/ 4; i
++, p
++)
1314 usdhi6_write(host
, USDHI6_SD_BUF0
, *p
);
1316 rest
= data
->blksz
% 4;
1317 for (i
= 0; i
< (rest
+ 1) / 2; i
++) {
1319 ((u8
*)&d
)[0] = ((u8
*)p
)[2 * i
];
1321 ((u8
*)&d
)[1] = ((u8
*)p
)[2 * i
+ 1];
1324 usdhi6_write16(host
, USDHI6_SD_BUF0
, d
);
1330 dev_dbg(mmc_dev(host
->mmc
), "%s(): %d\n", __func__
, data
->error
);
1331 host
->wait
= USDHI6_WAIT_FOR_REQUEST
;
1335 static int usdhi6_stop_cmd(struct usdhi6_host
*host
)
1337 struct mmc_request
*mrq
= host
->mrq
;
1339 switch (mrq
->cmd
->opcode
) {
1340 case MMC_READ_MULTIPLE_BLOCK
:
1341 case MMC_WRITE_MULTIPLE_BLOCK
:
1342 if (mrq
->stop
->opcode
== MMC_STOP_TRANSMISSION
) {
1343 host
->wait
= USDHI6_WAIT_FOR_STOP
;
1346 fallthrough
; /* Unsupported STOP command */
1348 dev_err(mmc_dev(host
->mmc
),
1349 "unsupported stop CMD%d for CMD%d\n",
1350 mrq
->stop
->opcode
, mrq
->cmd
->opcode
);
1351 mrq
->stop
->error
= -EOPNOTSUPP
;
1357 static bool usdhi6_end_cmd(struct usdhi6_host
*host
)
1359 struct mmc_request
*mrq
= host
->mrq
;
1360 struct mmc_command
*cmd
= mrq
->cmd
;
1362 if (host
->io_error
) {
1363 cmd
->error
= usdhi6_error_code(host
);
1367 usdhi6_resp_read(host
);
1372 if (host
->dma_active
) {
1373 usdhi6_dma_kick(host
);
1375 host
->wait
= USDHI6_WAIT_FOR_DMA
;
1376 else if (usdhi6_stop_cmd(host
) < 0)
1378 } else if (mrq
->data
->flags
& MMC_DATA_READ
) {
1379 if (cmd
->opcode
== MMC_READ_MULTIPLE_BLOCK
||
1380 (cmd
->opcode
== SD_IO_RW_EXTENDED
&&
1381 mrq
->data
->blocks
> 1))
1382 host
->wait
= USDHI6_WAIT_FOR_MREAD
;
1384 host
->wait
= USDHI6_WAIT_FOR_READ
;
1386 if (cmd
->opcode
== MMC_WRITE_MULTIPLE_BLOCK
||
1387 (cmd
->opcode
== SD_IO_RW_EXTENDED
&&
1388 mrq
->data
->blocks
> 1))
1389 host
->wait
= USDHI6_WAIT_FOR_MWRITE
;
1391 host
->wait
= USDHI6_WAIT_FOR_WRITE
;
1397 static bool usdhi6_read_block(struct usdhi6_host
*host
)
1399 /* ACCESS_END IRQ is already unmasked */
1400 int ret
= usdhi6_blk_read(host
);
1403 * Have to force unmapping both pages: the single block could have been
1404 * cross-page, in which case for single-block IO host->page_idx == 0.
1405 * So, if we don't force, the second page won't be unmapped.
1407 usdhi6_sg_unmap(host
, true);
1412 host
->wait
= USDHI6_WAIT_FOR_DATA_END
;
1416 static bool usdhi6_mread_block(struct usdhi6_host
*host
)
1418 int ret
= usdhi6_blk_read(host
);
1423 usdhi6_sg_advance(host
);
1425 return !host
->mrq
->data
->error
&&
1426 (host
->wait
!= USDHI6_WAIT_FOR_DATA_END
|| !host
->mrq
->stop
);
1429 static bool usdhi6_write_block(struct usdhi6_host
*host
)
1431 int ret
= usdhi6_blk_write(host
);
1433 /* See comment in usdhi6_read_block() */
1434 usdhi6_sg_unmap(host
, true);
1439 host
->wait
= USDHI6_WAIT_FOR_DATA_END
;
1443 static bool usdhi6_mwrite_block(struct usdhi6_host
*host
)
1445 int ret
= usdhi6_blk_write(host
);
1450 usdhi6_sg_advance(host
);
1452 return !host
->mrq
->data
->error
&&
1453 (host
->wait
!= USDHI6_WAIT_FOR_DATA_END
|| !host
->mrq
->stop
);
1456 /* Interrupt & timeout handlers */
1458 static irqreturn_t
usdhi6_sd_bh(int irq
, void *dev_id
)
1460 struct usdhi6_host
*host
= dev_id
;
1461 struct mmc_request
*mrq
;
1462 struct mmc_command
*cmd
;
1463 struct mmc_data
*data
;
1464 bool io_wait
= false;
1466 cancel_delayed_work_sync(&host
->timeout_work
);
1475 switch (host
->wait
) {
1476 case USDHI6_WAIT_FOR_REQUEST
:
1477 /* We're too late, the timeout has already kicked in */
1479 case USDHI6_WAIT_FOR_CMD
:
1480 /* Wait for data? */
1481 io_wait
= usdhi6_end_cmd(host
);
1483 case USDHI6_WAIT_FOR_MREAD
:
1484 /* Wait for more data? */
1485 io_wait
= usdhi6_mread_block(host
);
1487 case USDHI6_WAIT_FOR_READ
:
1488 /* Wait for data end? */
1489 io_wait
= usdhi6_read_block(host
);
1491 case USDHI6_WAIT_FOR_MWRITE
:
1492 /* Wait data to write? */
1493 io_wait
= usdhi6_mwrite_block(host
);
1495 case USDHI6_WAIT_FOR_WRITE
:
1496 /* Wait for data end? */
1497 io_wait
= usdhi6_write_block(host
);
1499 case USDHI6_WAIT_FOR_DMA
:
1500 usdhi6_dma_check_error(host
);
1502 case USDHI6_WAIT_FOR_STOP
:
1503 usdhi6_write(host
, USDHI6_SD_STOP
, 0);
1504 if (host
->io_error
) {
1505 int ret
= usdhi6_error_code(host
);
1507 mrq
->stop
->error
= ret
;
1509 mrq
->data
->error
= ret
;
1510 dev_warn(mmc_dev(host
->mmc
), "%s(): %d\n", __func__
, ret
);
1513 usdhi6_resp_cmd12(host
);
1514 mrq
->stop
->error
= 0;
1516 case USDHI6_WAIT_FOR_DATA_END
:
1517 if (host
->io_error
) {
1518 mrq
->data
->error
= usdhi6_error_code(host
);
1519 dev_warn(mmc_dev(host
->mmc
), "%s(): %d\n", __func__
,
1524 cmd
->error
= -EFAULT
;
1525 dev_err(mmc_dev(host
->mmc
), "Invalid state %u\n", host
->wait
);
1526 usdhi6_request_done(host
);
1531 schedule_delayed_work(&host
->timeout_work
, host
->timeout
);
1532 /* Wait for more data or ACCESS_END */
1533 if (!host
->dma_active
)
1534 usdhi6_wait_for_brwe(host
, mrq
->data
->flags
& MMC_DATA_READ
);
1541 if (host
->wait
!= USDHI6_WAIT_FOR_STOP
&&
1543 !host
->mrq
->stop
->error
&&
1544 !usdhi6_stop_cmd(host
)) {
1546 usdhi6_wait_for_resp(host
);
1548 schedule_delayed_work(&host
->timeout_work
,
1554 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
1556 /* Data error: might need to unmap the last page */
1557 dev_warn(mmc_dev(host
->mmc
), "%s(): data error %d\n",
1558 __func__
, data
->error
);
1559 usdhi6_sg_unmap(host
, true);
1561 } else if (cmd
->opcode
== MMC_APP_CMD
) {
1562 host
->app_cmd
= true;
1566 usdhi6_request_done(host
);
1571 static irqreturn_t
usdhi6_sd(int irq
, void *dev_id
)
1573 struct usdhi6_host
*host
= dev_id
;
1574 u16 status
, status2
, error
;
1576 status
= usdhi6_read(host
, USDHI6_SD_INFO1
) & ~host
->status_mask
&
1577 ~USDHI6_SD_INFO1_CARD
;
1578 status2
= usdhi6_read(host
, USDHI6_SD_INFO2
) & ~host
->status2_mask
;
1580 usdhi6_only_cd(host
);
1582 dev_dbg(mmc_dev(host
->mmc
),
1583 "IRQ status = 0x%08x, status2 = 0x%08x\n", status
, status2
);
1585 if (!status
&& !status2
)
1588 error
= status2
& USDHI6_SD_INFO2_ERR
;
1590 /* Ack / clear interrupts */
1591 if (USDHI6_SD_INFO1_IRQ
& status
)
1592 usdhi6_write(host
, USDHI6_SD_INFO1
,
1593 0xffff & ~(USDHI6_SD_INFO1_IRQ
& status
));
1595 if (USDHI6_SD_INFO2_IRQ
& status2
) {
1597 /* In error cases BWE and BRE aren't cleared automatically */
1598 status2
|= USDHI6_SD_INFO2_BWE
| USDHI6_SD_INFO2_BRE
;
1600 usdhi6_write(host
, USDHI6_SD_INFO2
,
1601 0xffff & ~(USDHI6_SD_INFO2_IRQ
& status2
));
1604 host
->io_error
= error
;
1605 host
->irq_status
= status
;
1608 /* Don't pollute the log with unsupported command timeouts */
1609 if (host
->wait
!= USDHI6_WAIT_FOR_CMD
||
1610 error
!= USDHI6_SD_INFO2_RSP_TOUT
)
1611 dev_warn(mmc_dev(host
->mmc
),
1612 "%s(): INFO2 error bits 0x%08x\n",
1615 dev_dbg(mmc_dev(host
->mmc
),
1616 "%s(): INFO2 error bits 0x%08x\n",
1620 return IRQ_WAKE_THREAD
;
1623 static irqreturn_t
usdhi6_sdio(int irq
, void *dev_id
)
1625 struct usdhi6_host
*host
= dev_id
;
1626 u32 status
= usdhi6_read(host
, USDHI6_SDIO_INFO1
) & ~host
->sdio_mask
;
1628 dev_dbg(mmc_dev(host
->mmc
), "%s(): status 0x%x\n", __func__
, status
);
1633 usdhi6_write(host
, USDHI6_SDIO_INFO1
, ~status
);
1635 mmc_signal_sdio_irq(host
->mmc
);
1640 static irqreturn_t
usdhi6_cd(int irq
, void *dev_id
)
1642 struct usdhi6_host
*host
= dev_id
;
1643 struct mmc_host
*mmc
= host
->mmc
;
1646 /* We're only interested in hotplug events here */
1647 status
= usdhi6_read(host
, USDHI6_SD_INFO1
) & ~host
->status_mask
&
1648 USDHI6_SD_INFO1_CARD
;
1654 usdhi6_write(host
, USDHI6_SD_INFO1
, ~status
);
1656 if (!work_pending(&mmc
->detect
.work
) &&
1657 (((status
& USDHI6_SD_INFO1_CARD_INSERT
) &&
1659 ((status
& USDHI6_SD_INFO1_CARD_EJECT
) &&
1661 mmc_detect_change(mmc
, msecs_to_jiffies(100));
1667 * Actually this should not be needed, if the built-in timeout works reliably in
1668 * the both PIO cases and DMA never fails. But if DMA does fail, a timeout
1669 * handler might be the only way to catch the error.
1671 static void usdhi6_timeout_work(struct work_struct
*work
)
1673 struct delayed_work
*d
= to_delayed_work(work
);
1674 struct usdhi6_host
*host
= container_of(d
, struct usdhi6_host
, timeout_work
);
1675 struct mmc_request
*mrq
= host
->mrq
;
1676 struct mmc_data
*data
= mrq
? mrq
->data
: NULL
;
1677 struct scatterlist
*sg
;
1679 dev_warn(mmc_dev(host
->mmc
),
1680 "%s timeout wait %u CMD%d: IRQ 0x%08x:0x%08x, last IRQ 0x%08x\n",
1681 host
->dma_active
? "DMA" : "PIO",
1682 host
->wait
, mrq
? mrq
->cmd
->opcode
: -1,
1683 usdhi6_read(host
, USDHI6_SD_INFO1
),
1684 usdhi6_read(host
, USDHI6_SD_INFO2
), host
->irq_status
);
1686 if (host
->dma_active
) {
1687 usdhi6_dma_kill(host
);
1688 usdhi6_dma_stop_unmap(host
);
1691 switch (host
->wait
) {
1693 dev_err(mmc_dev(host
->mmc
), "Invalid state %u\n", host
->wait
);
1694 fallthrough
; /* mrq can be NULL, but is impossible */
1695 case USDHI6_WAIT_FOR_CMD
:
1696 usdhi6_error_code(host
);
1698 mrq
->cmd
->error
= -ETIMEDOUT
;
1700 case USDHI6_WAIT_FOR_STOP
:
1701 usdhi6_error_code(host
);
1702 mrq
->stop
->error
= -ETIMEDOUT
;
1704 case USDHI6_WAIT_FOR_DMA
:
1705 case USDHI6_WAIT_FOR_MREAD
:
1706 case USDHI6_WAIT_FOR_MWRITE
:
1707 case USDHI6_WAIT_FOR_READ
:
1708 case USDHI6_WAIT_FOR_WRITE
:
1709 sg
= host
->sg
?: data
->sg
;
1710 dev_dbg(mmc_dev(host
->mmc
),
1711 "%c: page #%u @ +0x%zx %ux%u in SG%u. Current SG %u bytes @ %u\n",
1712 data
->flags
& MMC_DATA_READ
? 'R' : 'W', host
->page_idx
,
1713 host
->offset
, data
->blocks
, data
->blksz
, data
->sg_len
,
1714 sg_dma_len(sg
), sg
->offset
);
1715 usdhi6_sg_unmap(host
, true);
1716 fallthrough
; /* page unmapped in USDHI6_WAIT_FOR_DATA_END */
1717 case USDHI6_WAIT_FOR_DATA_END
:
1718 usdhi6_error_code(host
);
1719 data
->error
= -ETIMEDOUT
;
1723 usdhi6_request_done(host
);
1726 /* Probe / release */
1728 static const struct of_device_id usdhi6_of_match
[] = {
1729 {.compatible
= "renesas,usdhi6rol0"},
1732 MODULE_DEVICE_TABLE(of
, usdhi6_of_match
);
1734 static int usdhi6_probe(struct platform_device
*pdev
)
1736 struct device
*dev
= &pdev
->dev
;
1737 struct mmc_host
*mmc
;
1738 struct usdhi6_host
*host
;
1739 struct resource
*res
;
1740 int irq_cd
, irq_sd
, irq_sdio
;
1747 irq_cd
= platform_get_irq_byname(pdev
, "card detect");
1748 irq_sd
= platform_get_irq_byname(pdev
, "data");
1749 irq_sdio
= platform_get_irq_byname(pdev
, "SDIO");
1750 if (irq_sd
< 0 || irq_sdio
< 0)
1753 mmc
= mmc_alloc_host(sizeof(struct usdhi6_host
), dev
);
1757 ret
= mmc_regulator_get_supply(mmc
);
1761 ret
= mmc_of_parse(mmc
);
1765 host
= mmc_priv(mmc
);
1767 host
->wait
= USDHI6_WAIT_FOR_REQUEST
;
1768 host
->timeout
= msecs_to_jiffies(USDHI6_REQ_TIMEOUT_MS
);
1770 * We use a fixed timeout of 4s, hence inform the core about it. A
1771 * future improvement should instead respect the cmd->busy_timeout.
1773 mmc
->max_busy_timeout
= USDHI6_REQ_TIMEOUT_MS
;
1775 host
->pinctrl
= devm_pinctrl_get(&pdev
->dev
);
1776 if (IS_ERR(host
->pinctrl
)) {
1777 ret
= PTR_ERR(host
->pinctrl
);
1781 host
->pins_uhs
= pinctrl_lookup_state(host
->pinctrl
, "state_uhs");
1783 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1784 host
->base
= devm_ioremap_resource(dev
, res
);
1785 if (IS_ERR(host
->base
)) {
1786 ret
= PTR_ERR(host
->base
);
1790 host
->clk
= devm_clk_get(dev
, NULL
);
1791 if (IS_ERR(host
->clk
)) {
1792 ret
= PTR_ERR(host
->clk
);
1796 host
->imclk
= clk_get_rate(host
->clk
);
1798 ret
= clk_prepare_enable(host
->clk
);
1802 version
= usdhi6_read(host
, USDHI6_VERSION
);
1803 if ((version
& 0xfff) != 0xa0d) {
1804 dev_err(dev
, "Version not recognized %x\n", version
);
1808 dev_info(dev
, "A USDHI6ROL0 SD host detected with %d ports\n",
1809 usdhi6_read(host
, USDHI6_SD_PORT_SEL
) >> USDHI6_SD_PORT_SEL_PORTS_SHIFT
);
1811 usdhi6_mask_all(host
);
1814 ret
= devm_request_irq(dev
, irq_cd
, usdhi6_cd
, 0,
1815 dev_name(dev
), host
);
1819 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
1822 ret
= devm_request_threaded_irq(dev
, irq_sd
, usdhi6_sd
, usdhi6_sd_bh
, 0,
1823 dev_name(dev
), host
);
1827 ret
= devm_request_irq(dev
, irq_sdio
, usdhi6_sdio
, 0,
1828 dev_name(dev
), host
);
1832 INIT_DELAYED_WORK(&host
->timeout_work
, usdhi6_timeout_work
);
1834 usdhi6_dma_request(host
, res
->start
);
1836 mmc
->ops
= &usdhi6_ops
;
1837 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
|
1839 /* Set .max_segs to some random number. Feel free to adjust. */
1841 mmc
->max_blk_size
= 512;
1842 mmc
->max_req_size
= PAGE_SIZE
* mmc
->max_segs
;
1843 mmc
->max_blk_count
= mmc
->max_req_size
/ mmc
->max_blk_size
;
1845 * Setting .max_seg_size to 1 page would simplify our page-mapping code,
1846 * But OTOH, having large segments makes DMA more efficient. We could
1847 * check, whether we managed to get DMA and fall back to 1 page
1848 * segments, but if we do manage to obtain DMA and then it fails at
1849 * run-time and we fall back to PIO, we will continue getting large
1850 * segments. So, we wouldn't be able to get rid of the code anyway.
1852 mmc
->max_seg_size
= mmc
->max_req_size
;
1854 mmc
->f_max
= host
->imclk
;
1855 mmc
->f_min
= host
->imclk
/ 512;
1857 platform_set_drvdata(pdev
, host
);
1859 ret
= mmc_add_host(mmc
);
1866 clk_disable_unprepare(host
->clk
);
1873 static int usdhi6_remove(struct platform_device
*pdev
)
1875 struct usdhi6_host
*host
= platform_get_drvdata(pdev
);
1877 mmc_remove_host(host
->mmc
);
1879 usdhi6_mask_all(host
);
1880 cancel_delayed_work_sync(&host
->timeout_work
);
1881 usdhi6_dma_release(host
);
1882 clk_disable_unprepare(host
->clk
);
1883 mmc_free_host(host
->mmc
);
1888 static struct platform_driver usdhi6_driver
= {
1889 .probe
= usdhi6_probe
,
1890 .remove
= usdhi6_remove
,
1892 .name
= "usdhi6rol0",
1893 .probe_type
= PROBE_PREFER_ASYNCHRONOUS
,
1894 .of_match_table
= usdhi6_of_match
,
1898 module_platform_driver(usdhi6_driver
);
1900 MODULE_DESCRIPTION("Renesas usdhi6rol0 SD/SDIO host driver");
1901 MODULE_LICENSE("GPL v2");
1902 MODULE_ALIAS("platform:usdhi6rol0");
1903 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");