?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / mtd / nand / raw / mtk_ecc.c
blob75f1fa3d4d35ca249b97684a31b1fab5e9bf78c6
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * MTK ECC controller driver.
4 * Copyright (C) 2016 MediaTek Inc.
5 * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
7 */
8
9 #include <linux/platform_device.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/iopoll.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/mutex.h>
18
19 #include "mtk_ecc.h"
20
21 #define ECC_IDLE_MASK BIT(0)
22 #define ECC_IRQ_EN BIT(0)
23 #define ECC_PG_IRQ_SEL BIT(1)
24 #define ECC_OP_ENABLE (1)
25 #define ECC_OP_DISABLE (0)
26
27 #define ECC_ENCCON (0x00)
28 #define ECC_ENCCNFG (0x04)
29 #define ECC_MS_SHIFT (16)
30 #define ECC_ENCDIADDR (0x08)
31 #define ECC_ENCIDLE (0x0C)
32 #define ECC_DECCON (0x100)
33 #define ECC_DECCNFG (0x104)
34 #define DEC_EMPTY_EN BIT(31)
35 #define DEC_CNFG_CORRECT (0x3 << 12)
36 #define ECC_DECIDLE (0x10C)
37 #define ECC_DECENUM0 (0x114)
38
39 #define ECC_TIMEOUT (500000)
40
41 #define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
42 #define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
43
44 struct mtk_ecc_caps {
45 u32 err_mask;
46 const u8 *ecc_strength;
47 const u32 *ecc_regs;
48 u8 num_ecc_strength;
49 u8 ecc_mode_shift;
50 u32 parity_bits;
51 int pg_irq_sel;
52 };
53
54 struct mtk_ecc {
55 struct device *dev;
56 const struct mtk_ecc_caps *caps;
57 void __iomem *regs;
58 struct clk *clk;
59
60 struct completion done;
61 struct mutex lock;
62 u32 sectors;
63
64 u8 *eccdata;
65 };
66
67 /* ecc strength that each IP supports */
68 static const u8 ecc_strength_mt2701[] = {
69 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
70 40, 44, 48, 52, 56, 60
71 };
72
73 static const u8 ecc_strength_mt2712[] = {
74 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
75 40, 44, 48, 52, 56, 60, 68, 72, 80
76 };
77
78 static const u8 ecc_strength_mt7622[] = {
79 4, 6, 8, 10, 12, 14, 16
80 };
81
82 enum mtk_ecc_regs {
83 ECC_ENCPAR00,
84 ECC_ENCIRQ_EN,
85 ECC_ENCIRQ_STA,
86 ECC_DECDONE,
87 ECC_DECIRQ_EN,
88 ECC_DECIRQ_STA,
89 };
90
91 static int mt2701_ecc_regs[] = {
92 [ECC_ENCPAR00] = 0x10,
93 [ECC_ENCIRQ_EN] = 0x80,
94 [ECC_ENCIRQ_STA] = 0x84,
95 [ECC_DECDONE] = 0x124,
96 [ECC_DECIRQ_EN] = 0x200,
97 [ECC_DECIRQ_STA] = 0x204,
98 };
99
100 static int mt2712_ecc_regs[] = {
101 [ECC_ENCPAR00] = 0x300,
102 [ECC_ENCIRQ_EN] = 0x80,
103 [ECC_ENCIRQ_STA] = 0x84,
104 [ECC_DECDONE] = 0x124,
105 [ECC_DECIRQ_EN] = 0x200,
106 [ECC_DECIRQ_STA] = 0x204,
107 };
108
109 static int mt7622_ecc_regs[] = {
110 [ECC_ENCPAR00] = 0x10,
111 [ECC_ENCIRQ_EN] = 0x30,
112 [ECC_ENCIRQ_STA] = 0x34,
113 [ECC_DECDONE] = 0x11c,
114 [ECC_DECIRQ_EN] = 0x140,
115 [ECC_DECIRQ_STA] = 0x144,
116 };
117
118 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
119 enum mtk_ecc_operation op)
120 {
121 struct device *dev = ecc->dev;
122 u32 val;
123 int ret;
124
125 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
126 val & ECC_IDLE_MASK,
127 10, ECC_TIMEOUT);
128 if (ret)
129 dev_warn(dev, "%s NOT idle\n",
130 op == ECC_ENCODE ? "encoder" : "decoder");
131 }
132
133 static irqreturn_t mtk_ecc_irq(int irq, void *id)
134 {
135 struct mtk_ecc *ecc = id;
136 u32 dec, enc;
137
138 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
139 & ECC_IRQ_EN;
140 if (dec) {
141 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
142 if (dec & ecc->sectors) {
143 /*
144 * Clear decode IRQ status once again to ensure that
145 * there will be no extra IRQ.
146 */
147 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
148 ecc->sectors = 0;
149 complete(&ecc->done);
150 } else {
151 return IRQ_HANDLED;
152 }
153 } else {
154 enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
155 & ECC_IRQ_EN;
156 if (enc)
157 complete(&ecc->done);
158 else
159 return IRQ_NONE;
160 }
161
162 return IRQ_HANDLED;
163 }
164
165 static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
166 {
167 u32 ecc_bit, dec_sz, enc_sz;
168 u32 reg, i;
169
170 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
171 if (ecc->caps->ecc_strength[i] == config->strength)
172 break;
173 }
174
175 if (i == ecc->caps->num_ecc_strength) {
176 dev_err(ecc->dev, "invalid ecc strength %d\n",
177 config->strength);
178 return -EINVAL;
179 }
180
181 ecc_bit = i;
182
183 if (config->op == ECC_ENCODE) {
184 /* configure ECC encoder (in bits) */
185 enc_sz = config->len << 3;
186
187 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
188 reg |= (enc_sz << ECC_MS_SHIFT);
189 writel(reg, ecc->regs + ECC_ENCCNFG);
190
191 if (config->mode != ECC_NFI_MODE)
192 writel(lower_32_bits(config->addr),
193 ecc->regs + ECC_ENCDIADDR);
194
195 } else {
196 /* configure ECC decoder (in bits) */
197 dec_sz = (config->len << 3) +
198 config->strength * ecc->caps->parity_bits;
199
200 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
201 reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
202 reg |= DEC_EMPTY_EN;
203 writel(reg, ecc->regs + ECC_DECCNFG);
204
205 if (config->sectors)
206 ecc->sectors = 1 << (config->sectors - 1);
207 }
208
209 return 0;
210 }
211
212 void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
213 int sectors)
214 {
215 u32 offset, i, err;
216 u32 bitflips = 0;
217
218 stats->corrected = 0;
219 stats->failed = 0;
220
221 for (i = 0; i < sectors; i++) {
222 offset = (i >> 2) << 2;
223 err = readl(ecc->regs + ECC_DECENUM0 + offset);
224 err = err >> ((i % 4) * 8);
225 err &= ecc->caps->err_mask;
226 if (err == ecc->caps->err_mask) {
227 /* uncorrectable errors */
228 stats->failed++;
229 continue;
230 }
231
232 stats->corrected += err;
233 bitflips = max_t(u32, bitflips, err);
234 }
235
236 stats->bitflips = bitflips;
237 }
238 EXPORT_SYMBOL(mtk_ecc_get_stats);
239
240 void mtk_ecc_release(struct mtk_ecc *ecc)
241 {
242 clk_disable_unprepare(ecc->clk);
243 put_device(ecc->dev);
244 }
245 EXPORT_SYMBOL(mtk_ecc_release);
246
247 static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
248 {
249 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
250 writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
251
252 mtk_ecc_wait_idle(ecc, ECC_DECODE);
253 writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
254 }
255
256 static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
257 {
258 struct platform_device *pdev;
259 struct mtk_ecc *ecc;
260
261 pdev = of_find_device_by_node(np);
262 if (!pdev)
263 return ERR_PTR(-EPROBE_DEFER);
264
265 ecc = platform_get_drvdata(pdev);
266 if (!ecc) {
267 put_device(&pdev->dev);
268 return ERR_PTR(-EPROBE_DEFER);
269 }
270
271 clk_prepare_enable(ecc->clk);
272 mtk_ecc_hw_init(ecc);
273
274 return ecc;
275 }
276
277 struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
278 {
279 struct mtk_ecc *ecc = NULL;
280 struct device_node *np;
281
282 np = of_parse_phandle(of_node, "ecc-engine", 0);
283 if (np) {
284 ecc = mtk_ecc_get(np);
285 of_node_put(np);
286 }
287
288 return ecc;
289 }
290 EXPORT_SYMBOL(of_mtk_ecc_get);
291
292 int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
293 {
294 enum mtk_ecc_operation op = config->op;
295 u16 reg_val;
296 int ret;
297
298 ret = mutex_lock_interruptible(&ecc->lock);
299 if (ret) {
300 dev_err(ecc->dev, "interrupted when attempting to lock\n");
301 return ret;
302 }
303
304 mtk_ecc_wait_idle(ecc, op);
305
306 ret = mtk_ecc_config(ecc, config);
307 if (ret) {
308 mutex_unlock(&ecc->lock);
309 return ret;
310 }
311
312 if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
313 init_completion(&ecc->done);
314 reg_val = ECC_IRQ_EN;
315 /*
316 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
317 * means this chip can only generate one ecc irq during page
318 * read / write. If is 0, generate one ecc irq each ecc step.
319 */
320 if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
321 reg_val |= ECC_PG_IRQ_SEL;
322 if (op == ECC_ENCODE)
323 writew(reg_val, ecc->regs +
324 ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
325 else
326 writew(reg_val, ecc->regs +
327 ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
328 }
329
330 writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
331
332 return 0;
333 }
334 EXPORT_SYMBOL(mtk_ecc_enable);
335
336 void mtk_ecc_disable(struct mtk_ecc *ecc)
337 {
338 enum mtk_ecc_operation op = ECC_ENCODE;
339
340 /* find out the running operation */
341 if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
342 op = ECC_DECODE;
343
344 /* disable it */
345 mtk_ecc_wait_idle(ecc, op);
346 if (op == ECC_DECODE) {
347 /*
348 * Clear decode IRQ status in case there is a timeout to wait
349 * decode IRQ.
350 */
351 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
352 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
353 } else {
354 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
355 }
356
357 writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
358
359 mutex_unlock(&ecc->lock);
360 }
361 EXPORT_SYMBOL(mtk_ecc_disable);
362
363 int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
364 {
365 int ret;
366
367 ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
368 if (!ret) {
369 dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
370 (op == ECC_ENCODE) ? "encoder" : "decoder");
371 return -ETIMEDOUT;
372 }
373
374 return 0;
375 }
376 EXPORT_SYMBOL(mtk_ecc_wait_done);
377
378 int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
379 u8 *data, u32 bytes)
380 {
381 dma_addr_t addr;
382 u32 len;
383 int ret;
384
385 addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
386 ret = dma_mapping_error(ecc->dev, addr);
387 if (ret) {
388 dev_err(ecc->dev, "dma mapping error\n");
389 return -EINVAL;
390 }
391
392 config->op = ECC_ENCODE;
393 config->addr = addr;
394 ret = mtk_ecc_enable(ecc, config);
395 if (ret) {
396 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
397 return ret;
398 }
399
400 ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
401 if (ret)
402 goto timeout;
403
404 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
405
406 /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
407 len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
408
409 /* write the parity bytes generated by the ECC back to temp buffer */
410 __ioread32_copy(ecc->eccdata,
411 ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
412 round_up(len, 4));
413
414 /* copy into possibly unaligned OOB region with actual length */
415 memcpy(data + bytes, ecc->eccdata, len);
416 timeout:
417
418 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
419 mtk_ecc_disable(ecc);
420
421 return ret;
422 }
423 EXPORT_SYMBOL(mtk_ecc_encode);
424
425 void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
426 {
427 const u8 *ecc_strength = ecc->caps->ecc_strength;
428 int i;
429
430 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
431 if (*p <= ecc_strength[i]) {
432 if (!i)
433 *p = ecc_strength[i];
434 else if (*p != ecc_strength[i])
435 *p = ecc_strength[i - 1];
436 return;
437 }
438 }
439
440 *p = ecc_strength[ecc->caps->num_ecc_strength - 1];
441 }
442 EXPORT_SYMBOL(mtk_ecc_adjust_strength);
443
444 unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
445 {
446 return ecc->caps->parity_bits;
447 }
448 EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
449
450 static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
451 .err_mask = 0x3f,
452 .ecc_strength = ecc_strength_mt2701,
453 .ecc_regs = mt2701_ecc_regs,
454 .num_ecc_strength = 20,
455 .ecc_mode_shift = 5,
456 .parity_bits = 14,
457 .pg_irq_sel = 0,
458 };
459
460 static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
461 .err_mask = 0x7f,
462 .ecc_strength = ecc_strength_mt2712,
463 .ecc_regs = mt2712_ecc_regs,
464 .num_ecc_strength = 23,
465 .ecc_mode_shift = 5,
466 .parity_bits = 14,
467 .pg_irq_sel = 1,
468 };
469
470 static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {
471 .err_mask = 0x3f,
472 .ecc_strength = ecc_strength_mt7622,
473 .ecc_regs = mt7622_ecc_regs,
474 .num_ecc_strength = 7,
475 .ecc_mode_shift = 4,
476 .parity_bits = 13,
477 .pg_irq_sel = 0,
478 };
479
480 static const struct of_device_id mtk_ecc_dt_match[] = {
481 {
482 .compatible = "mediatek,mt2701-ecc",
483 .data = &mtk_ecc_caps_mt2701,
484 }, {
485 .compatible = "mediatek,mt2712-ecc",
486 .data = &mtk_ecc_caps_mt2712,
487 }, {
488 .compatible = "mediatek,mt7622-ecc",
489 .data = &mtk_ecc_caps_mt7622,
490 },
491 {},
492 };
493
494 static int mtk_ecc_probe(struct platform_device *pdev)
495 {
496 struct device *dev = &pdev->dev;
497 struct mtk_ecc *ecc;
498 struct resource *res;
499 u32 max_eccdata_size;
500 int irq, ret;
501
502 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
503 if (!ecc)
504 return -ENOMEM;
505
506 ecc->caps = of_device_get_match_data(dev);
507
508 max_eccdata_size = ecc->caps->num_ecc_strength - 1;
509 max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
510 max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
511 max_eccdata_size = round_up(max_eccdata_size, 4);
512 ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
513 if (!ecc->eccdata)
514 return -ENOMEM;
515
516 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
517 ecc->regs = devm_ioremap_resource(dev, res);
518 if (IS_ERR(ecc->regs)) {
519 dev_err(dev, "failed to map regs: %ld\n", PTR_ERR(ecc->regs));
520 return PTR_ERR(ecc->regs);
521 }
522
523 ecc->clk = devm_clk_get(dev, NULL);
524 if (IS_ERR(ecc->clk)) {
525 dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
526 return PTR_ERR(ecc->clk);
527 }
528
529 irq = platform_get_irq(pdev, 0);
530 if (irq < 0)
531 return irq;
532
533 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
534 if (ret) {
535 dev_err(dev, "failed to set DMA mask\n");
536 return ret;
537 }
538
539 ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
540 if (ret) {
541 dev_err(dev, "failed to request irq\n");
542 return -EINVAL;
543 }
544
545 ecc->dev = dev;
546 mutex_init(&ecc->lock);
547 platform_set_drvdata(pdev, ecc);
548 dev_info(dev, "probed\n");
549
550 return 0;
551 }
552
553 #ifdef CONFIG_PM_SLEEP
554 static int mtk_ecc_suspend(struct device *dev)
555 {
556 struct mtk_ecc *ecc = dev_get_drvdata(dev);
557
558 clk_disable_unprepare(ecc->clk);
559
560 return 0;
561 }
562
563 static int mtk_ecc_resume(struct device *dev)
564 {
565 struct mtk_ecc *ecc = dev_get_drvdata(dev);
566 int ret;
567
568 ret = clk_prepare_enable(ecc->clk);
569 if (ret) {
570 dev_err(dev, "failed to enable clk\n");
571 return ret;
572 }
573
574 return 0;
575 }
576
577 static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
578 #endif
579
580 MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
581
582 static struct platform_driver mtk_ecc_driver = {
583 .probe = mtk_ecc_probe,
584 .driver = {
585 .name = "mtk-ecc",
586 .of_match_table = of_match_ptr(mtk_ecc_dt_match),
587 #ifdef CONFIG_PM_SLEEP
588 .pm = &mtk_ecc_pm_ops,
589 #endif
590 },
591 };
592
593 module_platform_driver(mtk_ecc_driver);
594
595 MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
596 MODULE_DESCRIPTION("MTK Nand ECC Driver");
597 MODULE_LICENSE("Dual MIT/GPL");
Linux with added FPC-III support