?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / mtd / nand / raw / nandsim.c
blobf2b9250c0ea830b4096c2011e4442498fca95944
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * NAND flash simulator.
4 *
5 * Author: Artem B. Bityuckiy <dedekind@oktetlabs.ru>, <dedekind@infradead.org>
6 *
7 * Copyright (C) 2004 Nokia Corporation
8 *
9 * Note: NS means "NAND Simulator".
10 * Note: Input means input TO flash chip, output means output FROM chip.
11 */
12
13 #define pr_fmt(fmt) "[nandsim]" fmt
14
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/vmalloc.h>
20 #include <linux/math64.h>
21 #include <linux/slab.h>
22 #include <linux/errno.h>
23 #include <linux/string.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/rawnand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/delay.h>
28 #include <linux/list.h>
29 #include <linux/random.h>
30 #include <linux/sched.h>
31 #include <linux/sched/mm.h>
32 #include <linux/fs.h>
33 #include <linux/pagemap.h>
34 #include <linux/seq_file.h>
35 #include <linux/debugfs.h>
36
37 /* Default simulator parameters values */
38 #if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \
39 !defined(CONFIG_NANDSIM_SECOND_ID_BYTE) || \
40 !defined(CONFIG_NANDSIM_THIRD_ID_BYTE) || \
41 !defined(CONFIG_NANDSIM_FOURTH_ID_BYTE)
42 #define CONFIG_NANDSIM_FIRST_ID_BYTE 0x98
43 #define CONFIG_NANDSIM_SECOND_ID_BYTE 0x39
44 #define CONFIG_NANDSIM_THIRD_ID_BYTE 0xFF /* No byte */
45 #define CONFIG_NANDSIM_FOURTH_ID_BYTE 0xFF /* No byte */
46 #endif
47
48 #ifndef CONFIG_NANDSIM_ACCESS_DELAY
49 #define CONFIG_NANDSIM_ACCESS_DELAY 25
50 #endif
51 #ifndef CONFIG_NANDSIM_PROGRAMM_DELAY
52 #define CONFIG_NANDSIM_PROGRAMM_DELAY 200
53 #endif
54 #ifndef CONFIG_NANDSIM_ERASE_DELAY
55 #define CONFIG_NANDSIM_ERASE_DELAY 2
56 #endif
57 #ifndef CONFIG_NANDSIM_OUTPUT_CYCLE
58 #define CONFIG_NANDSIM_OUTPUT_CYCLE 40
59 #endif
60 #ifndef CONFIG_NANDSIM_INPUT_CYCLE
61 #define CONFIG_NANDSIM_INPUT_CYCLE 50
62 #endif
63 #ifndef CONFIG_NANDSIM_BUS_WIDTH
64 #define CONFIG_NANDSIM_BUS_WIDTH 8
65 #endif
66 #ifndef CONFIG_NANDSIM_DO_DELAYS
67 #define CONFIG_NANDSIM_DO_DELAYS 0
68 #endif
69 #ifndef CONFIG_NANDSIM_LOG
70 #define CONFIG_NANDSIM_LOG 0
71 #endif
72 #ifndef CONFIG_NANDSIM_DBG
73 #define CONFIG_NANDSIM_DBG 0
74 #endif
75 #ifndef CONFIG_NANDSIM_MAX_PARTS
76 #define CONFIG_NANDSIM_MAX_PARTS 32
77 #endif
78
79 static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY;
80 static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY;
81 static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY;
82 static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE;
83 static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE;
84 static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH;
85 static uint do_delays = CONFIG_NANDSIM_DO_DELAYS;
86 static uint log = CONFIG_NANDSIM_LOG;
87 static uint dbg = CONFIG_NANDSIM_DBG;
88 static unsigned long parts[CONFIG_NANDSIM_MAX_PARTS];
89 static unsigned int parts_num;
90 static char *badblocks = NULL;
91 static char *weakblocks = NULL;
92 static char *weakpages = NULL;
93 static unsigned int bitflips = 0;
94 static char *gravepages = NULL;
95 static unsigned int overridesize = 0;
96 static char *cache_file = NULL;
97 static unsigned int bbt;
98 static unsigned int bch;
99 static u_char id_bytes[8] = {
100 [0] = CONFIG_NANDSIM_FIRST_ID_BYTE,
101 [1] = CONFIG_NANDSIM_SECOND_ID_BYTE,
102 [2] = CONFIG_NANDSIM_THIRD_ID_BYTE,
103 [3] = CONFIG_NANDSIM_FOURTH_ID_BYTE,
104 [4 ... 7] = 0xFF,
105 };
106
107 module_param_array(id_bytes, byte, NULL, 0400);
108 module_param_named(first_id_byte, id_bytes[0], byte, 0400);
109 module_param_named(second_id_byte, id_bytes[1], byte, 0400);
110 module_param_named(third_id_byte, id_bytes[2], byte, 0400);
111 module_param_named(fourth_id_byte, id_bytes[3], byte, 0400);
112 module_param(access_delay, uint, 0400);
113 module_param(programm_delay, uint, 0400);
114 module_param(erase_delay, uint, 0400);
115 module_param(output_cycle, uint, 0400);
116 module_param(input_cycle, uint, 0400);
117 module_param(bus_width, uint, 0400);
118 module_param(do_delays, uint, 0400);
119 module_param(log, uint, 0400);
120 module_param(dbg, uint, 0400);
121 module_param_array(parts, ulong, &parts_num, 0400);
122 module_param(badblocks, charp, 0400);
123 module_param(weakblocks, charp, 0400);
124 module_param(weakpages, charp, 0400);
125 module_param(bitflips, uint, 0400);
126 module_param(gravepages, charp, 0400);
127 module_param(overridesize, uint, 0400);
128 module_param(cache_file, charp, 0400);
129 module_param(bbt, uint, 0400);
130 module_param(bch, uint, 0400);
131
132 MODULE_PARM_DESC(id_bytes, "The ID bytes returned by NAND Flash 'read ID' command");
133 MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufacturer ID) (obsolete)");
134 MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID) (obsolete)");
135 MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command (obsolete)");
136 MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command (obsolete)");
137 MODULE_PARM_DESC(access_delay, "Initial page access delay (microseconds)");
138 MODULE_PARM_DESC(programm_delay, "Page programm delay (microseconds");
139 MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)");
140 MODULE_PARM_DESC(output_cycle, "Word output (from flash) time (nanoseconds)");
141 MODULE_PARM_DESC(input_cycle, "Word input (to flash) time (nanoseconds)");
142 MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
143 MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero");
144 MODULE_PARM_DESC(log, "Perform logging if not zero");
145 MODULE_PARM_DESC(dbg, "Output debug information if not zero");
146 MODULE_PARM_DESC(parts, "Partition sizes (in erase blocks) separated by commas");
147 /* Page and erase block positions for the following parameters are independent of any partitions */
148 MODULE_PARM_DESC(badblocks, "Erase blocks that are initially marked bad, separated by commas");
149 MODULE_PARM_DESC(weakblocks, "Weak erase blocks [: remaining erase cycles (defaults to 3)]"
150 " separated by commas e.g. 113:2 means eb 113"
151 " can be erased only twice before failing");
152 MODULE_PARM_DESC(weakpages, "Weak pages [: maximum writes (defaults to 3)]"
153 " separated by commas e.g. 1401:2 means page 1401"
154 " can be written only twice before failing");
155 MODULE_PARM_DESC(bitflips, "Maximum number of random bit flips per page (zero by default)");
156 MODULE_PARM_DESC(gravepages, "Pages that lose data [: maximum reads (defaults to 3)]"
157 " separated by commas e.g. 1401:2 means page 1401"
158 " can be read only twice before failing");
159 MODULE_PARM_DESC(overridesize, "Specifies the NAND Flash size overriding the ID bytes. "
160 "The size is specified in erase blocks and as the exponent of a power of two"
161 " e.g. 5 means a size of 32 erase blocks");
162 MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory");
163 MODULE_PARM_DESC(bbt, "0 OOB, 1 BBT with marker in OOB, 2 BBT with marker in data area");
164 MODULE_PARM_DESC(bch, "Enable BCH ecc and set how many bits should "
165 "be correctable in 512-byte blocks");
166
167 /* The largest possible page size */
168 #define NS_LARGEST_PAGE_SIZE 4096
169
170 /* Simulator's output macros (logging, debugging, warning, error) */
171 #define NS_LOG(args...) \
172 do { if (log) pr_debug(" log: " args); } while(0)
173 #define NS_DBG(args...) \
174 do { if (dbg) pr_debug(" debug: " args); } while(0)
175 #define NS_WARN(args...) \
176 do { pr_warn(" warning: " args); } while(0)
177 #define NS_ERR(args...) \
178 do { pr_err(" error: " args); } while(0)
179 #define NS_INFO(args...) \
180 do { pr_info(" " args); } while(0)
181
182 /* Busy-wait delay macros (microseconds, milliseconds) */
183 #define NS_UDELAY(us) \
184 do { if (do_delays) udelay(us); } while(0)
185 #define NS_MDELAY(us) \
186 do { if (do_delays) mdelay(us); } while(0)
187
188 /* Is the nandsim structure initialized ? */
189 #define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0)
190
191 /* Good operation completion status */
192 #define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))
193
194 /* Operation failed completion status */
195 #define NS_STATUS_FAILED(ns) (NAND_STATUS_FAIL | NS_STATUS_OK(ns))
196
197 /* Calculate the page offset in flash RAM image by (row, column) address */
198 #define NS_RAW_OFFSET(ns) \
199 (((ns)->regs.row * (ns)->geom.pgszoob) + (ns)->regs.column)
200
201 /* Calculate the OOB offset in flash RAM image by (row, column) address */
202 #define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz)
203
204 /* After a command is input, the simulator goes to one of the following states */
205 #define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */
206 #define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */
207 #define STATE_CMD_READSTART 0x00000003 /* read data second command (large page devices) */
208 #define STATE_CMD_PAGEPROG 0x00000004 /* start page program */
209 #define STATE_CMD_READOOB 0x00000005 /* read OOB area */
210 #define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */
211 #define STATE_CMD_STATUS 0x00000007 /* read status */
212 #define STATE_CMD_SEQIN 0x00000009 /* sequential data input */
213 #define STATE_CMD_READID 0x0000000A /* read ID */
214 #define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */
215 #define STATE_CMD_RESET 0x0000000C /* reset */
216 #define STATE_CMD_RNDOUT 0x0000000D /* random output command */
217 #define STATE_CMD_RNDOUTSTART 0x0000000E /* random output start command */
218 #define STATE_CMD_MASK 0x0000000F /* command states mask */
219
220 /* After an address is input, the simulator goes to one of these states */
221 #define STATE_ADDR_PAGE 0x00000010 /* full (row, column) address is accepted */
222 #define STATE_ADDR_SEC 0x00000020 /* sector address was accepted */
223 #define STATE_ADDR_COLUMN 0x00000030 /* column address was accepted */
224 #define STATE_ADDR_ZERO 0x00000040 /* one byte zero address was accepted */
225 #define STATE_ADDR_MASK 0x00000070 /* address states mask */
226
227 /* During data input/output the simulator is in these states */
228 #define STATE_DATAIN 0x00000100 /* waiting for data input */
229 #define STATE_DATAIN_MASK 0x00000100 /* data input states mask */
230
231 #define STATE_DATAOUT 0x00001000 /* waiting for page data output */
232 #define STATE_DATAOUT_ID 0x00002000 /* waiting for ID bytes output */
233 #define STATE_DATAOUT_STATUS 0x00003000 /* waiting for status output */
234 #define STATE_DATAOUT_MASK 0x00007000 /* data output states mask */
235
236 /* Previous operation is done, ready to accept new requests */
237 #define STATE_READY 0x00000000
238
239 /* This state is used to mark that the next state isn't known yet */
240 #define STATE_UNKNOWN 0x10000000
241
242 /* Simulator's actions bit masks */
243 #define ACTION_CPY 0x00100000 /* copy page/OOB to the internal buffer */
244 #define ACTION_PRGPAGE 0x00200000 /* program the internal buffer to flash */
245 #define ACTION_SECERASE 0x00300000 /* erase sector */
246 #define ACTION_ZEROOFF 0x00400000 /* don't add any offset to address */
247 #define ACTION_HALFOFF 0x00500000 /* add to address half of page */
248 #define ACTION_OOBOFF 0x00600000 /* add to address OOB offset */
249 #define ACTION_MASK 0x00700000 /* action mask */
250
251 #define NS_OPER_NUM 13 /* Number of operations supported by the simulator */
252 #define NS_OPER_STATES 6 /* Maximum number of states in operation */
253
254 #define OPT_ANY 0xFFFFFFFF /* any chip supports this operation */
255 #define OPT_PAGE512 0x00000002 /* 512-byte page chips */
256 #define OPT_PAGE2048 0x00000008 /* 2048-byte page chips */
257 #define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */
258 #define OPT_PAGE4096 0x00000080 /* 4096-byte page chips */
259 #define OPT_LARGEPAGE (OPT_PAGE2048 | OPT_PAGE4096) /* 2048 & 4096-byte page chips */
260 #define OPT_SMALLPAGE (OPT_PAGE512) /* 512-byte page chips */
261
262 /* Remove action bits from state */
263 #define NS_STATE(x) ((x) & ~ACTION_MASK)
264
265 /*
266 * Maximum previous states which need to be saved. Currently saving is
267 * only needed for page program operation with preceded read command
268 * (which is only valid for 512-byte pages).
269 */
270 #define NS_MAX_PREVSTATES 1
271
272 /* Maximum page cache pages needed to read or write a NAND page to the cache_file */
273 #define NS_MAX_HELD_PAGES 16
274
275 /*
276 * A union to represent flash memory contents and flash buffer.
277 */
278 union ns_mem {
279 u_char *byte; /* for byte access */
280 uint16_t *word; /* for 16-bit word access */
281 };
282
283 /*
284 * The structure which describes all the internal simulator data.
285 */
286 struct nandsim {
287 struct nand_chip chip;
288 struct nand_controller base;
289 struct mtd_partition partitions[CONFIG_NANDSIM_MAX_PARTS];
290 unsigned int nbparts;
291
292 uint busw; /* flash chip bus width (8 or 16) */
293 u_char ids[8]; /* chip's ID bytes */
294 uint32_t options; /* chip's characteristic bits */
295 uint32_t state; /* current chip state */
296 uint32_t nxstate; /* next expected state */
297
298 uint32_t *op; /* current operation, NULL operations isn't known yet */
299 uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */
300 uint16_t npstates; /* number of previous states saved */
301 uint16_t stateidx; /* current state index */
302
303 /* The simulated NAND flash pages array */
304 union ns_mem *pages;
305
306 /* Slab allocator for nand pages */
307 struct kmem_cache *nand_pages_slab;
308
309 /* Internal buffer of page + OOB size bytes */
310 union ns_mem buf;
311
312 /* NAND flash "geometry" */
313 struct {
314 uint64_t totsz; /* total flash size, bytes */
315 uint32_t secsz; /* flash sector (erase block) size, bytes */
316 uint pgsz; /* NAND flash page size, bytes */
317 uint oobsz; /* page OOB area size, bytes */
318 uint64_t totszoob; /* total flash size including OOB, bytes */
319 uint pgszoob; /* page size including OOB , bytes*/
320 uint secszoob; /* sector size including OOB, bytes */
321 uint pgnum; /* total number of pages */
322 uint pgsec; /* number of pages per sector */
323 uint secshift; /* bits number in sector size */
324 uint pgshift; /* bits number in page size */
325 uint pgaddrbytes; /* bytes per page address */
326 uint secaddrbytes; /* bytes per sector address */
327 uint idbytes; /* the number ID bytes that this chip outputs */
328 } geom;
329
330 /* NAND flash internal registers */
331 struct {
332 unsigned command; /* the command register */
333 u_char status; /* the status register */
334 uint row; /* the page number */
335 uint column; /* the offset within page */
336 uint count; /* internal counter */
337 uint num; /* number of bytes which must be processed */
338 uint off; /* fixed page offset */
339 } regs;
340
341 /* NAND flash lines state */
342 struct {
343 int ce; /* chip Enable */
344 int cle; /* command Latch Enable */
345 int ale; /* address Latch Enable */
346 int wp; /* write Protect */
347 } lines;
348
349 /* Fields needed when using a cache file */
350 struct file *cfile; /* Open file */
351 unsigned long *pages_written; /* Which pages have been written */
352 void *file_buf;
353 struct page *held_pages[NS_MAX_HELD_PAGES];
354 int held_cnt;
355
356 /* debugfs entry */
357 struct dentry *dent;
358 };
359
360 /*
361 * Operations array. To perform any operation the simulator must pass
362 * through the correspondent states chain.
363 */
364 static struct nandsim_operations {
365 uint32_t reqopts; /* options which are required to perform the operation */
366 uint32_t states[NS_OPER_STATES]; /* operation's states */
367 } ops[NS_OPER_NUM] = {
368 /* Read page + OOB from the beginning */
369 {OPT_SMALLPAGE, {STATE_CMD_READ0 | ACTION_ZEROOFF, STATE_ADDR_PAGE | ACTION_CPY,
370 STATE_DATAOUT, STATE_READY}},
371 /* Read page + OOB from the second half */
372 {OPT_PAGE512_8BIT, {STATE_CMD_READ1 | ACTION_HALFOFF, STATE_ADDR_PAGE | ACTION_CPY,
373 STATE_DATAOUT, STATE_READY}},
374 /* Read OOB */
375 {OPT_SMALLPAGE, {STATE_CMD_READOOB | ACTION_OOBOFF, STATE_ADDR_PAGE | ACTION_CPY,
376 STATE_DATAOUT, STATE_READY}},
377 /* Program page starting from the beginning */
378 {OPT_ANY, {STATE_CMD_SEQIN, STATE_ADDR_PAGE, STATE_DATAIN,
379 STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
380 /* Program page starting from the beginning */
381 {OPT_SMALLPAGE, {STATE_CMD_READ0, STATE_CMD_SEQIN | ACTION_ZEROOFF, STATE_ADDR_PAGE,
382 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
383 /* Program page starting from the second half */
384 {OPT_PAGE512, {STATE_CMD_READ1, STATE_CMD_SEQIN | ACTION_HALFOFF, STATE_ADDR_PAGE,
385 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
386 /* Program OOB */
387 {OPT_SMALLPAGE, {STATE_CMD_READOOB, STATE_CMD_SEQIN | ACTION_OOBOFF, STATE_ADDR_PAGE,
388 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
389 /* Erase sector */
390 {OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}},
391 /* Read status */
392 {OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}},
393 /* Read ID */
394 {OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}},
395 /* Large page devices read page */
396 {OPT_LARGEPAGE, {STATE_CMD_READ0, STATE_ADDR_PAGE, STATE_CMD_READSTART | ACTION_CPY,
397 STATE_DATAOUT, STATE_READY}},
398 /* Large page devices random page read */
399 {OPT_LARGEPAGE, {STATE_CMD_RNDOUT, STATE_ADDR_COLUMN, STATE_CMD_RNDOUTSTART | ACTION_CPY,
400 STATE_DATAOUT, STATE_READY}},
401 };
402
403 struct weak_block {
404 struct list_head list;
405 unsigned int erase_block_no;
406 unsigned int max_erases;
407 unsigned int erases_done;
408 };
409
410 static LIST_HEAD(weak_blocks);
411
412 struct weak_page {
413 struct list_head list;
414 unsigned int page_no;
415 unsigned int max_writes;
416 unsigned int writes_done;
417 };
418
419 static LIST_HEAD(weak_pages);
420
421 struct grave_page {
422 struct list_head list;
423 unsigned int page_no;
424 unsigned int max_reads;
425 unsigned int reads_done;
426 };
427
428 static LIST_HEAD(grave_pages);
429
430 static unsigned long *erase_block_wear = NULL;
431 static unsigned int wear_eb_count = 0;
432 static unsigned long total_wear = 0;
433
434 /* MTD structure for NAND controller */
435 static struct mtd_info *nsmtd;
436
437 static int ns_show(struct seq_file *m, void *private)
438 {
439 unsigned long wmin = -1, wmax = 0, avg;
440 unsigned long deciles[10], decile_max[10], tot = 0;
441 unsigned int i;
442
443 /* Calc wear stats */
444 for (i = 0; i < wear_eb_count; ++i) {
445 unsigned long wear = erase_block_wear[i];
446 if (wear < wmin)
447 wmin = wear;
448 if (wear > wmax)
449 wmax = wear;
450 tot += wear;
451 }
452
453 for (i = 0; i < 9; ++i) {
454 deciles[i] = 0;
455 decile_max[i] = (wmax * (i + 1) + 5) / 10;
456 }
457 deciles[9] = 0;
458 decile_max[9] = wmax;
459 for (i = 0; i < wear_eb_count; ++i) {
460 int d;
461 unsigned long wear = erase_block_wear[i];
462 for (d = 0; d < 10; ++d)
463 if (wear <= decile_max[d]) {
464 deciles[d] += 1;
465 break;
466 }
467 }
468 avg = tot / wear_eb_count;
469
470 /* Output wear report */
471 seq_printf(m, "Total numbers of erases: %lu\n", tot);
472 seq_printf(m, "Number of erase blocks: %u\n", wear_eb_count);
473 seq_printf(m, "Average number of erases: %lu\n", avg);
474 seq_printf(m, "Maximum number of erases: %lu\n", wmax);
475 seq_printf(m, "Minimum number of erases: %lu\n", wmin);
476 for (i = 0; i < 10; ++i) {
477 unsigned long from = (i ? decile_max[i - 1] + 1 : 0);
478 if (from > decile_max[i])
479 continue;
480 seq_printf(m, "Number of ebs with erase counts from %lu to %lu : %lu\n",
481 from,
482 decile_max[i],
483 deciles[i]);
484 }
485
486 return 0;
487 }
488 DEFINE_SHOW_ATTRIBUTE(ns);
489
490 /**
491 * ns_debugfs_create - initialize debugfs
492 * @ns: nandsim device description object
493 *
494 * This function creates all debugfs files for UBI device @ubi. Returns zero in
495 * case of success and a negative error code in case of failure.
496 */
497 static int ns_debugfs_create(struct nandsim *ns)
498 {
499 struct dentry *root = nsmtd->dbg.dfs_dir;
500
501 /*
502 * Just skip debugfs initialization when the debugfs directory is
503 * missing.
504 */
505 if (IS_ERR_OR_NULL(root)) {
506 if (IS_ENABLED(CONFIG_DEBUG_FS) &&
507 !IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER))
508 NS_WARN("CONFIG_MTD_PARTITIONED_MASTER must be enabled to expose debugfs stuff\n");
509 return 0;
510 }
511
512 ns->dent = debugfs_create_file("nandsim_wear_report", 0400, root, ns,
513 &ns_fops);
514 if (IS_ERR_OR_NULL(ns->dent)) {
515 NS_ERR("cannot create \"nandsim_wear_report\" debugfs entry\n");
516 return -1;
517 }
518
519 return 0;
520 }
521
522 static void ns_debugfs_remove(struct nandsim *ns)
523 {
524 debugfs_remove_recursive(ns->dent);
525 }
526
527 /*
528 * Allocate array of page pointers, create slab allocation for an array
529 * and initialize the array by NULL pointers.
530 *
531 * RETURNS: 0 if success, -ENOMEM if memory alloc fails.
532 */
533 static int __init ns_alloc_device(struct nandsim *ns)
534 {
535 struct file *cfile;
536 int i, err;
537
538 if (cache_file) {
539 cfile = filp_open(cache_file, O_CREAT | O_RDWR | O_LARGEFILE, 0600);
540 if (IS_ERR(cfile))
541 return PTR_ERR(cfile);
542 if (!(cfile->f_mode & FMODE_CAN_READ)) {
543 NS_ERR("alloc_device: cache file not readable\n");
544 err = -EINVAL;
545 goto err_close_filp;
546 }
547 if (!(cfile->f_mode & FMODE_CAN_WRITE)) {
548 NS_ERR("alloc_device: cache file not writeable\n");
549 err = -EINVAL;
550 goto err_close_filp;
551 }
552 ns->pages_written =
553 vzalloc(array_size(sizeof(unsigned long),
554 BITS_TO_LONGS(ns->geom.pgnum)));
555 if (!ns->pages_written) {
556 NS_ERR("alloc_device: unable to allocate pages written array\n");
557 err = -ENOMEM;
558 goto err_close_filp;
559 }
560 ns->file_buf = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
561 if (!ns->file_buf) {
562 NS_ERR("alloc_device: unable to allocate file buf\n");
563 err = -ENOMEM;
564 goto err_free_pw;
565 }
566 ns->cfile = cfile;
567
568 return 0;
569
570 err_free_pw:
571 vfree(ns->pages_written);
572 err_close_filp:
573 filp_close(cfile, NULL);
574
575 return err;
576 }
577
578 ns->pages = vmalloc(array_size(sizeof(union ns_mem), ns->geom.pgnum));
579 if (!ns->pages) {
580 NS_ERR("alloc_device: unable to allocate page array\n");
581 return -ENOMEM;
582 }
583 for (i = 0; i < ns->geom.pgnum; i++) {
584 ns->pages[i].byte = NULL;
585 }
586 ns->nand_pages_slab = kmem_cache_create("nandsim",
587 ns->geom.pgszoob, 0, 0, NULL);
588 if (!ns->nand_pages_slab) {
589 NS_ERR("cache_create: unable to create kmem_cache\n");
590 err = -ENOMEM;
591 goto err_free_pg;
592 }
593
594 return 0;
595
596 err_free_pg:
597 vfree(ns->pages);
598
599 return err;
600 }
601
602 /*
603 * Free any allocated pages, and free the array of page pointers.
604 */
605 static void ns_free_device(struct nandsim *ns)
606 {
607 int i;
608
609 if (ns->cfile) {
610 kfree(ns->file_buf);
611 vfree(ns->pages_written);
612 filp_close(ns->cfile, NULL);
613 return;
614 }
615
616 if (ns->pages) {
617 for (i = 0; i < ns->geom.pgnum; i++) {
618 if (ns->pages[i].byte)
619 kmem_cache_free(ns->nand_pages_slab,
620 ns->pages[i].byte);
621 }
622 kmem_cache_destroy(ns->nand_pages_slab);
623 vfree(ns->pages);
624 }
625 }
626
627 static char __init *ns_get_partition_name(int i)
628 {
629 return kasprintf(GFP_KERNEL, "NAND simulator partition %d", i);
630 }
631
632 /*
633 * Initialize the nandsim structure.
634 *
635 * RETURNS: 0 if success, -ERRNO if failure.
636 */
637 static int __init ns_init(struct mtd_info *mtd)
638 {
639 struct nand_chip *chip = mtd_to_nand(mtd);
640 struct nandsim *ns = nand_get_controller_data(chip);
641 int i, ret = 0;
642 uint64_t remains;
643 uint64_t next_offset;
644
645 if (NS_IS_INITIALIZED(ns)) {
646 NS_ERR("init_nandsim: nandsim is already initialized\n");
647 return -EIO;
648 }
649
650 /* Initialize the NAND flash parameters */
651 ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8;
652 ns->geom.totsz = mtd->size;
653 ns->geom.pgsz = mtd->writesize;
654 ns->geom.oobsz = mtd->oobsize;
655 ns->geom.secsz = mtd->erasesize;
656 ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz;
657 ns->geom.pgnum = div_u64(ns->geom.totsz, ns->geom.pgsz);
658 ns->geom.totszoob = ns->geom.totsz + (uint64_t)ns->geom.pgnum * ns->geom.oobsz;
659 ns->geom.secshift = ffs(ns->geom.secsz) - 1;
660 ns->geom.pgshift = chip->page_shift;
661 ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz;
662 ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec;
663 ns->options = 0;
664
665 if (ns->geom.pgsz == 512) {
666 ns->options |= OPT_PAGE512;
667 if (ns->busw == 8)
668 ns->options |= OPT_PAGE512_8BIT;
669 } else if (ns->geom.pgsz == 2048) {
670 ns->options |= OPT_PAGE2048;
671 } else if (ns->geom.pgsz == 4096) {
672 ns->options |= OPT_PAGE4096;
673 } else {
674 NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz);
675 return -EIO;
676 }
677
678 if (ns->options & OPT_SMALLPAGE) {
679 if (ns->geom.totsz <= (32 << 20)) {
680 ns->geom.pgaddrbytes = 3;
681 ns->geom.secaddrbytes = 2;
682 } else {
683 ns->geom.pgaddrbytes = 4;
684 ns->geom.secaddrbytes = 3;
685 }
686 } else {
687 if (ns->geom.totsz <= (128 << 20)) {
688 ns->geom.pgaddrbytes = 4;
689 ns->geom.secaddrbytes = 2;
690 } else {
691 ns->geom.pgaddrbytes = 5;
692 ns->geom.secaddrbytes = 3;
693 }
694 }
695
696 /* Fill the partition_info structure */
697 if (parts_num > ARRAY_SIZE(ns->partitions)) {
698 NS_ERR("too many partitions.\n");
699 return -EINVAL;
700 }
701 remains = ns->geom.totsz;
702 next_offset = 0;
703 for (i = 0; i < parts_num; ++i) {
704 uint64_t part_sz = (uint64_t)parts[i] * ns->geom.secsz;
705
706 if (!part_sz || part_sz > remains) {
707 NS_ERR("bad partition size.\n");
708 return -EINVAL;
709 }
710 ns->partitions[i].name = ns_get_partition_name(i);
711 if (!ns->partitions[i].name) {
712 NS_ERR("unable to allocate memory.\n");
713 return -ENOMEM;
714 }
715 ns->partitions[i].offset = next_offset;
716 ns->partitions[i].size = part_sz;
717 next_offset += ns->partitions[i].size;
718 remains -= ns->partitions[i].size;
719 }
720 ns->nbparts = parts_num;
721 if (remains) {
722 if (parts_num + 1 > ARRAY_SIZE(ns->partitions)) {
723 NS_ERR("too many partitions.\n");
724 ret = -EINVAL;
725 goto free_partition_names;
726 }
727 ns->partitions[i].name = ns_get_partition_name(i);
728 if (!ns->partitions[i].name) {
729 NS_ERR("unable to allocate memory.\n");
730 ret = -ENOMEM;
731 goto free_partition_names;
732 }
733 ns->partitions[i].offset = next_offset;
734 ns->partitions[i].size = remains;
735 ns->nbparts += 1;
736 }
737
738 if (ns->busw == 16)
739 NS_WARN("16-bit flashes support wasn't tested\n");
740
741 printk("flash size: %llu MiB\n",
742 (unsigned long long)ns->geom.totsz >> 20);
743 printk("page size: %u bytes\n", ns->geom.pgsz);
744 printk("OOB area size: %u bytes\n", ns->geom.oobsz);
745 printk("sector size: %u KiB\n", ns->geom.secsz >> 10);
746 printk("pages number: %u\n", ns->geom.pgnum);
747 printk("pages per sector: %u\n", ns->geom.pgsec);
748 printk("bus width: %u\n", ns->busw);
749 printk("bits in sector size: %u\n", ns->geom.secshift);
750 printk("bits in page size: %u\n", ns->geom.pgshift);
751 printk("bits in OOB size: %u\n", ffs(ns->geom.oobsz) - 1);
752 printk("flash size with OOB: %llu KiB\n",
753 (unsigned long long)ns->geom.totszoob >> 10);
754 printk("page address bytes: %u\n", ns->geom.pgaddrbytes);
755 printk("sector address bytes: %u\n", ns->geom.secaddrbytes);
756 printk("options: %#x\n", ns->options);
757
758 ret = ns_alloc_device(ns);
759 if (ret)
760 goto free_partition_names;
761
762 /* Allocate / initialize the internal buffer */
763 ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
764 if (!ns->buf.byte) {
765 NS_ERR("init_nandsim: unable to allocate %u bytes for the internal buffer\n",
766 ns->geom.pgszoob);
767 ret = -ENOMEM;
768 goto free_device;
769 }
770 memset(ns->buf.byte, 0xFF, ns->geom.pgszoob);
771
772 return 0;
773
774 free_device:
775 ns_free_device(ns);
776 free_partition_names:
777 for (i = 0; i < ARRAY_SIZE(ns->partitions); ++i)
778 kfree(ns->partitions[i].name);
779
780 return ret;
781 }
782
783 /*
784 * Free the nandsim structure.
785 */
786 static void ns_free(struct nandsim *ns)
787 {
788 int i;
789
790 for (i = 0; i < ARRAY_SIZE(ns->partitions); ++i)
791 kfree(ns->partitions[i].name);
792
793 kfree(ns->buf.byte);
794 ns_free_device(ns);
795
796 return;
797 }
798
799 static int ns_parse_badblocks(struct nandsim *ns, struct mtd_info *mtd)
800 {
801 char *w;
802 int zero_ok;
803 unsigned int erase_block_no;
804 loff_t offset;
805
806 if (!badblocks)
807 return 0;
808 w = badblocks;
809 do {
810 zero_ok = (*w == '0' ? 1 : 0);
811 erase_block_no = simple_strtoul(w, &w, 0);
812 if (!zero_ok && !erase_block_no) {
813 NS_ERR("invalid badblocks.\n");
814 return -EINVAL;
815 }
816 offset = (loff_t)erase_block_no * ns->geom.secsz;
817 if (mtd_block_markbad(mtd, offset)) {
818 NS_ERR("invalid badblocks.\n");
819 return -EINVAL;
820 }
821 if (*w == ',')
822 w += 1;
823 } while (*w);
824 return 0;
825 }
826
827 static int ns_parse_weakblocks(void)
828 {
829 char *w;
830 int zero_ok;
831 unsigned int erase_block_no;
832 unsigned int max_erases;
833 struct weak_block *wb;
834
835 if (!weakblocks)
836 return 0;
837 w = weakblocks;
838 do {
839 zero_ok = (*w == '0' ? 1 : 0);
840 erase_block_no = simple_strtoul(w, &w, 0);
841 if (!zero_ok && !erase_block_no) {
842 NS_ERR("invalid weakblocks.\n");
843 return -EINVAL;
844 }
845 max_erases = 3;
846 if (*w == ':') {
847 w += 1;
848 max_erases = simple_strtoul(w, &w, 0);
849 }
850 if (*w == ',')
851 w += 1;
852 wb = kzalloc(sizeof(*wb), GFP_KERNEL);
853 if (!wb) {
854 NS_ERR("unable to allocate memory.\n");
855 return -ENOMEM;
856 }
857 wb->erase_block_no = erase_block_no;
858 wb->max_erases = max_erases;
859 list_add(&wb->list, &weak_blocks);
860 } while (*w);
861 return 0;
862 }
863
864 static int ns_erase_error(unsigned int erase_block_no)
865 {
866 struct weak_block *wb;
867
868 list_for_each_entry(wb, &weak_blocks, list)
869 if (wb->erase_block_no == erase_block_no) {
870 if (wb->erases_done >= wb->max_erases)
871 return 1;
872 wb->erases_done += 1;
873 return 0;
874 }
875 return 0;
876 }
877
878 static int ns_parse_weakpages(void)
879 {
880 char *w;
881 int zero_ok;
882 unsigned int page_no;
883 unsigned int max_writes;
884 struct weak_page *wp;
885
886 if (!weakpages)
887 return 0;
888 w = weakpages;
889 do {
890 zero_ok = (*w == '0' ? 1 : 0);
891 page_no = simple_strtoul(w, &w, 0);
892 if (!zero_ok && !page_no) {
893 NS_ERR("invalid weakpages.\n");
894 return -EINVAL;
895 }
896 max_writes = 3;
897 if (*w == ':') {
898 w += 1;
899 max_writes = simple_strtoul(w, &w, 0);
900 }
901 if (*w == ',')
902 w += 1;
903 wp = kzalloc(sizeof(*wp), GFP_KERNEL);
904 if (!wp) {
905 NS_ERR("unable to allocate memory.\n");
906 return -ENOMEM;
907 }
908 wp->page_no = page_no;
909 wp->max_writes = max_writes;
910 list_add(&wp->list, &weak_pages);
911 } while (*w);
912 return 0;
913 }
914
915 static int ns_write_error(unsigned int page_no)
916 {
917 struct weak_page *wp;
918
919 list_for_each_entry(wp, &weak_pages, list)
920 if (wp->page_no == page_no) {
921 if (wp->writes_done >= wp->max_writes)
922 return 1;
923 wp->writes_done += 1;
924 return 0;
925 }
926 return 0;
927 }
928
929 static int ns_parse_gravepages(void)
930 {
931 char *g;
932 int zero_ok;
933 unsigned int page_no;
934 unsigned int max_reads;
935 struct grave_page *gp;
936
937 if (!gravepages)
938 return 0;
939 g = gravepages;
940 do {
941 zero_ok = (*g == '0' ? 1 : 0);
942 page_no = simple_strtoul(g, &g, 0);
943 if (!zero_ok && !page_no) {
944 NS_ERR("invalid gravepagess.\n");
945 return -EINVAL;
946 }
947 max_reads = 3;
948 if (*g == ':') {
949 g += 1;
950 max_reads = simple_strtoul(g, &g, 0);
951 }
952 if (*g == ',')
953 g += 1;
954 gp = kzalloc(sizeof(*gp), GFP_KERNEL);
955 if (!gp) {
956 NS_ERR("unable to allocate memory.\n");
957 return -ENOMEM;
958 }
959 gp->page_no = page_no;
960 gp->max_reads = max_reads;
961 list_add(&gp->list, &grave_pages);
962 } while (*g);
963 return 0;
964 }
965
966 static int ns_read_error(unsigned int page_no)
967 {
968 struct grave_page *gp;
969
970 list_for_each_entry(gp, &grave_pages, list)
971 if (gp->page_no == page_no) {
972 if (gp->reads_done >= gp->max_reads)
973 return 1;
974 gp->reads_done += 1;
975 return 0;
976 }
977 return 0;
978 }
979
980 static int ns_setup_wear_reporting(struct mtd_info *mtd)
981 {
982 size_t mem;
983
984 wear_eb_count = div_u64(mtd->size, mtd->erasesize);
985 mem = wear_eb_count * sizeof(unsigned long);
986 if (mem / sizeof(unsigned long) != wear_eb_count) {
987 NS_ERR("Too many erase blocks for wear reporting\n");
988 return -ENOMEM;
989 }
990 erase_block_wear = kzalloc(mem, GFP_KERNEL);
991 if (!erase_block_wear) {
992 NS_ERR("Too many erase blocks for wear reporting\n");
993 return -ENOMEM;
994 }
995 return 0;
996 }
997
998 static void ns_update_wear(unsigned int erase_block_no)
999 {
1000 if (!erase_block_wear)
1001 return;
1002 total_wear += 1;
1003 /*
1004 * TODO: Notify this through a debugfs entry,
1005 * instead of showing an error message.
1006 */
1007 if (total_wear == 0)
1008 NS_ERR("Erase counter total overflow\n");
1009 erase_block_wear[erase_block_no] += 1;
1010 if (erase_block_wear[erase_block_no] == 0)
1011 NS_ERR("Erase counter overflow for erase block %u\n", erase_block_no);
1012 }
1013
1014 /*
1015 * Returns the string representation of 'state' state.
1016 */
1017 static char *ns_get_state_name(uint32_t state)
1018 {
1019 switch (NS_STATE(state)) {
1020 case STATE_CMD_READ0:
1021 return "STATE_CMD_READ0";
1022 case STATE_CMD_READ1:
1023 return "STATE_CMD_READ1";
1024 case STATE_CMD_PAGEPROG:
1025 return "STATE_CMD_PAGEPROG";
1026 case STATE_CMD_READOOB:
1027 return "STATE_CMD_READOOB";
1028 case STATE_CMD_READSTART:
1029 return "STATE_CMD_READSTART";
1030 case STATE_CMD_ERASE1:
1031 return "STATE_CMD_ERASE1";
1032 case STATE_CMD_STATUS:
1033 return "STATE_CMD_STATUS";
1034 case STATE_CMD_SEQIN:
1035 return "STATE_CMD_SEQIN";
1036 case STATE_CMD_READID:
1037 return "STATE_CMD_READID";
1038 case STATE_CMD_ERASE2:
1039 return "STATE_CMD_ERASE2";
1040 case STATE_CMD_RESET:
1041 return "STATE_CMD_RESET";
1042 case STATE_CMD_RNDOUT:
1043 return "STATE_CMD_RNDOUT";
1044 case STATE_CMD_RNDOUTSTART:
1045 return "STATE_CMD_RNDOUTSTART";
1046 case STATE_ADDR_PAGE:
1047 return "STATE_ADDR_PAGE";
1048 case STATE_ADDR_SEC:
1049 return "STATE_ADDR_SEC";
1050 case STATE_ADDR_ZERO:
1051 return "STATE_ADDR_ZERO";
1052 case STATE_ADDR_COLUMN:
1053 return "STATE_ADDR_COLUMN";
1054 case STATE_DATAIN:
1055 return "STATE_DATAIN";
1056 case STATE_DATAOUT:
1057 return "STATE_DATAOUT";
1058 case STATE_DATAOUT_ID:
1059 return "STATE_DATAOUT_ID";
1060 case STATE_DATAOUT_STATUS:
1061 return "STATE_DATAOUT_STATUS";
1062 case STATE_READY:
1063 return "STATE_READY";
1064 case STATE_UNKNOWN:
1065 return "STATE_UNKNOWN";
1066 }
1067
1068 NS_ERR("get_state_name: unknown state, BUG\n");
1069 return NULL;
1070 }
1071
1072 /*
1073 * Check if command is valid.
1074 *
1075 * RETURNS: 1 if wrong command, 0 if right.
1076 */
1077 static int ns_check_command(int cmd)
1078 {
1079 switch (cmd) {
1080
1081 case NAND_CMD_READ0:
1082 case NAND_CMD_READ1:
1083 case NAND_CMD_READSTART:
1084 case NAND_CMD_PAGEPROG:
1085 case NAND_CMD_READOOB:
1086 case NAND_CMD_ERASE1:
1087 case NAND_CMD_STATUS:
1088 case NAND_CMD_SEQIN:
1089 case NAND_CMD_READID:
1090 case NAND_CMD_ERASE2:
1091 case NAND_CMD_RESET:
1092 case NAND_CMD_RNDOUT:
1093 case NAND_CMD_RNDOUTSTART:
1094 return 0;
1095
1096 default:
1097 return 1;
1098 }
1099 }
1100
1101 /*
1102 * Returns state after command is accepted by command number.
1103 */
1104 static uint32_t ns_get_state_by_command(unsigned command)
1105 {
1106 switch (command) {
1107 case NAND_CMD_READ0:
1108 return STATE_CMD_READ0;
1109 case NAND_CMD_READ1:
1110 return STATE_CMD_READ1;
1111 case NAND_CMD_PAGEPROG:
1112 return STATE_CMD_PAGEPROG;
1113 case NAND_CMD_READSTART:
1114 return STATE_CMD_READSTART;
1115 case NAND_CMD_READOOB:
1116 return STATE_CMD_READOOB;
1117 case NAND_CMD_ERASE1:
1118 return STATE_CMD_ERASE1;
1119 case NAND_CMD_STATUS:
1120 return STATE_CMD_STATUS;
1121 case NAND_CMD_SEQIN:
1122 return STATE_CMD_SEQIN;
1123 case NAND_CMD_READID:
1124 return STATE_CMD_READID;
1125 case NAND_CMD_ERASE2:
1126 return STATE_CMD_ERASE2;
1127 case NAND_CMD_RESET:
1128 return STATE_CMD_RESET;
1129 case NAND_CMD_RNDOUT:
1130 return STATE_CMD_RNDOUT;
1131 case NAND_CMD_RNDOUTSTART:
1132 return STATE_CMD_RNDOUTSTART;
1133 }
1134
1135 NS_ERR("get_state_by_command: unknown command, BUG\n");
1136 return 0;
1137 }
1138
1139 /*
1140 * Move an address byte to the correspondent internal register.
1141 */
1142 static inline void ns_accept_addr_byte(struct nandsim *ns, u_char bt)
1143 {
1144 uint byte = (uint)bt;
1145
1146 if (ns->regs.count < (ns->geom.pgaddrbytes - ns->geom.secaddrbytes))
1147 ns->regs.column |= (byte << 8 * ns->regs.count);
1148 else {
1149 ns->regs.row |= (byte << 8 * (ns->regs.count -
1150 ns->geom.pgaddrbytes +
1151 ns->geom.secaddrbytes));
1152 }
1153
1154 return;
1155 }
1156
1157 /*
1158 * Switch to STATE_READY state.
1159 */
1160 static inline void ns_switch_to_ready_state(struct nandsim *ns, u_char status)
1161 {
1162 NS_DBG("switch_to_ready_state: switch to %s state\n",
1163 ns_get_state_name(STATE_READY));
1164
1165 ns->state = STATE_READY;
1166 ns->nxstate = STATE_UNKNOWN;
1167 ns->op = NULL;
1168 ns->npstates = 0;
1169 ns->stateidx = 0;
1170 ns->regs.num = 0;
1171 ns->regs.count = 0;
1172 ns->regs.off = 0;
1173 ns->regs.row = 0;
1174 ns->regs.column = 0;
1175 ns->regs.status = status;
1176 }
1177
1178 /*
1179 * If the operation isn't known yet, try to find it in the global array
1180 * of supported operations.
1181 *
1182 * Operation can be unknown because of the following.
1183 * 1. New command was accepted and this is the first call to find the
1184 * correspondent states chain. In this case ns->npstates = 0;
1185 * 2. There are several operations which begin with the same command(s)
1186 * (for example program from the second half and read from the
1187 * second half operations both begin with the READ1 command). In this
1188 * case the ns->pstates[] array contains previous states.
1189 *
1190 * Thus, the function tries to find operation containing the following
1191 * states (if the 'flag' parameter is 0):
1192 * ns->pstates[0], ... ns->pstates[ns->npstates], ns->state
1193 *
1194 * If (one and only one) matching operation is found, it is accepted (
1195 * ns->ops, ns->state, ns->nxstate are initialized, ns->npstate is
1196 * zeroed).
1197 *
1198 * If there are several matches, the current state is pushed to the
1199 * ns->pstates.
1200 *
1201 * The operation can be unknown only while commands are input to the chip.
1202 * As soon as address command is accepted, the operation must be known.
1203 * In such situation the function is called with 'flag' != 0, and the
1204 * operation is searched using the following pattern:
1205 * ns->pstates[0], ... ns->pstates[ns->npstates], <address input>
1206 *
1207 * It is supposed that this pattern must either match one operation or
1208 * none. There can't be ambiguity in that case.
1209 *
1210 * If no matches found, the function does the following:
1211 * 1. if there are saved states present, try to ignore them and search
1212 * again only using the last command. If nothing was found, switch
1213 * to the STATE_READY state.
1214 * 2. if there are no saved states, switch to the STATE_READY state.
1215 *
1216 * RETURNS: -2 - no matched operations found.
1217 * -1 - several matches.
1218 * 0 - operation is found.
1219 */
1220 static int ns_find_operation(struct nandsim *ns, uint32_t flag)
1221 {
1222 int opsfound = 0;
1223 int i, j, idx = 0;
1224
1225 for (i = 0; i < NS_OPER_NUM; i++) {
1226
1227 int found = 1;
1228
1229 if (!(ns->options & ops[i].reqopts))
1230 /* Ignore operations we can't perform */
1231 continue;
1232
1233 if (flag) {
1234 if (!(ops[i].states[ns->npstates] & STATE_ADDR_MASK))
1235 continue;
1236 } else {
1237 if (NS_STATE(ns->state) != NS_STATE(ops[i].states[ns->npstates]))
1238 continue;
1239 }
1240
1241 for (j = 0; j < ns->npstates; j++)
1242 if (NS_STATE(ops[i].states[j]) != NS_STATE(ns->pstates[j])
1243 && (ns->options & ops[idx].reqopts)) {
1244 found = 0;
1245 break;
1246 }
1247
1248 if (found) {
1249 idx = i;
1250 opsfound += 1;
1251 }
1252 }
1253
1254 if (opsfound == 1) {
1255 /* Exact match */
1256 ns->op = &ops[idx].states[0];
1257 if (flag) {
1258 /*
1259 * In this case the find_operation function was
1260 * called when address has just began input. But it isn't
1261 * yet fully input and the current state must
1262 * not be one of STATE_ADDR_*, but the STATE_ADDR_*
1263 * state must be the next state (ns->nxstate).
1264 */
1265 ns->stateidx = ns->npstates - 1;
1266 } else {
1267 ns->stateidx = ns->npstates;
1268 }
1269 ns->npstates = 0;
1270 ns->state = ns->op[ns->stateidx];
1271 ns->nxstate = ns->op[ns->stateidx + 1];
1272 NS_DBG("find_operation: operation found, index: %d, state: %s, nxstate %s\n",
1273 idx, ns_get_state_name(ns->state),
1274 ns_get_state_name(ns->nxstate));
1275 return 0;
1276 }
1277
1278 if (opsfound == 0) {
1279 /* Nothing was found. Try to ignore previous commands (if any) and search again */
1280 if (ns->npstates != 0) {
1281 NS_DBG("find_operation: no operation found, try again with state %s\n",
1282 ns_get_state_name(ns->state));
1283 ns->npstates = 0;
1284 return ns_find_operation(ns, 0);
1285
1286 }
1287 NS_DBG("find_operation: no operations found\n");
1288 ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1289 return -2;
1290 }
1291
1292 if (flag) {
1293 /* This shouldn't happen */
1294 NS_DBG("find_operation: BUG, operation must be known if address is input\n");
1295 return -2;
1296 }
1297
1298 NS_DBG("find_operation: there is still ambiguity\n");
1299
1300 ns->pstates[ns->npstates++] = ns->state;
1301
1302 return -1;
1303 }
1304
1305 static void ns_put_pages(struct nandsim *ns)
1306 {
1307 int i;
1308
1309 for (i = 0; i < ns->held_cnt; i++)
1310 put_page(ns->held_pages[i]);
1311 }
1312
1313 /* Get page cache pages in advance to provide NOFS memory allocation */
1314 static int ns_get_pages(struct nandsim *ns, struct file *file, size_t count,
1315 loff_t pos)
1316 {
1317 pgoff_t index, start_index, end_index;
1318 struct page *page;
1319 struct address_space *mapping = file->f_mapping;
1320
1321 start_index = pos >> PAGE_SHIFT;
1322 end_index = (pos + count - 1) >> PAGE_SHIFT;
1323 if (end_index - start_index + 1 > NS_MAX_HELD_PAGES)
1324 return -EINVAL;
1325 ns->held_cnt = 0;
1326 for (index = start_index; index <= end_index; index++) {
1327 page = find_get_page(mapping, index);
1328 if (page == NULL) {
1329 page = find_or_create_page(mapping, index, GFP_NOFS);
1330 if (page == NULL) {
1331 write_inode_now(mapping->host, 1);
1332 page = find_or_create_page(mapping, index, GFP_NOFS);
1333 }
1334 if (page == NULL) {
1335 ns_put_pages(ns);
1336 return -ENOMEM;
1337 }
1338 unlock_page(page);
1339 }
1340 ns->held_pages[ns->held_cnt++] = page;
1341 }
1342 return 0;
1343 }
1344
1345 static ssize_t ns_read_file(struct nandsim *ns, struct file *file, void *buf,
1346 size_t count, loff_t pos)
1347 {
1348 ssize_t tx;
1349 int err;
1350 unsigned int noreclaim_flag;
1351
1352 err = ns_get_pages(ns, file, count, pos);
1353 if (err)
1354 return err;
1355 noreclaim_flag = memalloc_noreclaim_save();
1356 tx = kernel_read(file, buf, count, &pos);
1357 memalloc_noreclaim_restore(noreclaim_flag);
1358 ns_put_pages(ns);
1359 return tx;
1360 }
1361
1362 static ssize_t ns_write_file(struct nandsim *ns, struct file *file, void *buf,
1363 size_t count, loff_t pos)
1364 {
1365 ssize_t tx;
1366 int err;
1367 unsigned int noreclaim_flag;
1368
1369 err = ns_get_pages(ns, file, count, pos);
1370 if (err)
1371 return err;
1372 noreclaim_flag = memalloc_noreclaim_save();
1373 tx = kernel_write(file, buf, count, &pos);
1374 memalloc_noreclaim_restore(noreclaim_flag);
1375 ns_put_pages(ns);
1376 return tx;
1377 }
1378
1379 /*
1380 * Returns a pointer to the current page.
1381 */
1382 static inline union ns_mem *NS_GET_PAGE(struct nandsim *ns)
1383 {
1384 return &(ns->pages[ns->regs.row]);
1385 }
1386
1387 /*
1388 * Retuns a pointer to the current byte, within the current page.
1389 */
1390 static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns)
1391 {
1392 return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off;
1393 }
1394
1395 static int ns_do_read_error(struct nandsim *ns, int num)
1396 {
1397 unsigned int page_no = ns->regs.row;
1398
1399 if (ns_read_error(page_no)) {
1400 prandom_bytes(ns->buf.byte, num);
1401 NS_WARN("simulating read error in page %u\n", page_no);
1402 return 1;
1403 }
1404 return 0;
1405 }
1406
1407 static void ns_do_bit_flips(struct nandsim *ns, int num)
1408 {
1409 if (bitflips && prandom_u32() < (1 << 22)) {
1410 int flips = 1;
1411 if (bitflips > 1)
1412 flips = (prandom_u32() % (int) bitflips) + 1;
1413 while (flips--) {
1414 int pos = prandom_u32() % (num * 8);
1415 ns->buf.byte[pos / 8] ^= (1 << (pos % 8));
1416 NS_WARN("read_page: flipping bit %d in page %d "
1417 "reading from %d ecc: corrected=%u failed=%u\n",
1418 pos, ns->regs.row, ns->regs.column + ns->regs.off,
1419 nsmtd->ecc_stats.corrected, nsmtd->ecc_stats.failed);
1420 }
1421 }
1422 }
1423
1424 /*
1425 * Fill the NAND buffer with data read from the specified page.
1426 */
1427 static void ns_read_page(struct nandsim *ns, int num)
1428 {
1429 union ns_mem *mypage;
1430
1431 if (ns->cfile) {
1432 if (!test_bit(ns->regs.row, ns->pages_written)) {
1433 NS_DBG("read_page: page %d not written\n", ns->regs.row);
1434 memset(ns->buf.byte, 0xFF, num);
1435 } else {
1436 loff_t pos;
1437 ssize_t tx;
1438
1439 NS_DBG("read_page: page %d written, reading from %d\n",
1440 ns->regs.row, ns->regs.column + ns->regs.off);
1441 if (ns_do_read_error(ns, num))
1442 return;
1443 pos = (loff_t)NS_RAW_OFFSET(ns) + ns->regs.off;
1444 tx = ns_read_file(ns, ns->cfile, ns->buf.byte, num,
1445 pos);
1446 if (tx != num) {
1447 NS_ERR("read_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1448 return;
1449 }
1450 ns_do_bit_flips(ns, num);
1451 }
1452 return;
1453 }
1454
1455 mypage = NS_GET_PAGE(ns);
1456 if (mypage->byte == NULL) {
1457 NS_DBG("read_page: page %d not allocated\n", ns->regs.row);
1458 memset(ns->buf.byte, 0xFF, num);
1459 } else {
1460 NS_DBG("read_page: page %d allocated, reading from %d\n",
1461 ns->regs.row, ns->regs.column + ns->regs.off);
1462 if (ns_do_read_error(ns, num))
1463 return;
1464 memcpy(ns->buf.byte, NS_PAGE_BYTE_OFF(ns), num);
1465 ns_do_bit_flips(ns, num);
1466 }
1467 }
1468
1469 /*
1470 * Erase all pages in the specified sector.
1471 */
1472 static void ns_erase_sector(struct nandsim *ns)
1473 {
1474 union ns_mem *mypage;
1475 int i;
1476
1477 if (ns->cfile) {
1478 for (i = 0; i < ns->geom.pgsec; i++)
1479 if (__test_and_clear_bit(ns->regs.row + i,
1480 ns->pages_written)) {
1481 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row + i);
1482 }
1483 return;
1484 }
1485
1486 mypage = NS_GET_PAGE(ns);
1487 for (i = 0; i < ns->geom.pgsec; i++) {
1488 if (mypage->byte != NULL) {
1489 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row+i);
1490 kmem_cache_free(ns->nand_pages_slab, mypage->byte);
1491 mypage->byte = NULL;
1492 }
1493 mypage++;
1494 }
1495 }
1496
1497 /*
1498 * Program the specified page with the contents from the NAND buffer.
1499 */
1500 static int ns_prog_page(struct nandsim *ns, int num)
1501 {
1502 int i;
1503 union ns_mem *mypage;
1504 u_char *pg_off;
1505
1506 if (ns->cfile) {
1507 loff_t off;
1508 ssize_t tx;
1509 int all;
1510
1511 NS_DBG("prog_page: writing page %d\n", ns->regs.row);
1512 pg_off = ns->file_buf + ns->regs.column + ns->regs.off;
1513 off = (loff_t)NS_RAW_OFFSET(ns) + ns->regs.off;
1514 if (!test_bit(ns->regs.row, ns->pages_written)) {
1515 all = 1;
1516 memset(ns->file_buf, 0xff, ns->geom.pgszoob);
1517 } else {
1518 all = 0;
1519 tx = ns_read_file(ns, ns->cfile, pg_off, num, off);
1520 if (tx != num) {
1521 NS_ERR("prog_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1522 return -1;
1523 }
1524 }
1525 for (i = 0; i < num; i++)
1526 pg_off[i] &= ns->buf.byte[i];
1527 if (all) {
1528 loff_t pos = (loff_t)ns->regs.row * ns->geom.pgszoob;
1529 tx = ns_write_file(ns, ns->cfile, ns->file_buf,
1530 ns->geom.pgszoob, pos);
1531 if (tx != ns->geom.pgszoob) {
1532 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1533 return -1;
1534 }
1535 __set_bit(ns->regs.row, ns->pages_written);
1536 } else {
1537 tx = ns_write_file(ns, ns->cfile, pg_off, num, off);
1538 if (tx != num) {
1539 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1540 return -1;
1541 }
1542 }
1543 return 0;
1544 }
1545
1546 mypage = NS_GET_PAGE(ns);
1547 if (mypage->byte == NULL) {
1548 NS_DBG("prog_page: allocating page %d\n", ns->regs.row);
1549 /*
1550 * We allocate memory with GFP_NOFS because a flash FS may
1551 * utilize this. If it is holding an FS lock, then gets here,
1552 * then kernel memory alloc runs writeback which goes to the FS
1553 * again and deadlocks. This was seen in practice.
1554 */
1555 mypage->byte = kmem_cache_alloc(ns->nand_pages_slab, GFP_NOFS);
1556 if (mypage->byte == NULL) {
1557 NS_ERR("prog_page: error allocating memory for page %d\n", ns->regs.row);
1558 return -1;
1559 }
1560 memset(mypage->byte, 0xFF, ns->geom.pgszoob);
1561 }
1562
1563 pg_off = NS_PAGE_BYTE_OFF(ns);
1564 for (i = 0; i < num; i++)
1565 pg_off[i] &= ns->buf.byte[i];
1566
1567 return 0;
1568 }
1569
1570 /*
1571 * If state has any action bit, perform this action.
1572 *
1573 * RETURNS: 0 if success, -1 if error.
1574 */
1575 static int ns_do_state_action(struct nandsim *ns, uint32_t action)
1576 {
1577 int num;
1578 int busdiv = ns->busw == 8 ? 1 : 2;
1579 unsigned int erase_block_no, page_no;
1580
1581 action &= ACTION_MASK;
1582
1583 /* Check that page address input is correct */
1584 if (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) {
1585 NS_WARN("do_state_action: wrong page number (%#x)\n", ns->regs.row);
1586 return -1;
1587 }
1588
1589 switch (action) {
1590
1591 case ACTION_CPY:
1592 /*
1593 * Copy page data to the internal buffer.
1594 */
1595
1596 /* Column shouldn't be very large */
1597 if (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) {
1598 NS_ERR("do_state_action: column number is too large\n");
1599 break;
1600 }
1601 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1602 ns_read_page(ns, num);
1603
1604 NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n",
1605 num, NS_RAW_OFFSET(ns) + ns->regs.off);
1606
1607 if (ns->regs.off == 0)
1608 NS_LOG("read page %d\n", ns->regs.row);
1609 else if (ns->regs.off < ns->geom.pgsz)
1610 NS_LOG("read page %d (second half)\n", ns->regs.row);
1611 else
1612 NS_LOG("read OOB of page %d\n", ns->regs.row);
1613
1614 NS_UDELAY(access_delay);
1615 NS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv);
1616
1617 break;
1618
1619 case ACTION_SECERASE:
1620 /*
1621 * Erase sector.
1622 */
1623
1624 if (ns->lines.wp) {
1625 NS_ERR("do_state_action: device is write-protected, ignore sector erase\n");
1626 return -1;
1627 }
1628
1629 if (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec
1630 || (ns->regs.row & ~(ns->geom.secsz - 1))) {
1631 NS_ERR("do_state_action: wrong sector address (%#x)\n", ns->regs.row);
1632 return -1;
1633 }
1634
1635 ns->regs.row = (ns->regs.row <<
1636 8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column;
1637 ns->regs.column = 0;
1638
1639 erase_block_no = ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift);
1640
1641 NS_DBG("do_state_action: erase sector at address %#x, off = %d\n",
1642 ns->regs.row, NS_RAW_OFFSET(ns));
1643 NS_LOG("erase sector %u\n", erase_block_no);
1644
1645 ns_erase_sector(ns);
1646
1647 NS_MDELAY(erase_delay);
1648
1649 if (erase_block_wear)
1650 ns_update_wear(erase_block_no);
1651
1652 if (ns_erase_error(erase_block_no)) {
1653 NS_WARN("simulating erase failure in erase block %u\n", erase_block_no);
1654 return -1;
1655 }
1656
1657 break;
1658
1659 case ACTION_PRGPAGE:
1660 /*
1661 * Program page - move internal buffer data to the page.
1662 */
1663
1664 if (ns->lines.wp) {
1665 NS_WARN("do_state_action: device is write-protected, programm\n");
1666 return -1;
1667 }
1668
1669 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1670 if (num != ns->regs.count) {
1671 NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n",
1672 ns->regs.count, num);
1673 return -1;
1674 }
1675
1676 if (ns_prog_page(ns, num) == -1)
1677 return -1;
1678
1679 page_no = ns->regs.row;
1680
1681 NS_DBG("do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\n",
1682 num, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off);
1683 NS_LOG("programm page %d\n", ns->regs.row);
1684
1685 NS_UDELAY(programm_delay);
1686 NS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv);
1687
1688 if (ns_write_error(page_no)) {
1689 NS_WARN("simulating write failure in page %u\n", page_no);
1690 return -1;
1691 }
1692
1693 break;
1694
1695 case ACTION_ZEROOFF:
1696 NS_DBG("do_state_action: set internal offset to 0\n");
1697 ns->regs.off = 0;
1698 break;
1699
1700 case ACTION_HALFOFF:
1701 if (!(ns->options & OPT_PAGE512_8BIT)) {
1702 NS_ERR("do_state_action: BUG! can't skip half of page for non-512"
1703 "byte page size 8x chips\n");
1704 return -1;
1705 }
1706 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz/2);
1707 ns->regs.off = ns->geom.pgsz/2;
1708 break;
1709
1710 case ACTION_OOBOFF:
1711 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz);
1712 ns->regs.off = ns->geom.pgsz;
1713 break;
1714
1715 default:
1716 NS_DBG("do_state_action: BUG! unknown action\n");
1717 }
1718
1719 return 0;
1720 }
1721
1722 /*
1723 * Switch simulator's state.
1724 */
1725 static void ns_switch_state(struct nandsim *ns)
1726 {
1727 if (ns->op) {
1728 /*
1729 * The current operation have already been identified.
1730 * Just follow the states chain.
1731 */
1732
1733 ns->stateidx += 1;
1734 ns->state = ns->nxstate;
1735 ns->nxstate = ns->op[ns->stateidx + 1];
1736
1737 NS_DBG("switch_state: operation is known, switch to the next state, "
1738 "state: %s, nxstate: %s\n",
1739 ns_get_state_name(ns->state),
1740 ns_get_state_name(ns->nxstate));
1741
1742 /* See, whether we need to do some action */
1743 if ((ns->state & ACTION_MASK) &&
1744 ns_do_state_action(ns, ns->state) < 0) {
1745 ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1746 return;
1747 }
1748
1749 } else {
1750 /*
1751 * We don't yet know which operation we perform.
1752 * Try to identify it.
1753 */
1754
1755 /*
1756 * The only event causing the switch_state function to
1757 * be called with yet unknown operation is new command.
1758 */
1759 ns->state = ns_get_state_by_command(ns->regs.command);
1760
1761 NS_DBG("switch_state: operation is unknown, try to find it\n");
1762
1763 if (ns_find_operation(ns, 0))
1764 return;
1765
1766 if ((ns->state & ACTION_MASK) &&
1767 ns_do_state_action(ns, ns->state) < 0) {
1768 ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1769 return;
1770 }
1771 }
1772
1773 /* For 16x devices column means the page offset in words */
1774 if ((ns->nxstate & STATE_ADDR_MASK) && ns->busw == 16) {
1775 NS_DBG("switch_state: double the column number for 16x device\n");
1776 ns->regs.column <<= 1;
1777 }
1778
1779 if (NS_STATE(ns->nxstate) == STATE_READY) {
1780 /*
1781 * The current state is the last. Return to STATE_READY
1782 */
1783
1784 u_char status = NS_STATUS_OK(ns);
1785
1786 /* In case of data states, see if all bytes were input/output */
1787 if ((ns->state & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK))
1788 && ns->regs.count != ns->regs.num) {
1789 NS_WARN("switch_state: not all bytes were processed, %d left\n",
1790 ns->regs.num - ns->regs.count);
1791 status = NS_STATUS_FAILED(ns);
1792 }
1793
1794 NS_DBG("switch_state: operation complete, switch to STATE_READY state\n");
1795
1796 ns_switch_to_ready_state(ns, status);
1797
1798 return;
1799 } else if (ns->nxstate & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) {
1800 /*
1801 * If the next state is data input/output, switch to it now
1802 */
1803
1804 ns->state = ns->nxstate;
1805 ns->nxstate = ns->op[++ns->stateidx + 1];
1806 ns->regs.num = ns->regs.count = 0;
1807
1808 NS_DBG("switch_state: the next state is data I/O, switch, "
1809 "state: %s, nxstate: %s\n",
1810 ns_get_state_name(ns->state),
1811 ns_get_state_name(ns->nxstate));
1812
1813 /*
1814 * Set the internal register to the count of bytes which
1815 * are expected to be input or output
1816 */
1817 switch (NS_STATE(ns->state)) {
1818 case STATE_DATAIN:
1819 case STATE_DATAOUT:
1820 ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1821 break;
1822
1823 case STATE_DATAOUT_ID:
1824 ns->regs.num = ns->geom.idbytes;
1825 break;
1826
1827 case STATE_DATAOUT_STATUS:
1828 ns->regs.count = ns->regs.num = 0;
1829 break;
1830
1831 default:
1832 NS_ERR("switch_state: BUG! unknown data state\n");
1833 }
1834
1835 } else if (ns->nxstate & STATE_ADDR_MASK) {
1836 /*
1837 * If the next state is address input, set the internal
1838 * register to the number of expected address bytes
1839 */
1840
1841 ns->regs.count = 0;
1842
1843 switch (NS_STATE(ns->nxstate)) {
1844 case STATE_ADDR_PAGE:
1845 ns->regs.num = ns->geom.pgaddrbytes;
1846
1847 break;
1848 case STATE_ADDR_SEC:
1849 ns->regs.num = ns->geom.secaddrbytes;
1850 break;
1851
1852 case STATE_ADDR_ZERO:
1853 ns->regs.num = 1;
1854 break;
1855
1856 case STATE_ADDR_COLUMN:
1857 /* Column address is always 2 bytes */
1858 ns->regs.num = ns->geom.pgaddrbytes - ns->geom.secaddrbytes;
1859 break;
1860
1861 default:
1862 NS_ERR("switch_state: BUG! unknown address state\n");
1863 }
1864 } else {
1865 /*
1866 * Just reset internal counters.
1867 */
1868
1869 ns->regs.num = 0;
1870 ns->regs.count = 0;
1871 }
1872 }
1873
1874 static u_char ns_nand_read_byte(struct nand_chip *chip)
1875 {
1876 struct nandsim *ns = nand_get_controller_data(chip);
1877 u_char outb = 0x00;
1878
1879 /* Sanity and correctness checks */
1880 if (!ns->lines.ce) {
1881 NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb);
1882 return outb;
1883 }
1884 if (ns->lines.ale || ns->lines.cle) {
1885 NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb);
1886 return outb;
1887 }
1888 if (!(ns->state & STATE_DATAOUT_MASK)) {
1889 NS_WARN("read_byte: unexpected data output cycle, state is %s return %#x\n",
1890 ns_get_state_name(ns->state), (uint)outb);
1891 return outb;
1892 }
1893
1894 /* Status register may be read as many times as it is wanted */
1895 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS) {
1896 NS_DBG("read_byte: return %#x status\n", ns->regs.status);
1897 return ns->regs.status;
1898 }
1899
1900 /* Check if there is any data in the internal buffer which may be read */
1901 if (ns->regs.count == ns->regs.num) {
1902 NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb);
1903 return outb;
1904 }
1905
1906 switch (NS_STATE(ns->state)) {
1907 case STATE_DATAOUT:
1908 if (ns->busw == 8) {
1909 outb = ns->buf.byte[ns->regs.count];
1910 ns->regs.count += 1;
1911 } else {
1912 outb = (u_char)cpu_to_le16(ns->buf.word[ns->regs.count >> 1]);
1913 ns->regs.count += 2;
1914 }
1915 break;
1916 case STATE_DATAOUT_ID:
1917 NS_DBG("read_byte: read ID byte %d, total = %d\n", ns->regs.count, ns->regs.num);
1918 outb = ns->ids[ns->regs.count];
1919 ns->regs.count += 1;
1920 break;
1921 default:
1922 BUG();
1923 }
1924
1925 if (ns->regs.count == ns->regs.num) {
1926 NS_DBG("read_byte: all bytes were read\n");
1927
1928 if (NS_STATE(ns->nxstate) == STATE_READY)
1929 ns_switch_state(ns);
1930 }
1931
1932 return outb;
1933 }
1934
1935 static void ns_nand_write_byte(struct nand_chip *chip, u_char byte)
1936 {
1937 struct nandsim *ns = nand_get_controller_data(chip);
1938
1939 /* Sanity and correctness checks */
1940 if (!ns->lines.ce) {
1941 NS_ERR("write_byte: chip is disabled, ignore write\n");
1942 return;
1943 }
1944 if (ns->lines.ale && ns->lines.cle) {
1945 NS_ERR("write_byte: ALE and CLE pins are high simultaneously, ignore write\n");
1946 return;
1947 }
1948
1949 if (ns->lines.cle == 1) {
1950 /*
1951 * The byte written is a command.
1952 */
1953
1954 if (byte == NAND_CMD_RESET) {
1955 NS_LOG("reset chip\n");
1956 ns_switch_to_ready_state(ns, NS_STATUS_OK(ns));
1957 return;
1958 }
1959
1960 /* Check that the command byte is correct */
1961 if (ns_check_command(byte)) {
1962 NS_ERR("write_byte: unknown command %#x\n", (uint)byte);
1963 return;
1964 }
1965
1966 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS
1967 || NS_STATE(ns->state) == STATE_DATAOUT) {
1968 int row = ns->regs.row;
1969
1970 ns_switch_state(ns);
1971 if (byte == NAND_CMD_RNDOUT)
1972 ns->regs.row = row;
1973 }
1974
1975 /* Check if chip is expecting command */
1976 if (NS_STATE(ns->nxstate) != STATE_UNKNOWN && !(ns->nxstate & STATE_CMD_MASK)) {
1977 /* Do not warn if only 2 id bytes are read */
1978 if (!(ns->regs.command == NAND_CMD_READID &&
1979 NS_STATE(ns->state) == STATE_DATAOUT_ID && ns->regs.count == 2)) {
1980 /*
1981 * We are in situation when something else (not command)
1982 * was expected but command was input. In this case ignore
1983 * previous command(s)/state(s) and accept the last one.
1984 */
1985 NS_WARN("write_byte: command (%#x) wasn't expected, expected state is %s, ignore previous states\n",
1986 (uint)byte,
1987 ns_get_state_name(ns->nxstate));
1988 }
1989 ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1990 }
1991
1992 NS_DBG("command byte corresponding to %s state accepted\n",
1993 ns_get_state_name(ns_get_state_by_command(byte)));
1994 ns->regs.command = byte;
1995 ns_switch_state(ns);
1996
1997 } else if (ns->lines.ale == 1) {
1998 /*
1999 * The byte written is an address.
2000 */
2001
2002 if (NS_STATE(ns->nxstate) == STATE_UNKNOWN) {
2003
2004 NS_DBG("write_byte: operation isn't known yet, identify it\n");
2005
2006 if (ns_find_operation(ns, 1) < 0)
2007 return;
2008
2009 if ((ns->state & ACTION_MASK) &&
2010 ns_do_state_action(ns, ns->state) < 0) {
2011 ns_switch_to_ready_state(ns,
2012 NS_STATUS_FAILED(ns));
2013 return;
2014 }
2015
2016 ns->regs.count = 0;
2017 switch (NS_STATE(ns->nxstate)) {
2018 case STATE_ADDR_PAGE:
2019 ns->regs.num = ns->geom.pgaddrbytes;
2020 break;
2021 case STATE_ADDR_SEC:
2022 ns->regs.num = ns->geom.secaddrbytes;
2023 break;
2024 case STATE_ADDR_ZERO:
2025 ns->regs.num = 1;
2026 break;
2027 default:
2028 BUG();
2029 }
2030 }
2031
2032 /* Check that chip is expecting address */
2033 if (!(ns->nxstate & STATE_ADDR_MASK)) {
2034 NS_ERR("write_byte: address (%#x) isn't expected, expected state is %s, switch to STATE_READY\n",
2035 (uint)byte, ns_get_state_name(ns->nxstate));
2036 ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2037 return;
2038 }
2039
2040 /* Check if this is expected byte */
2041 if (ns->regs.count == ns->regs.num) {
2042 NS_ERR("write_byte: no more address bytes expected\n");
2043 ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2044 return;
2045 }
2046
2047 ns_accept_addr_byte(ns, byte);
2048
2049 ns->regs.count += 1;
2050
2051 NS_DBG("write_byte: address byte %#x was accepted (%d bytes input, %d expected)\n",
2052 (uint)byte, ns->regs.count, ns->regs.num);
2053
2054 if (ns->regs.count == ns->regs.num) {
2055 NS_DBG("address (%#x, %#x) is accepted\n", ns->regs.row, ns->regs.column);
2056 ns_switch_state(ns);
2057 }
2058
2059 } else {
2060 /*
2061 * The byte written is an input data.
2062 */
2063
2064 /* Check that chip is expecting data input */
2065 if (!(ns->state & STATE_DATAIN_MASK)) {
2066 NS_ERR("write_byte: data input (%#x) isn't expected, state is %s, switch to %s\n",
2067 (uint)byte, ns_get_state_name(ns->state),
2068 ns_get_state_name(STATE_READY));
2069 ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2070 return;
2071 }
2072
2073 /* Check if this is expected byte */
2074 if (ns->regs.count == ns->regs.num) {
2075 NS_WARN("write_byte: %u input bytes has already been accepted, ignore write\n",
2076 ns->regs.num);
2077 return;
2078 }
2079
2080 if (ns->busw == 8) {
2081 ns->buf.byte[ns->regs.count] = byte;
2082 ns->regs.count += 1;
2083 } else {
2084 ns->buf.word[ns->regs.count >> 1] = cpu_to_le16((uint16_t)byte);
2085 ns->regs.count += 2;
2086 }
2087 }
2088
2089 return;
2090 }
2091
2092 static void ns_nand_write_buf(struct nand_chip *chip, const u_char *buf,
2093 int len)
2094 {
2095 struct nandsim *ns = nand_get_controller_data(chip);
2096
2097 /* Check that chip is expecting data input */
2098 if (!(ns->state & STATE_DATAIN_MASK)) {
2099 NS_ERR("write_buf: data input isn't expected, state is %s, switch to STATE_READY\n",
2100 ns_get_state_name(ns->state));
2101 ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2102 return;
2103 }
2104
2105 /* Check if these are expected bytes */
2106 if (ns->regs.count + len > ns->regs.num) {
2107 NS_ERR("write_buf: too many input bytes\n");
2108 ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2109 return;
2110 }
2111
2112 memcpy(ns->buf.byte + ns->regs.count, buf, len);
2113 ns->regs.count += len;
2114
2115 if (ns->regs.count == ns->regs.num) {
2116 NS_DBG("write_buf: %d bytes were written\n", ns->regs.count);
2117 }
2118 }
2119
2120 static void ns_nand_read_buf(struct nand_chip *chip, u_char *buf, int len)
2121 {
2122 struct nandsim *ns = nand_get_controller_data(chip);
2123
2124 /* Sanity and correctness checks */
2125 if (!ns->lines.ce) {
2126 NS_ERR("read_buf: chip is disabled\n");
2127 return;
2128 }
2129 if (ns->lines.ale || ns->lines.cle) {
2130 NS_ERR("read_buf: ALE or CLE pin is high\n");
2131 return;
2132 }
2133 if (!(ns->state & STATE_DATAOUT_MASK)) {
2134 NS_WARN("read_buf: unexpected data output cycle, current state is %s\n",
2135 ns_get_state_name(ns->state));
2136 return;
2137 }
2138
2139 if (NS_STATE(ns->state) != STATE_DATAOUT) {
2140 int i;
2141
2142 for (i = 0; i < len; i++)
2143 buf[i] = ns_nand_read_byte(chip);
2144
2145 return;
2146 }
2147
2148 /* Check if these are expected bytes */
2149 if (ns->regs.count + len > ns->regs.num) {
2150 NS_ERR("read_buf: too many bytes to read\n");
2151 ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2152 return;
2153 }
2154
2155 memcpy(buf, ns->buf.byte + ns->regs.count, len);
2156 ns->regs.count += len;
2157
2158 if (ns->regs.count == ns->regs.num) {
2159 if (NS_STATE(ns->nxstate) == STATE_READY)
2160 ns_switch_state(ns);
2161 }
2162
2163 return;
2164 }
2165
2166 static int ns_exec_op(struct nand_chip *chip, const struct nand_operation *op,
2167 bool check_only)
2168 {
2169 int i;
2170 unsigned int op_id;
2171 const struct nand_op_instr *instr = NULL;
2172 struct nandsim *ns = nand_get_controller_data(chip);
2173
2174 if (check_only)
2175 return 0;
2176
2177 ns->lines.ce = 1;
2178
2179 for (op_id = 0; op_id < op->ninstrs; op_id++) {
2180 instr = &op->instrs[op_id];
2181 ns->lines.cle = 0;
2182 ns->lines.ale = 0;
2183
2184 switch (instr->type) {
2185 case NAND_OP_CMD_INSTR:
2186 ns->lines.cle = 1;
2187 ns_nand_write_byte(chip, instr->ctx.cmd.opcode);
2188 break;
2189 case NAND_OP_ADDR_INSTR:
2190 ns->lines.ale = 1;
2191 for (i = 0; i < instr->ctx.addr.naddrs; i++)
2192 ns_nand_write_byte(chip, instr->ctx.addr.addrs[i]);
2193 break;
2194 case NAND_OP_DATA_IN_INSTR:
2195 ns_nand_read_buf(chip, instr->ctx.data.buf.in, instr->ctx.data.len);
2196 break;
2197 case NAND_OP_DATA_OUT_INSTR:
2198 ns_nand_write_buf(chip, instr->ctx.data.buf.out, instr->ctx.data.len);
2199 break;
2200 case NAND_OP_WAITRDY_INSTR:
2201 /* we are always ready */
2202 break;
2203 }
2204 }
2205
2206 return 0;
2207 }
2208
2209 static int ns_attach_chip(struct nand_chip *chip)
2210 {
2211 unsigned int eccsteps, eccbytes;
2212
2213 if (!bch)
2214 return 0;
2215
2216 if (!IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)) {
2217 NS_ERR("BCH ECC support is disabled\n");
2218 return -EINVAL;
2219 }
2220
2221 /* Use 512-byte ecc blocks */
2222 eccsteps = nsmtd->writesize / 512;
2223 eccbytes = ((bch * 13) + 7) / 8;
2224
2225 /* Do not bother supporting small page devices */
2226 if (nsmtd->oobsize < 64 || !eccsteps) {
2227 NS_ERR("BCH not available on small page devices\n");
2228 return -EINVAL;
2229 }
2230
2231 if (((eccbytes * eccsteps) + 2) > nsmtd->oobsize) {
2232 NS_ERR("Invalid BCH value %u\n", bch);
2233 return -EINVAL;
2234 }
2235
2236 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
2237 chip->ecc.algo = NAND_ECC_ALGO_BCH;
2238 chip->ecc.size = 512;
2239 chip->ecc.strength = bch;
2240 chip->ecc.bytes = eccbytes;
2241
2242 NS_INFO("Using %u-bit/%u bytes BCH ECC\n", bch, chip->ecc.size);
2243
2244 return 0;
2245 }
2246
2247 static const struct nand_controller_ops ns_controller_ops = {
2248 .attach_chip = ns_attach_chip,
2249 .exec_op = ns_exec_op,
2250 };
2251
2252 /*
2253 * Module initialization function
2254 */
2255 static int __init ns_init_module(void)
2256 {
2257 struct list_head *pos, *n;
2258 struct nand_chip *chip;
2259 struct nandsim *ns;
2260 int ret;
2261
2262 if (bus_width != 8 && bus_width != 16) {
2263 NS_ERR("wrong bus width (%d), use only 8 or 16\n", bus_width);
2264 return -EINVAL;
2265 }
2266
2267 ns = kzalloc(sizeof(struct nandsim), GFP_KERNEL);
2268 if (!ns) {
2269 NS_ERR("unable to allocate core structures.\n");
2270 return -ENOMEM;
2271 }
2272 chip = &ns->chip;
2273 nsmtd = nand_to_mtd(chip);
2274 nand_set_controller_data(chip, (void *)ns);
2275
2276 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
2277 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
2278 /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
2279 /* and 'badblocks' parameters to work */
2280 chip->options |= NAND_SKIP_BBTSCAN;
2281
2282 switch (bbt) {
2283 case 2:
2284 chip->bbt_options |= NAND_BBT_NO_OOB;
2285 fallthrough;
2286 case 1:
2287 chip->bbt_options |= NAND_BBT_USE_FLASH;
2288 fallthrough;
2289 case 0:
2290 break;
2291 default:
2292 NS_ERR("bbt has to be 0..2\n");
2293 ret = -EINVAL;
2294 goto free_ns_struct;
2295 }
2296 /*
2297 * Perform minimum nandsim structure initialization to handle
2298 * the initial ID read command correctly
2299 */
2300 if (id_bytes[6] != 0xFF || id_bytes[7] != 0xFF)
2301 ns->geom.idbytes = 8;
2302 else if (id_bytes[4] != 0xFF || id_bytes[5] != 0xFF)
2303 ns->geom.idbytes = 6;
2304 else if (id_bytes[2] != 0xFF || id_bytes[3] != 0xFF)
2305 ns->geom.idbytes = 4;
2306 else
2307 ns->geom.idbytes = 2;
2308 ns->regs.status = NS_STATUS_OK(ns);
2309 ns->nxstate = STATE_UNKNOWN;
2310 ns->options |= OPT_PAGE512; /* temporary value */
2311 memcpy(ns->ids, id_bytes, sizeof(ns->ids));
2312 if (bus_width == 16) {
2313 ns->busw = 16;
2314 chip->options |= NAND_BUSWIDTH_16;
2315 }
2316
2317 nsmtd->owner = THIS_MODULE;
2318
2319 ret = ns_parse_weakblocks();
2320 if (ret)
2321 goto free_ns_struct;
2322
2323 ret = ns_parse_weakpages();
2324 if (ret)
2325 goto free_wb_list;
2326
2327 ret = ns_parse_gravepages();
2328 if (ret)
2329 goto free_wp_list;
2330
2331 nand_controller_init(&ns->base);
2332 ns->base.ops = &ns_controller_ops;
2333 chip->controller = &ns->base;
2334
2335 ret = nand_scan(chip, 1);
2336 if (ret) {
2337 NS_ERR("Could not scan NAND Simulator device\n");
2338 goto free_gp_list;
2339 }
2340
2341 if (overridesize) {
2342 uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize;
2343 struct nand_memory_organization *memorg;
2344 u64 targetsize;
2345
2346 memorg = nanddev_get_memorg(&chip->base);
2347
2348 if (new_size >> overridesize != nsmtd->erasesize) {
2349 NS_ERR("overridesize is too big\n");
2350 ret = -EINVAL;
2351 goto cleanup_nand;
2352 }
2353
2354 /* N.B. This relies on nand_scan not doing anything with the size before we change it */
2355 nsmtd->size = new_size;
2356 memorg->eraseblocks_per_lun = 1 << overridesize;
2357 targetsize = nanddev_target_size(&chip->base);
2358 chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1;
2359 chip->pagemask = (targetsize >> chip->page_shift) - 1;
2360 }
2361
2362 ret = ns_setup_wear_reporting(nsmtd);
2363 if (ret)
2364 goto cleanup_nand;
2365
2366 ret = ns_init(nsmtd);
2367 if (ret)
2368 goto free_ebw;
2369
2370 ret = nand_create_bbt(chip);
2371 if (ret)
2372 goto free_ns_object;
2373
2374 ret = ns_parse_badblocks(ns, nsmtd);
2375 if (ret)
2376 goto free_ns_object;
2377
2378 /* Register NAND partitions */
2379 ret = mtd_device_register(nsmtd, &ns->partitions[0], ns->nbparts);
2380 if (ret)
2381 goto free_ns_object;
2382
2383 ret = ns_debugfs_create(ns);
2384 if (ret)
2385 goto unregister_mtd;
2386
2387 return 0;
2388
2389 unregister_mtd:
2390 WARN_ON(mtd_device_unregister(nsmtd));
2391 free_ns_object:
2392 ns_free(ns);
2393 free_ebw:
2394 kfree(erase_block_wear);
2395 cleanup_nand:
2396 nand_cleanup(chip);
2397 free_gp_list:
2398 list_for_each_safe(pos, n, &grave_pages) {
2399 list_del(pos);
2400 kfree(list_entry(pos, struct grave_page, list));
2401 }
2402 free_wp_list:
2403 list_for_each_safe(pos, n, &weak_pages) {
2404 list_del(pos);
2405 kfree(list_entry(pos, struct weak_page, list));
2406 }
2407 free_wb_list:
2408 list_for_each_safe(pos, n, &weak_blocks) {
2409 list_del(pos);
2410 kfree(list_entry(pos, struct weak_block, list));
2411 }
2412 free_ns_struct:
2413 kfree(ns);
2414
2415 return ret;
2416 }
2417
2418 module_init(ns_init_module);
2419
2420 /*
2421 * Module clean-up function
2422 */
2423 static void __exit ns_cleanup_module(void)
2424 {
2425 struct nand_chip *chip = mtd_to_nand(nsmtd);
2426 struct nandsim *ns = nand_get_controller_data(chip);
2427 struct list_head *pos, *n;
2428
2429 ns_debugfs_remove(ns);
2430 WARN_ON(mtd_device_unregister(nsmtd));
2431 ns_free(ns);
2432 kfree(erase_block_wear);
2433 nand_cleanup(chip);
2434
2435 list_for_each_safe(pos, n, &grave_pages) {
2436 list_del(pos);
2437 kfree(list_entry(pos, struct grave_page, list));
2438 }
2439
2440 list_for_each_safe(pos, n, &weak_pages) {
2441 list_del(pos);
2442 kfree(list_entry(pos, struct weak_page, list));
2443 }
2444
2445 list_for_each_safe(pos, n, &weak_blocks) {
2446 list_del(pos);
2447 kfree(list_entry(pos, struct weak_block, list));
2448 }
2449
2450 kfree(ns);
2451 }
2452
2453 module_exit(ns_cleanup_module);
2454
2455 MODULE_LICENSE ("GPL");
2456 MODULE_AUTHOR ("Artem B. Bityuckiy");
2457 MODULE_DESCRIPTION ("The NAND flash simulator");
Linux with added FPC-III support