drivers/net/phy/national.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/national.c
   4  *
   5  * Driver for National Semiconductor PHYs
   6  *
   7  * Author: Stuart Menefy <stuart.menefy@st.com>
   8  * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
   9  *
  10  * Copyright (c) 2008 STMicroelectronics Limited
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/mii.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/netdevice.h>
  21
  22 #define DEBUG
  23
  24 /* DP83865 phy identifier values */
  25 #define DP83865_PHY_ID  0x20005c7a
  26
  27 #define DP83865_INT_STATUS      0x14
  28 #define DP83865_INT_MASK        0x15
  29 #define DP83865_INT_CLEAR       0x17
  30
  31 #define DP83865_INT_REMOTE_FAULT 0x0008
  32 #define DP83865_INT_ANE_COMPLETED 0x0010
  33 #define DP83865_INT_LINK_CHANGE 0xe000
  34 #define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \
  35                                 DP83865_INT_ANE_COMPLETED | \
  36                                 DP83865_INT_LINK_CHANGE)
  37
  38 /* Advanced proprietary configuration */
  39 #define NS_EXP_MEM_CTL  0x16
  40 #define NS_EXP_MEM_DATA 0x1d
  41 #define NS_EXP_MEM_ADD  0x1e
  42
  43 #define LED_CTRL_REG 0x13
  44 #define AN_FALLBACK_AN 0x0001
  45 #define AN_FALLBACK_CRC 0x0002
  46 #define AN_FALLBACK_IE 0x0004
  47 #define ALL_FALLBACK_ON (AN_FALLBACK_AN |  AN_FALLBACK_CRC | AN_FALLBACK_IE)
  48
  49 enum hdx_loopback {
  50         hdx_loopback_on = 0,
  51         hdx_loopback_off = 1,
  52 };
  53
  54 static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
  55 {
  56         phy_write(phydev, NS_EXP_MEM_ADD, reg);
  57         return phy_read(phydev, NS_EXP_MEM_DATA);
  58 }
  59
  60 static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
  61 {
  62         phy_write(phydev, NS_EXP_MEM_ADD, reg);
  63         phy_write(phydev, NS_EXP_MEM_DATA, data);
  64 }
  65
  66 static int ns_ack_interrupt(struct phy_device *phydev)
  67 {
  68         int ret = phy_read(phydev, DP83865_INT_STATUS);
  69         if (ret < 0)
  70                 return ret;
  71
  72         /* Clear the interrupt status bit by writing a “1”
  73          * to the corresponding bit in INT_CLEAR (2:0 are reserved) */
  74         ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
  75
  76         return ret;
  77 }
  78
  79 static irqreturn_t ns_handle_interrupt(struct phy_device *phydev)
  80 {
  81         int irq_status;
  82
  83         irq_status = phy_read(phydev, DP83865_INT_STATUS);
  84         if (irq_status < 0) {
  85                 phy_error(phydev);
  86                 return IRQ_NONE;
  87         }
  88
  89         if (!(irq_status & DP83865_INT_MASK_DEFAULT))
  90                 return IRQ_NONE;
  91
  92         /* clear the interrupt */
  93         phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7);
  94
  95         phy_trigger_machine(phydev);
  96
  97         return IRQ_HANDLED;
  98 }
  99
 100 static int ns_config_intr(struct phy_device *phydev)
 101 {
 102         int err;
 103
 104         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 105                 err = ns_ack_interrupt(phydev);
 106                 if (err)
 107                         return err;
 108
 109                 err = phy_write(phydev, DP83865_INT_MASK,
 110                                 DP83865_INT_MASK_DEFAULT);
 111         } else {
 112                 err = phy_write(phydev, DP83865_INT_MASK, 0);
 113                 if (err)
 114                         return err;
 115
 116                 err = ns_ack_interrupt(phydev);
 117         }
 118
 119         return err;
 120 }
 121
 122 static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
 123 {
 124         int bmcr = phy_read(phydev, MII_BMCR);
 125
 126         phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
 127
 128         /* Enable 8 bit expended memory read/write (no auto increment) */
 129         phy_write(phydev, NS_EXP_MEM_CTL, 0);
 130         phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
 131         phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
 132         phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
 133         phy_write(phydev, LED_CTRL_REG, mode);
 134 }
 135
 136 static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
 137 {
 138         u16 lb_dis = BIT(1);
 139
 140         if (disable)
 141                 ns_exp_write(phydev, 0x1c0,
 142                              ns_exp_read(phydev, 0x1c0) | lb_dis);
 143         else
 144                 ns_exp_write(phydev, 0x1c0,
 145                              ns_exp_read(phydev, 0x1c0) & ~lb_dis);
 146
 147         pr_debug("10BASE-T HDX loopback %s\n",
 148                  (ns_exp_read(phydev, 0x1c0) & lb_dis) ? "off" : "on");
 149 }
 150
 151 static int ns_config_init(struct phy_device *phydev)
 152 {
 153         ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
 154         /* In the latest MAC or switches design, the 10 Mbps loopback
 155            is desired to be turned off. */
 156         ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
 157         return ns_ack_interrupt(phydev);
 158 }
 159
 160 static struct phy_driver dp83865_driver[] = { {
 161         .phy_id = DP83865_PHY_ID,
 162         .phy_id_mask = 0xfffffff0,
 163         .name = "NatSemi DP83865",
 164         /* PHY_GBIT_FEATURES */
 165         .config_init = ns_config_init,
 166         .config_intr = ns_config_intr,
 167         .handle_interrupt = ns_handle_interrupt,
 168 } };
 169
 170 module_phy_driver(dp83865_driver);
 171
 172 MODULE_DESCRIPTION("NatSemi PHY driver");
 173 MODULE_AUTHOR("Stuart Menefy");
 174 MODULE_LICENSE("GPL");
 175
 176 static struct mdio_device_id __maybe_unused ns_tbl[] = {
 177         { DP83865_PHY_ID, 0xfffffff0 },
 178         { }
 179 };
 180
 181 MODULE_DEVICE_TABLE(mdio, ns_tbl);