drivers/net/phy/nxp-tja11xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* NXP TJA1100 BroadRReach PHY driver
   3  *
   4  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
   5  */
   6 #include <linux/delay.h>
   7 #include <linux/ethtool.h>
   8 #include <linux/ethtool_netlink.h>
   9 #include <linux/kernel.h>
  10 #include <linux/mdio.h>
  11 #include <linux/mii.h>
  12 #include <linux/module.h>
  13 #include <linux/phy.h>
  14 #include <linux/hwmon.h>
  15 #include <linux/bitfield.h>
  16 #include <linux/of_mdio.h>
  17 #include <linux/of_irq.h>
  18
  19 #define PHY_ID_MASK                     0xfffffff0
  20 #define PHY_ID_TJA1100                  0x0180dc40
  21 #define PHY_ID_TJA1101                  0x0180dd00
  22 #define PHY_ID_TJA1102                  0x0180dc80
  23
  24 #define MII_ECTRL                       17
  25 #define MII_ECTRL_LINK_CONTROL          BIT(15)
  26 #define MII_ECTRL_POWER_MODE_MASK       GENMASK(14, 11)
  27 #define MII_ECTRL_POWER_MODE_NO_CHANGE  (0x0 << 11)
  28 #define MII_ECTRL_POWER_MODE_NORMAL     (0x3 << 11)
  29 #define MII_ECTRL_POWER_MODE_STANDBY    (0xc << 11)
  30 #define MII_ECTRL_CABLE_TEST            BIT(5)
  31 #define MII_ECTRL_CONFIG_EN             BIT(2)
  32 #define MII_ECTRL_WAKE_REQUEST          BIT(0)
  33
  34 #define MII_CFG1                        18
  35 #define MII_CFG1_MASTER_SLAVE           BIT(15)
  36 #define MII_CFG1_AUTO_OP                BIT(14)
  37 #define MII_CFG1_SLEEP_CONFIRM          BIT(6)
  38 #define MII_CFG1_LED_MODE_MASK          GENMASK(5, 4)
  39 #define MII_CFG1_LED_MODE_LINKUP        0
  40 #define MII_CFG1_LED_ENABLE             BIT(3)
  41
  42 #define MII_CFG2                        19
  43 #define MII_CFG2_SLEEP_REQUEST_TO       GENMASK(1, 0)
  44 #define MII_CFG2_SLEEP_REQUEST_TO_16MS  0x3
  45
  46 #define MII_INTSRC                      21
  47 #define MII_INTSRC_LINK_FAIL            BIT(10)
  48 #define MII_INTSRC_LINK_UP              BIT(9)
  49 #define MII_INTSRC_MASK                 (MII_INTSRC_LINK_FAIL | MII_INTSRC_LINK_UP)
  50 #define MII_INTSRC_TEMP_ERR             BIT(1)
  51 #define MII_INTSRC_UV_ERR               BIT(3)
  52
  53 #define MII_INTEN                       22
  54 #define MII_INTEN_LINK_FAIL             BIT(10)
  55 #define MII_INTEN_LINK_UP               BIT(9)
  56
  57 #define MII_COMMSTAT                    23
  58 #define MII_COMMSTAT_LINK_UP            BIT(15)
  59 #define MII_COMMSTAT_SQI_STATE          GENMASK(7, 5)
  60 #define MII_COMMSTAT_SQI_MAX            7
  61
  62 #define MII_GENSTAT                     24
  63 #define MII_GENSTAT_PLL_LOCKED          BIT(14)
  64
  65 #define MII_EXTSTAT                     25
  66 #define MII_EXTSTAT_SHORT_DETECT        BIT(8)
  67 #define MII_EXTSTAT_OPEN_DETECT         BIT(7)
  68 #define MII_EXTSTAT_POLARITY_DETECT     BIT(6)
  69
  70 #define MII_COMMCFG                     27
  71 #define MII_COMMCFG_AUTO_OP             BIT(15)
  72
  73 struct tja11xx_priv {
  74         char            *hwmon_name;
  75         struct device   *hwmon_dev;
  76         struct phy_device *phydev;
  77         struct work_struct phy_register_work;
  78 };
  79
  80 struct tja11xx_phy_stats {
  81         const char      *string;
  82         u8              reg;
  83         u8              off;
  84         u16             mask;
  85 };
  86
  87 static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
  88         { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
  89         { "phy_polarity_detect", 25, 6, BIT(6) },
  90         { "phy_open_detect", 25, 7, BIT(7) },
  91         { "phy_short_detect", 25, 8, BIT(8) },
  92         { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
  93         { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
  94 };
  95
  96 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
  97 {
  98         int val;
  99
 100         return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set,
 101                                      150, 30000, false);
 102 }
 103
 104 static int phy_modify_check(struct phy_device *phydev, u8 reg,
 105                             u16 mask, u16 set)
 106 {
 107         int ret;
 108
 109         ret = phy_modify(phydev, reg, mask, set);
 110         if (ret)
 111                 return ret;
 112
 113         return tja11xx_check(phydev, reg, mask, set);
 114 }
 115
 116 static int tja11xx_enable_reg_write(struct phy_device *phydev)
 117 {
 118         return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
 119 }
 120
 121 static int tja11xx_enable_link_control(struct phy_device *phydev)
 122 {
 123         return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
 124 }
 125
 126 static int tja11xx_disable_link_control(struct phy_device *phydev)
 127 {
 128         return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
 129 }
 130
 131 static int tja11xx_wakeup(struct phy_device *phydev)
 132 {
 133         int ret;
 134
 135         ret = phy_read(phydev, MII_ECTRL);
 136         if (ret < 0)
 137                 return ret;
 138
 139         switch (ret & MII_ECTRL_POWER_MODE_MASK) {
 140         case MII_ECTRL_POWER_MODE_NO_CHANGE:
 141                 break;
 142         case MII_ECTRL_POWER_MODE_NORMAL:
 143                 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
 144                 if (ret)
 145                         return ret;
 146
 147                 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
 148                 if (ret)
 149                         return ret;
 150                 break;
 151         case MII_ECTRL_POWER_MODE_STANDBY:
 152                 ret = phy_modify_check(phydev, MII_ECTRL,
 153                                        MII_ECTRL_POWER_MODE_MASK,
 154                                        MII_ECTRL_POWER_MODE_STANDBY);
 155                 if (ret)
 156                         return ret;
 157
 158                 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
 159                                  MII_ECTRL_POWER_MODE_NORMAL);
 160                 if (ret)
 161                         return ret;
 162
 163                 ret = phy_modify_check(phydev, MII_GENSTAT,
 164                                        MII_GENSTAT_PLL_LOCKED,
 165                                        MII_GENSTAT_PLL_LOCKED);
 166                 if (ret)
 167                         return ret;
 168
 169                 return tja11xx_enable_link_control(phydev);
 170         default:
 171                 break;
 172         }
 173
 174         return 0;
 175 }
 176
 177 static int tja11xx_soft_reset(struct phy_device *phydev)
 178 {
 179         int ret;
 180
 181         ret = tja11xx_enable_reg_write(phydev);
 182         if (ret)
 183                 return ret;
 184
 185         return genphy_soft_reset(phydev);
 186 }
 187
 188 static int tja11xx_config_aneg_cable_test(struct phy_device *phydev)
 189 {
 190         bool finished = false;
 191         int ret;
 192
 193         if (phydev->link)
 194                 return 0;
 195
 196         if (!phydev->drv->cable_test_start ||
 197             !phydev->drv->cable_test_get_status)
 198                 return 0;
 199
 200         ret = ethnl_cable_test_alloc(phydev, ETHTOOL_MSG_CABLE_TEST_NTF);
 201         if (ret)
 202                 return ret;
 203
 204         ret = phydev->drv->cable_test_start(phydev);
 205         if (ret)
 206                 return ret;
 207
 208         /* According to the documentation this test takes 100 usec */
 209         usleep_range(100, 200);
 210
 211         ret = phydev->drv->cable_test_get_status(phydev, &finished);
 212         if (ret)
 213                 return ret;
 214
 215         if (finished)
 216                 ethnl_cable_test_finished(phydev);
 217
 218         return 0;
 219 }
 220
 221 static int tja11xx_config_aneg(struct phy_device *phydev)
 222 {
 223         int ret, changed = 0;
 224         u16 ctl = 0;
 225
 226         switch (phydev->master_slave_set) {
 227         case MASTER_SLAVE_CFG_MASTER_FORCE:
 228                 ctl |= MII_CFG1_MASTER_SLAVE;
 229                 break;
 230         case MASTER_SLAVE_CFG_SLAVE_FORCE:
 231                 break;
 232         case MASTER_SLAVE_CFG_UNKNOWN:
 233         case MASTER_SLAVE_CFG_UNSUPPORTED:
 234                 goto do_test;
 235         default:
 236                 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
 237                 return -ENOTSUPP;
 238         }
 239
 240         changed = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl);
 241         if (changed < 0)
 242                 return changed;
 243
 244 do_test:
 245         ret = tja11xx_config_aneg_cable_test(phydev);
 246         if (ret)
 247                 return ret;
 248
 249         return __genphy_config_aneg(phydev, changed);
 250 }
 251
 252 static int tja11xx_config_init(struct phy_device *phydev)
 253 {
 254         int ret;
 255
 256         ret = tja11xx_enable_reg_write(phydev);
 257         if (ret)
 258                 return ret;
 259
 260         phydev->autoneg = AUTONEG_DISABLE;
 261         phydev->speed = SPEED_100;
 262         phydev->duplex = DUPLEX_FULL;
 263
 264         switch (phydev->phy_id & PHY_ID_MASK) {
 265         case PHY_ID_TJA1100:
 266                 ret = phy_modify(phydev, MII_CFG1,
 267                                  MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
 268                                  MII_CFG1_LED_ENABLE,
 269                                  MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
 270                                  MII_CFG1_LED_ENABLE);
 271                 if (ret)
 272                         return ret;
 273                 break;
 274         case PHY_ID_TJA1101:
 275         case PHY_ID_TJA1102:
 276                 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
 277                 if (ret)
 278                         return ret;
 279                 break;
 280         default:
 281                 return -EINVAL;
 282         }
 283
 284         ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
 285         if (ret)
 286                 return ret;
 287
 288         ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
 289                          MII_CFG2_SLEEP_REQUEST_TO_16MS);
 290         if (ret)
 291                 return ret;
 292
 293         ret = tja11xx_wakeup(phydev);
 294         if (ret < 0)
 295                 return ret;
 296
 297         /* ACK interrupts by reading the status register */
 298         ret = phy_read(phydev, MII_INTSRC);
 299         if (ret < 0)
 300                 return ret;
 301
 302         return 0;
 303 }
 304
 305 static int tja11xx_read_status(struct phy_device *phydev)
 306 {
 307         int ret;
 308
 309         phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
 310         phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
 311
 312         ret = genphy_update_link(phydev);
 313         if (ret)
 314                 return ret;
 315
 316         ret = phy_read(phydev, MII_CFG1);
 317         if (ret < 0)
 318                 return ret;
 319
 320         if (ret & MII_CFG1_MASTER_SLAVE)
 321                 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
 322         else
 323                 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
 324
 325         if (phydev->link) {
 326                 ret = phy_read(phydev, MII_COMMSTAT);
 327                 if (ret < 0)
 328                         return ret;
 329
 330                 if (!(ret & MII_COMMSTAT_LINK_UP))
 331                         phydev->link = 0;
 332         }
 333
 334         return 0;
 335 }
 336
 337 static int tja11xx_get_sqi(struct phy_device *phydev)
 338 {
 339         int ret;
 340
 341         ret = phy_read(phydev, MII_COMMSTAT);
 342         if (ret < 0)
 343                 return ret;
 344
 345         return FIELD_GET(MII_COMMSTAT_SQI_STATE, ret);
 346 }
 347
 348 static int tja11xx_get_sqi_max(struct phy_device *phydev)
 349 {
 350         return MII_COMMSTAT_SQI_MAX;
 351 }
 352
 353 static int tja11xx_get_sset_count(struct phy_device *phydev)
 354 {
 355         return ARRAY_SIZE(tja11xx_hw_stats);
 356 }
 357
 358 static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
 359 {
 360         int i;
 361
 362         for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
 363                 strncpy(data + i * ETH_GSTRING_LEN,
 364                         tja11xx_hw_stats[i].string, ETH_GSTRING_LEN);
 365         }
 366 }
 367
 368 static void tja11xx_get_stats(struct phy_device *phydev,
 369                               struct ethtool_stats *stats, u64 *data)
 370 {
 371         int i, ret;
 372
 373         for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
 374                 ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
 375                 if (ret < 0)
 376                         data[i] = U64_MAX;
 377                 else {
 378                         data[i] = ret & tja11xx_hw_stats[i].mask;
 379                         data[i] >>= tja11xx_hw_stats[i].off;
 380                 }
 381         }
 382 }
 383
 384 static int tja11xx_hwmon_read(struct device *dev,
 385                               enum hwmon_sensor_types type,
 386                               u32 attr, int channel, long *value)
 387 {
 388         struct phy_device *phydev = dev_get_drvdata(dev);
 389         int ret;
 390
 391         if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
 392                 ret = phy_read(phydev, MII_INTSRC);
 393                 if (ret < 0)
 394                         return ret;
 395
 396                 *value = !!(ret & MII_INTSRC_TEMP_ERR);
 397                 return 0;
 398         }
 399
 400         if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
 401                 ret = phy_read(phydev, MII_INTSRC);
 402                 if (ret < 0)
 403                         return ret;
 404
 405                 *value = !!(ret & MII_INTSRC_UV_ERR);
 406                 return 0;
 407         }
 408
 409         return -EOPNOTSUPP;
 410 }
 411
 412 static umode_t tja11xx_hwmon_is_visible(const void *data,
 413                                         enum hwmon_sensor_types type,
 414                                         u32 attr, int channel)
 415 {
 416         if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
 417                 return 0444;
 418
 419         if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
 420                 return 0444;
 421
 422         return 0;
 423 }
 424
 425 static const struct hwmon_channel_info *tja11xx_hwmon_info[] = {
 426         HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
 427         HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
 428         NULL
 429 };
 430
 431 static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
 432         .is_visible     = tja11xx_hwmon_is_visible,
 433         .read           = tja11xx_hwmon_read,
 434 };
 435
 436 static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
 437         .ops            = &tja11xx_hwmon_hwmon_ops,
 438         .info           = tja11xx_hwmon_info,
 439 };
 440
 441 static int tja11xx_hwmon_register(struct phy_device *phydev,
 442                                   struct tja11xx_priv *priv)
 443 {
 444         struct device *dev = &phydev->mdio.dev;
 445         int i;
 446
 447         priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
 448         if (!priv->hwmon_name)
 449                 return -ENOMEM;
 450
 451         for (i = 0; priv->hwmon_name[i]; i++)
 452                 if (hwmon_is_bad_char(priv->hwmon_name[i]))
 453                         priv->hwmon_name[i] = '_';
 454
 455         priv->hwmon_dev =
 456                 devm_hwmon_device_register_with_info(dev, priv->hwmon_name,
 457                                                      phydev,
 458                                                      &tja11xx_hwmon_chip_info,
 459                                                      NULL);
 460
 461         return PTR_ERR_OR_ZERO(priv->hwmon_dev);
 462 }
 463
 464 static int tja11xx_probe(struct phy_device *phydev)
 465 {
 466         struct device *dev = &phydev->mdio.dev;
 467         struct tja11xx_priv *priv;
 468
 469         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 470         if (!priv)
 471                 return -ENOMEM;
 472
 473         priv->phydev = phydev;
 474
 475         return tja11xx_hwmon_register(phydev, priv);
 476 }
 477
 478 static void tja1102_p1_register(struct work_struct *work)
 479 {
 480         struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv,
 481                                                  phy_register_work);
 482         struct phy_device *phydev_phy0 = priv->phydev;
 483         struct mii_bus *bus = phydev_phy0->mdio.bus;
 484         struct device *dev = &phydev_phy0->mdio.dev;
 485         struct device_node *np = dev->of_node;
 486         struct device_node *child;
 487         int ret;
 488
 489         for_each_available_child_of_node(np, child) {
 490                 struct phy_device *phy;
 491                 int addr;
 492
 493                 addr = of_mdio_parse_addr(dev, child);
 494                 if (addr < 0) {
 495                         dev_err(dev, "Can't parse addr\n");
 496                         continue;
 497                 } else if (addr != phydev_phy0->mdio.addr + 1) {
 498                         /* Currently we care only about double PHY chip TJA1102.
 499                          * If some day NXP will decide to bring chips with more
 500                          * PHYs, this logic should be reworked.
 501                          */
 502                         dev_err(dev, "Unexpected address. Should be: %i\n",
 503                                 phydev_phy0->mdio.addr + 1);
 504                         continue;
 505                 }
 506
 507                 if (mdiobus_is_registered_device(bus, addr)) {
 508                         dev_err(dev, "device is already registered\n");
 509                         continue;
 510                 }
 511
 512                 /* Real PHY ID of Port 1 is 0 */
 513                 phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL);
 514                 if (IS_ERR(phy)) {
 515                         dev_err(dev, "Can't create PHY device for Port 1: %i\n",
 516                                 addr);
 517                         continue;
 518                 }
 519
 520                 /* Overwrite parent device. phy_device_create() set parent to
 521                  * the mii_bus->dev, which is not correct in case.
 522                  */
 523                 phy->mdio.dev.parent = dev;
 524
 525                 ret = of_mdiobus_phy_device_register(bus, phy, child, addr);
 526                 if (ret) {
 527                         /* All resources needed for Port 1 should be already
 528                          * available for Port 0. Both ports use the same
 529                          * interrupt line, so -EPROBE_DEFER would make no sense
 530                          * here.
 531                          */
 532                         dev_err(dev, "Can't register Port 1. Unexpected error: %i\n",
 533                                 ret);
 534                         phy_device_free(phy);
 535                 }
 536         }
 537 }
 538
 539 static int tja1102_p0_probe(struct phy_device *phydev)
 540 {
 541         struct device *dev = &phydev->mdio.dev;
 542         struct tja11xx_priv *priv;
 543         int ret;
 544
 545         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 546         if (!priv)
 547                 return -ENOMEM;
 548
 549         priv->phydev = phydev;
 550         INIT_WORK(&priv->phy_register_work, tja1102_p1_register);
 551
 552         ret = tja11xx_hwmon_register(phydev, priv);
 553         if (ret)
 554                 return ret;
 555
 556         schedule_work(&priv->phy_register_work);
 557
 558         return 0;
 559 }
 560
 561 static int tja1102_match_phy_device(struct phy_device *phydev, bool port0)
 562 {
 563         int ret;
 564
 565         if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102)
 566                 return 0;
 567
 568         ret = phy_read(phydev, MII_PHYSID2);
 569         if (ret < 0)
 570                 return ret;
 571
 572         /* TJA1102 Port 1 has phyid 0 and doesn't support temperature
 573          * and undervoltage alarms.
 574          */
 575         if (port0)
 576                 return ret ? 1 : 0;
 577
 578         return !ret;
 579 }
 580
 581 static int tja1102_p0_match_phy_device(struct phy_device *phydev)
 582 {
 583         return tja1102_match_phy_device(phydev, true);
 584 }
 585
 586 static int tja1102_p1_match_phy_device(struct phy_device *phydev)
 587 {
 588         return tja1102_match_phy_device(phydev, false);
 589 }
 590
 591 static int tja11xx_ack_interrupt(struct phy_device *phydev)
 592 {
 593         int ret;
 594
 595         ret = phy_read(phydev, MII_INTSRC);
 596
 597         return (ret < 0) ? ret : 0;
 598 }
 599
 600 static int tja11xx_config_intr(struct phy_device *phydev)
 601 {
 602         int value = 0;
 603         int err;
 604
 605         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 606                 err = tja11xx_ack_interrupt(phydev);
 607                 if (err)
 608                         return err;
 609
 610                 value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP;
 611                 err = phy_write(phydev, MII_INTEN, value);
 612         } else {
 613                 err = phy_write(phydev, MII_INTEN, value);
 614                 if (err)
 615                         return err;
 616
 617                 err = tja11xx_ack_interrupt(phydev);
 618         }
 619
 620         return err;
 621 }
 622
 623 static irqreturn_t tja11xx_handle_interrupt(struct phy_device *phydev)
 624 {
 625         int irq_status;
 626
 627         irq_status = phy_read(phydev, MII_INTSRC);
 628         if (irq_status < 0) {
 629                 phy_error(phydev);
 630                 return IRQ_NONE;
 631         }
 632
 633         if (!(irq_status & MII_INTSRC_MASK))
 634                 return IRQ_NONE;
 635
 636         phy_trigger_machine(phydev);
 637
 638         return IRQ_HANDLED;
 639 }
 640
 641 static int tja11xx_cable_test_start(struct phy_device *phydev)
 642 {
 643         int ret;
 644
 645         ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
 646         if (ret)
 647                 return ret;
 648
 649         ret = tja11xx_wakeup(phydev);
 650         if (ret < 0)
 651                 return ret;
 652
 653         ret = tja11xx_disable_link_control(phydev);
 654         if (ret < 0)
 655                 return ret;
 656
 657         return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST);
 658 }
 659
 660 /*
 661  * | BI_DA+           | BI_DA-                 | Result
 662  * | open             | open                   | open
 663  * | + short to -     | - short to +           | short
 664  * | short to Vdd     | open                   | open
 665  * | open             | shot to Vdd            | open
 666  * | short to Vdd     | short to Vdd           | short
 667  * | shot to GND      | open                   | open
 668  * | open             | shot to GND            | open
 669  * | short to GND     | shot to GND            | short
 670  * | connected to active link partner (master) | shot and open
 671  */
 672 static int tja11xx_cable_test_report_trans(u32 result)
 673 {
 674         u32 mask = MII_EXTSTAT_SHORT_DETECT | MII_EXTSTAT_OPEN_DETECT;
 675
 676         if ((result & mask) == mask) {
 677                 /* connected to active link partner (master) */
 678                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
 679         } else if ((result & mask) == 0) {
 680                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
 681         } else if (result & MII_EXTSTAT_SHORT_DETECT) {
 682                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
 683         } else if (result & MII_EXTSTAT_OPEN_DETECT) {
 684                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
 685         } else {
 686                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
 687         }
 688 }
 689
 690 static int tja11xx_cable_test_report(struct phy_device *phydev)
 691 {
 692         int ret;
 693
 694         ret = phy_read(phydev, MII_EXTSTAT);
 695         if (ret < 0)
 696                 return ret;
 697
 698         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
 699                                 tja11xx_cable_test_report_trans(ret));
 700
 701         return 0;
 702 }
 703
 704 static int tja11xx_cable_test_get_status(struct phy_device *phydev,
 705                                          bool *finished)
 706 {
 707         int ret;
 708
 709         *finished = false;
 710
 711         ret = phy_read(phydev, MII_ECTRL);
 712         if (ret < 0)
 713                 return ret;
 714
 715         if (!(ret & MII_ECTRL_CABLE_TEST)) {
 716                 *finished = true;
 717
 718                 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
 719                 if (ret)
 720                         return ret;
 721
 722                 return tja11xx_cable_test_report(phydev);
 723         }
 724
 725         return 0;
 726 }
 727
 728 static struct phy_driver tja11xx_driver[] = {
 729         {
 730                 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
 731                 .name           = "NXP TJA1100",
 732                 .features       = PHY_BASIC_T1_FEATURES,
 733                 .probe          = tja11xx_probe,
 734                 .soft_reset     = tja11xx_soft_reset,
 735                 .config_aneg    = tja11xx_config_aneg,
 736                 .config_init    = tja11xx_config_init,
 737                 .read_status    = tja11xx_read_status,
 738                 .get_sqi        = tja11xx_get_sqi,
 739                 .get_sqi_max    = tja11xx_get_sqi_max,
 740                 .suspend        = genphy_suspend,
 741                 .resume         = genphy_resume,
 742                 .set_loopback   = genphy_loopback,
 743                 /* Statistics */
 744                 .get_sset_count = tja11xx_get_sset_count,
 745                 .get_strings    = tja11xx_get_strings,
 746                 .get_stats      = tja11xx_get_stats,
 747         }, {
 748                 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
 749                 .name           = "NXP TJA1101",
 750                 .features       = PHY_BASIC_T1_FEATURES,
 751                 .probe          = tja11xx_probe,
 752                 .soft_reset     = tja11xx_soft_reset,
 753                 .config_aneg    = tja11xx_config_aneg,
 754                 .config_init    = tja11xx_config_init,
 755                 .read_status    = tja11xx_read_status,
 756                 .get_sqi        = tja11xx_get_sqi,
 757                 .get_sqi_max    = tja11xx_get_sqi_max,
 758                 .suspend        = genphy_suspend,
 759                 .resume         = genphy_resume,
 760                 .set_loopback   = genphy_loopback,
 761                 /* Statistics */
 762                 .get_sset_count = tja11xx_get_sset_count,
 763                 .get_strings    = tja11xx_get_strings,
 764                 .get_stats      = tja11xx_get_stats,
 765         }, {
 766                 .name           = "NXP TJA1102 Port 0",
 767                 .features       = PHY_BASIC_T1_FEATURES,
 768                 .flags          = PHY_POLL_CABLE_TEST,
 769                 .probe          = tja1102_p0_probe,
 770                 .soft_reset     = tja11xx_soft_reset,
 771                 .config_aneg    = tja11xx_config_aneg,
 772                 .config_init    = tja11xx_config_init,
 773                 .read_status    = tja11xx_read_status,
 774                 .get_sqi        = tja11xx_get_sqi,
 775                 .get_sqi_max    = tja11xx_get_sqi_max,
 776                 .match_phy_device = tja1102_p0_match_phy_device,
 777                 .suspend        = genphy_suspend,
 778                 .resume         = genphy_resume,
 779                 .set_loopback   = genphy_loopback,
 780                 /* Statistics */
 781                 .get_sset_count = tja11xx_get_sset_count,
 782                 .get_strings    = tja11xx_get_strings,
 783                 .get_stats      = tja11xx_get_stats,
 784                 .config_intr    = tja11xx_config_intr,
 785                 .handle_interrupt = tja11xx_handle_interrupt,
 786                 .cable_test_start = tja11xx_cable_test_start,
 787                 .cable_test_get_status = tja11xx_cable_test_get_status,
 788         }, {
 789                 .name           = "NXP TJA1102 Port 1",
 790                 .features       = PHY_BASIC_T1_FEATURES,
 791                 .flags          = PHY_POLL_CABLE_TEST,
 792                 /* currently no probe for Port 1 is need */
 793                 .soft_reset     = tja11xx_soft_reset,
 794                 .config_aneg    = tja11xx_config_aneg,
 795                 .config_init    = tja11xx_config_init,
 796                 .read_status    = tja11xx_read_status,
 797                 .get_sqi        = tja11xx_get_sqi,
 798                 .get_sqi_max    = tja11xx_get_sqi_max,
 799                 .match_phy_device = tja1102_p1_match_phy_device,
 800                 .suspend        = genphy_suspend,
 801                 .resume         = genphy_resume,
 802                 .set_loopback   = genphy_loopback,
 803                 /* Statistics */
 804                 .get_sset_count = tja11xx_get_sset_count,
 805                 .get_strings    = tja11xx_get_strings,
 806                 .get_stats      = tja11xx_get_stats,
 807                 .config_intr    = tja11xx_config_intr,
 808                 .handle_interrupt = tja11xx_handle_interrupt,
 809                 .cable_test_start = tja11xx_cable_test_start,
 810                 .cable_test_get_status = tja11xx_cable_test_get_status,
 811         }
 812 };
 813
 814 module_phy_driver(tja11xx_driver);
 815
 816 static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
 817         { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
 818         { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
 819         { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) },
 820         { }
 821 };
 822
 823 MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
 824
 825 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
 826 MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
 827 MODULE_LICENSE("GPL");