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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / net / wan / pc300too.c
blob001fd378d417aef46e02460a3e5b8f4079b60c50
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Cyclades PC300 synchronous serial card driver for Linux
4 *
5 * Copyright (C) 2000-2008 Krzysztof Halasa <khc@pm.waw.pl>
6 *
7 * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>.
8 *
9 * Sources of information:
10 * Hitachi HD64572 SCA-II User's Manual
11 * Original Cyclades PC300 Linux driver
12 *
13 * This driver currently supports only PC300/RSV (V.24/V.35) and
14 * PC300/X21 cards.
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/slab.h>
22 #include <linux/sched.h>
23 #include <linux/types.h>
24 #include <linux/fcntl.h>
25 #include <linux/in.h>
26 #include <linux/string.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/hdlc.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
35 #include <asm/io.h>
36
37 #include "hd64572.h"
38
39 #undef DEBUG_PKT
40 #define DEBUG_RINGS
41
42 #define PC300_PLX_SIZE 0x80 /* PLX control window size (128 B) */
43 #define PC300_SCA_SIZE 0x400 /* SCA window size (1 KB) */
44 #define MAX_TX_BUFFERS 10
45
46 static int pci_clock_freq = 33000000;
47 static int use_crystal_clock = 0;
48 static unsigned int CLOCK_BASE;
49
50 /* Masks to access the init_ctrl PLX register */
51 #define PC300_CLKSEL_MASK (0x00000004UL)
52 #define PC300_CHMEDIA_MASK(port) (0x00000020UL << ((port) * 3))
53 #define PC300_CTYPE_MASK (0x00000800UL)
54
55
56 enum { PC300_RSV = 1, PC300_X21, PC300_TE }; /* card types */
57
58 /*
59 * PLX PCI9050-1 local configuration and shared runtime registers.
60 * This structure can be used to access 9050 registers (memory mapped).
61 */
62 typedef struct {
63 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
64 u32 loc_rom_range; /* 10h : Local ROM Range */
65 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
66 u32 loc_rom_base; /* 24h : Local ROM Base */
67 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
68 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
69 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
70 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
71 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
72 }plx9050;
73
74
75
76 typedef struct port_s {
77 struct napi_struct napi;
78 struct net_device *netdev;
79 struct card_s *card;
80 spinlock_t lock; /* TX lock */
81 sync_serial_settings settings;
82 int rxpart; /* partial frame received, next frame invalid*/
83 unsigned short encoding;
84 unsigned short parity;
85 unsigned int iface;
86 u16 rxin; /* rx ring buffer 'in' pointer */
87 u16 txin; /* tx ring buffer 'in' and 'last' pointers */
88 u16 txlast;
89 u8 rxs, txs, tmc; /* SCA registers */
90 u8 chan; /* physical port # - 0 or 1 */
91 }port_t;
92
93
94
95 typedef struct card_s {
96 int type; /* RSV, X21, etc. */
97 int n_ports; /* 1 or 2 ports */
98 u8 __iomem *rambase; /* buffer memory base (virtual) */
99 u8 __iomem *scabase; /* SCA memory base (virtual) */
100 plx9050 __iomem *plxbase; /* PLX registers memory base (virtual) */
101 u32 init_ctrl_value; /* Saved value - 9050 bug workaround */
102 u16 rx_ring_buffers; /* number of buffers in a ring */
103 u16 tx_ring_buffers;
104 u16 buff_offset; /* offset of first buffer of first channel */
105 u8 irq; /* interrupt request level */
106
107 port_t ports[2];
108 }card_t;
109
110
111 #define get_port(card, port) ((port) < (card)->n_ports ? \
112 (&(card)->ports[port]) : (NULL))
113
114 #include "hd64572.c"
115
116
117 static void pc300_set_iface(port_t *port)
118 {
119 card_t *card = port->card;
120 u32 __iomem * init_ctrl = &card->plxbase->init_ctrl;
121 u16 msci = get_msci(port);
122 u8 rxs = port->rxs & CLK_BRG_MASK;
123 u8 txs = port->txs & CLK_BRG_MASK;
124
125 sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
126 port->card);
127 switch(port->settings.clock_type) {
128 case CLOCK_INT:
129 rxs |= CLK_BRG; /* BRG output */
130 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
131 break;
132
133 case CLOCK_TXINT:
134 rxs |= CLK_LINE; /* RXC input */
135 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
136 break;
137
138 case CLOCK_TXFROMRX:
139 rxs |= CLK_LINE; /* RXC input */
140 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
141 break;
142
143 default: /* EXTernal clock */
144 rxs |= CLK_LINE; /* RXC input */
145 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
146 break;
147 }
148
149 port->rxs = rxs;
150 port->txs = txs;
151 sca_out(rxs, msci + RXS, card);
152 sca_out(txs, msci + TXS, card);
153 sca_set_port(port);
154
155 if (port->card->type == PC300_RSV) {
156 if (port->iface == IF_IFACE_V35)
157 writel(card->init_ctrl_value |
158 PC300_CHMEDIA_MASK(port->chan), init_ctrl);
159 else
160 writel(card->init_ctrl_value &
161 ~PC300_CHMEDIA_MASK(port->chan), init_ctrl);
162 }
163 }
164
165
166
167 static int pc300_open(struct net_device *dev)
168 {
169 port_t *port = dev_to_port(dev);
170
171 int result = hdlc_open(dev);
172 if (result)
173 return result;
174
175 sca_open(dev);
176 pc300_set_iface(port);
177 return 0;
178 }
179
180
181
182 static int pc300_close(struct net_device *dev)
183 {
184 sca_close(dev);
185 hdlc_close(dev);
186 return 0;
187 }
188
189
190
191 static int pc300_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
192 {
193 const size_t size = sizeof(sync_serial_settings);
194 sync_serial_settings new_line;
195 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
196 int new_type;
197 port_t *port = dev_to_port(dev);
198
199 #ifdef DEBUG_RINGS
200 if (cmd == SIOCDEVPRIVATE) {
201 sca_dump_rings(dev);
202 return 0;
203 }
204 #endif
205 if (cmd != SIOCWANDEV)
206 return hdlc_ioctl(dev, ifr, cmd);
207
208 if (ifr->ifr_settings.type == IF_GET_IFACE) {
209 ifr->ifr_settings.type = port->iface;
210 if (ifr->ifr_settings.size < size) {
211 ifr->ifr_settings.size = size; /* data size wanted */
212 return -ENOBUFS;
213 }
214 if (copy_to_user(line, &port->settings, size))
215 return -EFAULT;
216 return 0;
217
218 }
219
220 if (port->card->type == PC300_X21 &&
221 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
222 ifr->ifr_settings.type == IF_IFACE_X21))
223 new_type = IF_IFACE_X21;
224
225 else if (port->card->type == PC300_RSV &&
226 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
227 ifr->ifr_settings.type == IF_IFACE_V35))
228 new_type = IF_IFACE_V35;
229
230 else if (port->card->type == PC300_RSV &&
231 ifr->ifr_settings.type == IF_IFACE_V24)
232 new_type = IF_IFACE_V24;
233
234 else
235 return hdlc_ioctl(dev, ifr, cmd);
236
237 if (!capable(CAP_NET_ADMIN))
238 return -EPERM;
239
240 if (copy_from_user(&new_line, line, size))
241 return -EFAULT;
242
243 if (new_line.clock_type != CLOCK_EXT &&
244 new_line.clock_type != CLOCK_TXFROMRX &&
245 new_line.clock_type != CLOCK_INT &&
246 new_line.clock_type != CLOCK_TXINT)
247 return -EINVAL; /* No such clock setting */
248
249 if (new_line.loopback != 0 && new_line.loopback != 1)
250 return -EINVAL;
251
252 memcpy(&port->settings, &new_line, size); /* Update settings */
253 port->iface = new_type;
254 pc300_set_iface(port);
255 return 0;
256 }
257
258
259
260 static void pc300_pci_remove_one(struct pci_dev *pdev)
261 {
262 int i;
263 card_t *card = pci_get_drvdata(pdev);
264
265 for (i = 0; i < 2; i++)
266 if (card->ports[i].card)
267 unregister_hdlc_device(card->ports[i].netdev);
268
269 if (card->irq)
270 free_irq(card->irq, card);
271
272 if (card->rambase)
273 iounmap(card->rambase);
274 if (card->scabase)
275 iounmap(card->scabase);
276 if (card->plxbase)
277 iounmap(card->plxbase);
278
279 pci_release_regions(pdev);
280 pci_disable_device(pdev);
281 if (card->ports[0].netdev)
282 free_netdev(card->ports[0].netdev);
283 if (card->ports[1].netdev)
284 free_netdev(card->ports[1].netdev);
285 kfree(card);
286 }
287
288 static const struct net_device_ops pc300_ops = {
289 .ndo_open = pc300_open,
290 .ndo_stop = pc300_close,
291 .ndo_start_xmit = hdlc_start_xmit,
292 .ndo_do_ioctl = pc300_ioctl,
293 };
294
295 static int pc300_pci_init_one(struct pci_dev *pdev,
296 const struct pci_device_id *ent)
297 {
298 card_t *card;
299 u32 __iomem *p;
300 int i;
301 u32 ramsize;
302 u32 ramphys; /* buffer memory base */
303 u32 scaphys; /* SCA memory base */
304 u32 plxphys; /* PLX registers memory base */
305
306 i = pci_enable_device(pdev);
307 if (i)
308 return i;
309
310 i = pci_request_regions(pdev, "PC300");
311 if (i) {
312 pci_disable_device(pdev);
313 return i;
314 }
315
316 card = kzalloc(sizeof(card_t), GFP_KERNEL);
317 if (card == NULL) {
318 pci_release_regions(pdev);
319 pci_disable_device(pdev);
320 return -ENOBUFS;
321 }
322 pci_set_drvdata(pdev, card);
323
324 if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE ||
325 pci_resource_len(pdev, 2) != PC300_SCA_SIZE ||
326 pci_resource_len(pdev, 3) < 16384) {
327 pr_err("invalid card EEPROM parameters\n");
328 pc300_pci_remove_one(pdev);
329 return -EFAULT;
330 }
331
332 plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK;
333 card->plxbase = ioremap(plxphys, PC300_PLX_SIZE);
334
335 scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK;
336 card->scabase = ioremap(scaphys, PC300_SCA_SIZE);
337
338 ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK;
339 card->rambase = pci_ioremap_bar(pdev, 3);
340
341 if (card->plxbase == NULL ||
342 card->scabase == NULL ||
343 card->rambase == NULL) {
344 pr_err("ioremap() failed\n");
345 pc300_pci_remove_one(pdev);
346 return -ENOMEM;
347 }
348
349 /* PLX PCI 9050 workaround for local configuration register read bug */
350 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys);
351 card->init_ctrl_value = readl(&((plx9050 __iomem *)card->scabase)->init_ctrl);
352 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys);
353
354 if (pdev->device == PCI_DEVICE_ID_PC300_TE_1 ||
355 pdev->device == PCI_DEVICE_ID_PC300_TE_2)
356 card->type = PC300_TE; /* not fully supported */
357 else if (card->init_ctrl_value & PC300_CTYPE_MASK)
358 card->type = PC300_X21;
359 else
360 card->type = PC300_RSV;
361
362 if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 ||
363 pdev->device == PCI_DEVICE_ID_PC300_TE_1)
364 card->n_ports = 1;
365 else
366 card->n_ports = 2;
367
368 for (i = 0; i < card->n_ports; i++)
369 if (!(card->ports[i].netdev = alloc_hdlcdev(&card->ports[i]))) {
370 pr_err("unable to allocate memory\n");
371 pc300_pci_remove_one(pdev);
372 return -ENOMEM;
373 }
374
375 /* Reset PLX */
376 p = &card->plxbase->init_ctrl;
377 writel(card->init_ctrl_value | 0x40000000, p);
378 readl(p); /* Flush the write - do not use sca_flush */
379 udelay(1);
380
381 writel(card->init_ctrl_value, p);
382 readl(p); /* Flush the write - do not use sca_flush */
383 udelay(1);
384
385 /* Reload Config. Registers from EEPROM */
386 writel(card->init_ctrl_value | 0x20000000, p);
387 readl(p); /* Flush the write - do not use sca_flush */
388 udelay(1);
389
390 writel(card->init_ctrl_value, p);
391 readl(p); /* Flush the write - do not use sca_flush */
392 udelay(1);
393
394 ramsize = sca_detect_ram(card, card->rambase,
395 pci_resource_len(pdev, 3));
396
397 if (use_crystal_clock)
398 card->init_ctrl_value &= ~PC300_CLKSEL_MASK;
399 else
400 card->init_ctrl_value |= PC300_CLKSEL_MASK;
401
402 writel(card->init_ctrl_value, &card->plxbase->init_ctrl);
403 /* number of TX + RX buffers for one port */
404 i = ramsize / (card->n_ports * (sizeof(pkt_desc) + HDLC_MAX_MRU));
405 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
406 card->rx_ring_buffers = i - card->tx_ring_buffers;
407
408 card->buff_offset = card->n_ports * sizeof(pkt_desc) *
409 (card->tx_ring_buffers + card->rx_ring_buffers);
410
411 pr_info("PC300/%s, %u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n",
412 card->type == PC300_X21 ? "X21" :
413 card->type == PC300_TE ? "TE" : "RSV",
414 ramsize / 1024, ramphys, pdev->irq,
415 card->tx_ring_buffers, card->rx_ring_buffers);
416
417 if (card->tx_ring_buffers < 1) {
418 pr_err("RAM test failed\n");
419 pc300_pci_remove_one(pdev);
420 return -EFAULT;
421 }
422
423 /* Enable interrupts on the PCI bridge, LINTi1 active low */
424 writew(0x0041, &card->plxbase->intr_ctrl_stat);
425
426 /* Allocate IRQ */
427 if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pc300", card)) {
428 pr_warn("could not allocate IRQ%d\n", pdev->irq);
429 pc300_pci_remove_one(pdev);
430 return -EBUSY;
431 }
432 card->irq = pdev->irq;
433
434 sca_init(card, 0);
435
436 // COTE not set - allows better TX DMA settings
437 // sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card);
438
439 sca_out(0x10, BTCR, card);
440
441 for (i = 0; i < card->n_ports; i++) {
442 port_t *port = &card->ports[i];
443 struct net_device *dev = port->netdev;
444 hdlc_device *hdlc = dev_to_hdlc(dev);
445 port->chan = i;
446
447 spin_lock_init(&port->lock);
448 dev->irq = card->irq;
449 dev->mem_start = ramphys;
450 dev->mem_end = ramphys + ramsize - 1;
451 dev->tx_queue_len = 50;
452 dev->netdev_ops = &pc300_ops;
453 hdlc->attach = sca_attach;
454 hdlc->xmit = sca_xmit;
455 port->settings.clock_type = CLOCK_EXT;
456 port->card = card;
457 if (card->type == PC300_X21)
458 port->iface = IF_IFACE_X21;
459 else
460 port->iface = IF_IFACE_V35;
461
462 sca_init_port(port);
463 if (register_hdlc_device(dev)) {
464 pr_err("unable to register hdlc device\n");
465 port->card = NULL;
466 pc300_pci_remove_one(pdev);
467 return -ENOBUFS;
468 }
469
470 netdev_info(dev, "PC300 channel %d\n", port->chan);
471 }
472 return 0;
473 }
474
475
476
477 static const struct pci_device_id pc300_pci_tbl[] = {
478 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID,
479 PCI_ANY_ID, 0, 0, 0 },
480 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID,
481 PCI_ANY_ID, 0, 0, 0 },
482 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID,
483 PCI_ANY_ID, 0, 0, 0 },
484 { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID,
485 PCI_ANY_ID, 0, 0, 0 },
486 { 0, }
487 };
488
489
490 static struct pci_driver pc300_pci_driver = {
491 .name = "PC300",
492 .id_table = pc300_pci_tbl,
493 .probe = pc300_pci_init_one,
494 .remove = pc300_pci_remove_one,
495 };
496
497
498 static int __init pc300_init_module(void)
499 {
500 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
501 pr_err("Invalid PCI clock frequency\n");
502 return -EINVAL;
503 }
504 if (use_crystal_clock != 0 && use_crystal_clock != 1) {
505 pr_err("Invalid 'use_crystal_clock' value\n");
506 return -EINVAL;
507 }
508
509 CLOCK_BASE = use_crystal_clock ? 24576000 : pci_clock_freq;
510
511 return pci_register_driver(&pc300_pci_driver);
512 }
513
514
515
516 static void __exit pc300_cleanup_module(void)
517 {
518 pci_unregister_driver(&pc300_pci_driver);
519 }
520
521 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
522 MODULE_DESCRIPTION("Cyclades PC300 serial port driver");
523 MODULE_LICENSE("GPL v2");
524 MODULE_DEVICE_TABLE(pci, pc300_pci_tbl);
525 module_param(pci_clock_freq, int, 0444);
526 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
527 module_param(use_crystal_clock, int, 0444);
528 MODULE_PARM_DESC(use_crystal_clock,
529 "Use 24.576 MHz clock instead of PCI clock");
530 module_init(pc300_init_module);
531 module_exit(pc300_cleanup_module);
Linux with added FPC-III support