1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * (c) Copyright 1998 Alan Cox <alan@lxorguk.ukuu.org.uk>
5 * (c) Copyright 2000, 2001 Red Hat Inc
7 * Development of this driver was funded by Equiinet Ltd
8 * http://www.equiinet.com
12 * Asynchronous mode dropped for 2.2. For 2.5 we will attempt the
13 * unification of all the Z85x30 asynchronous drivers for real.
15 * DMA now uses get_free_page as kmalloc buffers may span a 64K
18 * Modified for SMP safety and SMP locking by Alan Cox
19 * <alan@lxorguk.ukuu.org.uk>
24 * Non DMA you want a 486DX50 or better to do 64Kbits. 9600 baud
25 * X.25 is not unrealistic on all machines. DMA mode can in theory
26 * handle T1/E1 quite nicely. In practice the limit seems to be about
27 * 512Kbit->1Mbit depending on motherboard.
30 * 64K will take DMA, 9600 baud X.25 should be ok.
33 * Synchronous mode without DMA is unlikely to pass about 2400 baud.
36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
38 #include <linux/module.h>
39 #include <linux/kernel.h>
41 #include <linux/net.h>
42 #include <linux/skbuff.h>
43 #include <linux/netdevice.h>
44 #include <linux/if_arp.h>
45 #include <linux/delay.h>
46 #include <linux/hdlc.h>
47 #include <linux/ioport.h>
48 #include <linux/init.h>
49 #include <linux/gfp.h>
54 #include <linux/spinlock.h>
60 * z8530_read_port - Architecture specific interface function
63 * Provided port access methods. The Comtrol SV11 requires no delays
64 * between accesses and uses PC I/O. Some drivers may need a 5uS delay
66 * In the longer term this should become an architecture specific
67 * section so that this can become a generic driver interface for all
68 * platforms. For now we only handle PC I/O ports with or without the
69 * dread 5uS sanity delay.
71 * The caller must hold sufficient locks to avoid violating the horrible
75 static inline int z8530_read_port(unsigned long p
)
77 u8 r
=inb(Z8530_PORT_OF(p
));
78 if(p
&Z8530_PORT_SLEEP
) /* gcc should figure this out efficiently ! */
84 * z8530_write_port - Architecture specific interface function
88 * Write a value to a port with delays if need be. Note that the
89 * caller must hold locks to avoid read/writes from other contexts
90 * violating the 5uS rule
92 * In the longer term this should become an architecture specific
93 * section so that this can become a generic driver interface for all
94 * platforms. For now we only handle PC I/O ports with or without the
95 * dread 5uS sanity delay.
99 static inline void z8530_write_port(unsigned long p
, u8 d
)
101 outb(d
,Z8530_PORT_OF(p
));
102 if(p
&Z8530_PORT_SLEEP
)
108 static void z8530_rx_done(struct z8530_channel
*c
);
109 static void z8530_tx_done(struct z8530_channel
*c
);
113 * read_zsreg - Read a register from a Z85230
114 * @c: Z8530 channel to read from (2 per chip)
115 * @reg: Register to read
116 * FIXME: Use a spinlock.
118 * Most of the Z8530 registers are indexed off the control registers.
119 * A read is done by writing to the control register and reading the
120 * register back. The caller must hold the lock
123 static inline u8
read_zsreg(struct z8530_channel
*c
, u8 reg
)
126 z8530_write_port(c
->ctrlio
, reg
);
127 return z8530_read_port(c
->ctrlio
);
131 * read_zsdata - Read the data port of a Z8530 channel
132 * @c: The Z8530 channel to read the data port from
134 * The data port provides fast access to some things. We still
135 * have all the 5uS delays to worry about.
138 static inline u8
read_zsdata(struct z8530_channel
*c
)
141 r
=z8530_read_port(c
->dataio
);
146 * write_zsreg - Write to a Z8530 channel register
147 * @c: The Z8530 channel
148 * @reg: Register number
149 * @val: Value to write
151 * Write a value to an indexed register. The caller must hold the lock
152 * to honour the irritating delay rules. We know about register 0
153 * being fast to access.
155 * Assumes c->lock is held.
157 static inline void write_zsreg(struct z8530_channel
*c
, u8 reg
, u8 val
)
160 z8530_write_port(c
->ctrlio
, reg
);
161 z8530_write_port(c
->ctrlio
, val
);
166 * write_zsctrl - Write to a Z8530 control register
167 * @c: The Z8530 channel
168 * @val: Value to write
170 * Write directly to the control register on the Z8530
173 static inline void write_zsctrl(struct z8530_channel
*c
, u8 val
)
175 z8530_write_port(c
->ctrlio
, val
);
179 * write_zsdata - Write to a Z8530 control register
180 * @c: The Z8530 channel
181 * @val: Value to write
183 * Write directly to the data register on the Z8530
187 static inline void write_zsdata(struct z8530_channel
*c
, u8 val
)
189 z8530_write_port(c
->dataio
, val
);
193 * Register loading parameters for a dead port
196 u8 z8530_dead_port
[]=
201 EXPORT_SYMBOL(z8530_dead_port
);
204 * Register loading parameters for currently supported circuit types
209 * Data clocked by telco end. This is the correct data for the UK
210 * "kilostream" service, and most other similar services.
213 u8 z8530_hdlc_kilostream
[]=
215 4, SYNC_ENAB
|SDLC
|X1CLK
,
216 2, 0, /* No vector */
218 3, ENT_HM
|RxCRC_ENAB
|Rx8
,
219 5, TxCRC_ENAB
|RTS
|TxENAB
|Tx8
|DTR
,
220 9, 0, /* Disable interrupts */
223 10, ABUNDER
|NRZ
|CRCPS
,/*MARKIDLE ??*/
226 15, DCDIE
|SYNCIE
|CTSIE
|TxUIE
|BRKIE
,
227 1, EXT_INT_ENAB
|TxINT_ENAB
|INT_ALL_Rx
,
232 EXPORT_SYMBOL(z8530_hdlc_kilostream
);
235 * As above but for enhanced chips.
238 u8 z8530_hdlc_kilostream_85230
[]=
240 4, SYNC_ENAB
|SDLC
|X1CLK
,
241 2, 0, /* No vector */
243 3, ENT_HM
|RxCRC_ENAB
|Rx8
,
244 5, TxCRC_ENAB
|RTS
|TxENAB
|Tx8
|DTR
,
245 9, 0, /* Disable interrupts */
248 10, ABUNDER
|NRZ
|CRCPS
, /* MARKIDLE?? */
251 15, DCDIE
|SYNCIE
|CTSIE
|TxUIE
|BRKIE
,
252 1, EXT_INT_ENAB
|TxINT_ENAB
|INT_ALL_Rx
,
254 23, 3, /* Extended mode AUTO TX and EOM*/
259 EXPORT_SYMBOL(z8530_hdlc_kilostream_85230
);
262 * z8530_flush_fifo - Flush on chip RX FIFO
263 * @c: Channel to flush
265 * Flush the receive FIFO. There is no specific option for this, we
266 * blindly read bytes and discard them. Reading when there is no data
267 * is harmless. The 8530 has a 4 byte FIFO, the 85230 has 8 bytes.
269 * All locking is handled for the caller. On return data may still be
270 * present if it arrived during the flush.
273 static void z8530_flush_fifo(struct z8530_channel
*c
)
279 if(c
->dev
->type
==Z85230
)
289 * z8530_rtsdtr - Control the outgoing DTS/RTS line
290 * @c: The Z8530 channel to control;
291 * @set: 1 to set, 0 to clear
293 * Sets or clears DTR/RTS on the requested line. All locking is handled
294 * by the caller. For now we assume all boards use the actual RTS/DTR
295 * on the chip. Apparently one or two don't. We'll scream about them
299 static void z8530_rtsdtr(struct z8530_channel
*c
, int set
)
302 c
->regs
[5] |= (RTS
| DTR
);
304 c
->regs
[5] &= ~(RTS
| DTR
);
305 write_zsreg(c
, R5
, c
->regs
[5]);
309 * z8530_rx - Handle a PIO receive event
310 * @c: Z8530 channel to process
312 * Receive handler for receiving in PIO mode. This is much like the
313 * async one but not quite the same or as complex
315 * Note: Its intended that this handler can easily be separated from
316 * the main code to run realtime. That'll be needed for some machines
317 * (eg to ever clock 64kbits on a sparc ;)).
319 * The RT_LOCK macros don't do anything now. Keep the code covered
320 * by them as short as possible in all circumstances - clocks cost
321 * baud. The interrupt handler is assumed to be atomic w.r.t. to
322 * other code - this is true in the RT case too.
324 * We only cover the sync cases for this. If you want 2Mbit async
325 * do it yourself but consider medical assistance first. This non DMA
326 * synchronous mode is portable code. The DMA mode assumes PCI like
329 * Called with the device lock held
332 static void z8530_rx(struct z8530_channel
*c
)
339 if(!(read_zsreg(c
, R0
)&1))
342 stat
=read_zsreg(c
, R1
);
347 if(c
->count
< c
->max
)
359 if(stat
&(Rx_OVR
|CRC_ERR
))
361 /* Rewind the buffer and return */
363 c
->dptr
=c
->skb
->data
;
367 pr_warn("%s: overrun\n", c
->dev
->name
);
373 /* printk("crc error\n"); */
375 /* Shove the frame upstream */
380 * Drop the lock for RX processing, or
381 * there are deadlocks
384 write_zsctrl(c
, RES_Rx_CRC
);
391 write_zsctrl(c
, ERR_RES
);
392 write_zsctrl(c
, RES_H_IUS
);
397 * z8530_tx - Handle a PIO transmit event
398 * @c: Z8530 channel to process
400 * Z8530 transmit interrupt handler for the PIO mode. The basic
401 * idea is to attempt to keep the FIFO fed. We fill as many bytes
402 * in as possible, its quite possible that we won't keep up with the
403 * data rate otherwise.
406 static void z8530_tx(struct z8530_channel
*c
)
410 if(!(read_zsreg(c
, R0
)&4))
414 * Shovel out the byte
416 write_zsreg(c
, R8
, *c
->tx_ptr
++);
417 write_zsctrl(c
, RES_H_IUS
);
418 /* We are about to underflow */
421 write_zsctrl(c
, RES_EOM_L
);
422 write_zsreg(c
, R10
, c
->regs
[10]&~ABUNDER
);
428 * End of frame TX - fire another one
431 write_zsctrl(c
, RES_Tx_P
);
434 write_zsctrl(c
, RES_H_IUS
);
438 * z8530_status - Handle a PIO status exception
439 * @chan: Z8530 channel to process
441 * A status event occurred in PIO synchronous mode. There are several
442 * reasons the chip will bother us here. A transmit underrun means we
443 * failed to feed the chip fast enough and just broke a packet. A DCD
444 * change is a line up or down.
447 static void z8530_status(struct z8530_channel
*chan
)
451 status
= read_zsreg(chan
, R0
);
452 altered
= chan
->status
^ status
;
454 chan
->status
= status
;
456 if (status
& TxEOM
) {
457 /* printk("%s: Tx underrun.\n", chan->dev->name); */
458 chan
->netdevice
->stats
.tx_fifo_errors
++;
459 write_zsctrl(chan
, ERR_RES
);
463 if (altered
& chan
->dcdcheck
)
465 if (status
& chan
->dcdcheck
) {
466 pr_info("%s: DCD raised\n", chan
->dev
->name
);
467 write_zsreg(chan
, R3
, chan
->regs
[3] | RxENABLE
);
469 netif_carrier_on(chan
->netdevice
);
471 pr_info("%s: DCD lost\n", chan
->dev
->name
);
472 write_zsreg(chan
, R3
, chan
->regs
[3] & ~RxENABLE
);
473 z8530_flush_fifo(chan
);
475 netif_carrier_off(chan
->netdevice
);
479 write_zsctrl(chan
, RES_EXT_INT
);
480 write_zsctrl(chan
, RES_H_IUS
);
483 struct z8530_irqhandler z8530_sync
= {
486 .status
= z8530_status
,
489 EXPORT_SYMBOL(z8530_sync
);
492 * z8530_dma_rx - Handle a DMA RX event
493 * @chan: Channel to handle
495 * Non bus mastering DMA interfaces for the Z8x30 devices. This
496 * is really pretty PC specific. The DMA mode means that most receive
497 * events are handled by the DMA hardware. We get a kick here only if
501 static void z8530_dma_rx(struct z8530_channel
*chan
)
505 /* Special condition check only */
508 read_zsreg(chan
, R7
);
509 read_zsreg(chan
, R6
);
511 status
=read_zsreg(chan
, R1
);
515 z8530_rx_done(chan
); /* Fire up the next one */
517 write_zsctrl(chan
, ERR_RES
);
518 write_zsctrl(chan
, RES_H_IUS
);
522 /* DMA is off right now, drain the slow way */
528 * z8530_dma_tx - Handle a DMA TX event
529 * @chan: The Z8530 channel to handle
531 * We have received an interrupt while doing DMA transmissions. It
532 * shouldn't happen. Scream loudly if it does.
535 static void z8530_dma_tx(struct z8530_channel
*chan
)
539 pr_warn("Hey who turned the DMA off?\n");
543 /* This shouldn't occur in DMA mode */
544 pr_err("DMA tx - bogus event!\n");
549 * z8530_dma_status - Handle a DMA status exception
550 * @chan: Z8530 channel to process
552 * A status event occurred on the Z8530. We receive these for two reasons
553 * when in DMA mode. Firstly if we finished a packet transfer we get one
554 * and kick the next packet out. Secondly we may see a DCD change.
558 static void z8530_dma_status(struct z8530_channel
*chan
)
562 status
=read_zsreg(chan
, R0
);
563 altered
=chan
->status
^status
;
574 flags
=claim_dma_lock();
575 disable_dma(chan
->txdma
);
576 clear_dma_ff(chan
->txdma
);
578 release_dma_lock(flags
);
583 if (altered
& chan
->dcdcheck
)
585 if (status
& chan
->dcdcheck
) {
586 pr_info("%s: DCD raised\n", chan
->dev
->name
);
587 write_zsreg(chan
, R3
, chan
->regs
[3] | RxENABLE
);
589 netif_carrier_on(chan
->netdevice
);
591 pr_info("%s: DCD lost\n", chan
->dev
->name
);
592 write_zsreg(chan
, R3
, chan
->regs
[3] & ~RxENABLE
);
593 z8530_flush_fifo(chan
);
595 netif_carrier_off(chan
->netdevice
);
599 write_zsctrl(chan
, RES_EXT_INT
);
600 write_zsctrl(chan
, RES_H_IUS
);
603 static struct z8530_irqhandler z8530_dma_sync
= {
606 .status
= z8530_dma_status
,
609 static struct z8530_irqhandler z8530_txdma_sync
= {
612 .status
= z8530_dma_status
,
616 * z8530_rx_clear - Handle RX events from a stopped chip
617 * @c: Z8530 channel to shut up
619 * Receive interrupt vectors for a Z8530 that is in 'parked' mode.
620 * For machines with PCI Z85x30 cards, or level triggered interrupts
621 * (eg the MacII) we must clear the interrupt cause or die.
625 static void z8530_rx_clear(struct z8530_channel
*c
)
628 * Data and status bytes
633 stat
=read_zsreg(c
, R1
);
636 write_zsctrl(c
, RES_Rx_CRC
);
640 write_zsctrl(c
, ERR_RES
);
641 write_zsctrl(c
, RES_H_IUS
);
645 * z8530_tx_clear - Handle TX events from a stopped chip
646 * @c: Z8530 channel to shut up
648 * Transmit interrupt vectors for a Z8530 that is in 'parked' mode.
649 * For machines with PCI Z85x30 cards, or level triggered interrupts
650 * (eg the MacII) we must clear the interrupt cause or die.
653 static void z8530_tx_clear(struct z8530_channel
*c
)
655 write_zsctrl(c
, RES_Tx_P
);
656 write_zsctrl(c
, RES_H_IUS
);
660 * z8530_status_clear - Handle status events from a stopped chip
661 * @chan: Z8530 channel to shut up
663 * Status interrupt vectors for a Z8530 that is in 'parked' mode.
664 * For machines with PCI Z85x30 cards, or level triggered interrupts
665 * (eg the MacII) we must clear the interrupt cause or die.
668 static void z8530_status_clear(struct z8530_channel
*chan
)
670 u8 status
=read_zsreg(chan
, R0
);
672 write_zsctrl(chan
, ERR_RES
);
673 write_zsctrl(chan
, RES_EXT_INT
);
674 write_zsctrl(chan
, RES_H_IUS
);
677 struct z8530_irqhandler z8530_nop
= {
678 .rx
= z8530_rx_clear
,
679 .tx
= z8530_tx_clear
,
680 .status
= z8530_status_clear
,
684 EXPORT_SYMBOL(z8530_nop
);
687 * z8530_interrupt - Handle an interrupt from a Z8530
688 * @irq: Interrupt number
689 * @dev_id: The Z8530 device that is interrupting.
691 * A Z85[2]30 device has stuck its hand in the air for attention.
692 * We scan both the channels on the chip for events and then call
693 * the channel specific call backs for each channel that has events.
694 * We have to use callback functions because the two channels can be
695 * in different modes.
697 * Locking is done for the handlers. Note that locking is done
698 * at the chip level (the 5uS delay issue is per chip not per
699 * channel). c->lock for both channels points to dev->lock
702 irqreturn_t
z8530_interrupt(int irq
, void *dev_id
)
704 struct z8530_dev
*dev
=dev_id
;
706 static volatile int locker
=0;
708 struct z8530_irqhandler
*irqs
;
712 pr_err("IRQ re-enter\n");
717 spin_lock(&dev
->lock
);
722 intr
= read_zsreg(&dev
->chanA
, R3
);
723 if(!(intr
& (CHARxIP
|CHATxIP
|CHAEXT
|CHBRxIP
|CHBTxIP
|CHBEXT
)))
726 /* This holds the IRQ status. On the 8530 you must read it from chan
727 A even though it applies to the whole chip */
729 /* Now walk the chip and see what it is wanting - it may be
730 an IRQ for someone else remember */
732 irqs
=dev
->chanA
.irqs
;
734 if(intr
& (CHARxIP
|CHATxIP
|CHAEXT
))
737 irqs
->rx(&dev
->chanA
);
739 irqs
->tx(&dev
->chanA
);
741 irqs
->status(&dev
->chanA
);
744 irqs
=dev
->chanB
.irqs
;
746 if(intr
& (CHBRxIP
|CHBTxIP
|CHBEXT
))
749 irqs
->rx(&dev
->chanB
);
751 irqs
->tx(&dev
->chanB
);
753 irqs
->status(&dev
->chanB
);
756 spin_unlock(&dev
->lock
);
758 pr_err("%s: interrupt jammed - abort(0x%X)!\n",
765 EXPORT_SYMBOL(z8530_interrupt
);
767 static const u8 reg_init
[16]=
777 * z8530_sync_open - Open a Z8530 channel for PIO
778 * @dev: The network interface we are using
779 * @c: The Z8530 channel to open in synchronous PIO mode
781 * Switch a Z8530 into synchronous mode without DMA assist. We
782 * raise the RTS/DTR and commence network operation.
785 int z8530_sync_open(struct net_device
*dev
, struct z8530_channel
*c
)
789 spin_lock_irqsave(c
->lock
, flags
);
792 c
->mtu
= dev
->mtu
+64;
796 c
->irqs
= &z8530_sync
;
798 /* This loads the double buffer up */
799 z8530_rx_done(c
); /* Load the frame ring */
800 z8530_rx_done(c
); /* Load the backup frame */
803 c
->regs
[R1
]|=TxINT_ENAB
;
804 write_zsreg(c
, R1
, c
->regs
[R1
]);
805 write_zsreg(c
, R3
, c
->regs
[R3
]|RxENABLE
);
807 spin_unlock_irqrestore(c
->lock
, flags
);
812 EXPORT_SYMBOL(z8530_sync_open
);
815 * z8530_sync_close - Close a PIO Z8530 channel
816 * @dev: Network device to close
817 * @c: Z8530 channel to disassociate and move to idle
819 * Close down a Z8530 interface and switch its interrupt handlers
820 * to discard future events.
823 int z8530_sync_close(struct net_device
*dev
, struct z8530_channel
*c
)
828 spin_lock_irqsave(c
->lock
, flags
);
829 c
->irqs
= &z8530_nop
;
833 chk
=read_zsreg(c
,R0
);
834 write_zsreg(c
, R3
, c
->regs
[R3
]);
837 spin_unlock_irqrestore(c
->lock
, flags
);
841 EXPORT_SYMBOL(z8530_sync_close
);
844 * z8530_sync_dma_open - Open a Z8530 for DMA I/O
845 * @dev: The network device to attach
846 * @c: The Z8530 channel to configure in sync DMA mode.
848 * Set up a Z85x30 device for synchronous DMA in both directions. Two
849 * ISA DMA channels must be available for this to work. We assume ISA
850 * DMA driven I/O and PC limits on access.
853 int z8530_sync_dma_open(struct net_device
*dev
, struct z8530_channel
*c
)
855 unsigned long cflags
, dflags
;
858 c
->mtu
= dev
->mtu
+64;
863 * Load the DMA interfaces up
869 * Allocate the DMA flip buffers. Limit by page size.
870 * Everyone runs 1500 mtu or less on wan links so this
874 if(c
->mtu
> PAGE_SIZE
/2)
877 c
->rx_buf
[0]=(void *)get_zeroed_page(GFP_KERNEL
|GFP_DMA
);
878 if(c
->rx_buf
[0]==NULL
)
880 c
->rx_buf
[1]=c
->rx_buf
[0]+PAGE_SIZE
/2;
882 c
->tx_dma_buf
[0]=(void *)get_zeroed_page(GFP_KERNEL
|GFP_DMA
);
883 if(c
->tx_dma_buf
[0]==NULL
)
885 free_page((unsigned long)c
->rx_buf
[0]);
889 c
->tx_dma_buf
[1]=c
->tx_dma_buf
[0]+PAGE_SIZE
/2;
897 * Enable DMA control mode
900 spin_lock_irqsave(c
->lock
, cflags
);
906 c
->regs
[R14
]|= DTRREQ
;
907 write_zsreg(c
, R14
, c
->regs
[R14
]);
909 c
->regs
[R1
]&= ~TxINT_ENAB
;
910 write_zsreg(c
, R1
, c
->regs
[R1
]);
916 c
->regs
[R1
]|= WT_FN_RDYFN
;
917 c
->regs
[R1
]|= WT_RDY_RT
;
918 c
->regs
[R1
]|= INT_ERR_Rx
;
919 c
->regs
[R1
]&= ~TxINT_ENAB
;
920 write_zsreg(c
, R1
, c
->regs
[R1
]);
921 c
->regs
[R1
]|= WT_RDY_ENAB
;
922 write_zsreg(c
, R1
, c
->regs
[R1
]);
929 * Set up the DMA configuration
932 dflags
=claim_dma_lock();
934 disable_dma(c
->rxdma
);
935 clear_dma_ff(c
->rxdma
);
936 set_dma_mode(c
->rxdma
, DMA_MODE_READ
|0x10);
937 set_dma_addr(c
->rxdma
, virt_to_bus(c
->rx_buf
[0]));
938 set_dma_count(c
->rxdma
, c
->mtu
);
939 enable_dma(c
->rxdma
);
941 disable_dma(c
->txdma
);
942 clear_dma_ff(c
->txdma
);
943 set_dma_mode(c
->txdma
, DMA_MODE_WRITE
);
944 disable_dma(c
->txdma
);
946 release_dma_lock(dflags
);
949 * Select the DMA interrupt handlers
956 c
->irqs
= &z8530_dma_sync
;
958 write_zsreg(c
, R3
, c
->regs
[R3
]|RxENABLE
);
960 spin_unlock_irqrestore(c
->lock
, cflags
);
965 EXPORT_SYMBOL(z8530_sync_dma_open
);
968 * z8530_sync_dma_close - Close down DMA I/O
969 * @dev: Network device to detach
970 * @c: Z8530 channel to move into discard mode
972 * Shut down a DMA mode synchronous interface. Halt the DMA, and
976 int z8530_sync_dma_close(struct net_device
*dev
, struct z8530_channel
*c
)
981 c
->irqs
= &z8530_nop
;
986 * Disable the PC DMA channels
989 flags
=claim_dma_lock();
990 disable_dma(c
->rxdma
);
991 clear_dma_ff(c
->rxdma
);
995 disable_dma(c
->txdma
);
996 clear_dma_ff(c
->txdma
);
997 release_dma_lock(flags
);
1002 spin_lock_irqsave(c
->lock
, flags
);
1005 * Disable DMA control mode
1008 c
->regs
[R1
]&= ~WT_RDY_ENAB
;
1009 write_zsreg(c
, R1
, c
->regs
[R1
]);
1010 c
->regs
[R1
]&= ~(WT_RDY_RT
|WT_FN_RDYFN
|INT_ERR_Rx
);
1011 c
->regs
[R1
]|= INT_ALL_Rx
;
1012 write_zsreg(c
, R1
, c
->regs
[R1
]);
1013 c
->regs
[R14
]&= ~DTRREQ
;
1014 write_zsreg(c
, R14
, c
->regs
[R14
]);
1018 free_page((unsigned long)c
->rx_buf
[0]);
1021 if(c
->tx_dma_buf
[0])
1023 free_page((unsigned long)c
->tx_dma_buf
[0]);
1024 c
->tx_dma_buf
[0]=NULL
;
1026 chk
=read_zsreg(c
,R0
);
1027 write_zsreg(c
, R3
, c
->regs
[R3
]);
1030 spin_unlock_irqrestore(c
->lock
, flags
);
1035 EXPORT_SYMBOL(z8530_sync_dma_close
);
1038 * z8530_sync_txdma_open - Open a Z8530 for TX driven DMA
1039 * @dev: The network device to attach
1040 * @c: The Z8530 channel to configure in sync DMA mode.
1042 * Set up a Z85x30 device for synchronous DMA transmission. One
1043 * ISA DMA channel must be available for this to work. The receive
1044 * side is run in PIO mode, but then it has the bigger FIFO.
1047 int z8530_sync_txdma_open(struct net_device
*dev
, struct z8530_channel
*c
)
1049 unsigned long cflags
, dflags
;
1051 printk("Opening sync interface for TX-DMA\n");
1053 c
->mtu
= dev
->mtu
+64;
1059 * Allocate the DMA flip buffers. Limit by page size.
1060 * Everyone runs 1500 mtu or less on wan links so this
1064 if(c
->mtu
> PAGE_SIZE
/2)
1067 c
->tx_dma_buf
[0]=(void *)get_zeroed_page(GFP_KERNEL
|GFP_DMA
);
1068 if(c
->tx_dma_buf
[0]==NULL
)
1071 c
->tx_dma_buf
[1] = c
->tx_dma_buf
[0] + PAGE_SIZE
/2;
1074 spin_lock_irqsave(c
->lock
, cflags
);
1077 * Load the PIO receive ring
1084 * Load the DMA interfaces up
1096 * Enable DMA control mode
1100 * TX DMA via DIR/REQ
1102 c
->regs
[R14
]|= DTRREQ
;
1103 write_zsreg(c
, R14
, c
->regs
[R14
]);
1105 c
->regs
[R1
]&= ~TxINT_ENAB
;
1106 write_zsreg(c
, R1
, c
->regs
[R1
]);
1109 * Set up the DMA configuration
1112 dflags
= claim_dma_lock();
1114 disable_dma(c
->txdma
);
1115 clear_dma_ff(c
->txdma
);
1116 set_dma_mode(c
->txdma
, DMA_MODE_WRITE
);
1117 disable_dma(c
->txdma
);
1119 release_dma_lock(dflags
);
1122 * Select the DMA interrupt handlers
1129 c
->irqs
= &z8530_txdma_sync
;
1131 write_zsreg(c
, R3
, c
->regs
[R3
]|RxENABLE
);
1132 spin_unlock_irqrestore(c
->lock
, cflags
);
1137 EXPORT_SYMBOL(z8530_sync_txdma_open
);
1140 * z8530_sync_txdma_close - Close down a TX driven DMA channel
1141 * @dev: Network device to detach
1142 * @c: Z8530 channel to move into discard mode
1144 * Shut down a DMA/PIO split mode synchronous interface. Halt the DMA,
1145 * and free the buffers.
1148 int z8530_sync_txdma_close(struct net_device
*dev
, struct z8530_channel
*c
)
1150 unsigned long dflags
, cflags
;
1154 spin_lock_irqsave(c
->lock
, cflags
);
1156 c
->irqs
= &z8530_nop
;
1161 * Disable the PC DMA channels
1164 dflags
= claim_dma_lock();
1166 disable_dma(c
->txdma
);
1167 clear_dma_ff(c
->txdma
);
1171 release_dma_lock(dflags
);
1174 * Disable DMA control mode
1177 c
->regs
[R1
]&= ~WT_RDY_ENAB
;
1178 write_zsreg(c
, R1
, c
->regs
[R1
]);
1179 c
->regs
[R1
]&= ~(WT_RDY_RT
|WT_FN_RDYFN
|INT_ERR_Rx
);
1180 c
->regs
[R1
]|= INT_ALL_Rx
;
1181 write_zsreg(c
, R1
, c
->regs
[R1
]);
1182 c
->regs
[R14
]&= ~DTRREQ
;
1183 write_zsreg(c
, R14
, c
->regs
[R14
]);
1185 if(c
->tx_dma_buf
[0])
1187 free_page((unsigned long)c
->tx_dma_buf
[0]);
1188 c
->tx_dma_buf
[0]=NULL
;
1190 chk
=read_zsreg(c
,R0
);
1191 write_zsreg(c
, R3
, c
->regs
[R3
]);
1194 spin_unlock_irqrestore(c
->lock
, cflags
);
1199 EXPORT_SYMBOL(z8530_sync_txdma_close
);
1203 * Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny
1207 static const char *z8530_type_name
[]={
1214 * z8530_describe - Uniformly describe a Z8530 port
1215 * @dev: Z8530 device to describe
1216 * @mapping: string holding mapping type (eg "I/O" or "Mem")
1217 * @io: the port value in question
1219 * Describe a Z8530 in a standard format. We must pass the I/O as
1220 * the port offset isn't predictable. The main reason for this function
1221 * is to try and get a common format of report.
1224 void z8530_describe(struct z8530_dev
*dev
, char *mapping
, unsigned long io
)
1226 pr_info("%s: %s found at %s 0x%lX, IRQ %d\n",
1228 z8530_type_name
[dev
->type
],
1234 EXPORT_SYMBOL(z8530_describe
);
1237 * Locked operation part of the z8530 init code
1240 static inline int do_z8530_init(struct z8530_dev
*dev
)
1242 /* NOP the interrupt handlers first - we might get a
1243 floating IRQ transition when we reset the chip */
1244 dev
->chanA
.irqs
=&z8530_nop
;
1245 dev
->chanB
.irqs
=&z8530_nop
;
1246 dev
->chanA
.dcdcheck
=DCD
;
1247 dev
->chanB
.dcdcheck
=DCD
;
1249 /* Reset the chip */
1250 write_zsreg(&dev
->chanA
, R9
, 0xC0);
1252 /* Now check its valid */
1253 write_zsreg(&dev
->chanA
, R12
, 0xAA);
1254 if(read_zsreg(&dev
->chanA
, R12
)!=0xAA)
1256 write_zsreg(&dev
->chanA
, R12
, 0x55);
1257 if(read_zsreg(&dev
->chanA
, R12
)!=0x55)
1263 * See the application note.
1266 write_zsreg(&dev
->chanA
, R15
, 0x01);
1269 * If we can set the low bit of R15 then
1270 * the chip is enhanced.
1273 if(read_zsreg(&dev
->chanA
, R15
)==0x01)
1275 /* This C30 versus 230 detect is from Klaus Kudielka's dmascc */
1276 /* Put a char in the fifo */
1277 write_zsreg(&dev
->chanA
, R8
, 0);
1278 if(read_zsreg(&dev
->chanA
, R0
)&Tx_BUF_EMP
)
1279 dev
->type
= Z85230
; /* Has a FIFO */
1281 dev
->type
= Z85C30
; /* Z85C30, 1 byte FIFO */
1285 * The code assumes R7' and friends are
1286 * off. Use write_zsext() for these and keep
1290 write_zsreg(&dev
->chanA
, R15
, 0);
1293 * At this point it looks like the chip is behaving
1296 memcpy(dev
->chanA
.regs
, reg_init
, 16);
1297 memcpy(dev
->chanB
.regs
, reg_init
,16);
1303 * z8530_init - Initialise a Z8530 device
1304 * @dev: Z8530 device to initialise.
1306 * Configure up a Z8530/Z85C30 or Z85230 chip. We check the device
1307 * is present, identify the type and then program it to hopefully
1308 * keep quite and behave. This matters a lot, a Z8530 in the wrong
1309 * state will sometimes get into stupid modes generating 10Khz
1310 * interrupt streams and the like.
1312 * We set the interrupt handler up to discard any events, in case
1313 * we get them during reset or setp.
1315 * Return 0 for success, or a negative value indicating the problem
1319 int z8530_init(struct z8530_dev
*dev
)
1321 unsigned long flags
;
1324 /* Set up the chip level lock */
1325 spin_lock_init(&dev
->lock
);
1326 dev
->chanA
.lock
= &dev
->lock
;
1327 dev
->chanB
.lock
= &dev
->lock
;
1329 spin_lock_irqsave(&dev
->lock
, flags
);
1330 ret
= do_z8530_init(dev
);
1331 spin_unlock_irqrestore(&dev
->lock
, flags
);
1337 EXPORT_SYMBOL(z8530_init
);
1340 * z8530_shutdown - Shutdown a Z8530 device
1341 * @dev: The Z8530 chip to shutdown
1343 * We set the interrupt handlers to silence any interrupts. We then
1344 * reset the chip and wait 100uS to be sure the reset completed. Just
1345 * in case the caller then tries to do stuff.
1347 * This is called without the lock held
1350 int z8530_shutdown(struct z8530_dev
*dev
)
1352 unsigned long flags
;
1353 /* Reset the chip */
1355 spin_lock_irqsave(&dev
->lock
, flags
);
1356 dev
->chanA
.irqs
=&z8530_nop
;
1357 dev
->chanB
.irqs
=&z8530_nop
;
1358 write_zsreg(&dev
->chanA
, R9
, 0xC0);
1359 /* We must lock the udelay, the chip is offlimits here */
1361 spin_unlock_irqrestore(&dev
->lock
, flags
);
1365 EXPORT_SYMBOL(z8530_shutdown
);
1368 * z8530_channel_load - Load channel data
1369 * @c: Z8530 channel to configure
1370 * @rtable: table of register, value pairs
1371 * FIXME: ioctl to allow user uploaded tables
1373 * Load a Z8530 channel up from the system data. We use +16 to
1374 * indicate the "prime" registers. The value 255 terminates the
1378 int z8530_channel_load(struct z8530_channel
*c
, u8
*rtable
)
1380 unsigned long flags
;
1382 spin_lock_irqsave(c
->lock
, flags
);
1388 write_zsreg(c
, R15
, c
->regs
[15]|1);
1389 write_zsreg(c
, reg
&0x0F, *rtable
);
1391 write_zsreg(c
, R15
, c
->regs
[15]&~1);
1392 c
->regs
[reg
]=*rtable
++;
1394 c
->rx_function
=z8530_null_rx
;
1397 c
->tx_next_skb
=NULL
;
1401 c
->status
=read_zsreg(c
, R0
);
1403 write_zsreg(c
, R3
, c
->regs
[R3
]|RxENABLE
);
1405 spin_unlock_irqrestore(c
->lock
, flags
);
1409 EXPORT_SYMBOL(z8530_channel_load
);
1413 * z8530_tx_begin - Begin packet transmission
1414 * @c: The Z8530 channel to kick
1416 * This is the speed sensitive side of transmission. If we are called
1417 * and no buffer is being transmitted we commence the next buffer. If
1418 * nothing is queued we idle the sync.
1420 * Note: We are handling this code path in the interrupt path, keep it
1421 * fast or bad things will happen.
1423 * Called with the lock held.
1426 static void z8530_tx_begin(struct z8530_channel
*c
)
1428 unsigned long flags
;
1432 c
->tx_skb
=c
->tx_next_skb
;
1433 c
->tx_next_skb
=NULL
;
1434 c
->tx_ptr
=c
->tx_next_ptr
;
1441 flags
=claim_dma_lock();
1442 disable_dma(c
->txdma
);
1444 * Check if we crapped out.
1446 if (get_dma_residue(c
->txdma
))
1448 c
->netdevice
->stats
.tx_dropped
++;
1449 c
->netdevice
->stats
.tx_fifo_errors
++;
1451 release_dma_lock(flags
);
1457 c
->txcount
=c
->tx_skb
->len
;
1463 * FIXME. DMA is broken for the original 8530,
1464 * on the older parts we need to set a flag and
1465 * wait for a further TX interrupt to fire this
1469 flags
=claim_dma_lock();
1470 disable_dma(c
->txdma
);
1473 * These two are needed by the 8530/85C30
1474 * and must be issued when idling.
1477 if(c
->dev
->type
!=Z85230
)
1479 write_zsctrl(c
, RES_Tx_CRC
);
1480 write_zsctrl(c
, RES_EOM_L
);
1482 write_zsreg(c
, R10
, c
->regs
[10]&~ABUNDER
);
1483 clear_dma_ff(c
->txdma
);
1484 set_dma_addr(c
->txdma
, virt_to_bus(c
->tx_ptr
));
1485 set_dma_count(c
->txdma
, c
->txcount
);
1486 enable_dma(c
->txdma
);
1487 release_dma_lock(flags
);
1488 write_zsctrl(c
, RES_EOM_L
);
1489 write_zsreg(c
, R5
, c
->regs
[R5
]|TxENAB
);
1495 write_zsreg(c
, R10
, c
->regs
[10]);
1496 write_zsctrl(c
, RES_Tx_CRC
);
1498 while(c
->txcount
&& (read_zsreg(c
,R0
)&Tx_BUF_EMP
))
1500 write_zsreg(c
, R8
, *c
->tx_ptr
++);
1507 * Since we emptied tx_skb we can ask for more
1509 netif_wake_queue(c
->netdevice
);
1513 * z8530_tx_done - TX complete callback
1514 * @c: The channel that completed a transmit.
1516 * This is called when we complete a packet send. We wake the queue,
1517 * start the next packet going and then free the buffer of the existing
1518 * packet. This code is fairly timing sensitive.
1520 * Called with the register lock held.
1523 static void z8530_tx_done(struct z8530_channel
*c
)
1525 struct sk_buff
*skb
;
1527 /* Actually this can happen.*/
1528 if (c
->tx_skb
== NULL
)
1534 c
->netdevice
->stats
.tx_packets
++;
1535 c
->netdevice
->stats
.tx_bytes
+= skb
->len
;
1536 dev_consume_skb_irq(skb
);
1540 * z8530_null_rx - Discard a packet
1541 * @c: The channel the packet arrived on
1544 * We point the receive handler at this function when idle. Instead
1545 * of processing the frames we get to throw them away.
1548 void z8530_null_rx(struct z8530_channel
*c
, struct sk_buff
*skb
)
1550 dev_kfree_skb_any(skb
);
1553 EXPORT_SYMBOL(z8530_null_rx
);
1556 * z8530_rx_done - Receive completion callback
1557 * @c: The channel that completed a receive
1559 * A new packet is complete. Our goal here is to get back into receive
1560 * mode as fast as possible. On the Z85230 we could change to using
1561 * ESCC mode, but on the older chips we have no choice. We flip to the
1562 * new buffer immediately in DMA mode so that the DMA of the next
1563 * frame can occur while we are copying the previous buffer to an sk_buff
1565 * Called with the lock held
1568 static void z8530_rx_done(struct z8530_channel
*c
)
1570 struct sk_buff
*skb
;
1574 * Is our receive engine in DMA mode
1580 * Save the ready state and the buffer currently
1581 * being used as the DMA target
1584 int ready
=c
->dma_ready
;
1585 unsigned char *rxb
=c
->rx_buf
[c
->dma_num
];
1586 unsigned long flags
;
1589 * Complete this DMA. Necessary to find the length
1592 flags
=claim_dma_lock();
1594 disable_dma(c
->rxdma
);
1595 clear_dma_ff(c
->rxdma
);
1597 ct
=c
->mtu
-get_dma_residue(c
->rxdma
);
1599 ct
=2; /* Shit happens.. */
1603 * Normal case: the other slot is free, start the next DMA
1604 * into it immediately.
1610 set_dma_mode(c
->rxdma
, DMA_MODE_READ
|0x10);
1611 set_dma_addr(c
->rxdma
, virt_to_bus(c
->rx_buf
[c
->dma_num
]));
1612 set_dma_count(c
->rxdma
, c
->mtu
);
1614 enable_dma(c
->rxdma
);
1615 /* Stop any frames that we missed the head of
1617 write_zsreg(c
, R0
, RES_Rx_CRC
);
1620 /* Can't occur as we dont reenable the DMA irq until
1621 after the flip is done */
1622 netdev_warn(c
->netdevice
, "DMA flip overrun!\n");
1624 release_dma_lock(flags
);
1627 * Shove the old buffer into an sk_buff. We can't DMA
1628 * directly into one on a PC - it might be above the 16Mb
1629 * boundary. Optimisation - we could check to see if we
1630 * can avoid the copy. Optimisation 2 - make the memcpy
1634 skb
= dev_alloc_skb(ct
);
1636 c
->netdevice
->stats
.rx_dropped
++;
1637 netdev_warn(c
->netdevice
, "Memory squeeze\n");
1640 skb_copy_to_linear_data(skb
, rxb
, ct
);
1641 c
->netdevice
->stats
.rx_packets
++;
1642 c
->netdevice
->stats
.rx_bytes
+= ct
;
1650 * The game we play for non DMA is similar. We want to
1651 * get the controller set up for the next packet as fast
1652 * as possible. We potentially only have one byte + the
1653 * fifo length for this. Thus we want to flip to the new
1654 * buffer and then mess around copying and allocating
1655 * things. For the current case it doesn't matter but
1656 * if you build a system where the sync irq isn't blocked
1657 * by the kernel IRQ disable then you need only block the
1658 * sync IRQ for the RT_LOCK area.
1667 c
->dptr
= c
->skb
->data
;
1675 c
->skb2
= dev_alloc_skb(c
->mtu
);
1676 if (c
->skb2
== NULL
)
1677 netdev_warn(c
->netdevice
, "memory squeeze\n");
1679 skb_put(c
->skb2
, c
->mtu
);
1680 c
->netdevice
->stats
.rx_packets
++;
1681 c
->netdevice
->stats
.rx_bytes
+= ct
;
1684 * If we received a frame we must now process it.
1688 c
->rx_function(c
, skb
);
1690 c
->netdevice
->stats
.rx_dropped
++;
1691 netdev_err(c
->netdevice
, "Lost a frame\n");
1696 * spans_boundary - Check a packet can be ISA DMA'd
1697 * @skb: The buffer to check
1699 * Returns true if the buffer cross a DMA boundary on a PC. The poor
1700 * thing can only DMA within a 64K block not across the edges of it.
1703 static inline int spans_boundary(struct sk_buff
*skb
)
1705 unsigned long a
=(unsigned long)skb
->data
;
1707 if(a
&0x00010000) /* If the 64K bit is different.. */
1713 * z8530_queue_xmit - Queue a packet
1714 * @c: The channel to use
1715 * @skb: The packet to kick down the channel
1717 * Queue a packet for transmission. Because we have rather
1718 * hard to hit interrupt latencies for the Z85230 per packet
1719 * even in DMA mode we do the flip to DMA buffer if needed here
1722 * Called from the network code. The lock is not held at this
1726 netdev_tx_t
z8530_queue_xmit(struct z8530_channel
*c
, struct sk_buff
*skb
)
1728 unsigned long flags
;
1730 netif_stop_queue(c
->netdevice
);
1732 return NETDEV_TX_BUSY
;
1735 /* PC SPECIFIC - DMA limits */
1738 * If we will DMA the transmit and its gone over the ISA bus
1739 * limit, then copy to the flip buffer
1742 if(c
->dma_tx
&& ((unsigned long)(virt_to_bus(skb
->data
+skb
->len
))>=16*1024*1024 || spans_boundary(skb
)))
1745 * Send the flip buffer, and flip the flippy bit.
1746 * We don't care which is used when just so long as
1747 * we never use the same buffer twice in a row. Since
1748 * only one buffer can be going out at a time the other
1751 c
->tx_next_ptr
=c
->tx_dma_buf
[c
->tx_dma_used
];
1752 c
->tx_dma_used
^=1; /* Flip temp buffer */
1753 skb_copy_from_linear_data(skb
, c
->tx_next_ptr
, skb
->len
);
1756 c
->tx_next_ptr
=skb
->data
;
1761 spin_lock_irqsave(c
->lock
, flags
);
1763 spin_unlock_irqrestore(c
->lock
, flags
);
1765 return NETDEV_TX_OK
;
1768 EXPORT_SYMBOL(z8530_queue_xmit
);
1773 static const char banner
[] __initconst
=
1774 KERN_INFO
"Generic Z85C30/Z85230 interface driver v0.02\n";
1776 static int __init
z85230_init_driver(void)
1781 module_init(z85230_init_driver
);
1783 static void __exit
z85230_cleanup_driver(void)
1786 module_exit(z85230_cleanup_driver
);
1788 MODULE_AUTHOR("Red Hat Inc.");
1789 MODULE_DESCRIPTION("Z85x30 synchronous driver core");
1790 MODULE_LICENSE("GPL");