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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / net / wireless / admtek / adm8211.c
blobc41e72508d3dbfdbea34422026ee11a50031e6e5
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 /*
4 * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
5 *
6 * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
7 * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
8 * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
9 * and used with permission.
10 *
11 * Much thanks to Infineon-ADMtek for their support of this driver.
12 */
13
14 #include <linux/interrupt.h>
15 #include <linux/if.h>
16 #include <linux/skbuff.h>
17 #include <linux/slab.h>
18 #include <linux/etherdevice.h>
19 #include <linux/pci.h>
20 #include <linux/delay.h>
21 #include <linux/crc32.h>
22 #include <linux/eeprom_93cx6.h>
23 #include <linux/module.h>
24 #include <net/mac80211.h>
25
26 #include "adm8211.h"
27
28 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
29 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
30 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
31 MODULE_SUPPORTED_DEVICE("ADM8211");
32 MODULE_LICENSE("GPL");
33
34 static unsigned int tx_ring_size __read_mostly = 16;
35 static unsigned int rx_ring_size __read_mostly = 16;
36
37 module_param(tx_ring_size, uint, 0);
38 module_param(rx_ring_size, uint, 0);
39
40 static const struct pci_device_id adm8211_pci_id_table[] = {
41 /* ADMtek ADM8211 */
42 { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
43 { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
44 { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
45 { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
46 { 0 }
47 };
48
49 static struct ieee80211_rate adm8211_rates[] = {
50 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
51 { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
52 { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
53 { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
54 { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
55 };
56
57 static const struct ieee80211_channel adm8211_channels[] = {
58 { .center_freq = 2412},
59 { .center_freq = 2417},
60 { .center_freq = 2422},
61 { .center_freq = 2427},
62 { .center_freq = 2432},
63 { .center_freq = 2437},
64 { .center_freq = 2442},
65 { .center_freq = 2447},
66 { .center_freq = 2452},
67 { .center_freq = 2457},
68 { .center_freq = 2462},
69 { .center_freq = 2467},
70 { .center_freq = 2472},
71 { .center_freq = 2484},
72 };
73
74
75 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
76 {
77 struct adm8211_priv *priv = eeprom->data;
78 u32 reg = ADM8211_CSR_READ(SPR);
79
80 eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
81 eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
82 eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
83 eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
84 }
85
86 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
87 {
88 struct adm8211_priv *priv = eeprom->data;
89 u32 reg = 0x4000 | ADM8211_SPR_SRS;
90
91 if (eeprom->reg_data_in)
92 reg |= ADM8211_SPR_SDI;
93 if (eeprom->reg_data_out)
94 reg |= ADM8211_SPR_SDO;
95 if (eeprom->reg_data_clock)
96 reg |= ADM8211_SPR_SCLK;
97 if (eeprom->reg_chip_select)
98 reg |= ADM8211_SPR_SCS;
99
100 ADM8211_CSR_WRITE(SPR, reg);
101 ADM8211_CSR_READ(SPR); /* eeprom_delay */
102 }
103
104 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
105 {
106 struct adm8211_priv *priv = dev->priv;
107 unsigned int words, i;
108 struct ieee80211_chan_range chan_range;
109 u16 cr49;
110 struct eeprom_93cx6 eeprom = {
111 .data = priv,
112 .register_read = adm8211_eeprom_register_read,
113 .register_write = adm8211_eeprom_register_write
114 };
115
116 if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
117 /* 256 * 16-bit = 512 bytes */
118 eeprom.width = PCI_EEPROM_WIDTH_93C66;
119 words = 256;
120 } else {
121 /* 64 * 16-bit = 128 bytes */
122 eeprom.width = PCI_EEPROM_WIDTH_93C46;
123 words = 64;
124 }
125
126 priv->eeprom_len = words * 2;
127 priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
128 if (!priv->eeprom)
129 return -ENOMEM;
130
131 eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
132
133 cr49 = le16_to_cpu(priv->eeprom->cr49);
134 priv->rf_type = (cr49 >> 3) & 0x7;
135 switch (priv->rf_type) {
136 case ADM8211_TYPE_INTERSIL:
137 case ADM8211_TYPE_RFMD:
138 case ADM8211_TYPE_MARVEL:
139 case ADM8211_TYPE_AIROHA:
140 case ADM8211_TYPE_ADMTEK:
141 break;
142
143 default:
144 if (priv->pdev->revision < ADM8211_REV_CA)
145 priv->rf_type = ADM8211_TYPE_RFMD;
146 else
147 priv->rf_type = ADM8211_TYPE_AIROHA;
148
149 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
150 pci_name(priv->pdev), (cr49 >> 3) & 0x7);
151 }
152
153 priv->bbp_type = cr49 & 0x7;
154 switch (priv->bbp_type) {
155 case ADM8211_TYPE_INTERSIL:
156 case ADM8211_TYPE_RFMD:
157 case ADM8211_TYPE_MARVEL:
158 case ADM8211_TYPE_AIROHA:
159 case ADM8211_TYPE_ADMTEK:
160 break;
161 default:
162 if (priv->pdev->revision < ADM8211_REV_CA)
163 priv->bbp_type = ADM8211_TYPE_RFMD;
164 else
165 priv->bbp_type = ADM8211_TYPE_ADMTEK;
166
167 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
168 pci_name(priv->pdev), cr49 >> 3);
169 }
170
171 if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
172 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
173 pci_name(priv->pdev), priv->eeprom->country_code);
174
175 chan_range = cranges[2];
176 } else
177 chan_range = cranges[priv->eeprom->country_code];
178
179 printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
180 pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
181
182 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
183
184 memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
185 priv->band.channels = priv->channels;
186 priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
187 priv->band.bitrates = adm8211_rates;
188 priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
189
190 for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
191 if (i < chan_range.min || i > chan_range.max)
192 priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
193
194 switch (priv->eeprom->specific_bbptype) {
195 case ADM8211_BBP_RFMD3000:
196 case ADM8211_BBP_RFMD3002:
197 case ADM8211_BBP_ADM8011:
198 priv->specific_bbptype = priv->eeprom->specific_bbptype;
199 break;
200
201 default:
202 if (priv->pdev->revision < ADM8211_REV_CA)
203 priv->specific_bbptype = ADM8211_BBP_RFMD3000;
204 else
205 priv->specific_bbptype = ADM8211_BBP_ADM8011;
206
207 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
208 pci_name(priv->pdev), priv->eeprom->specific_bbptype);
209 }
210
211 switch (priv->eeprom->specific_rftype) {
212 case ADM8211_RFMD2948:
213 case ADM8211_RFMD2958:
214 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
215 case ADM8211_MAX2820:
216 case ADM8211_AL2210L:
217 priv->transceiver_type = priv->eeprom->specific_rftype;
218 break;
219
220 default:
221 if (priv->pdev->revision == ADM8211_REV_BA)
222 priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
223 else if (priv->pdev->revision == ADM8211_REV_CA)
224 priv->transceiver_type = ADM8211_AL2210L;
225 else if (priv->pdev->revision == ADM8211_REV_AB)
226 priv->transceiver_type = ADM8211_RFMD2948;
227
228 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
229 pci_name(priv->pdev), priv->eeprom->specific_rftype);
230
231 break;
232 }
233
234 printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
235 "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
236 priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
237
238 return 0;
239 }
240
241 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
242 u32 addr, u32 data)
243 {
244 struct adm8211_priv *priv = dev->priv;
245
246 ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
247 (priv->pdev->revision < ADM8211_REV_BA ?
248 0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
249 ADM8211_CSR_READ(WEPCTL);
250 msleep(1);
251
252 ADM8211_CSR_WRITE(WESK, data);
253 ADM8211_CSR_READ(WESK);
254 msleep(1);
255 }
256
257 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
258 unsigned int addr, u8 *buf,
259 unsigned int len)
260 {
261 struct adm8211_priv *priv = dev->priv;
262 u32 reg = ADM8211_CSR_READ(WEPCTL);
263 unsigned int i;
264
265 if (priv->pdev->revision < ADM8211_REV_BA) {
266 for (i = 0; i < len; i += 2) {
267 u16 val = buf[i] | (buf[i + 1] << 8);
268 adm8211_write_sram(dev, addr + i / 2, val);
269 }
270 } else {
271 for (i = 0; i < len; i += 4) {
272 u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
273 (buf[i + 2] << 16) | (buf[i + 3] << 24);
274 adm8211_write_sram(dev, addr + i / 4, val);
275 }
276 }
277
278 ADM8211_CSR_WRITE(WEPCTL, reg);
279 }
280
281 static void adm8211_clear_sram(struct ieee80211_hw *dev)
282 {
283 struct adm8211_priv *priv = dev->priv;
284 u32 reg = ADM8211_CSR_READ(WEPCTL);
285 unsigned int addr;
286
287 for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
288 adm8211_write_sram(dev, addr, 0);
289
290 ADM8211_CSR_WRITE(WEPCTL, reg);
291 }
292
293 static int adm8211_get_stats(struct ieee80211_hw *dev,
294 struct ieee80211_low_level_stats *stats)
295 {
296 struct adm8211_priv *priv = dev->priv;
297
298 memcpy(stats, &priv->stats, sizeof(*stats));
299
300 return 0;
301 }
302
303 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
304 {
305 struct adm8211_priv *priv = dev->priv;
306 unsigned int dirty_tx;
307
308 spin_lock(&priv->lock);
309
310 for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
311 unsigned int entry = dirty_tx % priv->tx_ring_size;
312 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
313 struct ieee80211_tx_info *txi;
314 struct adm8211_tx_ring_info *info;
315 struct sk_buff *skb;
316
317 if (status & TDES0_CONTROL_OWN ||
318 !(status & TDES0_CONTROL_DONE))
319 break;
320
321 info = &priv->tx_buffers[entry];
322 skb = info->skb;
323 txi = IEEE80211_SKB_CB(skb);
324
325 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
326
327 dma_unmap_single(&priv->pdev->dev, info->mapping,
328 info->skb->len, DMA_TO_DEVICE);
329
330 ieee80211_tx_info_clear_status(txi);
331
332 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
333 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
334 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
335 !(status & TDES0_STATUS_ES))
336 txi->flags |= IEEE80211_TX_STAT_ACK;
337
338 ieee80211_tx_status_irqsafe(dev, skb);
339
340 info->skb = NULL;
341 }
342
343 if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
344 ieee80211_wake_queue(dev, 0);
345
346 priv->dirty_tx = dirty_tx;
347 spin_unlock(&priv->lock);
348 }
349
350
351 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
352 {
353 struct adm8211_priv *priv = dev->priv;
354 unsigned int entry = priv->cur_rx % priv->rx_ring_size;
355 u32 status;
356 unsigned int pktlen;
357 struct sk_buff *skb, *newskb;
358 unsigned int limit = priv->rx_ring_size;
359 u8 rssi, rate;
360
361 while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
362 if (!limit--)
363 break;
364
365 status = le32_to_cpu(priv->rx_ring[entry].status);
366 rate = (status & RDES0_STATUS_RXDR) >> 12;
367 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
368 RDES1_STATUS_RSSI;
369
370 pktlen = status & RDES0_STATUS_FL;
371 if (pktlen > RX_PKT_SIZE) {
372 if (net_ratelimit())
373 wiphy_debug(dev->wiphy, "frame too long (%d)\n",
374 pktlen);
375 pktlen = RX_PKT_SIZE;
376 }
377
378 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
379 skb = NULL; /* old buffer will be reused */
380 /* TODO: update RX error stats */
381 /* TODO: check RDES0_STATUS_CRC*E */
382 } else if (pktlen < RX_COPY_BREAK) {
383 skb = dev_alloc_skb(pktlen);
384 if (skb) {
385 dma_sync_single_for_cpu(&priv->pdev->dev,
386 priv->rx_buffers[entry].mapping,
387 pktlen,
388 DMA_FROM_DEVICE);
389 skb_put_data(skb,
390 skb_tail_pointer(priv->rx_buffers[entry].skb),
391 pktlen);
392 dma_sync_single_for_device(&priv->pdev->dev,
393 priv->rx_buffers[entry].mapping,
394 RX_PKT_SIZE,
395 DMA_FROM_DEVICE);
396 }
397 } else {
398 newskb = dev_alloc_skb(RX_PKT_SIZE);
399 if (newskb) {
400 skb = priv->rx_buffers[entry].skb;
401 skb_put(skb, pktlen);
402 dma_unmap_single(&priv->pdev->dev,
403 priv->rx_buffers[entry].mapping,
404 RX_PKT_SIZE, DMA_FROM_DEVICE);
405 priv->rx_buffers[entry].skb = newskb;
406 priv->rx_buffers[entry].mapping =
407 dma_map_single(&priv->pdev->dev,
408 skb_tail_pointer(newskb),
409 RX_PKT_SIZE,
410 DMA_FROM_DEVICE);
411 if (dma_mapping_error(&priv->pdev->dev,
412 priv->rx_buffers[entry].mapping)) {
413 priv->rx_buffers[entry].skb = NULL;
414 dev_kfree_skb(newskb);
415 skb = NULL;
416 /* TODO: update rx dropped stats */
417 }
418 } else {
419 skb = NULL;
420 /* TODO: update rx dropped stats */
421 }
422
423 priv->rx_ring[entry].buffer1 =
424 cpu_to_le32(priv->rx_buffers[entry].mapping);
425 }
426
427 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
428 RDES0_STATUS_SQL);
429 priv->rx_ring[entry].length =
430 cpu_to_le32(RX_PKT_SIZE |
431 (entry == priv->rx_ring_size - 1 ?
432 RDES1_CONTROL_RER : 0));
433
434 if (skb) {
435 struct ieee80211_rx_status rx_status = {0};
436
437 if (priv->pdev->revision < ADM8211_REV_CA)
438 rx_status.signal = rssi;
439 else
440 rx_status.signal = 100 - rssi;
441
442 rx_status.rate_idx = rate;
443
444 rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
445 rx_status.band = NL80211_BAND_2GHZ;
446
447 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
448 ieee80211_rx_irqsafe(dev, skb);
449 }
450
451 entry = (++priv->cur_rx) % priv->rx_ring_size;
452 }
453
454 /* TODO: check LPC and update stats? */
455 }
456
457
458 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
459 {
460 #define ADM8211_INT(x) \
461 do { \
462 if (unlikely(stsr & ADM8211_STSR_ ## x)) \
463 wiphy_debug(dev->wiphy, "%s\n", #x); \
464 } while (0)
465
466 struct ieee80211_hw *dev = dev_id;
467 struct adm8211_priv *priv = dev->priv;
468 u32 stsr = ADM8211_CSR_READ(STSR);
469 ADM8211_CSR_WRITE(STSR, stsr);
470 if (stsr == 0xffffffff)
471 return IRQ_HANDLED;
472
473 if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
474 return IRQ_HANDLED;
475
476 if (stsr & ADM8211_STSR_RCI)
477 adm8211_interrupt_rci(dev);
478 if (stsr & ADM8211_STSR_TCI)
479 adm8211_interrupt_tci(dev);
480
481 ADM8211_INT(PCF);
482 ADM8211_INT(BCNTC);
483 ADM8211_INT(GPINT);
484 ADM8211_INT(ATIMTC);
485 ADM8211_INT(TSFTF);
486 ADM8211_INT(TSCZ);
487 ADM8211_INT(SQL);
488 ADM8211_INT(WEPTD);
489 ADM8211_INT(ATIME);
490 ADM8211_INT(TEIS);
491 ADM8211_INT(FBE);
492 ADM8211_INT(REIS);
493 ADM8211_INT(GPTT);
494 ADM8211_INT(RPS);
495 ADM8211_INT(RDU);
496 ADM8211_INT(TUF);
497 ADM8211_INT(TPS);
498
499 return IRQ_HANDLED;
500
501 #undef ADM8211_INT
502 }
503
504 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
505 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev, \
506 u16 addr, u32 value) { \
507 struct adm8211_priv *priv = dev->priv; \
508 unsigned int i; \
509 u32 reg, bitbuf; \
510 \
511 value &= v_mask; \
512 addr &= a_mask; \
513 bitbuf = (value << v_shift) | (addr << a_shift); \
514 \
515 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1); \
516 ADM8211_CSR_READ(SYNRF); \
517 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0); \
518 ADM8211_CSR_READ(SYNRF); \
519 \
520 if (prewrite) { \
521 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0); \
522 ADM8211_CSR_READ(SYNRF); \
523 } \
524 \
525 for (i = 0; i <= bits; i++) { \
526 if (bitbuf & (1 << (bits - i))) \
527 reg = ADM8211_SYNRF_WRITE_SYNDATA_1; \
528 else \
529 reg = ADM8211_SYNRF_WRITE_SYNDATA_0; \
530 \
531 ADM8211_CSR_WRITE(SYNRF, reg); \
532 ADM8211_CSR_READ(SYNRF); \
533 \
534 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
535 ADM8211_CSR_READ(SYNRF); \
536 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
537 ADM8211_CSR_READ(SYNRF); \
538 } \
539 \
540 if (postwrite == 1) { \
541 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0); \
542 ADM8211_CSR_READ(SYNRF); \
543 } \
544 if (postwrite == 2) { \
545 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1); \
546 ADM8211_CSR_READ(SYNRF); \
547 } \
548 \
549 ADM8211_CSR_WRITE(SYNRF, 0); \
550 ADM8211_CSR_READ(SYNRF); \
551 }
552
553 WRITE_SYN(max2820, 0x00FFF, 0, 0x0F, 12, 15, 1, 1)
554 WRITE_SYN(al2210l, 0xFFFFF, 4, 0x0F, 0, 23, 1, 1)
555 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
556 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F, 0, 21, 0, 2)
557
558 #undef WRITE_SYN
559
560 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
561 {
562 struct adm8211_priv *priv = dev->priv;
563 unsigned int timeout;
564 u32 reg;
565
566 timeout = 10;
567 while (timeout > 0) {
568 reg = ADM8211_CSR_READ(BBPCTL);
569 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
570 break;
571 timeout--;
572 msleep(2);
573 }
574
575 if (timeout == 0) {
576 wiphy_debug(dev->wiphy,
577 "adm8211_write_bbp(%d,%d) failed prewrite (reg=0x%08x)\n",
578 addr, data, reg);
579 return -ETIMEDOUT;
580 }
581
582 switch (priv->bbp_type) {
583 case ADM8211_TYPE_INTERSIL:
584 reg = ADM8211_BBPCTL_MMISEL; /* three wire interface */
585 break;
586 case ADM8211_TYPE_RFMD:
587 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
588 (0x01 << 18);
589 break;
590 case ADM8211_TYPE_ADMTEK:
591 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
592 (0x05 << 18);
593 break;
594 }
595 reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
596
597 ADM8211_CSR_WRITE(BBPCTL, reg);
598
599 timeout = 10;
600 while (timeout > 0) {
601 reg = ADM8211_CSR_READ(BBPCTL);
602 if (!(reg & ADM8211_BBPCTL_WR))
603 break;
604 timeout--;
605 msleep(2);
606 }
607
608 if (timeout == 0) {
609 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
610 ~ADM8211_BBPCTL_WR);
611 wiphy_debug(dev->wiphy,
612 "adm8211_write_bbp(%d,%d) failed postwrite (reg=0x%08x)\n",
613 addr, data, reg);
614 return -ETIMEDOUT;
615 }
616
617 return 0;
618 }
619
620 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
621 {
622 static const u32 adm8211_rfmd2958_reg5[] =
623 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
624 0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
625 static const u32 adm8211_rfmd2958_reg6[] =
626 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
627 0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
628
629 struct adm8211_priv *priv = dev->priv;
630 u8 ant_power = priv->ant_power > 0x3F ?
631 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
632 u8 tx_power = priv->tx_power > 0x3F ?
633 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
634 u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
635 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
636 u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
637 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
638 u32 reg;
639
640 ADM8211_IDLE();
641
642 /* Program synthesizer to new channel */
643 switch (priv->transceiver_type) {
644 case ADM8211_RFMD2958:
645 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
646 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
647 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
648
649 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
650 adm8211_rfmd2958_reg5[chan - 1]);
651 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
652 adm8211_rfmd2958_reg6[chan - 1]);
653 break;
654
655 case ADM8211_RFMD2948:
656 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
657 SI4126_MAIN_XINDIV2);
658 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
659 SI4126_POWERDOWN_PDIB |
660 SI4126_POWERDOWN_PDRB);
661 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
662 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
663 (chan == 14 ?
664 2110 : (2033 + (chan * 5))));
665 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
666 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
667 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
668 break;
669
670 case ADM8211_MAX2820:
671 adm8211_rf_write_syn_max2820(dev, 0x3,
672 (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
673 break;
674
675 case ADM8211_AL2210L:
676 adm8211_rf_write_syn_al2210l(dev, 0x0,
677 (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
678 break;
679
680 default:
681 wiphy_debug(dev->wiphy, "unsupported transceiver type %d\n",
682 priv->transceiver_type);
683 break;
684 }
685
686 /* write BBP regs */
687 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
688
689 /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
690 /* TODO: remove if SMC 2635W doesn't need this */
691 if (priv->transceiver_type == ADM8211_RFMD2948) {
692 reg = ADM8211_CSR_READ(GPIO);
693 reg &= 0xfffc0000;
694 reg |= ADM8211_CSR_GPIO_EN0;
695 if (chan != 14)
696 reg |= ADM8211_CSR_GPIO_O0;
697 ADM8211_CSR_WRITE(GPIO, reg);
698 }
699
700 if (priv->transceiver_type == ADM8211_RFMD2958) {
701 /* set PCNT2 */
702 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
703 /* set PCNT1 P_DESIRED/MID_BIAS */
704 reg = le16_to_cpu(priv->eeprom->cr49);
705 reg >>= 13;
706 reg <<= 15;
707 reg |= ant_power << 9;
708 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
709 /* set TXRX TX_GAIN */
710 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
711 (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
712 } else {
713 reg = ADM8211_CSR_READ(PLCPHD);
714 reg &= 0xff00ffff;
715 reg |= tx_power << 18;
716 ADM8211_CSR_WRITE(PLCPHD, reg);
717 }
718
719 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
720 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
721 ADM8211_CSR_READ(SYNRF);
722 msleep(30);
723
724 /* RF3000 BBP */
725 if (priv->transceiver_type != ADM8211_RFMD2958)
726 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
727 tx_power<<2);
728 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
729 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
730 adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
731 priv->eeprom->cr28 : 0);
732 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
733
734 ADM8211_CSR_WRITE(SYNRF, 0);
735
736 /* Nothing to do for ADMtek BBP */
737 } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
738 wiphy_debug(dev->wiphy, "unsupported BBP type %d\n",
739 priv->bbp_type);
740
741 ADM8211_RESTORE();
742
743 /* update current channel for adhoc (and maybe AP mode) */
744 reg = ADM8211_CSR_READ(CAP0);
745 reg &= ~0xF;
746 reg |= chan;
747 ADM8211_CSR_WRITE(CAP0, reg);
748
749 return 0;
750 }
751
752 static void adm8211_update_mode(struct ieee80211_hw *dev)
753 {
754 struct adm8211_priv *priv = dev->priv;
755
756 ADM8211_IDLE();
757
758 priv->soft_rx_crc = 0;
759 switch (priv->mode) {
760 case NL80211_IFTYPE_STATION:
761 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
762 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
763 break;
764 case NL80211_IFTYPE_ADHOC:
765 priv->nar &= ~ADM8211_NAR_PR;
766 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
767
768 /* don't trust the error bits on rev 0x20 and up in adhoc */
769 if (priv->pdev->revision >= ADM8211_REV_BA)
770 priv->soft_rx_crc = 1;
771 break;
772 case NL80211_IFTYPE_MONITOR:
773 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
774 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
775 break;
776 }
777
778 ADM8211_RESTORE();
779 }
780
781 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
782 {
783 struct adm8211_priv *priv = dev->priv;
784
785 switch (priv->transceiver_type) {
786 case ADM8211_RFMD2958:
787 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
788 /* comments taken from ADMtek vendor driver */
789
790 /* Reset RF2958 after power on */
791 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
792 /* Initialize RF VCO Core Bias to maximum */
793 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
794 /* Initialize IF PLL */
795 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
796 /* Initialize IF PLL Coarse Tuning */
797 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
798 /* Initialize RF PLL */
799 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
800 /* Initialize RF PLL Coarse Tuning */
801 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
802 /* Initialize TX gain and filter BW (R9) */
803 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
804 (priv->transceiver_type == ADM8211_RFMD2958 ?
805 0x10050 : 0x00050));
806 /* Initialize CAL register */
807 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
808 break;
809
810 case ADM8211_MAX2820:
811 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
812 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
813 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
814 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
815 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
816 break;
817
818 case ADM8211_AL2210L:
819 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
820 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
821 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
822 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
823 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
824 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
825 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
826 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
827 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
828 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
829 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
830 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
831 break;
832
833 case ADM8211_RFMD2948:
834 default:
835 break;
836 }
837 }
838
839 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
840 {
841 struct adm8211_priv *priv = dev->priv;
842 u32 reg;
843
844 /* write addresses */
845 if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
846 ADM8211_CSR_WRITE(MMIWA, 0x100E0C0A);
847 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
848 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
849 } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
850 priv->bbp_type == ADM8211_TYPE_ADMTEK) {
851 /* check specific BBP type */
852 switch (priv->specific_bbptype) {
853 case ADM8211_BBP_RFMD3000:
854 case ADM8211_BBP_RFMD3002:
855 ADM8211_CSR_WRITE(MMIWA, 0x00009101);
856 ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
857 break;
858
859 case ADM8211_BBP_ADM8011:
860 ADM8211_CSR_WRITE(MMIWA, 0x00008903);
861 ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
862
863 reg = ADM8211_CSR_READ(BBPCTL);
864 reg &= ~ADM8211_BBPCTL_TYPE;
865 reg |= 0x5 << 18;
866 ADM8211_CSR_WRITE(BBPCTL, reg);
867 break;
868 }
869
870 switch (priv->pdev->revision) {
871 case ADM8211_REV_CA:
872 if (priv->transceiver_type == ADM8211_RFMD2958 ||
873 priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
874 priv->transceiver_type == ADM8211_RFMD2948)
875 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
876 else if (priv->transceiver_type == ADM8211_MAX2820 ||
877 priv->transceiver_type == ADM8211_AL2210L)
878 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
879 break;
880
881 case ADM8211_REV_BA:
882 reg = ADM8211_CSR_READ(MMIRD1);
883 reg &= 0x0000FFFF;
884 reg |= 0x7e100000;
885 ADM8211_CSR_WRITE(MMIRD1, reg);
886 break;
887
888 case ADM8211_REV_AB:
889 case ADM8211_REV_AF:
890 default:
891 ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
892 break;
893 }
894
895 /* For RFMD */
896 ADM8211_CSR_WRITE(MACTEST, 0x800);
897 }
898
899 adm8211_hw_init_syn(dev);
900
901 /* Set RF Power control IF pin to PE1+PHYRST# */
902 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
903 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
904 ADM8211_CSR_READ(SYNRF);
905 msleep(20);
906
907 /* write BBP regs */
908 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
909 /* RF3000 BBP */
910 /* another set:
911 * 11: c8
912 * 14: 14
913 * 15: 50 (chan 1..13; chan 14: d0)
914 * 1c: 00
915 * 1d: 84
916 */
917 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
918 /* antenna selection: diversity */
919 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
920 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
921 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
922 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
923
924 if (priv->eeprom->major_version < 2) {
925 adm8211_write_bbp(dev, 0x1c, 0x00);
926 adm8211_write_bbp(dev, 0x1d, 0x80);
927 } else {
928 if (priv->pdev->revision == ADM8211_REV_BA)
929 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
930 else
931 adm8211_write_bbp(dev, 0x1c, 0x00);
932
933 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
934 }
935 } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
936 /* reset baseband */
937 adm8211_write_bbp(dev, 0x00, 0xFF);
938 /* antenna selection: diversity */
939 adm8211_write_bbp(dev, 0x07, 0x0A);
940
941 /* TODO: find documentation for this */
942 switch (priv->transceiver_type) {
943 case ADM8211_RFMD2958:
944 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
945 adm8211_write_bbp(dev, 0x00, 0x00);
946 adm8211_write_bbp(dev, 0x01, 0x00);
947 adm8211_write_bbp(dev, 0x02, 0x00);
948 adm8211_write_bbp(dev, 0x03, 0x00);
949 adm8211_write_bbp(dev, 0x06, 0x0f);
950 adm8211_write_bbp(dev, 0x09, 0x00);
951 adm8211_write_bbp(dev, 0x0a, 0x00);
952 adm8211_write_bbp(dev, 0x0b, 0x00);
953 adm8211_write_bbp(dev, 0x0c, 0x00);
954 adm8211_write_bbp(dev, 0x0f, 0xAA);
955 adm8211_write_bbp(dev, 0x10, 0x8c);
956 adm8211_write_bbp(dev, 0x11, 0x43);
957 adm8211_write_bbp(dev, 0x18, 0x40);
958 adm8211_write_bbp(dev, 0x20, 0x23);
959 adm8211_write_bbp(dev, 0x21, 0x02);
960 adm8211_write_bbp(dev, 0x22, 0x28);
961 adm8211_write_bbp(dev, 0x23, 0x30);
962 adm8211_write_bbp(dev, 0x24, 0x2d);
963 adm8211_write_bbp(dev, 0x28, 0x35);
964 adm8211_write_bbp(dev, 0x2a, 0x8c);
965 adm8211_write_bbp(dev, 0x2b, 0x81);
966 adm8211_write_bbp(dev, 0x2c, 0x44);
967 adm8211_write_bbp(dev, 0x2d, 0x0A);
968 adm8211_write_bbp(dev, 0x29, 0x40);
969 adm8211_write_bbp(dev, 0x60, 0x08);
970 adm8211_write_bbp(dev, 0x64, 0x01);
971 break;
972
973 case ADM8211_MAX2820:
974 adm8211_write_bbp(dev, 0x00, 0x00);
975 adm8211_write_bbp(dev, 0x01, 0x00);
976 adm8211_write_bbp(dev, 0x02, 0x00);
977 adm8211_write_bbp(dev, 0x03, 0x00);
978 adm8211_write_bbp(dev, 0x06, 0x0f);
979 adm8211_write_bbp(dev, 0x09, 0x05);
980 adm8211_write_bbp(dev, 0x0a, 0x02);
981 adm8211_write_bbp(dev, 0x0b, 0x00);
982 adm8211_write_bbp(dev, 0x0c, 0x0f);
983 adm8211_write_bbp(dev, 0x0f, 0x55);
984 adm8211_write_bbp(dev, 0x10, 0x8d);
985 adm8211_write_bbp(dev, 0x11, 0x43);
986 adm8211_write_bbp(dev, 0x18, 0x4a);
987 adm8211_write_bbp(dev, 0x20, 0x20);
988 adm8211_write_bbp(dev, 0x21, 0x02);
989 adm8211_write_bbp(dev, 0x22, 0x23);
990 adm8211_write_bbp(dev, 0x23, 0x30);
991 adm8211_write_bbp(dev, 0x24, 0x2d);
992 adm8211_write_bbp(dev, 0x2a, 0x8c);
993 adm8211_write_bbp(dev, 0x2b, 0x81);
994 adm8211_write_bbp(dev, 0x2c, 0x44);
995 adm8211_write_bbp(dev, 0x29, 0x4a);
996 adm8211_write_bbp(dev, 0x60, 0x2b);
997 adm8211_write_bbp(dev, 0x64, 0x01);
998 break;
999
1000 case ADM8211_AL2210L:
1001 adm8211_write_bbp(dev, 0x00, 0x00);
1002 adm8211_write_bbp(dev, 0x01, 0x00);
1003 adm8211_write_bbp(dev, 0x02, 0x00);
1004 adm8211_write_bbp(dev, 0x03, 0x00);
1005 adm8211_write_bbp(dev, 0x06, 0x0f);
1006 adm8211_write_bbp(dev, 0x07, 0x05);
1007 adm8211_write_bbp(dev, 0x08, 0x03);
1008 adm8211_write_bbp(dev, 0x09, 0x00);
1009 adm8211_write_bbp(dev, 0x0a, 0x00);
1010 adm8211_write_bbp(dev, 0x0b, 0x00);
1011 adm8211_write_bbp(dev, 0x0c, 0x10);
1012 adm8211_write_bbp(dev, 0x0f, 0x55);
1013 adm8211_write_bbp(dev, 0x10, 0x8d);
1014 adm8211_write_bbp(dev, 0x11, 0x43);
1015 adm8211_write_bbp(dev, 0x18, 0x4a);
1016 adm8211_write_bbp(dev, 0x20, 0x20);
1017 adm8211_write_bbp(dev, 0x21, 0x02);
1018 adm8211_write_bbp(dev, 0x22, 0x23);
1019 adm8211_write_bbp(dev, 0x23, 0x30);
1020 adm8211_write_bbp(dev, 0x24, 0x2d);
1021 adm8211_write_bbp(dev, 0x2a, 0xaa);
1022 adm8211_write_bbp(dev, 0x2b, 0x81);
1023 adm8211_write_bbp(dev, 0x2c, 0x44);
1024 adm8211_write_bbp(dev, 0x29, 0xfa);
1025 adm8211_write_bbp(dev, 0x60, 0x2d);
1026 adm8211_write_bbp(dev, 0x64, 0x01);
1027 break;
1028
1029 case ADM8211_RFMD2948:
1030 break;
1031
1032 default:
1033 wiphy_debug(dev->wiphy, "unsupported transceiver %d\n",
1034 priv->transceiver_type);
1035 break;
1036 }
1037 } else
1038 wiphy_debug(dev->wiphy, "unsupported BBP %d\n", priv->bbp_type);
1039
1040 ADM8211_CSR_WRITE(SYNRF, 0);
1041
1042 /* Set RF CAL control source to MAC control */
1043 reg = ADM8211_CSR_READ(SYNCTL);
1044 reg |= ADM8211_SYNCTL_SELCAL;
1045 ADM8211_CSR_WRITE(SYNCTL, reg);
1046
1047 return 0;
1048 }
1049
1050 /* configures hw beacons/probe responses */
1051 static int adm8211_set_rate(struct ieee80211_hw *dev)
1052 {
1053 struct adm8211_priv *priv = dev->priv;
1054 u32 reg;
1055 int i = 0;
1056 u8 rate_buf[12] = {0};
1057
1058 /* write supported rates */
1059 if (priv->pdev->revision != ADM8211_REV_BA) {
1060 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1061 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1062 rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1063 } else {
1064 /* workaround for rev BA specific bug */
1065 rate_buf[0] = 0x04;
1066 rate_buf[1] = 0x82;
1067 rate_buf[2] = 0x04;
1068 rate_buf[3] = 0x0b;
1069 rate_buf[4] = 0x16;
1070 }
1071
1072 adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1073 ARRAY_SIZE(adm8211_rates) + 1);
1074
1075 reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1076 reg |= 1 << 15; /* short preamble */
1077 reg |= 110 << 24;
1078 ADM8211_CSR_WRITE(PLCPHD, reg);
1079
1080 /* MTMLT = 512 TU (max TX MSDU lifetime)
1081 * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1082 * SRTYLIM = 224 (short retry limit, TX header value is default) */
1083 ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1084
1085 return 0;
1086 }
1087
1088 static void adm8211_hw_init(struct ieee80211_hw *dev)
1089 {
1090 struct adm8211_priv *priv = dev->priv;
1091 u32 reg;
1092 u8 cline;
1093
1094 reg = ADM8211_CSR_READ(PAR);
1095 reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1096 reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1097
1098 if (!pci_set_mwi(priv->pdev)) {
1099 reg |= 0x1 << 24;
1100 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1101
1102 switch (cline) {
1103 case 0x8:
1104 reg |= (0x1 << 14);
1105 break;
1106 case 0x10:
1107 reg |= (0x2 << 14);
1108 break;
1109 case 0x20:
1110 reg |= (0x3 << 14);
1111 break;
1112 default:
1113 reg |= (0x0 << 14);
1114 break;
1115 }
1116 }
1117
1118 ADM8211_CSR_WRITE(PAR, reg);
1119
1120 reg = ADM8211_CSR_READ(CSR_TEST1);
1121 reg &= ~(0xF << 28);
1122 reg |= (1 << 28) | (1 << 31);
1123 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1124
1125 /* lose link after 4 lost beacons */
1126 reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1127 ADM8211_CSR_WRITE(WCSR, reg);
1128
1129 /* Disable APM, enable receive FIFO threshold, and set drain receive
1130 * threshold to store-and-forward */
1131 reg = ADM8211_CSR_READ(CMDR);
1132 reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1133 reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1134 ADM8211_CSR_WRITE(CMDR, reg);
1135
1136 adm8211_set_rate(dev);
1137
1138 /* 4-bit values:
1139 * PWR1UP = 8 * 2 ms
1140 * PWR0PAPE = 8 us or 5 us
1141 * PWR1PAPE = 1 us or 3 us
1142 * PWR0TRSW = 5 us
1143 * PWR1TRSW = 12 us
1144 * PWR0PE2 = 13 us
1145 * PWR1PE2 = 1 us
1146 * PWR0TXPE = 8 or 6 */
1147 if (priv->pdev->revision < ADM8211_REV_CA)
1148 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1149 else
1150 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1151
1152 /* Enable store and forward for transmit */
1153 priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1154 ADM8211_CSR_WRITE(NAR, priv->nar);
1155
1156 /* Reset RF */
1157 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1158 ADM8211_CSR_READ(SYNRF);
1159 msleep(10);
1160 ADM8211_CSR_WRITE(SYNRF, 0);
1161 ADM8211_CSR_READ(SYNRF);
1162 msleep(5);
1163
1164 /* Set CFP Max Duration to 0x10 TU */
1165 reg = ADM8211_CSR_READ(CFPP);
1166 reg &= ~(0xffff << 8);
1167 reg |= 0x0010 << 8;
1168 ADM8211_CSR_WRITE(CFPP, reg);
1169
1170 /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1171 * TUCNT = 0x3ff - Tu counter 1024 us */
1172 ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1173
1174 /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1175 * DIFS=50 us, EIFS=100 us */
1176 if (priv->pdev->revision < ADM8211_REV_CA)
1177 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1178 (50 << 9) | 100);
1179 else
1180 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1181 (50 << 9) | 100);
1182
1183 /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1184 * RMRD = 2346 * 8 + 1 us (max RX duration) */
1185 ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1186
1187 /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1188 ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1189
1190 /* Initialize BBP (and SYN) */
1191 adm8211_hw_init_bbp(dev);
1192
1193 /* make sure interrupts are off */
1194 ADM8211_CSR_WRITE(IER, 0);
1195
1196 /* ACK interrupts */
1197 ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1198
1199 /* Setup WEP (turns it off for now) */
1200 reg = ADM8211_CSR_READ(MACTEST);
1201 reg &= ~(7 << 20);
1202 ADM8211_CSR_WRITE(MACTEST, reg);
1203
1204 reg = ADM8211_CSR_READ(WEPCTL);
1205 reg &= ~ADM8211_WEPCTL_WEPENABLE;
1206 reg |= ADM8211_WEPCTL_WEPRXBYP;
1207 ADM8211_CSR_WRITE(WEPCTL, reg);
1208
1209 /* Clear the missed-packet counter. */
1210 ADM8211_CSR_READ(LPC);
1211 }
1212
1213 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1214 {
1215 struct adm8211_priv *priv = dev->priv;
1216 u32 reg, tmp;
1217 int timeout = 100;
1218
1219 /* Power-on issue */
1220 /* TODO: check if this is necessary */
1221 ADM8211_CSR_WRITE(FRCTL, 0);
1222
1223 /* Reset the chip */
1224 tmp = ADM8211_CSR_READ(PAR);
1225 ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1226
1227 while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1228 msleep(50);
1229
1230 if (timeout <= 0)
1231 return -ETIMEDOUT;
1232
1233 ADM8211_CSR_WRITE(PAR, tmp);
1234
1235 if (priv->pdev->revision == ADM8211_REV_BA &&
1236 (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1237 priv->transceiver_type == ADM8211_RFMD2958)) {
1238 reg = ADM8211_CSR_READ(CSR_TEST1);
1239 reg |= (1 << 4) | (1 << 5);
1240 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1241 } else if (priv->pdev->revision == ADM8211_REV_CA) {
1242 reg = ADM8211_CSR_READ(CSR_TEST1);
1243 reg &= ~((1 << 4) | (1 << 5));
1244 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1245 }
1246
1247 ADM8211_CSR_WRITE(FRCTL, 0);
1248
1249 reg = ADM8211_CSR_READ(CSR_TEST0);
1250 reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1251 ADM8211_CSR_WRITE(CSR_TEST0, reg);
1252
1253 adm8211_clear_sram(dev);
1254
1255 return 0;
1256 }
1257
1258 static u64 adm8211_get_tsft(struct ieee80211_hw *dev,
1259 struct ieee80211_vif *vif)
1260 {
1261 struct adm8211_priv *priv = dev->priv;
1262 u32 tsftl;
1263 u64 tsft;
1264
1265 tsftl = ADM8211_CSR_READ(TSFTL);
1266 tsft = ADM8211_CSR_READ(TSFTH);
1267 tsft <<= 32;
1268 tsft |= tsftl;
1269
1270 return tsft;
1271 }
1272
1273 static void adm8211_set_interval(struct ieee80211_hw *dev,
1274 unsigned short bi, unsigned short li)
1275 {
1276 struct adm8211_priv *priv = dev->priv;
1277 u32 reg;
1278
1279 /* BP (beacon interval) = data->beacon_interval
1280 * LI (listen interval) = data->listen_interval (in beacon intervals) */
1281 reg = (bi << 16) | li;
1282 ADM8211_CSR_WRITE(BPLI, reg);
1283 }
1284
1285 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1286 {
1287 struct adm8211_priv *priv = dev->priv;
1288 u32 reg;
1289
1290 ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1291 reg = ADM8211_CSR_READ(ABDA1);
1292 reg &= 0x0000ffff;
1293 reg |= (bssid[4] << 16) | (bssid[5] << 24);
1294 ADM8211_CSR_WRITE(ABDA1, reg);
1295 }
1296
1297 static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
1298 {
1299 struct adm8211_priv *priv = dev->priv;
1300 struct ieee80211_conf *conf = &dev->conf;
1301 int channel =
1302 ieee80211_frequency_to_channel(conf->chandef.chan->center_freq);
1303
1304 if (channel != priv->channel) {
1305 priv->channel = channel;
1306 adm8211_rf_set_channel(dev, priv->channel);
1307 }
1308
1309 return 0;
1310 }
1311
1312 static void adm8211_bss_info_changed(struct ieee80211_hw *dev,
1313 struct ieee80211_vif *vif,
1314 struct ieee80211_bss_conf *conf,
1315 u32 changes)
1316 {
1317 struct adm8211_priv *priv = dev->priv;
1318
1319 if (!(changes & BSS_CHANGED_BSSID))
1320 return;
1321
1322 if (!ether_addr_equal(conf->bssid, priv->bssid)) {
1323 adm8211_set_bssid(dev, conf->bssid);
1324 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1325 }
1326 }
1327
1328 static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw,
1329 struct netdev_hw_addr_list *mc_list)
1330 {
1331 unsigned int bit_nr;
1332 u32 mc_filter[2];
1333 struct netdev_hw_addr *ha;
1334
1335 mc_filter[1] = mc_filter[0] = 0;
1336
1337 netdev_hw_addr_list_for_each(ha, mc_list) {
1338 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1339
1340 bit_nr &= 0x3F;
1341 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1342 }
1343
1344 return mc_filter[0] | ((u64)(mc_filter[1]) << 32);
1345 }
1346
1347 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1348 unsigned int changed_flags,
1349 unsigned int *total_flags,
1350 u64 multicast)
1351 {
1352 static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1353 struct adm8211_priv *priv = dev->priv;
1354 unsigned int new_flags;
1355 u32 mc_filter[2];
1356
1357 mc_filter[0] = multicast;
1358 mc_filter[1] = multicast >> 32;
1359
1360 new_flags = 0;
1361
1362 if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) {
1363 new_flags |= FIF_ALLMULTI;
1364 priv->nar &= ~ADM8211_NAR_PR;
1365 priv->nar |= ADM8211_NAR_MM;
1366 mc_filter[1] = mc_filter[0] = ~0;
1367 } else {
1368 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1369 }
1370
1371 ADM8211_IDLE_RX();
1372
1373 ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1374 ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1375 ADM8211_CSR_READ(NAR);
1376
1377 if (priv->nar & ADM8211_NAR_PR)
1378 ieee80211_hw_set(dev, RX_INCLUDES_FCS);
1379 else
1380 __clear_bit(IEEE80211_HW_RX_INCLUDES_FCS, dev->flags);
1381
1382 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1383 adm8211_set_bssid(dev, bcast);
1384 else
1385 adm8211_set_bssid(dev, priv->bssid);
1386
1387 ADM8211_RESTORE();
1388
1389 *total_flags = new_flags;
1390 }
1391
1392 static int adm8211_add_interface(struct ieee80211_hw *dev,
1393 struct ieee80211_vif *vif)
1394 {
1395 struct adm8211_priv *priv = dev->priv;
1396 if (priv->mode != NL80211_IFTYPE_MONITOR)
1397 return -EOPNOTSUPP;
1398
1399 switch (vif->type) {
1400 case NL80211_IFTYPE_STATION:
1401 priv->mode = vif->type;
1402 break;
1403 default:
1404 return -EOPNOTSUPP;
1405 }
1406
1407 ADM8211_IDLE();
1408
1409 ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)vif->addr));
1410 ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1411
1412 adm8211_update_mode(dev);
1413
1414 ADM8211_RESTORE();
1415
1416 return 0;
1417 }
1418
1419 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1420 struct ieee80211_vif *vif)
1421 {
1422 struct adm8211_priv *priv = dev->priv;
1423 priv->mode = NL80211_IFTYPE_MONITOR;
1424 }
1425
1426 static int adm8211_init_rings(struct ieee80211_hw *dev)
1427 {
1428 struct adm8211_priv *priv = dev->priv;
1429 struct adm8211_desc *desc = NULL;
1430 struct adm8211_rx_ring_info *rx_info;
1431 struct adm8211_tx_ring_info *tx_info;
1432 unsigned int i;
1433
1434 for (i = 0; i < priv->rx_ring_size; i++) {
1435 desc = &priv->rx_ring[i];
1436 desc->status = 0;
1437 desc->length = cpu_to_le32(RX_PKT_SIZE);
1438 priv->rx_buffers[i].skb = NULL;
1439 }
1440 /* Mark the end of RX ring; hw returns to base address after this
1441 * descriptor */
1442 desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1443
1444 for (i = 0; i < priv->rx_ring_size; i++) {
1445 desc = &priv->rx_ring[i];
1446 rx_info = &priv->rx_buffers[i];
1447
1448 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1449 if (rx_info->skb == NULL)
1450 break;
1451 rx_info->mapping = dma_map_single(&priv->pdev->dev,
1452 skb_tail_pointer(rx_info->skb),
1453 RX_PKT_SIZE,
1454 DMA_FROM_DEVICE);
1455 if (dma_mapping_error(&priv->pdev->dev, rx_info->mapping)) {
1456 dev_kfree_skb(rx_info->skb);
1457 rx_info->skb = NULL;
1458 break;
1459 }
1460
1461 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1462 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1463 }
1464
1465 /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1466 for (i = 0; i < priv->tx_ring_size; i++) {
1467 desc = &priv->tx_ring[i];
1468 tx_info = &priv->tx_buffers[i];
1469
1470 tx_info->skb = NULL;
1471 tx_info->mapping = 0;
1472 desc->status = 0;
1473 }
1474 desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1475
1476 priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1477 ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1478 ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1479
1480 return 0;
1481 }
1482
1483 static void adm8211_free_rings(struct ieee80211_hw *dev)
1484 {
1485 struct adm8211_priv *priv = dev->priv;
1486 unsigned int i;
1487
1488 for (i = 0; i < priv->rx_ring_size; i++) {
1489 if (!priv->rx_buffers[i].skb)
1490 continue;
1491
1492 dma_unmap_single(&priv->pdev->dev,
1493 priv->rx_buffers[i].mapping, RX_PKT_SIZE,
1494 DMA_FROM_DEVICE);
1495
1496 dev_kfree_skb(priv->rx_buffers[i].skb);
1497 }
1498
1499 for (i = 0; i < priv->tx_ring_size; i++) {
1500 if (!priv->tx_buffers[i].skb)
1501 continue;
1502
1503 dma_unmap_single(&priv->pdev->dev,
1504 priv->tx_buffers[i].mapping,
1505 priv->tx_buffers[i].skb->len, DMA_TO_DEVICE);
1506
1507 dev_kfree_skb(priv->tx_buffers[i].skb);
1508 }
1509 }
1510
1511 static int adm8211_start(struct ieee80211_hw *dev)
1512 {
1513 struct adm8211_priv *priv = dev->priv;
1514 int retval;
1515
1516 /* Power up MAC and RF chips */
1517 retval = adm8211_hw_reset(dev);
1518 if (retval) {
1519 wiphy_err(dev->wiphy, "hardware reset failed\n");
1520 goto fail;
1521 }
1522
1523 retval = adm8211_init_rings(dev);
1524 if (retval) {
1525 wiphy_err(dev->wiphy, "failed to initialize rings\n");
1526 goto fail;
1527 }
1528
1529 /* Init hardware */
1530 adm8211_hw_init(dev);
1531 adm8211_rf_set_channel(dev, priv->channel);
1532
1533 retval = request_irq(priv->pdev->irq, adm8211_interrupt,
1534 IRQF_SHARED, "adm8211", dev);
1535 if (retval) {
1536 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
1537 goto fail;
1538 }
1539
1540 ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1541 ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1542 ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1543 priv->mode = NL80211_IFTYPE_MONITOR;
1544 adm8211_update_mode(dev);
1545 ADM8211_CSR_WRITE(RDR, 0);
1546
1547 adm8211_set_interval(dev, 100, 10);
1548 return 0;
1549
1550 fail:
1551 return retval;
1552 }
1553
1554 static void adm8211_stop(struct ieee80211_hw *dev)
1555 {
1556 struct adm8211_priv *priv = dev->priv;
1557
1558 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1559 priv->nar = 0;
1560 ADM8211_CSR_WRITE(NAR, 0);
1561 ADM8211_CSR_WRITE(IER, 0);
1562 ADM8211_CSR_READ(NAR);
1563
1564 free_irq(priv->pdev->irq, dev);
1565
1566 adm8211_free_rings(dev);
1567 }
1568
1569 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1570 int plcp_signal, int short_preamble)
1571 {
1572 /* Alternative calculation from NetBSD: */
1573
1574 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1575 #define IEEE80211_DUR_DS_LONG_PREAMBLE 144
1576 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1577 #define IEEE80211_DUR_DS_FAST_PLCPHDR 24
1578 #define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
1579 #define IEEE80211_DUR_DS_SLOW_ACK 112
1580 #define IEEE80211_DUR_DS_FAST_ACK 56
1581 #define IEEE80211_DUR_DS_SLOW_CTS 112
1582 #define IEEE80211_DUR_DS_FAST_CTS 56
1583 #define IEEE80211_DUR_DS_SLOT 20
1584 #define IEEE80211_DUR_DS_SIFS 10
1585
1586 int remainder;
1587
1588 *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1589 / plcp_signal;
1590
1591 if (plcp_signal <= PLCP_SIGNAL_2M)
1592 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1593 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1594 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1595 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1596 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1597 else
1598 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1599 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1600 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1601 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1602 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1603
1604 /* lengthen duration if long preamble */
1605 if (!short_preamble)
1606 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1607 IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1608 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1609 IEEE80211_DUR_DS_FAST_PLCPHDR);
1610
1611
1612 *plcp = (80 * len) / plcp_signal;
1613 remainder = (80 * len) % plcp_signal;
1614 if (plcp_signal == PLCP_SIGNAL_11M &&
1615 remainder <= 30 && remainder > 0)
1616 *plcp = (*plcp | 0x8000) + 1;
1617 else if (remainder)
1618 (*plcp)++;
1619 }
1620
1621 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1622 static int adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1623 u16 plcp_signal,
1624 size_t hdrlen)
1625 {
1626 struct adm8211_priv *priv = dev->priv;
1627 unsigned long flags;
1628 dma_addr_t mapping;
1629 unsigned int entry;
1630 u32 flag;
1631
1632 mapping = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
1633 DMA_TO_DEVICE);
1634 if (dma_mapping_error(&priv->pdev->dev, mapping))
1635 return -ENOMEM;
1636
1637 spin_lock_irqsave(&priv->lock, flags);
1638
1639 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1640 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1641 else
1642 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1643
1644 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1645 ieee80211_stop_queue(dev, 0);
1646
1647 entry = priv->cur_tx % priv->tx_ring_size;
1648
1649 priv->tx_buffers[entry].skb = skb;
1650 priv->tx_buffers[entry].mapping = mapping;
1651 priv->tx_buffers[entry].hdrlen = hdrlen;
1652 priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1653
1654 if (entry == priv->tx_ring_size - 1)
1655 flag |= TDES1_CONTROL_TER;
1656 priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1657
1658 /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1659 flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1660 priv->tx_ring[entry].status = cpu_to_le32(flag);
1661
1662 priv->cur_tx++;
1663
1664 spin_unlock_irqrestore(&priv->lock, flags);
1665
1666 /* Trigger transmit poll */
1667 ADM8211_CSR_WRITE(TDR, 0);
1668
1669 return 0;
1670 }
1671
1672 /* Put adm8211_tx_hdr on skb and transmit */
1673 static void adm8211_tx(struct ieee80211_hw *dev,
1674 struct ieee80211_tx_control *control,
1675 struct sk_buff *skb)
1676 {
1677 struct adm8211_tx_hdr *txhdr;
1678 size_t payload_len, hdrlen;
1679 int plcp, dur, len, plcp_signal, short_preamble;
1680 struct ieee80211_hdr *hdr;
1681 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1682 struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
1683 u8 rc_flags;
1684
1685 rc_flags = info->control.rates[0].flags;
1686 short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1687 plcp_signal = txrate->bitrate;
1688
1689 hdr = (struct ieee80211_hdr *)skb->data;
1690 hdrlen = ieee80211_hdrlen(hdr->frame_control);
1691 memcpy(skb->cb, skb->data, hdrlen);
1692 hdr = (struct ieee80211_hdr *)skb->cb;
1693 skb_pull(skb, hdrlen);
1694 payload_len = skb->len;
1695
1696 txhdr = skb_push(skb, sizeof(*txhdr));
1697 memset(txhdr, 0, sizeof(*txhdr));
1698 memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1699 txhdr->signal = plcp_signal;
1700 txhdr->frame_body_size = cpu_to_le16(payload_len);
1701 txhdr->frame_control = hdr->frame_control;
1702
1703 len = hdrlen + payload_len + FCS_LEN;
1704
1705 txhdr->frag = cpu_to_le16(0x0FFF);
1706 adm8211_calc_durations(&dur, &plcp, payload_len,
1707 len, plcp_signal, short_preamble);
1708 txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1709 txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1710 txhdr->dur_frag_head = cpu_to_le16(dur);
1711 txhdr->dur_frag_tail = cpu_to_le16(dur);
1712
1713 txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1714
1715 if (short_preamble)
1716 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1717
1718 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1719 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1720
1721 txhdr->retry_limit = info->control.rates[0].count;
1722
1723 if (adm8211_tx_raw(dev, skb, plcp_signal, hdrlen)) {
1724 /* Drop packet */
1725 ieee80211_free_txskb(dev, skb);
1726 }
1727 }
1728
1729 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1730 {
1731 struct adm8211_priv *priv = dev->priv;
1732 unsigned int ring_size;
1733
1734 priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1735 sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1736 if (!priv->rx_buffers)
1737 return -ENOMEM;
1738
1739 priv->tx_buffers = (void *)priv->rx_buffers +
1740 sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1741
1742 /* Allocate TX/RX descriptors */
1743 ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1744 sizeof(struct adm8211_desc) * priv->tx_ring_size;
1745 priv->rx_ring = dma_alloc_coherent(&priv->pdev->dev, ring_size,
1746 &priv->rx_ring_dma, GFP_KERNEL);
1747
1748 if (!priv->rx_ring) {
1749 kfree(priv->rx_buffers);
1750 priv->rx_buffers = NULL;
1751 priv->tx_buffers = NULL;
1752 return -ENOMEM;
1753 }
1754
1755 priv->tx_ring = priv->rx_ring + priv->rx_ring_size;
1756 priv->tx_ring_dma = priv->rx_ring_dma +
1757 sizeof(struct adm8211_desc) * priv->rx_ring_size;
1758
1759 return 0;
1760 }
1761
1762 static const struct ieee80211_ops adm8211_ops = {
1763 .tx = adm8211_tx,
1764 .start = adm8211_start,
1765 .stop = adm8211_stop,
1766 .add_interface = adm8211_add_interface,
1767 .remove_interface = adm8211_remove_interface,
1768 .config = adm8211_config,
1769 .bss_info_changed = adm8211_bss_info_changed,
1770 .prepare_multicast = adm8211_prepare_multicast,
1771 .configure_filter = adm8211_configure_filter,
1772 .get_stats = adm8211_get_stats,
1773 .get_tsf = adm8211_get_tsft
1774 };
1775
1776 static int adm8211_probe(struct pci_dev *pdev,
1777 const struct pci_device_id *id)
1778 {
1779 struct ieee80211_hw *dev;
1780 struct adm8211_priv *priv;
1781 unsigned long mem_len;
1782 unsigned int io_len;
1783 int err;
1784 u32 reg;
1785 u8 perm_addr[ETH_ALEN];
1786
1787 err = pci_enable_device(pdev);
1788 if (err) {
1789 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1790 pci_name(pdev));
1791 return err;
1792 }
1793
1794 io_len = pci_resource_len(pdev, 0);
1795 mem_len = pci_resource_len(pdev, 1);
1796 if (io_len < 256 || mem_len < 1024) {
1797 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1798 pci_name(pdev));
1799 err = -ENOMEM;
1800 goto err_disable_pdev;
1801 }
1802
1803
1804 /* check signature */
1805 pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1806 if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1807 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1808 pci_name(pdev), reg);
1809 err = -EINVAL;
1810 goto err_disable_pdev;
1811 }
1812
1813 err = pci_request_regions(pdev, "adm8211");
1814 if (err) {
1815 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1816 pci_name(pdev));
1817 return err; /* someone else grabbed it? don't disable it */
1818 }
1819
1820 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1821 if (err) {
1822 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1823 pci_name(pdev));
1824 goto err_free_reg;
1825 }
1826
1827 pci_set_master(pdev);
1828
1829 dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1830 if (!dev) {
1831 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1832 pci_name(pdev));
1833 err = -ENOMEM;
1834 goto err_free_reg;
1835 }
1836 priv = dev->priv;
1837 priv->pdev = pdev;
1838
1839 spin_lock_init(&priv->lock);
1840
1841 SET_IEEE80211_DEV(dev, &pdev->dev);
1842
1843 pci_set_drvdata(pdev, dev);
1844
1845 priv->map = pci_iomap(pdev, 1, mem_len);
1846 if (!priv->map)
1847 priv->map = pci_iomap(pdev, 0, io_len);
1848
1849 if (!priv->map) {
1850 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1851 pci_name(pdev));
1852 err = -ENOMEM;
1853 goto err_free_dev;
1854 }
1855
1856 priv->rx_ring_size = rx_ring_size;
1857 priv->tx_ring_size = tx_ring_size;
1858
1859 err = adm8211_alloc_rings(dev);
1860 if (err) {
1861 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1862 pci_name(pdev));
1863 goto err_iounmap;
1864 }
1865
1866 *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1867 *(__le16 *)&perm_addr[4] =
1868 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
1869
1870 if (!is_valid_ether_addr(perm_addr)) {
1871 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1872 pci_name(pdev));
1873 eth_random_addr(perm_addr);
1874 }
1875 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1876
1877 dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1878 /* dev->flags = RX_INCLUDES_FCS in promisc mode */
1879 ieee80211_hw_set(dev, SIGNAL_UNSPEC);
1880 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1881
1882 dev->max_signal = 100; /* FIXME: find better value */
1883
1884 dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1885
1886 priv->retry_limit = 3;
1887 priv->ant_power = 0x40;
1888 priv->tx_power = 0x40;
1889 priv->lpf_cutoff = 0xFF;
1890 priv->lnags_threshold = 0xFF;
1891 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1892
1893 /* Power-on issue. EEPROM won't read correctly without */
1894 if (pdev->revision >= ADM8211_REV_BA) {
1895 ADM8211_CSR_WRITE(FRCTL, 0);
1896 ADM8211_CSR_READ(FRCTL);
1897 ADM8211_CSR_WRITE(FRCTL, 1);
1898 ADM8211_CSR_READ(FRCTL);
1899 msleep(100);
1900 }
1901
1902 err = adm8211_read_eeprom(dev);
1903 if (err) {
1904 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1905 pci_name(pdev));
1906 goto err_free_desc;
1907 }
1908
1909 priv->channel = 1;
1910
1911 dev->wiphy->bands[NL80211_BAND_2GHZ] = &priv->band;
1912
1913 wiphy_ext_feature_set(dev->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
1914
1915 err = ieee80211_register_hw(dev);
1916 if (err) {
1917 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1918 pci_name(pdev));
1919 goto err_free_eeprom;
1920 }
1921
1922 wiphy_info(dev->wiphy, "hwaddr %pM, Rev 0x%02x\n",
1923 dev->wiphy->perm_addr, pdev->revision);
1924
1925 return 0;
1926
1927 err_free_eeprom:
1928 kfree(priv->eeprom);
1929
1930 err_free_desc:
1931 dma_free_coherent(&pdev->dev,
1932 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1933 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1934 priv->rx_ring, priv->rx_ring_dma);
1935 kfree(priv->rx_buffers);
1936
1937 err_iounmap:
1938 pci_iounmap(pdev, priv->map);
1939
1940 err_free_dev:
1941 ieee80211_free_hw(dev);
1942
1943 err_free_reg:
1944 pci_release_regions(pdev);
1945
1946 err_disable_pdev:
1947 pci_disable_device(pdev);
1948 return err;
1949 }
1950
1951
1952 static void adm8211_remove(struct pci_dev *pdev)
1953 {
1954 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1955 struct adm8211_priv *priv;
1956
1957 if (!dev)
1958 return;
1959
1960 ieee80211_unregister_hw(dev);
1961
1962 priv = dev->priv;
1963
1964 dma_free_coherent(&pdev->dev,
1965 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1966 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1967 priv->rx_ring, priv->rx_ring_dma);
1968
1969 kfree(priv->rx_buffers);
1970 kfree(priv->eeprom);
1971 pci_iounmap(pdev, priv->map);
1972 pci_release_regions(pdev);
1973 pci_disable_device(pdev);
1974 ieee80211_free_hw(dev);
1975 }
1976
1977
1978 #define adm8211_suspend NULL
1979 #define adm8211_resume NULL
1980
1981 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
1982
1983 static SIMPLE_DEV_PM_OPS(adm8211_pm_ops, adm8211_suspend, adm8211_resume);
1984
1985 /* TODO: implement enable_wake */
1986 static struct pci_driver adm8211_driver = {
1987 .name = "adm8211",
1988 .id_table = adm8211_pci_id_table,
1989 .probe = adm8211_probe,
1990 .remove = adm8211_remove,
1991 .driver.pm = &adm8211_pm_ops,
1992 };
1993
1994 module_pci_driver(adm8211_driver);
Linux with added FPC-III support