drivers/net/wireless/marvell/mwifiex/sdio.h

   1 /*
   2  * NXP Wireless LAN device driver: SDIO specific definitions
   3  *
   4  * Copyright 2011-2020 NXP
   5  *
   6  * This software file (the "File") is distributed by NXP
   7  * under the terms of the GNU General Public License Version 2, June 1991
   8  * (the "License").  You may use, redistribute and/or modify this File in
   9  * accordance with the terms and conditions of the License, a copy of which
  10  * is available by writing to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  12  * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  13  *
  14  * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
  17  * this warranty disclaimer.
  18  */
  19
  20 #ifndef _MWIFIEX_SDIO_H
  21 #define _MWIFIEX_SDIO_H
  22
  23
  24 #include <linux/completion.h>
  25 #include <linux/mmc/sdio.h>
  26 #include <linux/mmc/sdio_ids.h>
  27 #include <linux/mmc/sdio_func.h>
  28 #include <linux/mmc/card.h>
  29 #include <linux/mmc/host.h>
  30
  31 #include "main.h"
  32
  33 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
  34 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
  35 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
  36 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
  37 #define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
  38 #define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
  39 #define SD8977_DEFAULT_FW_NAME "mrvl/sdsd8977_combo_v2.bin"
  40 #define SD8987_DEFAULT_FW_NAME "mrvl/sd8987_uapsta.bin"
  41 #define SD8997_DEFAULT_FW_NAME "mrvl/sdsd8997_combo_v4.bin"
  42
  43 #define BLOCK_MODE      1
  44 #define BYTE_MODE       0
  45
  46 #define MWIFIEX_SDIO_IO_PORT_MASK               0xfffff
  47
  48 #define MWIFIEX_SDIO_BYTE_MODE_MASK     0x80000000
  49
  50 #define MWIFIEX_MAX_FUNC2_REG_NUM       13
  51 #define MWIFIEX_SDIO_SCRATCH_SIZE       10
  52
  53 #define SDIO_MPA_ADDR_BASE              0x1000
  54 #define CTRL_PORT                       0
  55 #define CTRL_PORT_MASK                  0x0001
  56
  57 #define CMD_PORT_UPLD_INT_MASK          (0x1U<<6)
  58 #define CMD_PORT_DNLD_INT_MASK          (0x1U<<7)
  59 #define HOST_TERM_CMD53                 (0x1U << 2)
  60 #define REG_PORT                        0
  61 #define MEM_PORT                        0x10000
  62
  63 #define CMD53_NEW_MODE                  (0x1U << 0)
  64 #define CMD_PORT_RD_LEN_EN              (0x1U << 2)
  65 #define CMD_PORT_AUTO_EN                (0x1U << 0)
  66 #define CMD_PORT_SLCT                   0x8000
  67 #define UP_LD_CMD_PORT_HOST_INT_STATUS  (0x40U)
  68 #define DN_LD_CMD_PORT_HOST_INT_STATUS  (0x80U)
  69
  70 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K    (16384)
  71 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K    (32768)
  72 /* we leave one block of 256 bytes for DMA alignment*/
  73 #define MWIFIEX_MP_AGGR_BUF_SIZE_MAX    (65280)
  74
  75 /* Misc. Config Register : Auto Re-enable interrupts */
  76 #define AUTO_RE_ENABLE_INT              BIT(4)
  77
  78 /* Host Control Registers : Configuration */
  79 #define CONFIGURATION_REG               0x00
  80 /* Host Control Registers : Host power up */
  81 #define HOST_POWER_UP                   (0x1U << 1)
  82
  83 /* Host Control Registers : Upload host interrupt mask */
  84 #define UP_LD_HOST_INT_MASK             (0x1U)
  85 /* Host Control Registers : Download host interrupt mask */
  86 #define DN_LD_HOST_INT_MASK             (0x2U)
  87
  88 /* Host Control Registers : Upload host interrupt status */
  89 #define UP_LD_HOST_INT_STATUS           (0x1U)
  90 /* Host Control Registers : Download host interrupt status */
  91 #define DN_LD_HOST_INT_STATUS           (0x2U)
  92
  93 /* Host Control Registers : Host interrupt status */
  94 #define CARD_INT_STATUS_REG             0x28
  95
  96 /* Card Control Registers : Card I/O ready */
  97 #define CARD_IO_READY                   (0x1U << 3)
  98 /* Card Control Registers : Download card ready */
  99 #define DN_LD_CARD_RDY                  (0x1U << 0)
 100
 101 /* Max retry number of CMD53 write */
 102 #define MAX_WRITE_IOMEM_RETRY           2
 103
 104 /* SDIO Tx aggregation in progress ? */
 105 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
 106
 107 /* SDIO Tx aggregation buffer room for next packet ? */
 108 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)        \
 109                                                 <= a->mpa_tx.buf_size)
 110
 111 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
 112 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {              \
 113         memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],                      \
 114                         payload, pkt_len);                              \
 115         a->mpa_tx.buf_len += pkt_len;                                   \
 116         if (!a->mpa_tx.pkt_cnt)                                         \
 117                 a->mpa_tx.start_port = port;                            \
 118         if (a->mpa_tx.start_port <= port)                               \
 119                 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));            \
 120         else                                                            \
 121                 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+            \
 122                                                 (a->max_ports - \
 123                                                 a->mp_end_port)));      \
 124         a->mpa_tx.pkt_cnt++;                                            \
 125 } while (0)
 126
 127 /* SDIO Tx aggregation limit ? */
 128 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a)                                 \
 129                         (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
 130
 131 /* Reset SDIO Tx aggregation buffer parameters */
 132 #define MP_TX_AGGR_BUF_RESET(a) do {                                    \
 133         a->mpa_tx.pkt_cnt = 0;                                          \
 134         a->mpa_tx.buf_len = 0;                                          \
 135         a->mpa_tx.ports = 0;                                            \
 136         a->mpa_tx.start_port = 0;                                       \
 137 } while (0)
 138
 139 /* SDIO Rx aggregation limit ? */
 140 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a)                                 \
 141                         (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
 142
 143 /* SDIO Rx aggregation in progress ? */
 144 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
 145
 146 /* SDIO Rx aggregation buffer room for next packet ? */
 147 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)                              \
 148                         ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
 149
 150 /* Reset SDIO Rx aggregation buffer parameters */
 151 #define MP_RX_AGGR_BUF_RESET(a) do {                                    \
 152         a->mpa_rx.pkt_cnt = 0;                                          \
 153         a->mpa_rx.buf_len = 0;                                          \
 154         a->mpa_rx.ports = 0;                                            \
 155         a->mpa_rx.start_port = 0;                                       \
 156 } while (0)
 157
 158 /* data structure for SDIO MPA TX */
 159 struct mwifiex_sdio_mpa_tx {
 160         /* multiport tx aggregation buffer pointer */
 161         u8 *buf;
 162         u32 buf_len;
 163         u32 pkt_cnt;
 164         u32 ports;
 165         u16 start_port;
 166         u8 enabled;
 167         u32 buf_size;
 168         u32 pkt_aggr_limit;
 169 };
 170
 171 struct mwifiex_sdio_mpa_rx {
 172         u8 *buf;
 173         u32 buf_len;
 174         u32 pkt_cnt;
 175         u32 ports;
 176         u16 start_port;
 177
 178         struct sk_buff **skb_arr;
 179         u32 *len_arr;
 180
 181         u8 enabled;
 182         u32 buf_size;
 183         u32 pkt_aggr_limit;
 184 };
 185
 186 int mwifiex_bus_register(void);
 187 void mwifiex_bus_unregister(void);
 188
 189 struct mwifiex_sdio_card_reg {
 190         u8 start_rd_port;
 191         u8 start_wr_port;
 192         u8 base_0_reg;
 193         u8 base_1_reg;
 194         u8 poll_reg;
 195         u8 host_int_enable;
 196         u8 host_int_rsr_reg;
 197         u8 host_int_status_reg;
 198         u8 host_int_mask_reg;
 199         u8 status_reg_0;
 200         u8 status_reg_1;
 201         u8 sdio_int_mask;
 202         u32 data_port_mask;
 203         u8 io_port_0_reg;
 204         u8 io_port_1_reg;
 205         u8 io_port_2_reg;
 206         u8 max_mp_regs;
 207         u8 rd_bitmap_l;
 208         u8 rd_bitmap_u;
 209         u8 rd_bitmap_1l;
 210         u8 rd_bitmap_1u;
 211         u8 wr_bitmap_l;
 212         u8 wr_bitmap_u;
 213         u8 wr_bitmap_1l;
 214         u8 wr_bitmap_1u;
 215         u8 rd_len_p0_l;
 216         u8 rd_len_p0_u;
 217         u8 card_misc_cfg_reg;
 218         u8 card_cfg_2_1_reg;
 219         u8 cmd_rd_len_0;
 220         u8 cmd_rd_len_1;
 221         u8 cmd_rd_len_2;
 222         u8 cmd_rd_len_3;
 223         u8 cmd_cfg_0;
 224         u8 cmd_cfg_1;
 225         u8 cmd_cfg_2;
 226         u8 cmd_cfg_3;
 227         u8 fw_dump_host_ready;
 228         u8 fw_dump_ctrl;
 229         u8 fw_dump_start;
 230         u8 fw_dump_end;
 231         u8 func1_dump_reg_start;
 232         u8 func1_dump_reg_end;
 233         u8 func1_scratch_reg;
 234         u8 func1_spec_reg_num;
 235         u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
 236 };
 237
 238 struct sdio_mmc_card {
 239         struct sdio_func *func;
 240         struct mwifiex_adapter *adapter;
 241
 242         struct completion fw_done;
 243         const char *firmware;
 244         const struct mwifiex_sdio_card_reg *reg;
 245         u8 max_ports;
 246         u8 mp_agg_pkt_limit;
 247         u16 tx_buf_size;
 248         u32 mp_tx_agg_buf_size;
 249         u32 mp_rx_agg_buf_size;
 250
 251         u32 mp_rd_bitmap;
 252         u32 mp_wr_bitmap;
 253
 254         u16 mp_end_port;
 255         u32 mp_data_port_mask;
 256
 257         u8 curr_rd_port;
 258         u8 curr_wr_port;
 259
 260         u8 *mp_regs;
 261         bool supports_sdio_new_mode;
 262         bool has_control_mask;
 263         bool can_dump_fw;
 264         bool fw_dump_enh;
 265         bool can_auto_tdls;
 266         bool can_ext_scan;
 267
 268         struct mwifiex_sdio_mpa_tx mpa_tx;
 269         struct mwifiex_sdio_mpa_rx mpa_rx;
 270
 271         struct work_struct work;
 272         unsigned long work_flags;
 273 };
 274
 275 struct mwifiex_sdio_device {
 276         const char *firmware;
 277         const struct mwifiex_sdio_card_reg *reg;
 278         u8 max_ports;
 279         u8 mp_agg_pkt_limit;
 280         u16 tx_buf_size;
 281         u32 mp_tx_agg_buf_size;
 282         u32 mp_rx_agg_buf_size;
 283         bool supports_sdio_new_mode;
 284         bool has_control_mask;
 285         bool can_dump_fw;
 286         bool fw_dump_enh;
 287         bool can_auto_tdls;
 288         bool can_ext_scan;
 289 };
 290
 291 /*
 292  * .cmdrsp_complete handler
 293  */
 294 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
 295                                                struct sk_buff *skb)
 296 {
 297         dev_kfree_skb_any(skb);
 298         return 0;
 299 }
 300
 301 /*
 302  * .event_complete handler
 303  */
 304 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
 305                                               struct sk_buff *skb)
 306 {
 307         dev_kfree_skb_any(skb);
 308         return 0;
 309 }
 310
 311 static inline bool
 312 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
 313 {
 314         u8 tmp;
 315
 316         if (card->curr_rd_port < card->mpa_rx.start_port) {
 317                 if (card->supports_sdio_new_mode)
 318                         tmp = card->mp_end_port >> 1;
 319                 else
 320                         tmp = card->mp_agg_pkt_limit;
 321
 322                 if (((card->max_ports - card->mpa_rx.start_port) +
 323                     card->curr_rd_port) >= tmp)
 324                         return true;
 325         }
 326
 327         if (!card->supports_sdio_new_mode)
 328                 return false;
 329
 330         if ((card->curr_rd_port - card->mpa_rx.start_port) >=
 331             (card->mp_end_port >> 1))
 332                 return true;
 333
 334         return false;
 335 }
 336
 337 static inline bool
 338 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
 339 {
 340         u16 tmp;
 341
 342         if (card->curr_wr_port < card->mpa_tx.start_port) {
 343                 if (card->supports_sdio_new_mode)
 344                         tmp = card->mp_end_port >> 1;
 345                 else
 346                         tmp = card->mp_agg_pkt_limit;
 347
 348                 if (((card->max_ports - card->mpa_tx.start_port) +
 349                     card->curr_wr_port) >= tmp)
 350                         return true;
 351         }
 352
 353         if (!card->supports_sdio_new_mode)
 354                 return false;
 355
 356         if ((card->curr_wr_port - card->mpa_tx.start_port) >=
 357             (card->mp_end_port >> 1))
 358                 return true;
 359
 360         return false;
 361 }
 362
 363 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
 364 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
 365                                     u16 rx_len, u8 port)
 366 {
 367         card->mpa_rx.buf_len += rx_len;
 368
 369         if (!card->mpa_rx.pkt_cnt)
 370                 card->mpa_rx.start_port = port;
 371
 372         if (card->supports_sdio_new_mode) {
 373                 card->mpa_rx.ports |= (1 << port);
 374         } else {
 375                 if (card->mpa_rx.start_port <= port)
 376                         card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
 377                 else
 378                         card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
 379         }
 380         card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL;
 381         card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len;
 382         card->mpa_rx.pkt_cnt++;
 383 }
 384 #endif /* _MWIFIEX_SDIO_H */