drivers/net/wireless/realtek/rtlwifi/rtl8723ae/rf.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
   3
   4 #include "../wifi.h"
   5 #include "reg.h"
   6 #include "def.h"
   7 #include "phy.h"
   8 #include "rf.h"
   9 #include "dm.h"
  10
  11 static bool _rtl8723e_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
  12
  13 void rtl8723e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
  14 {
  15         struct rtl_priv *rtlpriv = rtl_priv(hw);
  16         struct rtl_phy *rtlphy = &rtlpriv->phy;
  17
  18         switch (bandwidth) {
  19         case HT_CHANNEL_WIDTH_20:
  20                 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  21                                              0xfffff3ff) | 0x0400);
  22                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  23                               rtlphy->rfreg_chnlval[0]);
  24                 break;
  25         case HT_CHANNEL_WIDTH_20_40:
  26                 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  27                                              0xfffff3ff));
  28                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  29                               rtlphy->rfreg_chnlval[0]);
  30                 break;
  31         default:
  32                 pr_err("unknown bandwidth: %#X\n", bandwidth);
  33                 break;
  34         }
  35 }
  36
  37 void rtl8723e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
  38                                          u8 *ppowerlevel)
  39 {
  40         struct rtl_priv *rtlpriv = rtl_priv(hw);
  41         struct rtl_phy *rtlphy = &rtlpriv->phy;
  42         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  43         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  44         u32 tx_agc[2] = {0, 0}, tmpval;
  45         bool turbo_scanoff = false;
  46         u8 idx1, idx2;
  47         u8 *ptr;
  48
  49         if (rtlefuse->eeprom_regulatory != 0)
  50                 turbo_scanoff = true;
  51
  52         if (mac->act_scanning) {
  53                 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
  54                 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
  55
  56                 if (turbo_scanoff) {
  57                         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B;
  58                                 idx1++) {
  59                                 tx_agc[idx1] = ppowerlevel[idx1] |
  60                                     (ppowerlevel[idx1] << 8) |
  61                                     (ppowerlevel[idx1] << 16) |
  62                                     (ppowerlevel[idx1] << 24);
  63                         }
  64                 }
  65         } else {
  66                 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  67                         tx_agc[idx1] = ppowerlevel[idx1] |
  68                             (ppowerlevel[idx1] << 8) |
  69                             (ppowerlevel[idx1] << 16) |
  70                             (ppowerlevel[idx1] << 24);
  71                 }
  72
  73                 if (rtlefuse->eeprom_regulatory == 0) {
  74                         tmpval =
  75                             (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
  76                             (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
  77                              8);
  78                         tx_agc[RF90_PATH_A] += tmpval;
  79
  80                         tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
  81                             (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
  82                              24);
  83                         tx_agc[RF90_PATH_B] += tmpval;
  84                 }
  85         }
  86
  87         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  88                 ptr = (u8 *)&tx_agc[idx1];
  89                 for (idx2 = 0; idx2 < 4; idx2++) {
  90                         if (*ptr > RF6052_MAX_TX_PWR)
  91                                 *ptr = RF6052_MAX_TX_PWR;
  92                         ptr++;
  93                 }
  94         }
  95
  96         tmpval = tx_agc[RF90_PATH_A] & 0xff;
  97         rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
  98
  99         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 100                 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
 101                  RTXAGC_A_CCK1_MCS32);
 102
 103         tmpval = tx_agc[RF90_PATH_A] >> 8;
 104
 105         tmpval = tmpval & 0xff00ffff;
 106
 107         rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
 108
 109         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 110                 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
 111                  RTXAGC_B_CCK11_A_CCK2_11);
 112
 113         tmpval = tx_agc[RF90_PATH_B] >> 24;
 114         rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
 115
 116         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 117                 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
 118                  RTXAGC_B_CCK11_A_CCK2_11);
 119
 120         tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
 121         rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
 122
 123         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 124                 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
 125                  RTXAGC_B_CCK1_55_MCS32);
 126 }
 127
 128 static void rtl8723e_phy_get_power_base(struct ieee80211_hw *hw,
 129                                         u8 *ppowerlevel, u8 channel,
 130                                         u32 *ofdmbase, u32 *mcsbase)
 131 {
 132         struct rtl_priv *rtlpriv = rtl_priv(hw);
 133         struct rtl_phy *rtlphy = &rtlpriv->phy;
 134         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 135         u32 powerbase0, powerbase1;
 136         u8 legacy_pwrdiff, ht20_pwrdiff;
 137         u8 i, powerlevel[2];
 138
 139         for (i = 0; i < 2; i++) {
 140                 powerlevel[i] = ppowerlevel[i];
 141                 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
 142                 powerbase0 = powerlevel[i] + legacy_pwrdiff;
 143
 144                 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
 145                     (powerbase0 << 8) | powerbase0;
 146                 *(ofdmbase + i) = powerbase0;
 147                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 148                         " [OFDM power base index rf(%c) = 0x%x]\n",
 149                          ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
 150         }
 151
 152         for (i = 0; i < 2; i++) {
 153                 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
 154                         ht20_pwrdiff =
 155                                 rtlefuse->txpwr_ht20diff[i][channel - 1];
 156                         powerlevel[i] += ht20_pwrdiff;
 157                 }
 158                 powerbase1 = powerlevel[i];
 159                 powerbase1 = (powerbase1 << 24) |
 160                     (powerbase1 << 16) | (powerbase1 << 8) | powerbase1;
 161
 162                 *(mcsbase + i) = powerbase1;
 163
 164                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 165                         " [MCS power base index rf(%c) = 0x%x]\n",
 166                          ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
 167         }
 168 }
 169
 170 static void get_txpower_writeval_by_reg(struct ieee80211_hw *hw,
 171                                         u8 channel, u8 index,
 172                                         u32 *powerbase0,
 173                                         u32 *powerbase1,
 174                                         u32 *p_outwriteval)
 175 {
 176         struct rtl_priv *rtlpriv = rtl_priv(hw);
 177         struct rtl_phy *rtlphy = &rtlpriv->phy;
 178         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 179         u8 i, chnlgroup = 0, pwr_diff_limit[4];
 180         u32 writeval, customer_limit, rf;
 181
 182         for (rf = 0; rf < 2; rf++) {
 183                 switch (rtlefuse->eeprom_regulatory) {
 184                 case 0:
 185                         chnlgroup = 0;
 186
 187                         writeval =
 188                             rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
 189                                                                 (rf ? 8 : 0)]
 190                             + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
 191
 192                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 193                                 "RTK better performance, writeval(%c) = 0x%x\n",
 194                                 ((rf == 0) ? 'A' : 'B'), writeval);
 195                         break;
 196                 case 1:
 197                         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
 198                                 writeval = ((index < 2) ? powerbase0[rf] :
 199                                             powerbase1[rf]);
 200
 201                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 202                                         "Realtek regulatory, 40MHz, writeval(%c) = 0x%x\n",
 203                                         ((rf == 0) ? 'A' : 'B'), writeval);
 204                         } else {
 205                                 if (rtlphy->pwrgroup_cnt == 1)
 206                                         chnlgroup = 0;
 207                                 if (rtlphy->pwrgroup_cnt >= 3) {
 208                                         if (channel <= 3)
 209                                                 chnlgroup = 0;
 210                                         else if (channel >= 4 && channel <= 9)
 211                                                 chnlgroup = 1;
 212                                         else if (channel > 9)
 213                                                 chnlgroup = 2;
 214                                         if (rtlphy->current_chan_bw ==
 215                                                 HT_CHANNEL_WIDTH_20)
 216                                                 chnlgroup++;
 217                                         else
 218                                                 chnlgroup += 4;
 219                                 }
 220
 221                                 writeval =
 222                                     rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
 223                                     [index + (rf ? 8 : 0)] + ((index < 2) ?
 224                                                               powerbase0[rf] :
 225                                                               powerbase1[rf]);
 226
 227                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 228                                         "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
 229                                         ((rf == 0) ? 'A' : 'B'), writeval);
 230                         }
 231                         break;
 232                 case 2:
 233                         writeval =
 234                             ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
 235
 236                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 237                                 "Better regulatory, writeval(%c) = 0x%x\n",
 238                                 ((rf == 0) ? 'A' : 'B'), writeval);
 239                         break;
 240                 case 3:
 241                         chnlgroup = 0;
 242
 243                         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
 244                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 245                                         "customer's limit, 40MHz rf(%c) = 0x%x\n",
 246                                         ((rf == 0) ? 'A' : 'B'),
 247                                         rtlefuse->pwrgroup_ht40[rf][channel -
 248                                                                      1]);
 249                         } else {
 250                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 251                                         "customer's limit, 20MHz rf(%c) = 0x%x\n",
 252                                         ((rf == 0) ? 'A' : 'B'),
 253                                         rtlefuse->pwrgroup_ht20[rf][channel -
 254                                                                      1]);
 255                         }
 256                         for (i = 0; i < 4; i++) {
 257                                 pwr_diff_limit[i] =
 258                                     (u8)((rtlphy->mcs_txpwrlevel_origoffset
 259                                           [chnlgroup][index +
 260                                                 (rf ? 8 : 0)] & (0x7f <<
 261                                                 (i * 8))) >> (i * 8));
 262
 263                                 if (rtlphy->current_chan_bw ==
 264                                     HT_CHANNEL_WIDTH_20_40) {
 265                                         if (pwr_diff_limit[i] >
 266                                             rtlefuse->
 267                                             pwrgroup_ht40[rf][channel - 1])
 268                                                 pwr_diff_limit[i] =
 269                                                     rtlefuse->pwrgroup_ht40[rf]
 270                                                     [channel - 1];
 271                                 } else {
 272                                         if (pwr_diff_limit[i] >
 273                                             rtlefuse->
 274                                             pwrgroup_ht20[rf][channel - 1])
 275                                                 pwr_diff_limit[i] =
 276                                                     rtlefuse->pwrgroup_ht20[rf]
 277                                                     [channel - 1];
 278                                 }
 279                         }
 280
 281                         customer_limit = (pwr_diff_limit[3] << 24) |
 282                             (pwr_diff_limit[2] << 16) |
 283                             (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
 284
 285                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 286                                 "Customer's limit rf(%c) = 0x%x\n",
 287                                  ((rf == 0) ? 'A' : 'B'), customer_limit);
 288
 289                         writeval = customer_limit +
 290                             ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
 291
 292                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 293                                 "Customer, writeval rf(%c)= 0x%x\n",
 294                                  ((rf == 0) ? 'A' : 'B'), writeval);
 295                         break;
 296                 default:
 297                         chnlgroup = 0;
 298                         writeval =
 299                             rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
 300                             [index + (rf ? 8 : 0)]
 301                             + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
 302
 303                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 304                                 "RTK better performance, writeval rf(%c) = 0x%x\n",
 305                                 ((rf == 0) ? 'A' : 'B'), writeval);
 306                         break;
 307                 }
 308
 309                 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
 310                         writeval = writeval - 0x06060606;
 311                 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
 312                          TXHIGHPWRLEVEL_BT2)
 313                         writeval = writeval - 0x0c0c0c0c;
 314                 *(p_outwriteval + rf) = writeval;
 315         }
 316 }
 317
 318 static void _rtl8723e_write_ofdm_power_reg(struct ieee80211_hw *hw,
 319                                            u8 index, u32 *pvalue)
 320 {
 321         struct rtl_priv *rtlpriv = rtl_priv(hw);
 322         struct rtl_phy *rtlphy = &rtlpriv->phy;
 323
 324         u16 regoffset_a[6] = {
 325                 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
 326                 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
 327                 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
 328         };
 329         u16 regoffset_b[6] = {
 330                 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
 331                 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
 332                 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
 333         };
 334         u8 i, rf, pwr_val[4];
 335         u32 writeval;
 336         u16 regoffset;
 337
 338         for (rf = 0; rf < 2; rf++) {
 339                 writeval = pvalue[rf];
 340                 for (i = 0; i < 4; i++) {
 341                         pwr_val[i] = (u8)((writeval & (0x7f <<
 342                                            (i * 8))) >> (i * 8));
 343
 344                         if (pwr_val[i] > RF6052_MAX_TX_PWR)
 345                                 pwr_val[i] = RF6052_MAX_TX_PWR;
 346                 }
 347                 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
 348                     (pwr_val[1] << 8) | pwr_val[0];
 349
 350                 if (rf == 0)
 351                         regoffset = regoffset_a[index];
 352                 else
 353                         regoffset = regoffset_b[index];
 354                 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
 355
 356                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 357                         "Set 0x%x = %08x\n", regoffset, writeval);
 358
 359                 if (((get_rf_type(rtlphy) == RF_2T2R) &&
 360                      (regoffset == RTXAGC_A_MCS15_MCS12 ||
 361                       regoffset == RTXAGC_B_MCS15_MCS12)) ||
 362                     ((get_rf_type(rtlphy) != RF_2T2R) &&
 363                      (regoffset == RTXAGC_A_MCS07_MCS04 ||
 364                       regoffset == RTXAGC_B_MCS07_MCS04))) {
 365
 366                         writeval = pwr_val[3];
 367                         if (regoffset == RTXAGC_A_MCS15_MCS12 ||
 368                             regoffset == RTXAGC_A_MCS07_MCS04)
 369                                 regoffset = 0xc90;
 370                         if (regoffset == RTXAGC_B_MCS15_MCS12 ||
 371                             regoffset == RTXAGC_B_MCS07_MCS04)
 372                                 regoffset = 0xc98;
 373
 374                         for (i = 0; i < 3; i++) {
 375                                 writeval = (writeval > 6) ? (writeval - 6) : 0;
 376                                 rtl_write_byte(rtlpriv, (u32) (regoffset + i),
 377                                                (u8)writeval);
 378                         }
 379                 }
 380         }
 381 }
 382
 383 void rtl8723e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
 384                                           u8 *ppowerlevel, u8 channel)
 385 {
 386         u32 writeval[2], powerbase0[2], powerbase1[2];
 387         u8 index;
 388
 389         rtl8723e_phy_get_power_base(hw, ppowerlevel,
 390                                     channel, &powerbase0[0], &powerbase1[0]);
 391
 392         for (index = 0; index < 6; index++) {
 393                 get_txpower_writeval_by_reg(hw, channel, index, &powerbase0[0],
 394                                             &powerbase1[0],
 395                                             &writeval[0]);
 396
 397                 _rtl8723e_write_ofdm_power_reg(hw, index, &writeval[0]);
 398         }
 399 }
 400
 401 bool rtl8723e_phy_rf6052_config(struct ieee80211_hw *hw)
 402 {
 403         struct rtl_priv *rtlpriv = rtl_priv(hw);
 404         struct rtl_phy *rtlphy = &rtlpriv->phy;
 405
 406         if (rtlphy->rf_type == RF_1T1R)
 407                 rtlphy->num_total_rfpath = 1;
 408         else
 409                 rtlphy->num_total_rfpath = 2;
 410
 411         return _rtl8723e_phy_rf6052_config_parafile(hw);
 412 }
 413
 414 static bool _rtl8723e_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
 415 {
 416         struct rtl_priv *rtlpriv = rtl_priv(hw);
 417         struct rtl_phy *rtlphy = &rtlpriv->phy;
 418         u32 u4_regvalue = 0;
 419         u8 rfpath;
 420         bool rtstatus = true;
 421         struct bb_reg_def *pphyreg;
 422
 423         for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
 424
 425                 pphyreg = &rtlphy->phyreg_def[rfpath];
 426
 427                 switch (rfpath) {
 428                 case RF90_PATH_A:
 429                 case RF90_PATH_C:
 430                         u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
 431                                                     BRFSI_RFENV);
 432                         break;
 433                 case RF90_PATH_B:
 434                 case RF90_PATH_D:
 435                         u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
 436                                                     BRFSI_RFENV << 16);
 437                         break;
 438                 }
 439
 440                 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
 441                 udelay(1);
 442
 443                 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
 444                 udelay(1);
 445
 446                 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
 447                               B3WIREADDREAALENGTH, 0x0);
 448                 udelay(1);
 449
 450                 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
 451                 udelay(1);
 452
 453                 switch (rfpath) {
 454                 case RF90_PATH_A:
 455                         rtstatus = rtl8723e_phy_config_rf_with_headerfile(hw,
 456                                                 (enum radio_path)rfpath);
 457                         break;
 458                 case RF90_PATH_B:
 459                         rtstatus =
 460                           rtl8723e_phy_config_rf_with_headerfile(hw,
 461                                                 (enum radio_path)rfpath);
 462                         break;
 463                 case RF90_PATH_C:
 464                         break;
 465                 case RF90_PATH_D:
 466                         break;
 467                 }
 468
 469                 switch (rfpath) {
 470                 case RF90_PATH_A:
 471                 case RF90_PATH_C:
 472                         rtl_set_bbreg(hw, pphyreg->rfintfs,
 473                                       BRFSI_RFENV, u4_regvalue);
 474                         break;
 475                 case RF90_PATH_B:
 476                 case RF90_PATH_D:
 477                         rtl_set_bbreg(hw, pphyreg->rfintfs,
 478                                       BRFSI_RFENV << 16, u4_regvalue);
 479                         break;
 480                 }
 481
 482                 if (!rtstatus) {
 483                         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 484                                 "Radio[%d] Fail!!\n", rfpath);
 485                         return false;
 486                 }
 487         }
 488
 489         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
 490         return rtstatus;
 491 }