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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / net / wireless / realtek / rtlwifi / wifi.h
blobfdccfd29fd6186a32613705118500fc9cf7efe3b
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #ifndef __RTL_WIFI_H__
5 #define __RTL_WIFI_H__
6
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9 #include <linux/sched.h>
10 #include <linux/firmware.h>
11 #include <linux/etherdevice.h>
12 #include <linux/vmalloc.h>
13 #include <linux/usb.h>
14 #include <net/mac80211.h>
15 #include <linux/completion.h>
16 #include <linux/bitfield.h>
17 #include "debug.h"
18
19 #define MASKBYTE0 0xff
20 #define MASKBYTE1 0xff00
21 #define MASKBYTE2 0xff0000
22 #define MASKBYTE3 0xff000000
23 #define MASKHWORD 0xffff0000
24 #define MASKLWORD 0x0000ffff
25 #define MASKDWORD 0xffffffff
26 #define MASK12BITS 0xfff
27 #define MASKH4BITS 0xf0000000
28 #define MASKOFDM_D 0xffc00000
29 #define MASKCCK 0x3f3f3f3f
30
31 #define MASK4BITS 0x0f
32 #define MASK20BITS 0xfffff
33 #define RFREG_OFFSET_MASK 0xfffff
34
35 #define MASKBYTE0 0xff
36 #define MASKBYTE1 0xff00
37 #define MASKBYTE2 0xff0000
38 #define MASKBYTE3 0xff000000
39 #define MASKHWORD 0xffff0000
40 #define MASKLWORD 0x0000ffff
41 #define MASKDWORD 0xffffffff
42 #define MASK12BITS 0xfff
43 #define MASKH4BITS 0xf0000000
44 #define MASKOFDM_D 0xffc00000
45 #define MASKCCK 0x3f3f3f3f
46
47 #define MASK4BITS 0x0f
48 #define MASK20BITS 0xfffff
49 #define RFREG_OFFSET_MASK 0xfffff
50
51 #define RF_CHANGE_BY_INIT 0
52 #define RF_CHANGE_BY_IPS BIT(28)
53 #define RF_CHANGE_BY_PS BIT(29)
54 #define RF_CHANGE_BY_HW BIT(30)
55 #define RF_CHANGE_BY_SW BIT(31)
56
57 #define IQK_ADDA_REG_NUM 16
58 #define IQK_MAC_REG_NUM 4
59 #define IQK_THRESHOLD 8
60
61 #define MAX_KEY_LEN 61
62 #define KEY_BUF_SIZE 5
63
64 /* QoS related. */
65 /*aci: 0x00 Best Effort*/
66 /*aci: 0x01 Background*/
67 /*aci: 0x10 Video*/
68 /*aci: 0x11 Voice*/
69 /*Max: define total number.*/
70 #define AC0_BE 0
71 #define AC1_BK 1
72 #define AC2_VI 2
73 #define AC3_VO 3
74 #define AC_MAX 4
75 #define QOS_QUEUE_NUM 4
76 #define RTL_MAC80211_NUM_QUEUE 5
77 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
78 #define RTL_USB_MAX_RX_COUNT 100
79 #define QBSS_LOAD_SIZE 5
80 #define MAX_WMMELE_LENGTH 64
81 #define ASPM_L1_LATENCY 7
82
83 #define TOTAL_CAM_ENTRY 32
84
85 /*slot time for 11g. */
86 #define RTL_SLOT_TIME_9 9
87 #define RTL_SLOT_TIME_20 20
88
89 /*related to tcp/ip. */
90 #define SNAP_SIZE 6
91 #define PROTOC_TYPE_SIZE 2
92
93 /*related with 802.11 frame*/
94 #define MAC80211_3ADDR_LEN 24
95 #define MAC80211_4ADDR_LEN 30
96
97 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
98 #define CHANNEL_MAX_NUMBER_2G 14
99 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
100 *"phy_GetChnlGroup8812A" and
101 * "Hal_ReadTxPowerInfo8812A"
102 */
103 #define CHANNEL_MAX_NUMBER_5G_80M 7
104 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
105 #define MAX_PG_GROUP 13
106 #define CHANNEL_GROUP_MAX_2G 3
107 #define CHANNEL_GROUP_IDX_5GL 3
108 #define CHANNEL_GROUP_IDX_5GM 6
109 #define CHANNEL_GROUP_IDX_5GH 9
110 #define CHANNEL_GROUP_MAX_5G 9
111 #define CHANNEL_MAX_NUMBER_2G 14
112 #define AVG_THERMAL_NUM 8
113 #define AVG_THERMAL_NUM_88E 4
114 #define AVG_THERMAL_NUM_8723BE 4
115 #define MAX_TID_COUNT 9
116
117 /* for early mode */
118 #define FCS_LEN 4
119 #define EM_HDR_LEN 8
120
121 enum rtl8192c_h2c_cmd {
122 H2C_AP_OFFLOAD = 0,
123 H2C_SETPWRMODE = 1,
124 H2C_JOINBSSRPT = 2,
125 H2C_RSVDPAGE = 3,
126 H2C_RSSI_REPORT = 5,
127 H2C_RA_MASK = 6,
128 H2C_MACID_PS_MODE = 7,
129 H2C_P2P_PS_OFFLOAD = 8,
130 H2C_MAC_MODE_SEL = 9,
131 H2C_PWRM = 15,
132 H2C_P2P_PS_CTW_CMD = 24,
133 MAX_H2CCMD
134 };
135
136 enum {
137 H2C_BT_PORT_ID = 0x71,
138 };
139
140 enum rtl_c2h_evt_v1 {
141 C2H_DBG = 0,
142 C2H_LB = 1,
143 C2H_TXBF = 2,
144 C2H_TX_REPORT = 3,
145 C2H_BT_INFO = 9,
146 C2H_BT_MP = 11,
147 C2H_RA_RPT = 12,
148
149 C2H_FW_SWCHNL = 0x10,
150 C2H_IQK_FINISH = 0x11,
151
152 C2H_EXT_V2 = 0xFF,
153 };
154
155 enum rtl_c2h_evt_v2 {
156 C2H_V2_CCX_RPT = 0x0F,
157 };
158
159 #define GET_C2H_CMD_ID(c2h) ({u8 *__c2h = c2h; __c2h[0]; })
160 #define GET_C2H_SEQ(c2h) ({u8 *__c2h = c2h; __c2h[1]; })
161 #define C2H_DATA_OFFSET 2
162 #define GET_C2H_DATA_PTR(c2h) ({u8 *__c2h = c2h; &__c2h[C2H_DATA_OFFSET]; })
163
164 #define GET_TX_REPORT_SN_V1(c2h) (c2h[6])
165 #define GET_TX_REPORT_ST_V1(c2h) (c2h[0] & 0xC0)
166 #define GET_TX_REPORT_RETRY_V1(c2h) (c2h[2] & 0x3F)
167 #define GET_TX_REPORT_SN_V2(c2h) (c2h[6])
168 #define GET_TX_REPORT_ST_V2(c2h) (c2h[7] & 0xC0)
169 #define GET_TX_REPORT_RETRY_V2(c2h) (c2h[8] & 0x3F)
170
171 #define MAX_TX_COUNT 4
172 #define MAX_REGULATION_NUM 4
173 #define MAX_RF_PATH_NUM 4
174 #define MAX_RATE_SECTION_NUM 6 /* = MAX_RATE_SECTION */
175 #define MAX_2_4G_BANDWIDTH_NUM 4
176 #define MAX_5G_BANDWIDTH_NUM 4
177 #define MAX_RF_PATH 4
178 #define MAX_CHNL_GROUP_24G 6
179 #define MAX_CHNL_GROUP_5G 14
180
181 #define TX_PWR_BY_RATE_NUM_BAND 2
182 #define TX_PWR_BY_RATE_NUM_RF 4
183 #define TX_PWR_BY_RATE_NUM_SECTION 12
184 #define TX_PWR_BY_RATE_NUM_RATE 84 /* >= TX_PWR_BY_RATE_NUM_SECTION */
185 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 /* MAX_RATE_SECTION */
186 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 /* MAX_RATE_SECTION -1 */
187
188 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
189
190 #define DEL_SW_IDX_SZ 30
191
192 /* For now, it's just for 8192ee
193 * but not OK yet, keep it 0
194 */
195 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM
196
197 enum rf_tx_num {
198 RF_1TX = 0,
199 RF_2TX,
200 RF_MAX_TX_NUM,
201 RF_TX_NUM_NONIMPLEMENT,
202 };
203
204 #define PACKET_NORMAL 0
205 #define PACKET_DHCP 1
206 #define PACKET_ARP 2
207 #define PACKET_EAPOL 3
208
209 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
210 #define RSVD_WOL_PATTERN_NUM 1
211 #define WKFMCAM_ADDR_NUM 6
212 #define WKFMCAM_SIZE 24
213
214 #define MAX_WOL_BIT_MASK_SIZE 16
215 /* MIN LEN keeps 13 here */
216 #define MIN_WOL_PATTERN_SIZE 13
217 #define MAX_WOL_PATTERN_SIZE 128
218
219 #define WAKE_ON_MAGIC_PACKET BIT(0)
220 #define WAKE_ON_PATTERN_MATCH BIT(1)
221
222 #define WOL_REASON_PTK_UPDATE BIT(0)
223 #define WOL_REASON_GTK_UPDATE BIT(1)
224 #define WOL_REASON_DISASSOC BIT(2)
225 #define WOL_REASON_DEAUTH BIT(3)
226 #define WOL_REASON_AP_LOST BIT(4)
227 #define WOL_REASON_MAGIC_PKT BIT(5)
228 #define WOL_REASON_UNICAST_PKT BIT(6)
229 #define WOL_REASON_PATTERN_PKT BIT(7)
230 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
231 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
232 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
233
234 struct rtlwifi_firmware_header {
235 __le16 signature;
236 u8 category;
237 u8 function;
238 __le16 version;
239 u8 subversion;
240 u8 rsvd1;
241 u8 month;
242 u8 date;
243 u8 hour;
244 u8 minute;
245 __le16 ramcodesize;
246 __le16 rsvd2;
247 __le32 svnindex;
248 __le32 rsvd3;
249 __le32 rsvd4;
250 __le32 rsvd5;
251 };
252
253 struct txpower_info_2g {
254 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
255 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
256 /*If only one tx, only BW20 and OFDM are used.*/
257 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
258 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
259 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
260 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
261 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
262 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
263 };
264
265 struct txpower_info_5g {
266 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
267 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
268 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
269 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
270 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
271 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
272 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
273 };
274
275 enum rate_section {
276 CCK = 0,
277 OFDM,
278 HT_MCS0_MCS7,
279 HT_MCS8_MCS15,
280 VHT_1SSMCS0_1SSMCS9,
281 VHT_2SSMCS0_2SSMCS9,
282 MAX_RATE_SECTION,
283 };
284
285 enum intf_type {
286 INTF_PCI = 0,
287 INTF_USB = 1,
288 };
289
290 enum radio_path {
291 RF90_PATH_A = 0,
292 RF90_PATH_B = 1,
293 RF90_PATH_C = 2,
294 RF90_PATH_D = 3,
295 };
296
297 enum radio_mask {
298 RF_MASK_A = BIT(0),
299 RF_MASK_B = BIT(1),
300 RF_MASK_C = BIT(2),
301 RF_MASK_D = BIT(3),
302 };
303
304 enum regulation_txpwr_lmt {
305 TXPWR_LMT_FCC = 0,
306 TXPWR_LMT_MKK = 1,
307 TXPWR_LMT_ETSI = 2,
308 TXPWR_LMT_WW = 3,
309
310 TXPWR_LMT_MAX_REGULATION_NUM = 4
311 };
312
313 enum rt_eeprom_type {
314 EEPROM_93C46,
315 EEPROM_93C56,
316 EEPROM_BOOT_EFUSE,
317 };
318
319 enum ttl_status {
320 RTL_STATUS_INTERFACE_START = 0,
321 };
322
323 enum hardware_type {
324 HARDWARE_TYPE_RTL8192E,
325 HARDWARE_TYPE_RTL8192U,
326 HARDWARE_TYPE_RTL8192SE,
327 HARDWARE_TYPE_RTL8192SU,
328 HARDWARE_TYPE_RTL8192CE,
329 HARDWARE_TYPE_RTL8192CU,
330 HARDWARE_TYPE_RTL8192DE,
331 HARDWARE_TYPE_RTL8192DU,
332 HARDWARE_TYPE_RTL8723AE,
333 HARDWARE_TYPE_RTL8723U,
334 HARDWARE_TYPE_RTL8188EE,
335 HARDWARE_TYPE_RTL8723BE,
336 HARDWARE_TYPE_RTL8192EE,
337 HARDWARE_TYPE_RTL8821AE,
338 HARDWARE_TYPE_RTL8812AE,
339 HARDWARE_TYPE_RTL8822BE,
340
341 /* keep it last */
342 HARDWARE_TYPE_NUM
343 };
344
345 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type)
346 #define IS_NEW_GENERATION_IC(rtlpriv) \
347 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE)
348 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \
349 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE)
350 #define IS_HARDWARE_TYPE_8812(rtlpriv) \
351 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE)
352 #define IS_HARDWARE_TYPE_8821(rtlpriv) \
353 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE)
354 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \
355 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE)
356 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \
357 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE)
358 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \
359 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE)
360 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \
361 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE)
362
363 #define RX_HAL_IS_CCK_RATE(rxmcs) \
364 ((rxmcs) == DESC_RATE1M || \
365 (rxmcs) == DESC_RATE2M || \
366 (rxmcs) == DESC_RATE5_5M || \
367 (rxmcs) == DESC_RATE11M)
368
369 enum scan_operation_backup_opt {
370 SCAN_OPT_BACKUP = 0,
371 SCAN_OPT_BACKUP_BAND0 = 0,
372 SCAN_OPT_BACKUP_BAND1,
373 SCAN_OPT_RESTORE,
374 SCAN_OPT_MAX
375 };
376
377 /*RF state.*/
378 enum rf_pwrstate {
379 ERFON,
380 ERFSLEEP,
381 ERFOFF
382 };
383
384 struct bb_reg_def {
385 u32 rfintfs;
386 u32 rfintfi;
387 u32 rfintfo;
388 u32 rfintfe;
389 u32 rf3wire_offset;
390 u32 rflssi_select;
391 u32 rftxgain_stage;
392 u32 rfhssi_para1;
393 u32 rfhssi_para2;
394 u32 rfsw_ctrl;
395 u32 rfagc_control1;
396 u32 rfagc_control2;
397 u32 rfrxiq_imbal;
398 u32 rfrx_afe;
399 u32 rftxiq_imbal;
400 u32 rftx_afe;
401 u32 rf_rb; /* rflssi_readback */
402 u32 rf_rbpi; /* rflssi_readbackpi */
403 };
404
405 enum io_type {
406 IO_CMD_PAUSE_DM_BY_SCAN = 0,
407 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
408 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
409 IO_CMD_RESUME_DM_BY_SCAN = 2,
410 };
411
412 enum hw_variables {
413 HW_VAR_ETHER_ADDR = 0x0,
414 HW_VAR_MULTICAST_REG = 0x1,
415 HW_VAR_BASIC_RATE = 0x2,
416 HW_VAR_BSSID = 0x3,
417 HW_VAR_MEDIA_STATUS = 0x4,
418 HW_VAR_SECURITY_CONF = 0x5,
419 HW_VAR_BEACON_INTERVAL = 0x6,
420 HW_VAR_ATIM_WINDOW = 0x7,
421 HW_VAR_LISTEN_INTERVAL = 0x8,
422 HW_VAR_CS_COUNTER = 0x9,
423 HW_VAR_DEFAULTKEY0 = 0xa,
424 HW_VAR_DEFAULTKEY1 = 0xb,
425 HW_VAR_DEFAULTKEY2 = 0xc,
426 HW_VAR_DEFAULTKEY3 = 0xd,
427 HW_VAR_SIFS = 0xe,
428 HW_VAR_R2T_SIFS = 0xf,
429 HW_VAR_DIFS = 0x10,
430 HW_VAR_EIFS = 0x11,
431 HW_VAR_SLOT_TIME = 0x12,
432 HW_VAR_ACK_PREAMBLE = 0x13,
433 HW_VAR_CW_CONFIG = 0x14,
434 HW_VAR_CW_VALUES = 0x15,
435 HW_VAR_RATE_FALLBACK_CONTROL = 0x16,
436 HW_VAR_CONTENTION_WINDOW = 0x17,
437 HW_VAR_RETRY_COUNT = 0x18,
438 HW_VAR_TR_SWITCH = 0x19,
439 HW_VAR_COMMAND = 0x1a,
440 HW_VAR_WPA_CONFIG = 0x1b,
441 HW_VAR_AMPDU_MIN_SPACE = 0x1c,
442 HW_VAR_SHORTGI_DENSITY = 0x1d,
443 HW_VAR_AMPDU_FACTOR = 0x1e,
444 HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
445 HW_VAR_AC_PARAM = 0x20,
446 HW_VAR_ACM_CTRL = 0x21,
447 HW_VAR_DIS_REQ_QSIZE = 0x22,
448 HW_VAR_CCX_CHNL_LOAD = 0x23,
449 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
450 HW_VAR_CCX_CLM_NHM = 0x25,
451 HW_VAR_TXOPLIMIT = 0x26,
452 HW_VAR_TURBO_MODE = 0x27,
453 HW_VAR_RF_STATE = 0x28,
454 HW_VAR_RF_OFF_BY_HW = 0x29,
455 HW_VAR_BUS_SPEED = 0x2a,
456 HW_VAR_SET_DEV_POWER = 0x2b,
457
458 HW_VAR_RCR = 0x2c,
459 HW_VAR_RATR_0 = 0x2d,
460 HW_VAR_RRSR = 0x2e,
461 HW_VAR_CPU_RST = 0x2f,
462 HW_VAR_CHECK_BSSID = 0x30,
463 HW_VAR_LBK_MODE = 0x31,
464 HW_VAR_AES_11N_FIX = 0x32,
465 HW_VAR_USB_RX_AGGR = 0x33,
466 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
467 HW_VAR_RETRY_LIMIT = 0x35,
468 HW_VAR_INIT_TX_RATE = 0x36,
469 HW_VAR_TX_RATE_REG = 0x37,
470 HW_VAR_EFUSE_USAGE = 0x38,
471 HW_VAR_EFUSE_BYTES = 0x39,
472 HW_VAR_AUTOLOAD_STATUS = 0x3a,
473 HW_VAR_RF_2R_DISABLE = 0x3b,
474 HW_VAR_SET_RPWM = 0x3c,
475 HW_VAR_H2C_FW_PWRMODE = 0x3d,
476 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
477 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
478 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
479 HW_VAR_FW_PSMODE_STATUS = 0x41,
480 HW_VAR_INIT_RTS_RATE = 0x42,
481 HW_VAR_RESUME_CLK_ON = 0x43,
482 HW_VAR_FW_LPS_ACTION = 0x44,
483 HW_VAR_1X1_RECV_COMBINE = 0x45,
484 HW_VAR_STOP_SEND_BEACON = 0x46,
485 HW_VAR_TSF_TIMER = 0x47,
486 HW_VAR_IO_CMD = 0x48,
487
488 HW_VAR_RF_RECOVERY = 0x49,
489 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
490 HW_VAR_WF_MASK = 0x4b,
491 HW_VAR_WF_CRC = 0x4c,
492 HW_VAR_WF_IS_MAC_ADDR = 0x4d,
493 HW_VAR_H2C_FW_OFFLOAD = 0x4e,
494 HW_VAR_RESET_WFCRC = 0x4f,
495
496 HW_VAR_HANDLE_FW_C2H = 0x50,
497 HW_VAR_DL_FW_RSVD_PAGE = 0x51,
498 HW_VAR_AID = 0x52,
499 HW_VAR_HW_SEQ_ENABLE = 0x53,
500 HW_VAR_CORRECT_TSF = 0x54,
501 HW_VAR_BCN_VALID = 0x55,
502 HW_VAR_FWLPS_RF_ON = 0x56,
503 HW_VAR_DUAL_TSF_RST = 0x57,
504 HW_VAR_SWITCH_EPHY_WOWLAN = 0x58,
505 HW_VAR_INT_MIGRATION = 0x59,
506 HW_VAR_INT_AC = 0x5a,
507 HW_VAR_RF_TIMING = 0x5b,
508
509 HAL_DEF_WOWLAN = 0x5c,
510 HW_VAR_MRC = 0x5d,
511 HW_VAR_KEEP_ALIVE = 0x5e,
512 HW_VAR_NAV_UPPER = 0x5f,
513
514 HW_VAR_MGT_FILTER = 0x60,
515 HW_VAR_CTRL_FILTER = 0x61,
516 HW_VAR_DATA_FILTER = 0x62,
517 };
518
519 enum rt_media_status {
520 RT_MEDIA_DISCONNECT = 0,
521 RT_MEDIA_CONNECT = 1
522 };
523
524 enum rt_oem_id {
525 RT_CID_DEFAULT = 0,
526 RT_CID_8187_ALPHA0 = 1,
527 RT_CID_8187_SERCOMM_PS = 2,
528 RT_CID_8187_HW_LED = 3,
529 RT_CID_8187_NETGEAR = 4,
530 RT_CID_WHQL = 5,
531 RT_CID_819X_CAMEO = 6,
532 RT_CID_819X_RUNTOP = 7,
533 RT_CID_819X_SENAO = 8,
534 RT_CID_TOSHIBA = 9,
535 RT_CID_819X_NETCORE = 10,
536 RT_CID_NETTRONIX = 11,
537 RT_CID_DLINK = 12,
538 RT_CID_PRONET = 13,
539 RT_CID_COREGA = 14,
540 RT_CID_819X_ALPHA = 15,
541 RT_CID_819X_SITECOM = 16,
542 RT_CID_CCX = 17,
543 RT_CID_819X_LENOVO = 18,
544 RT_CID_819X_QMI = 19,
545 RT_CID_819X_EDIMAX_BELKIN = 20,
546 RT_CID_819X_SERCOMM_BELKIN = 21,
547 RT_CID_819X_CAMEO1 = 22,
548 RT_CID_819X_MSI = 23,
549 RT_CID_819X_ACER = 24,
550 RT_CID_819X_HP = 27,
551 RT_CID_819X_CLEVO = 28,
552 RT_CID_819X_ARCADYAN_BELKIN = 29,
553 RT_CID_819X_SAMSUNG = 30,
554 RT_CID_819X_WNC_COREGA = 31,
555 RT_CID_819X_FOXCOON = 32,
556 RT_CID_819X_DELL = 33,
557 RT_CID_819X_PRONETS = 34,
558 RT_CID_819X_EDIMAX_ASUS = 35,
559 RT_CID_NETGEAR = 36,
560 RT_CID_PLANEX = 37,
561 RT_CID_CC_C = 38,
562 RT_CID_LENOVO_CHINA = 40,
563 };
564
565 enum hw_descs {
566 HW_DESC_OWN,
567 HW_DESC_RXOWN,
568 HW_DESC_TX_NEXTDESC_ADDR,
569 HW_DESC_TXBUFF_ADDR,
570 HW_DESC_RXBUFF_ADDR,
571 HW_DESC_RXPKT_LEN,
572 HW_DESC_RXERO,
573 HW_DESC_RX_PREPARE,
574 };
575
576 enum prime_sc {
577 PRIME_CHNL_OFFSET_DONT_CARE = 0,
578 PRIME_CHNL_OFFSET_LOWER = 1,
579 PRIME_CHNL_OFFSET_UPPER = 2,
580 };
581
582 enum rf_type {
583 RF_1T1R = 0,
584 RF_1T2R = 1,
585 RF_2T2R = 2,
586 RF_2T2R_GREEN = 3,
587 RF_2T3R = 4,
588 RF_2T4R = 5,
589 RF_3T3R = 6,
590 RF_3T4R = 7,
591 RF_4T4R = 8,
592 };
593
594 enum ht_channel_width {
595 HT_CHANNEL_WIDTH_20 = 0,
596 HT_CHANNEL_WIDTH_20_40 = 1,
597 HT_CHANNEL_WIDTH_80 = 2,
598 HT_CHANNEL_WIDTH_MAX,
599 };
600
601 /* Ref: 802.11i spec D10.0 7.3.2.25.1
602 * Cipher Suites Encryption Algorithms
603 */
604 enum rt_enc_alg {
605 NO_ENCRYPTION = 0,
606 WEP40_ENCRYPTION = 1,
607 TKIP_ENCRYPTION = 2,
608 RSERVED_ENCRYPTION = 3,
609 AESCCMP_ENCRYPTION = 4,
610 WEP104_ENCRYPTION = 5,
611 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
612 };
613
614 enum rtl_hal_state {
615 _HAL_STATE_STOP = 0,
616 _HAL_STATE_START = 1,
617 };
618
619 enum rtl_desc_rate {
620 DESC_RATE1M = 0x00,
621 DESC_RATE2M = 0x01,
622 DESC_RATE5_5M = 0x02,
623 DESC_RATE11M = 0x03,
624
625 DESC_RATE6M = 0x04,
626 DESC_RATE9M = 0x05,
627 DESC_RATE12M = 0x06,
628 DESC_RATE18M = 0x07,
629 DESC_RATE24M = 0x08,
630 DESC_RATE36M = 0x09,
631 DESC_RATE48M = 0x0a,
632 DESC_RATE54M = 0x0b,
633
634 DESC_RATEMCS0 = 0x0c,
635 DESC_RATEMCS1 = 0x0d,
636 DESC_RATEMCS2 = 0x0e,
637 DESC_RATEMCS3 = 0x0f,
638 DESC_RATEMCS4 = 0x10,
639 DESC_RATEMCS5 = 0x11,
640 DESC_RATEMCS6 = 0x12,
641 DESC_RATEMCS7 = 0x13,
642 DESC_RATEMCS8 = 0x14,
643 DESC_RATEMCS9 = 0x15,
644 DESC_RATEMCS10 = 0x16,
645 DESC_RATEMCS11 = 0x17,
646 DESC_RATEMCS12 = 0x18,
647 DESC_RATEMCS13 = 0x19,
648 DESC_RATEMCS14 = 0x1a,
649 DESC_RATEMCS15 = 0x1b,
650 DESC_RATEMCS15_SG = 0x1c,
651 DESC_RATEMCS32 = 0x20,
652
653 DESC_RATEVHT1SS_MCS0 = 0x2c,
654 DESC_RATEVHT1SS_MCS1 = 0x2d,
655 DESC_RATEVHT1SS_MCS2 = 0x2e,
656 DESC_RATEVHT1SS_MCS3 = 0x2f,
657 DESC_RATEVHT1SS_MCS4 = 0x30,
658 DESC_RATEVHT1SS_MCS5 = 0x31,
659 DESC_RATEVHT1SS_MCS6 = 0x32,
660 DESC_RATEVHT1SS_MCS7 = 0x33,
661 DESC_RATEVHT1SS_MCS8 = 0x34,
662 DESC_RATEVHT1SS_MCS9 = 0x35,
663 DESC_RATEVHT2SS_MCS0 = 0x36,
664 DESC_RATEVHT2SS_MCS1 = 0x37,
665 DESC_RATEVHT2SS_MCS2 = 0x38,
666 DESC_RATEVHT2SS_MCS3 = 0x39,
667 DESC_RATEVHT2SS_MCS4 = 0x3a,
668 DESC_RATEVHT2SS_MCS5 = 0x3b,
669 DESC_RATEVHT2SS_MCS6 = 0x3c,
670 DESC_RATEVHT2SS_MCS7 = 0x3d,
671 DESC_RATEVHT2SS_MCS8 = 0x3e,
672 DESC_RATEVHT2SS_MCS9 = 0x3f,
673 };
674
675 enum rtl_var_map {
676 /*reg map */
677 SYS_ISO_CTRL = 0,
678 SYS_FUNC_EN,
679 SYS_CLK,
680 MAC_RCR_AM,
681 MAC_RCR_AB,
682 MAC_RCR_ACRC32,
683 MAC_RCR_ACF,
684 MAC_RCR_AAP,
685 MAC_HIMR,
686 MAC_HIMRE,
687 MAC_HSISR,
688
689 /*efuse map */
690 EFUSE_TEST,
691 EFUSE_CTRL,
692 EFUSE_CLK,
693 EFUSE_CLK_CTRL,
694 EFUSE_PWC_EV12V,
695 EFUSE_FEN_ELDR,
696 EFUSE_LOADER_CLK_EN,
697 EFUSE_ANA8M,
698 EFUSE_HWSET_MAX_SIZE,
699 EFUSE_MAX_SECTION_MAP,
700 EFUSE_REAL_CONTENT_SIZE,
701 EFUSE_OOB_PROTECT_BYTES_LEN,
702 EFUSE_ACCESS,
703
704 /*CAM map */
705 RWCAM,
706 WCAMI,
707 RCAMO,
708 CAMDBG,
709 SECR,
710 SEC_CAM_NONE,
711 SEC_CAM_WEP40,
712 SEC_CAM_TKIP,
713 SEC_CAM_AES,
714 SEC_CAM_WEP104,
715
716 /*IMR map */
717 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
718 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
719 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
720 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
721 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
722 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
723 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
724 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
725 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
726 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
727 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
728 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
729 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
730 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
731 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
732 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
733 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
734 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
735 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
736 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
737 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
738 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
739 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */
740 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
741 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
742 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
743 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
744 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
745 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
746 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
747 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
748 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
749 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
750 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
751 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
752 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
753 * RTL_IMR_TBDER)
754 */
755 RTL_IMR_C2HCMD, /*fw interrupt*/
756
757 /*CCK Rates, TxHT = 0 */
758 RTL_RC_CCK_RATE1M,
759 RTL_RC_CCK_RATE2M,
760 RTL_RC_CCK_RATE5_5M,
761 RTL_RC_CCK_RATE11M,
762
763 /*OFDM Rates, TxHT = 0 */
764 RTL_RC_OFDM_RATE6M,
765 RTL_RC_OFDM_RATE9M,
766 RTL_RC_OFDM_RATE12M,
767 RTL_RC_OFDM_RATE18M,
768 RTL_RC_OFDM_RATE24M,
769 RTL_RC_OFDM_RATE36M,
770 RTL_RC_OFDM_RATE48M,
771 RTL_RC_OFDM_RATE54M,
772
773 RTL_RC_HT_RATEMCS7,
774 RTL_RC_HT_RATEMCS15,
775
776 RTL_RC_VHT_RATE_1SS_MCS7,
777 RTL_RC_VHT_RATE_1SS_MCS8,
778 RTL_RC_VHT_RATE_1SS_MCS9,
779 RTL_RC_VHT_RATE_2SS_MCS7,
780 RTL_RC_VHT_RATE_2SS_MCS8,
781 RTL_RC_VHT_RATE_2SS_MCS9,
782
783 /*keep it last */
784 RTL_VAR_MAP_MAX,
785 };
786
787 /*Firmware PS mode for control LPS.*/
788 enum _fw_ps_mode {
789 FW_PS_ACTIVE_MODE = 0,
790 FW_PS_MIN_MODE = 1,
791 FW_PS_MAX_MODE = 2,
792 FW_PS_DTIM_MODE = 3,
793 FW_PS_VOIP_MODE = 4,
794 FW_PS_UAPSD_WMM_MODE = 5,
795 FW_PS_UAPSD_MODE = 6,
796 FW_PS_IBSS_MODE = 7,
797 FW_PS_WWLAN_MODE = 8,
798 FW_PS_PM_RADIO_OFF = 9,
799 FW_PS_PM_CARD_DISABLE = 10,
800 };
801
802 enum rt_psmode {
803 EACTIVE, /*Active/Continuous access. */
804 EMAXPS, /*Max power save mode. */
805 EFASTPS, /*Fast power save mode. */
806 EAUTOPS, /*Auto power save mode. */
807 };
808
809 /*LED related.*/
810 enum led_ctl_mode {
811 LED_CTL_POWER_ON = 1,
812 LED_CTL_LINK = 2,
813 LED_CTL_NO_LINK = 3,
814 LED_CTL_TX = 4,
815 LED_CTL_RX = 5,
816 LED_CTL_SITE_SURVEY = 6,
817 LED_CTL_POWER_OFF = 7,
818 LED_CTL_START_TO_LINK = 8,
819 LED_CTL_START_WPS = 9,
820 LED_CTL_STOP_WPS = 10,
821 };
822
823 enum rtl_led_pin {
824 LED_PIN_GPIO0,
825 LED_PIN_LED0,
826 LED_PIN_LED1,
827 LED_PIN_LED2
828 };
829
830 /*QoS related.*/
831 /*acm implementation method.*/
832 enum acm_method {
833 EACMWAY0_SWANDHW = 0,
834 EACMWAY1_HW = 1,
835 EACMWAY2_SW = 2,
836 };
837
838 enum macphy_mode {
839 SINGLEMAC_SINGLEPHY = 0,
840 DUALMAC_DUALPHY,
841 DUALMAC_SINGLEPHY,
842 };
843
844 enum band_type {
845 BAND_ON_2_4G = 0,
846 BAND_ON_5G,
847 BAND_ON_BOTH,
848 BANDMAX
849 };
850
851 /* aci/aifsn Field.
852 * Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
853 */
854 union aci_aifsn {
855 u8 char_data;
856
857 struct {
858 u8 aifsn:4;
859 u8 acm:1;
860 u8 aci:2;
861 u8 reserved:1;
862 } f; /* Field */
863 };
864
865 /*mlme related.*/
866 enum wireless_mode {
867 WIRELESS_MODE_UNKNOWN = 0x00,
868 WIRELESS_MODE_A = 0x01,
869 WIRELESS_MODE_B = 0x02,
870 WIRELESS_MODE_G = 0x04,
871 WIRELESS_MODE_AUTO = 0x08,
872 WIRELESS_MODE_N_24G = 0x10,
873 WIRELESS_MODE_N_5G = 0x20,
874 WIRELESS_MODE_AC_5G = 0x40,
875 WIRELESS_MODE_AC_24G = 0x80,
876 WIRELESS_MODE_AC_ONLY = 0x100,
877 WIRELESS_MODE_MAX = 0x800
878 };
879
880 #define IS_WIRELESS_MODE_A(wirelessmode) \
881 (wirelessmode == WIRELESS_MODE_A)
882 #define IS_WIRELESS_MODE_B(wirelessmode) \
883 (wirelessmode == WIRELESS_MODE_B)
884 #define IS_WIRELESS_MODE_G(wirelessmode) \
885 (wirelessmode == WIRELESS_MODE_G)
886 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
887 (wirelessmode == WIRELESS_MODE_N_24G)
888 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
889 (wirelessmode == WIRELESS_MODE_N_5G)
890
891 enum ratr_table_mode {
892 RATR_INX_WIRELESS_NGB = 0,
893 RATR_INX_WIRELESS_NG = 1,
894 RATR_INX_WIRELESS_NB = 2,
895 RATR_INX_WIRELESS_N = 3,
896 RATR_INX_WIRELESS_GB = 4,
897 RATR_INX_WIRELESS_G = 5,
898 RATR_INX_WIRELESS_B = 6,
899 RATR_INX_WIRELESS_MC = 7,
900 RATR_INX_WIRELESS_A = 8,
901 RATR_INX_WIRELESS_AC_5N = 8,
902 RATR_INX_WIRELESS_AC_24N = 9,
903 };
904
905 enum ratr_table_mode_new {
906 RATEID_IDX_BGN_40M_2SS = 0,
907 RATEID_IDX_BGN_40M_1SS = 1,
908 RATEID_IDX_BGN_20M_2SS_BN = 2,
909 RATEID_IDX_BGN_20M_1SS_BN = 3,
910 RATEID_IDX_GN_N2SS = 4,
911 RATEID_IDX_GN_N1SS = 5,
912 RATEID_IDX_BG = 6,
913 RATEID_IDX_G = 7,
914 RATEID_IDX_B = 8,
915 RATEID_IDX_VHT_2SS = 9,
916 RATEID_IDX_VHT_1SS = 10,
917 RATEID_IDX_MIX1 = 11,
918 RATEID_IDX_MIX2 = 12,
919 RATEID_IDX_VHT_3SS = 13,
920 RATEID_IDX_BGN_3SS = 14,
921 };
922
923 enum rtl_link_state {
924 MAC80211_NOLINK = 0,
925 MAC80211_LINKING = 1,
926 MAC80211_LINKED = 2,
927 MAC80211_LINKED_SCANNING = 3,
928 };
929
930 enum act_category {
931 ACT_CAT_QOS = 1,
932 ACT_CAT_DLS = 2,
933 ACT_CAT_BA = 3,
934 ACT_CAT_HT = 7,
935 ACT_CAT_WMM = 17,
936 };
937
938 enum ba_action {
939 ACT_ADDBAREQ = 0,
940 ACT_ADDBARSP = 1,
941 ACT_DELBA = 2,
942 };
943
944 enum rt_polarity_ctl {
945 RT_POLARITY_LOW_ACT = 0,
946 RT_POLARITY_HIGH_ACT = 1,
947 };
948
949 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
950 enum fw_wow_reason_v2 {
951 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
952 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
953 FW_WOW_V2_DISASSOC_EVENT = 0x04,
954 FW_WOW_V2_DEAUTH_EVENT = 0x08,
955 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
956 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
957 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
958 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
959 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
960 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
961 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
962 FW_WOW_V2_REASON_MAX = 0xff,
963 };
964
965 enum wolpattern_type {
966 UNICAST_PATTERN = 0,
967 MULTICAST_PATTERN = 1,
968 BROADCAST_PATTERN = 2,
969 DONT_CARE_DA = 3,
970 UNKNOWN_TYPE = 4,
971 };
972
973 enum package_type {
974 PACKAGE_DEFAULT,
975 PACKAGE_QFN68,
976 PACKAGE_TFBGA90,
977 PACKAGE_TFBGA80,
978 PACKAGE_TFBGA79
979 };
980
981 enum rtl_spec_ver {
982 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */
983 RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */
984 RTL_SPEC_EXT_C2H = BIT(2), /* extend FW C2H (e.g. TX REPORT) */
985 };
986
987 enum dm_info_query {
988 DM_INFO_FA_OFDM,
989 DM_INFO_FA_CCK,
990 DM_INFO_FA_TOTAL,
991 DM_INFO_CCA_OFDM,
992 DM_INFO_CCA_CCK,
993 DM_INFO_CCA_ALL,
994 DM_INFO_CRC32_OK_VHT,
995 DM_INFO_CRC32_OK_HT,
996 DM_INFO_CRC32_OK_LEGACY,
997 DM_INFO_CRC32_OK_CCK,
998 DM_INFO_CRC32_ERROR_VHT,
999 DM_INFO_CRC32_ERROR_HT,
1000 DM_INFO_CRC32_ERROR_LEGACY,
1001 DM_INFO_CRC32_ERROR_CCK,
1002 DM_INFO_EDCCA_FLAG,
1003 DM_INFO_OFDM_ENABLE,
1004 DM_INFO_CCK_ENABLE,
1005 DM_INFO_CRC32_OK_HT_AGG,
1006 DM_INFO_CRC32_ERROR_HT_AGG,
1007 DM_INFO_DBG_PORT_0,
1008 DM_INFO_CURR_IGI,
1009 DM_INFO_RSSI_MIN,
1010 DM_INFO_RSSI_MAX,
1011 DM_INFO_CLM_RATIO,
1012 DM_INFO_NHM_RATIO,
1013 DM_INFO_IQK_ALL,
1014 DM_INFO_IQK_OK,
1015 DM_INFO_IQK_NG,
1016 DM_INFO_SIZE,
1017 };
1018
1019 enum rx_packet_type {
1020 NORMAL_RX,
1021 TX_REPORT1,
1022 TX_REPORT2,
1023 HIS_REPORT,
1024 C2H_PACKET,
1025 };
1026
1027 struct rtlwifi_tx_info {
1028 int sn;
1029 unsigned long send_time;
1030 };
1031
1032 static inline struct rtlwifi_tx_info *rtl_tx_skb_cb_info(struct sk_buff *skb)
1033 {
1034 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1035
1036 BUILD_BUG_ON(sizeof(struct rtlwifi_tx_info) >
1037 sizeof(info->status.status_driver_data));
1038
1039 return (struct rtlwifi_tx_info *)(info->status.status_driver_data);
1040 }
1041
1042 struct octet_string {
1043 u8 *octet;
1044 u16 length;
1045 };
1046
1047 struct rtl_hdr_3addr {
1048 __le16 frame_ctl;
1049 __le16 duration_id;
1050 u8 addr1[ETH_ALEN];
1051 u8 addr2[ETH_ALEN];
1052 u8 addr3[ETH_ALEN];
1053 __le16 seq_ctl;
1054 u8 payload[];
1055 } __packed;
1056
1057 struct rtl_info_element {
1058 u8 id;
1059 u8 len;
1060 u8 data[];
1061 } __packed;
1062
1063 struct rtl_probe_rsp {
1064 struct rtl_hdr_3addr header;
1065 u32 time_stamp[2];
1066 __le16 beacon_interval;
1067 __le16 capability;
1068 /*SSID, supported rates, FH params, DS params,
1069 * CF params, IBSS params, TIM (if beacon), RSN
1070 */
1071 struct rtl_info_element info_element[];
1072 } __packed;
1073
1074 /*LED related.*/
1075 /*ledpin Identify how to implement this SW led.*/
1076 struct rtl_led {
1077 void *hw;
1078 enum rtl_led_pin ledpin;
1079 bool ledon;
1080 };
1081
1082 struct rtl_led_ctl {
1083 bool led_opendrain;
1084 struct rtl_led sw_led0;
1085 struct rtl_led sw_led1;
1086 };
1087
1088 struct rtl_qos_parameters {
1089 __le16 cw_min;
1090 __le16 cw_max;
1091 u8 aifs;
1092 u8 flag;
1093 __le16 tx_op;
1094 } __packed;
1095
1096 struct rt_smooth_data {
1097 u32 elements[100]; /*array to store values */
1098 u32 index; /*index to current array to store */
1099 u32 total_num; /*num of valid elements */
1100 u32 total_val; /*sum of valid elements */
1101 };
1102
1103 struct false_alarm_statistics {
1104 u32 cnt_parity_fail;
1105 u32 cnt_rate_illegal;
1106 u32 cnt_crc8_fail;
1107 u32 cnt_mcs_fail;
1108 u32 cnt_fast_fsync_fail;
1109 u32 cnt_sb_search_fail;
1110 u32 cnt_ofdm_fail;
1111 u32 cnt_cck_fail;
1112 u32 cnt_all;
1113 u32 cnt_ofdm_cca;
1114 u32 cnt_cck_cca;
1115 u32 cnt_cca_all;
1116 u32 cnt_bw_usc;
1117 u32 cnt_bw_lsc;
1118 };
1119
1120 struct init_gain {
1121 u8 xaagccore1;
1122 u8 xbagccore1;
1123 u8 xcagccore1;
1124 u8 xdagccore1;
1125 u8 cca;
1126
1127 };
1128
1129 struct wireless_stats {
1130 u64 txbytesunicast;
1131 u64 txbytesmulticast;
1132 u64 txbytesbroadcast;
1133 u64 rxbytesunicast;
1134
1135 u64 txbytesunicast_inperiod;
1136 u64 rxbytesunicast_inperiod;
1137 u32 txbytesunicast_inperiod_tp;
1138 u32 rxbytesunicast_inperiod_tp;
1139 u64 txbytesunicast_last;
1140 u64 rxbytesunicast_last;
1141
1142 long rx_snr_db[4];
1143 /*Correct smoothed ss in Dbm, only used
1144 * in driver to report real power now.
1145 */
1146 long recv_signal_power;
1147 long signal_quality;
1148 long last_sigstrength_inpercent;
1149
1150 u32 rssi_calculate_cnt;
1151 u32 pwdb_all_cnt;
1152
1153 /* Transformed, in dbm. Beautified signal
1154 * strength for UI, not correct.
1155 */
1156 long signal_strength;
1157
1158 u8 rx_rssi_percentage[4];
1159 u8 rx_evm_dbm[4];
1160 u8 rx_evm_percentage[2];
1161
1162 u16 rx_cfo_short[4];
1163 u16 rx_cfo_tail[4];
1164
1165 struct rt_smooth_data ui_rssi;
1166 struct rt_smooth_data ui_link_quality;
1167 };
1168
1169 struct rate_adaptive {
1170 u8 rate_adaptive_disabled;
1171 u8 ratr_state;
1172 u16 reserve;
1173
1174 u32 high_rssi_thresh_for_ra;
1175 u32 high2low_rssi_thresh_for_ra;
1176 u8 low2high_rssi_thresh_for_ra40m;
1177 u32 low_rssi_thresh_for_ra40m;
1178 u8 low2high_rssi_thresh_for_ra20m;
1179 u32 low_rssi_thresh_for_ra20m;
1180 u32 upper_rssi_threshold_ratr;
1181 u32 middleupper_rssi_threshold_ratr;
1182 u32 middle_rssi_threshold_ratr;
1183 u32 middlelow_rssi_threshold_ratr;
1184 u32 low_rssi_threshold_ratr;
1185 u32 ultralow_rssi_threshold_ratr;
1186 u32 low_rssi_threshold_ratr_40m;
1187 u32 low_rssi_threshold_ratr_20m;
1188 u8 ping_rssi_enable;
1189 u32 ping_rssi_ratr;
1190 u32 ping_rssi_thresh_for_ra;
1191 u32 last_ratr;
1192 u8 pre_ratr_state;
1193 u8 ldpc_thres;
1194 bool use_ldpc;
1195 bool lower_rts_rate;
1196 bool is_special_data;
1197 };
1198
1199 struct regd_pair_mapping {
1200 u16 reg_dmnenum;
1201 u16 reg_5ghz_ctl;
1202 u16 reg_2ghz_ctl;
1203 };
1204
1205 struct dynamic_primary_cca {
1206 u8 pricca_flag;
1207 u8 intf_flag;
1208 u8 intf_type;
1209 u8 dup_rts_flag;
1210 u8 monitor_flag;
1211 u8 ch_offset;
1212 u8 mf_state;
1213 };
1214
1215 struct rtl_regulatory {
1216 s8 alpha2[2];
1217 u16 country_code;
1218 u16 max_power_level;
1219 u32 tp_scale;
1220 u16 current_rd;
1221 u16 current_rd_ext;
1222 int16_t power_limit;
1223 struct regd_pair_mapping *regpair;
1224 };
1225
1226 struct rtl_rfkill {
1227 bool rfkill_state; /*0 is off, 1 is on */
1228 };
1229
1230 /*for P2P PS**/
1231 #define P2P_MAX_NOA_NUM 2
1232
1233 enum p2p_role {
1234 P2P_ROLE_DISABLE = 0,
1235 P2P_ROLE_DEVICE = 1,
1236 P2P_ROLE_CLIENT = 2,
1237 P2P_ROLE_GO = 3
1238 };
1239
1240 enum p2p_ps_state {
1241 P2P_PS_DISABLE = 0,
1242 P2P_PS_ENABLE = 1,
1243 P2P_PS_SCAN = 2,
1244 P2P_PS_SCAN_DONE = 3,
1245 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1246 };
1247
1248 enum p2p_ps_mode {
1249 P2P_PS_NONE = 0,
1250 P2P_PS_CTWINDOW = 1,
1251 P2P_PS_NOA = 2,
1252 P2P_PS_MIX = 3, /* CTWindow and NoA */
1253 };
1254
1255 struct rtl_p2p_ps_info {
1256 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1257 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1258 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1259 /* Client traffic window. A period of time in TU after TBTT. */
1260 u8 ctwindow;
1261 u8 opp_ps; /* opportunistic power save. */
1262 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1263 /* Count for owner, Type of client. */
1264 u8 noa_count_type[P2P_MAX_NOA_NUM];
1265 /* Max duration for owner, preferred or min acceptable duration
1266 * for client.
1267 */
1268 u32 noa_duration[P2P_MAX_NOA_NUM];
1269 /* Length of interval for owner, preferred or max acceptable intervali
1270 * of client.
1271 */
1272 u32 noa_interval[P2P_MAX_NOA_NUM];
1273 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1274 u32 noa_start_time[P2P_MAX_NOA_NUM];
1275 };
1276
1277 struct p2p_ps_offload_t {
1278 u8 offload_en:1;
1279 u8 role:1; /* 1: Owner, 0: Client */
1280 u8 ctwindow_en:1;
1281 u8 noa0_en:1;
1282 u8 noa1_en:1;
1283 u8 allstasleep:1;
1284 u8 discovery:1;
1285 u8 reserved:1;
1286 };
1287
1288 #define IQK_MATRIX_REG_NUM 8
1289 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1290
1291 struct iqk_matrix_regs {
1292 bool iqk_done;
1293 long value[1][IQK_MATRIX_REG_NUM];
1294 };
1295
1296 struct phy_parameters {
1297 u16 length;
1298 u32 *pdata;
1299 };
1300
1301 enum hw_param_tab_index {
1302 PHY_REG_2T,
1303 PHY_REG_1T,
1304 PHY_REG_PG,
1305 RADIOA_2T,
1306 RADIOB_2T,
1307 RADIOA_1T,
1308 RADIOB_1T,
1309 MAC_REG,
1310 AGCTAB_2T,
1311 AGCTAB_1T,
1312 MAX_TAB
1313 };
1314
1315 struct rtl_phy {
1316 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1317 struct init_gain initgain_backup;
1318 enum io_type current_io_type;
1319
1320 u8 rf_mode;
1321 u8 rf_type;
1322 u8 current_chan_bw;
1323 u8 set_bwmode_inprogress;
1324 u8 sw_chnl_inprogress;
1325 u8 sw_chnl_stage;
1326 u8 sw_chnl_step;
1327 u8 current_channel;
1328 u8 h2c_box_num;
1329 u8 set_io_inprogress;
1330 u8 lck_inprogress;
1331
1332 /* record for power tracking */
1333 s32 reg_e94;
1334 s32 reg_e9c;
1335 s32 reg_ea4;
1336 s32 reg_eac;
1337 s32 reg_eb4;
1338 s32 reg_ebc;
1339 s32 reg_ec4;
1340 s32 reg_ecc;
1341 u8 rfpienable;
1342 u8 reserve_0;
1343 u16 reserve_1;
1344 u32 reg_c04, reg_c08, reg_874;
1345 u32 adda_backup[16];
1346 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1347 u32 iqk_bb_backup[10];
1348 bool iqk_initialized;
1349
1350 bool rfpath_rx_enable[MAX_RF_PATH];
1351 u8 reg_837;
1352 /* Dual mac */
1353 bool need_iqk;
1354 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1355
1356 bool rfpi_enable;
1357 bool iqk_in_progress;
1358
1359 u8 pwrgroup_cnt;
1360 u8 cck_high_power;
1361 /* this is for 88E & 8723A */
1362 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1363 /* MAX_PG_GROUP groups of pwr diff by rates */
1364 u32 mcs_offset[MAX_PG_GROUP][16];
1365 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1366 [TX_PWR_BY_RATE_NUM_RF]
1367 [TX_PWR_BY_RATE_NUM_RF]
1368 [TX_PWR_BY_RATE_NUM_RATE];
1369 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1370 [TX_PWR_BY_RATE_NUM_RF]
1371 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1372 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1373 [TX_PWR_BY_RATE_NUM_RF]
1374 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1375 u8 default_initialgain[4];
1376
1377 /* the current Tx power level */
1378 u8 cur_cck_txpwridx;
1379 u8 cur_ofdm24g_txpwridx;
1380 u8 cur_bw20_txpwridx;
1381 u8 cur_bw40_txpwridx;
1382
1383 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1384 [MAX_2_4G_BANDWIDTH_NUM]
1385 [MAX_RATE_SECTION_NUM]
1386 [CHANNEL_MAX_NUMBER_2G]
1387 [MAX_RF_PATH_NUM];
1388 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1389 [MAX_5G_BANDWIDTH_NUM]
1390 [MAX_RATE_SECTION_NUM]
1391 [CHANNEL_MAX_NUMBER_5G]
1392 [MAX_RF_PATH_NUM];
1393
1394 u32 rfreg_chnlval[2];
1395 bool apk_done;
1396 u32 reg_rf3c[2]; /* pathA / pathB */
1397
1398 u32 backup_rf_0x1a;/*92ee*/
1399 /* bfsync */
1400 u8 framesync;
1401 u32 framesync_c34;
1402
1403 u8 num_total_rfpath;
1404 struct phy_parameters hwparam_tables[MAX_TAB];
1405 u16 rf_pathmap;
1406
1407 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1408 enum rt_polarity_ctl polarity_ctl;
1409 };
1410
1411 #define MAX_TID_COUNT 9
1412 #define RTL_AGG_STOP 0
1413 #define RTL_AGG_PROGRESS 1
1414 #define RTL_AGG_START 2
1415 #define RTL_AGG_OPERATIONAL 3
1416 #define RTL_AGG_OFF 0
1417 #define RTL_AGG_ON 1
1418 #define RTL_RX_AGG_START 1
1419 #define RTL_RX_AGG_STOP 0
1420 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1421 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1422
1423 struct rtl_ht_agg {
1424 u16 txq_id;
1425 u16 wait_for_ba;
1426 u16 start_idx;
1427 u64 bitmap;
1428 u32 rate_n_flags;
1429 u8 agg_state;
1430 u8 rx_agg_state;
1431 };
1432
1433 struct rssi_sta {
1434 long undec_sm_pwdb;
1435 long undec_sm_cck;
1436 };
1437
1438 struct rtl_tid_data {
1439 struct rtl_ht_agg agg;
1440 };
1441
1442 struct rtl_sta_info {
1443 struct list_head list;
1444 struct rtl_tid_data tids[MAX_TID_COUNT];
1445 /* just used for ap adhoc or mesh*/
1446 struct rssi_sta rssi_stat;
1447 u8 rssi_level;
1448 u16 wireless_mode;
1449 u8 ratr_index;
1450 u8 mimo_ps;
1451 u8 mac_addr[ETH_ALEN];
1452 } __packed;
1453
1454 struct rtl_priv;
1455 struct rtl_io {
1456 struct device *dev;
1457 struct mutex bb_mutex;
1458
1459 /*PCI MEM map */
1460 unsigned long pci_mem_end; /*shared mem end */
1461 unsigned long pci_mem_start; /*shared mem start */
1462
1463 /*PCI IO map */
1464 unsigned long pci_base_addr; /*device I/O address */
1465
1466 void (*write8_async)(struct rtl_priv *rtlpriv, u32 addr, u8 val);
1467 void (*write16_async)(struct rtl_priv *rtlpriv, u32 addr, u16 val);
1468 void (*write32_async)(struct rtl_priv *rtlpriv, u32 addr, u32 val);
1469 void (*writen_sync)(struct rtl_priv *rtlpriv, u32 addr, void *buf,
1470 u16 len);
1471
1472 u8 (*read8_sync)(struct rtl_priv *rtlpriv, u32 addr);
1473 u16 (*read16_sync)(struct rtl_priv *rtlpriv, u32 addr);
1474 u32 (*read32_sync)(struct rtl_priv *rtlpriv, u32 addr);
1475
1476 };
1477
1478 struct rtl_mac {
1479 u8 mac_addr[ETH_ALEN];
1480 u8 mac80211_registered;
1481 u8 beacon_enabled;
1482
1483 u32 tx_ss_num;
1484 u32 rx_ss_num;
1485
1486 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1487 struct ieee80211_hw *hw;
1488 struct ieee80211_vif *vif;
1489 enum nl80211_iftype opmode;
1490
1491 /*Probe Beacon management */
1492 struct rtl_tid_data tids[MAX_TID_COUNT];
1493 enum rtl_link_state link_state;
1494
1495 int n_channels;
1496 int n_bitrates;
1497
1498 bool offchan_delay;
1499 u8 p2p; /*using p2p role*/
1500 bool p2p_in_use;
1501
1502 /*filters */
1503 u32 rx_conf;
1504 u16 rx_mgt_filter;
1505 u16 rx_ctrl_filter;
1506 u16 rx_data_filter;
1507
1508 bool act_scanning;
1509 u8 cnt_after_linked;
1510 bool skip_scan;
1511
1512 /* early mode */
1513 /* skb wait queue */
1514 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1515
1516 u8 ht_stbc_cap;
1517 u8 ht_cur_stbc;
1518
1519 /*vht support*/
1520 u8 vht_enable;
1521 u8 bw_80;
1522 u8 vht_cur_ldpc;
1523 u8 vht_cur_stbc;
1524 u8 vht_stbc_cap;
1525 u8 vht_ldpc_cap;
1526
1527 /*RDG*/
1528 bool rdg_en;
1529
1530 /*AP*/
1531 u8 bssid[ETH_ALEN] __aligned(2);
1532 u32 vendor;
1533 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1534 u32 basic_rates; /* b/g rates */
1535 u8 ht_enable;
1536 u8 sgi_40;
1537 u8 sgi_20;
1538 u8 bw_40;
1539 u16 mode; /* wireless mode */
1540 u8 slot_time;
1541 u8 short_preamble;
1542 u8 use_cts_protect;
1543 u8 cur_40_prime_sc;
1544 u8 cur_40_prime_sc_bk;
1545 u8 cur_80_prime_sc;
1546 u64 tsf;
1547 u8 retry_short;
1548 u8 retry_long;
1549 u16 assoc_id;
1550 bool hiddenssid;
1551
1552 /*IBSS*/
1553 int beacon_interval;
1554
1555 /*AMPDU*/
1556 u8 min_space_cfg; /*For Min spacing configurations */
1557 u8 max_mss_density;
1558 u8 current_ampdu_factor;
1559 u8 current_ampdu_density;
1560
1561 /*QOS & EDCA */
1562 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1563 struct rtl_qos_parameters ac[AC_MAX];
1564
1565 /* counters */
1566 u64 last_txok_cnt;
1567 u64 last_rxok_cnt;
1568 u32 last_bt_edca_ul;
1569 u32 last_bt_edca_dl;
1570 };
1571
1572 struct btdm_8723 {
1573 bool all_off;
1574 bool agc_table_en;
1575 bool adc_back_off_on;
1576 bool b2_ant_hid_en;
1577 bool low_penalty_rate_adaptive;
1578 bool rf_rx_lpf_shrink;
1579 bool reject_aggre_pkt;
1580 bool tra_tdma_on;
1581 u8 tra_tdma_nav;
1582 u8 tra_tdma_ant;
1583 bool tdma_on;
1584 u8 tdma_ant;
1585 u8 tdma_nav;
1586 u8 tdma_dac_swing;
1587 u8 fw_dac_swing_lvl;
1588 bool ps_tdma_on;
1589 u8 ps_tdma_byte[5];
1590 bool pta_on;
1591 u32 val_0x6c0;
1592 u32 val_0x6c8;
1593 u32 val_0x6cc;
1594 bool sw_dac_swing_on;
1595 u32 sw_dac_swing_lvl;
1596 u32 wlan_act_hi;
1597 u32 wlan_act_lo;
1598 u32 bt_retry_index;
1599 bool dec_bt_pwr;
1600 bool ignore_wlan_act;
1601 };
1602
1603 struct bt_coexist_8723 {
1604 u32 high_priority_tx;
1605 u32 high_priority_rx;
1606 u32 low_priority_tx;
1607 u32 low_priority_rx;
1608 u8 c2h_bt_info;
1609 bool c2h_bt_info_req_sent;
1610 bool c2h_bt_inquiry_page;
1611 u32 bt_inq_page_start_time;
1612 u8 bt_retry_cnt;
1613 u8 c2h_bt_info_original;
1614 u8 bt_inquiry_page_cnt;
1615 struct btdm_8723 btdm;
1616 };
1617
1618 struct rtl_hal {
1619 struct ieee80211_hw *hw;
1620 bool driver_is_goingto_unload;
1621 bool up_first_time;
1622 bool first_init;
1623 bool being_init_adapter;
1624 bool bbrf_ready;
1625 bool mac_func_enable;
1626 bool pre_edcca_enable;
1627 struct bt_coexist_8723 hal_coex_8723;
1628
1629 enum intf_type interface;
1630 u16 hw_type; /*92c or 92d or 92s and so on */
1631 u8 ic_class;
1632 u8 oem_id;
1633 u32 version; /*version of chip */
1634 u8 state; /*stop 0, start 1 */
1635 u8 board_type;
1636 u8 package_type;
1637 u8 external_pa;
1638
1639 u8 pa_mode;
1640 u8 pa_type_2g;
1641 u8 pa_type_5g;
1642 u8 lna_type_2g;
1643 u8 lna_type_5g;
1644 u8 external_pa_2g;
1645 u8 external_lna_2g;
1646 u8 external_pa_5g;
1647 u8 external_lna_5g;
1648 u8 type_glna;
1649 u8 type_gpa;
1650 u8 type_alna;
1651 u8 type_apa;
1652 u8 rfe_type;
1653
1654 /*firmware */
1655 u32 fwsize;
1656 u8 *pfirmware;
1657 u16 fw_version;
1658 u16 fw_subversion;
1659 bool h2c_setinprogress;
1660 u8 last_hmeboxnum;
1661 bool fw_ready;
1662 /*Reserve page start offset except beacon in TxQ. */
1663 u8 fw_rsvdpage_startoffset;
1664 u8 h2c_txcmd_seq;
1665 u8 current_ra_rate;
1666
1667 /* FW Cmd IO related */
1668 u16 fwcmd_iomap;
1669 u32 fwcmd_ioparam;
1670 bool set_fwcmd_inprogress;
1671 u8 current_fwcmd_io;
1672
1673 struct p2p_ps_offload_t p2p_ps_offload;
1674 bool fw_clk_change_in_progress;
1675 bool allow_sw_to_change_hwclc;
1676 u8 fw_ps_state;
1677 /**/
1678 bool driver_going2unload;
1679
1680 /*AMPDU init min space*/
1681 u8 minspace_cfg; /*For Min spacing configurations */
1682
1683 /* Dual mac */
1684 enum macphy_mode macphymode;
1685 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1686 enum band_type current_bandtypebackup;
1687 enum band_type bandset;
1688 /* dual MAC 0--Mac0 1--Mac1 */
1689 u32 interfaceindex;
1690 /* just for DualMac S3S4 */
1691 u8 macphyctl_reg;
1692 bool earlymode_enable;
1693 u8 max_earlymode_num;
1694 /* Dual mac*/
1695 bool during_mac0init_radiob;
1696 bool during_mac1init_radioa;
1697 bool reloadtxpowerindex;
1698 /* True if IMR or IQK have done
1699 * for 2.4G in scan progress
1700 */
1701 bool load_imrandiqk_setting_for2g;
1702
1703 bool disable_amsdu_8k;
1704 bool master_of_dmsp;
1705 bool slave_of_dmsp;
1706
1707 u16 rx_tag;/*for 92ee*/
1708 u8 rts_en;
1709
1710 /*for wowlan*/
1711 bool wow_enable;
1712 bool enter_pnp_sleep;
1713 bool wake_from_pnp_sleep;
1714 bool wow_enabled;
1715 time64_t last_suspend_sec;
1716 u32 wowlan_fwsize;
1717 u8 *wowlan_firmware;
1718
1719 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1720
1721 bool real_wow_v2_enable;
1722 bool re_init_llt_table;
1723 };
1724
1725 struct rtl_security {
1726 /*default 0 */
1727 bool use_sw_sec;
1728
1729 bool being_setkey;
1730 bool use_defaultkey;
1731 /*Encryption Algorithm for Unicast Packet */
1732 enum rt_enc_alg pairwise_enc_algorithm;
1733 /*Encryption Algorithm for Brocast/Multicast */
1734 enum rt_enc_alg group_enc_algorithm;
1735 /*Cam Entry Bitmap */
1736 u32 hwsec_cam_bitmap;
1737 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1738 /*local Key buffer, indx 0 is for
1739 * pairwise key 1-4 is for agoup key.
1740 */
1741 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1742 u8 key_len[KEY_BUF_SIZE];
1743
1744 /*The pointer of Pairwise Key,
1745 * it always points to KeyBuf[4]
1746 */
1747 u8 *pairwise_key;
1748 };
1749
1750 #define ASSOCIATE_ENTRY_NUM 33
1751
1752 struct fast_ant_training {
1753 u8 bssid[6];
1754 u8 antsel_rx_keep_0;
1755 u8 antsel_rx_keep_1;
1756 u8 antsel_rx_keep_2;
1757 u32 ant_sum[7];
1758 u32 ant_cnt[7];
1759 u32 ant_ave[7];
1760 u8 fat_state;
1761 u32 train_idx;
1762 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1763 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1764 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1765 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1766 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1767 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1768 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1769 u8 rx_idle_ant;
1770 bool becomelinked;
1771 };
1772
1773 struct dm_phy_dbg_info {
1774 s8 rx_snrdb[4];
1775 u64 num_qry_phy_status;
1776 u64 num_qry_phy_status_cck;
1777 u64 num_qry_phy_status_ofdm;
1778 u16 num_qry_beacon_pkt;
1779 u16 num_non_be_pkt;
1780 s32 rx_evm[4];
1781 };
1782
1783 struct rtl_dm {
1784 /*PHY status for Dynamic Management */
1785 long entry_min_undec_sm_pwdb;
1786 long undec_sm_cck;
1787 long undec_sm_pwdb; /*out dm */
1788 long entry_max_undec_sm_pwdb;
1789 s32 ofdm_pkt_cnt;
1790 bool dm_initialgain_enable;
1791 bool dynamic_txpower_enable;
1792 bool current_turbo_edca;
1793 bool is_any_nonbepkts; /*out dm */
1794 bool is_cur_rdlstate;
1795 bool txpower_trackinginit;
1796 bool disable_framebursting;
1797 bool cck_inch14;
1798 bool txpower_tracking;
1799 bool useramask;
1800 bool rfpath_rxenable[4];
1801 bool inform_fw_driverctrldm;
1802 bool current_mrc_switch;
1803 u8 txpowercount;
1804 u8 powerindex_backup[6];
1805
1806 u8 thermalvalue_rxgain;
1807 u8 thermalvalue_iqk;
1808 u8 thermalvalue_lck;
1809 u8 thermalvalue;
1810 u8 last_dtp_lvl;
1811 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1812 u8 thermalvalue_avg_index;
1813 u8 tm_trigger;
1814 bool done_txpower;
1815 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1816 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1817 u8 dm_flag_tmp;
1818 u8 dm_type;
1819 u8 dm_rssi_sel;
1820 u8 txpower_track_control;
1821 bool interrupt_migration;
1822 bool disable_tx_int;
1823 s8 ofdm_index[MAX_RF_PATH];
1824 u8 default_ofdm_index;
1825 u8 default_cck_index;
1826 s8 cck_index;
1827 s8 delta_power_index[MAX_RF_PATH];
1828 s8 delta_power_index_last[MAX_RF_PATH];
1829 s8 power_index_offset[MAX_RF_PATH];
1830 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1831 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1832 s8 remnant_cck_idx;
1833 bool modify_txagc_flag_path_a;
1834 bool modify_txagc_flag_path_b;
1835
1836 bool one_entry_only;
1837 struct dm_phy_dbg_info dbginfo;
1838
1839 /* Dynamic ATC switch */
1840 bool atc_status;
1841 bool large_cfo_hit;
1842 bool is_freeze;
1843 int cfo_tail[2];
1844 int cfo_ave_pre;
1845 int crystal_cap;
1846 u8 cfo_threshold;
1847 u32 packet_count;
1848 u32 packet_count_pre;
1849 u8 tx_rate;
1850
1851 /*88e tx power tracking*/
1852 u8 swing_idx_ofdm[MAX_RF_PATH];
1853 u8 swing_idx_ofdm_cur;
1854 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1855 bool swing_flag_ofdm;
1856 u8 swing_idx_cck;
1857 u8 swing_idx_cck_cur;
1858 u8 swing_idx_cck_base;
1859 bool swing_flag_cck;
1860
1861 s8 swing_diff_2g;
1862 s8 swing_diff_5g;
1863
1864 /* DMSP */
1865 bool supp_phymode_switch;
1866
1867 /* DulMac */
1868 struct fast_ant_training fat_table;
1869
1870 u8 resp_tx_path;
1871 u8 path_sel;
1872 u32 patha_sum;
1873 u32 pathb_sum;
1874 u32 patha_cnt;
1875 u32 pathb_cnt;
1876
1877 u8 pre_channel;
1878 u8 *p_channel;
1879 u8 linked_interval;
1880
1881 u64 last_tx_ok_cnt;
1882 u64 last_rx_ok_cnt;
1883 };
1884
1885 #define EFUSE_MAX_LOGICAL_SIZE 512
1886
1887 struct rtl_efuse {
1888 const struct rtl_efuse_ops *efuse_ops;
1889 bool autoload_ok;
1890 bool bootfromefuse;
1891 u16 max_physical_size;
1892
1893 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1894 u16 efuse_usedbytes;
1895 u8 efuse_usedpercentage;
1896
1897 u8 autoload_failflag;
1898 u8 autoload_status;
1899
1900 short epromtype;
1901 u16 eeprom_vid;
1902 u16 eeprom_did;
1903 u16 eeprom_svid;
1904 u16 eeprom_smid;
1905 u8 eeprom_oemid;
1906 u16 eeprom_channelplan;
1907 u8 eeprom_version;
1908 u8 board_type;
1909 u8 external_pa;
1910
1911 u8 dev_addr[6];
1912 u8 wowlan_enable;
1913 u8 antenna_div_cfg;
1914 u8 antenna_div_type;
1915
1916 bool txpwr_fromeprom;
1917 u8 eeprom_crystalcap;
1918 u8 eeprom_tssi[2];
1919 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1920 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1921 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1922 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1923 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1924 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1925
1926 u8 internal_pa_5g[2]; /* pathA / pathB */
1927 u8 eeprom_c9;
1928 u8 eeprom_cc;
1929
1930 /*For power group */
1931 u8 eeprom_pwrgroup[2][3];
1932 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1933 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1934
1935 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1936 /*For HT 40MHZ pwr */
1937 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1938 /*For HT 40MHZ pwr */
1939 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1940
1941 /*--------------------------------------------------------*
1942 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1943 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1944 * define new arrays in Windows code.
1945 * BUT, in linux code, we use the same array for all ICs.
1946 *
1947 * The Correspondance relation between two arrays is:
1948 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1949 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1950 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1951 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1952 *
1953 * Sizes of these arrays are decided by the larger ones.
1954 */
1955 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1956 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1957 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1958 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1959
1960 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1961 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1962 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1963 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1964 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1965 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1966
1967 u8 txpwr_safetyflag; /* Band edge enable flag */
1968 u16 eeprom_txpowerdiff;
1969 u8 antenna_txpwdiff[3];
1970
1971 u8 eeprom_regulatory;
1972 u8 eeprom_thermalmeter;
1973 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1974 u16 tssi_13dbm;
1975 u8 crystalcap; /* CrystalCap. */
1976 u8 delta_iqk;
1977 u8 delta_lck;
1978
1979 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1980 bool apk_thermalmeterignore;
1981
1982 bool b1x1_recvcombine;
1983 bool b1ss_support;
1984
1985 /*channel plan */
1986 u8 channel_plan;
1987 };
1988
1989 struct rtl_efuse_ops {
1990 int (*efuse_onebyte_read)(struct ieee80211_hw *hw, u16 addr, u8 *data);
1991 void (*efuse_logical_map_read)(struct ieee80211_hw *hw, u8 type,
1992 u16 offset, u32 *value);
1993 };
1994
1995 struct rtl_tx_report {
1996 atomic_t sn;
1997 u16 last_sent_sn;
1998 unsigned long last_sent_time;
1999 u16 last_recv_sn;
2000 struct sk_buff_head queue;
2001 };
2002
2003 struct rtl_ps_ctl {
2004 bool pwrdomain_protect;
2005 bool in_powersavemode;
2006 bool rfchange_inprogress;
2007 bool swrf_processing;
2008 bool hwradiooff;
2009 /* just for PCIE ASPM
2010 * If it supports ASPM, Offset[560h] = 0x40,
2011 * otherwise Offset[560h] = 0x00.
2012 */
2013 bool support_aspm;
2014 bool support_backdoor;
2015
2016 /*for LPS */
2017 enum rt_psmode dot11_psmode; /*Power save mode configured. */
2018 bool swctrl_lps;
2019 bool leisure_ps;
2020 bool fwctrl_lps;
2021 u8 fwctrl_psmode;
2022 /*For Fw control LPS mode */
2023 u8 reg_fwctrl_lps;
2024 /*Record Fw PS mode status. */
2025 bool fw_current_inpsmode;
2026 u8 reg_max_lps_awakeintvl;
2027 bool report_linked;
2028 bool low_power_enable;/*for 32k*/
2029
2030 /*for IPS */
2031 bool inactiveps;
2032
2033 u32 rfoff_reason;
2034
2035 /*RF OFF Level */
2036 u32 cur_ps_level;
2037 u32 reg_rfps_level;
2038
2039 /*just for PCIE ASPM */
2040 u8 const_amdpci_aspm;
2041 bool pwrdown_mode;
2042
2043 enum rf_pwrstate inactive_pwrstate;
2044 enum rf_pwrstate rfpwr_state; /*cur power state */
2045
2046 /* for SW LPS*/
2047 bool sw_ps_enabled;
2048 bool state;
2049 bool state_inap;
2050 bool multi_buffered;
2051 u16 nullfunc_seq;
2052 unsigned int dtim_counter;
2053 unsigned int sleep_ms;
2054 unsigned long last_sleep_jiffies;
2055 unsigned long last_awake_jiffies;
2056 unsigned long last_delaylps_stamp_jiffies;
2057 unsigned long last_dtim;
2058 unsigned long last_beacon;
2059 unsigned long last_action;
2060 unsigned long last_slept;
2061
2062 /*For P2P PS */
2063 struct rtl_p2p_ps_info p2p_ps_info;
2064 u8 pwr_mode;
2065 u8 smart_ps;
2066
2067 /* wake up on line */
2068 u8 wo_wlan_mode;
2069 u8 arp_offload_enable;
2070 u8 gtk_offload_enable;
2071 /* Used for WOL, indicates the reason for waking event.*/
2072 u32 wakeup_reason;
2073 };
2074
2075 struct rtl_stats {
2076 u8 psaddr[ETH_ALEN];
2077 u32 mac_time[2];
2078 s8 rssi;
2079 u8 signal;
2080 u8 noise;
2081 u8 rate; /* hw desc rate */
2082 u8 received_channel;
2083 u8 control;
2084 u8 mask;
2085 u8 freq;
2086 u16 len;
2087 u64 tsf;
2088 u32 beacon_time;
2089 u8 nic_type;
2090 u16 length;
2091 u8 signalquality; /*in 0-100 index. */
2092 /* Real power in dBm for this packet,
2093 * no beautification and aggregation.
2094 */
2095 s32 recvsignalpower;
2096 s8 rxpower; /*in dBm Translate from PWdB */
2097 u8 signalstrength; /*in 0-100 index. */
2098 u16 hwerror:1;
2099 u16 crc:1;
2100 u16 icv:1;
2101 u16 shortpreamble:1;
2102 u16 antenna:1;
2103 u16 decrypted:1;
2104 u16 wakeup:1;
2105 u32 timestamp_low;
2106 u32 timestamp_high;
2107 bool shift;
2108
2109 u8 rx_drvinfo_size;
2110 u8 rx_bufshift;
2111 bool isampdu;
2112 bool isfirst_ampdu;
2113 bool rx_is40mhzpacket;
2114 u8 rx_packet_bw;
2115 u32 rx_pwdb_all;
2116 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
2117 s8 rx_mimo_signalquality[4];
2118 u8 rx_mimo_evm_dbm[4];
2119 u16 cfo_short[4]; /* per-path's Cfo_short */
2120 u16 cfo_tail[4];
2121
2122 s8 rx_mimo_sig_qual[4];
2123 u8 rx_pwr[4]; /* per-path's pwdb */
2124 u8 rx_snr[4]; /* per-path's SNR */
2125 u8 bandwidth;
2126 u8 bt_coex_pwr_adjust;
2127 bool packet_matchbssid;
2128 bool is_cck;
2129 bool is_ht;
2130 bool packet_toself;
2131 bool packet_beacon; /*for rssi */
2132 s8 cck_adc_pwdb[4]; /*for rx path selection */
2133
2134 bool is_vht;
2135 bool is_short_gi;
2136 u8 vht_nss;
2137
2138 u8 packet_report_type;
2139
2140 u32 macid;
2141 u32 bt_rx_rssi_percentage;
2142 u32 macid_valid_entry[2];
2143 };
2144
2145 struct rt_link_detect {
2146 /* count for roaming */
2147 u32 bcn_rx_inperiod;
2148 u32 roam_times;
2149
2150 u32 num_tx_in4period[4];
2151 u32 num_rx_in4period[4];
2152
2153 u32 num_tx_inperiod;
2154 u32 num_rx_inperiod;
2155
2156 bool busytraffic;
2157 bool tx_busy_traffic;
2158 bool rx_busy_traffic;
2159 bool higher_busytraffic;
2160 bool higher_busyrxtraffic;
2161
2162 u32 tidtx_in4period[MAX_TID_COUNT][4];
2163 u32 tidtx_inperiod[MAX_TID_COUNT];
2164 bool higher_busytxtraffic[MAX_TID_COUNT];
2165 };
2166
2167 struct rtl_tcb_desc {
2168 u8 packet_bw:2;
2169 u8 multicast:1;
2170 u8 broadcast:1;
2171
2172 u8 rts_stbc:1;
2173 u8 rts_enable:1;
2174 u8 cts_enable:1;
2175 u8 rts_use_shortpreamble:1;
2176 u8 rts_use_shortgi:1;
2177 u8 rts_sc:1;
2178 u8 rts_bw:1;
2179 u8 rts_rate;
2180
2181 u8 use_shortgi:1;
2182 u8 use_shortpreamble:1;
2183 u8 use_driver_rate:1;
2184 u8 disable_ratefallback:1;
2185
2186 u8 use_spe_rpt:1;
2187
2188 u8 ratr_index;
2189 u8 mac_id;
2190 u8 hw_rate;
2191
2192 u8 last_inipkt:1;
2193 u8 cmd_or_init:1;
2194 u8 queue_index;
2195
2196 /* early mode */
2197 u8 empkt_num;
2198 /* The max value by HW */
2199 u32 empkt_len[10];
2200 bool tx_enable_sw_calc_duration;
2201 };
2202
2203 struct rtl_wow_pattern {
2204 u8 type;
2205 u16 crc;
2206 u32 mask[4];
2207 };
2208
2209 /* struct to store contents of interrupt vectors */
2210 struct rtl_int {
2211 u32 inta;
2212 u32 intb;
2213 u32 intc;
2214 u32 intd;
2215 };
2216
2217 struct rtl_hal_ops {
2218 int (*init_sw_vars)(struct ieee80211_hw *hw);
2219 void (*deinit_sw_vars)(struct ieee80211_hw *hw);
2220 void (*read_chip_version)(struct ieee80211_hw *hw);
2221 void (*read_eeprom_info)(struct ieee80211_hw *hw);
2222 void (*interrupt_recognized)(struct ieee80211_hw *hw,
2223 struct rtl_int *intvec);
2224 int (*hw_init)(struct ieee80211_hw *hw);
2225 void (*hw_disable)(struct ieee80211_hw *hw);
2226 void (*hw_suspend)(struct ieee80211_hw *hw);
2227 void (*hw_resume)(struct ieee80211_hw *hw);
2228 void (*enable_interrupt)(struct ieee80211_hw *hw);
2229 void (*disable_interrupt)(struct ieee80211_hw *hw);
2230 int (*set_network_type)(struct ieee80211_hw *hw,
2231 enum nl80211_iftype type);
2232 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2233 bool check_bssid);
2234 void (*set_bw_mode)(struct ieee80211_hw *hw,
2235 enum nl80211_channel_type ch_type);
2236 u8 (*switch_channel)(struct ieee80211_hw *hw);
2237 void (*set_qos)(struct ieee80211_hw *hw, int aci);
2238 void (*set_bcn_reg)(struct ieee80211_hw *hw);
2239 void (*set_bcn_intv)(struct ieee80211_hw *hw);
2240 void (*update_interrupt_mask)(struct ieee80211_hw *hw,
2241 u32 add_msr, u32 rm_msr);
2242 void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2243 void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2244 void (*update_rate_tbl)(struct ieee80211_hw *hw,
2245 struct ieee80211_sta *sta, u8 rssi_leve,
2246 bool update_bw);
2247 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2248 u8 *desc, u8 queue_index,
2249 struct sk_buff *skb, dma_addr_t addr);
2250 void (*update_rate_mask)(struct ieee80211_hw *hw, u8 rssi_level);
2251 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2252 u8 queue_index);
2253 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2254 u8 queue_index);
2255 void (*fill_tx_desc)(struct ieee80211_hw *hw,
2256 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2257 u8 *pbd_desc_tx,
2258 struct ieee80211_tx_info *info,
2259 struct ieee80211_sta *sta,
2260 struct sk_buff *skb, u8 hw_queue,
2261 struct rtl_tcb_desc *ptcb_desc);
2262 void (*fill_fake_txdesc)(struct ieee80211_hw *hw, u8 *pdesc,
2263 u32 buffer_len, bool bsspspoll);
2264 void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc,
2265 bool firstseg, bool lastseg,
2266 struct sk_buff *skb);
2267 void (*fill_tx_special_desc)(struct ieee80211_hw *hw,
2268 u8 *pdesc, u8 *pbd_desc,
2269 struct sk_buff *skb, u8 hw_queue);
2270 bool (*query_rx_desc)(struct ieee80211_hw *hw,
2271 struct rtl_stats *stats,
2272 struct ieee80211_rx_status *rx_status,
2273 u8 *pdesc, struct sk_buff *skb);
2274 void (*set_channel_access)(struct ieee80211_hw *hw);
2275 bool (*radio_onoff_checking)(struct ieee80211_hw *hw, u8 *valid);
2276 void (*dm_watchdog)(struct ieee80211_hw *hw);
2277 void (*scan_operation_backup)(struct ieee80211_hw *hw, u8 operation);
2278 bool (*set_rf_power_state)(struct ieee80211_hw *hw,
2279 enum rf_pwrstate rfpwr_state);
2280 void (*led_control)(struct ieee80211_hw *hw,
2281 enum led_ctl_mode ledaction);
2282 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2283 u8 desc_name, u8 *val);
2284 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2285 u8 desc_name);
2286 bool (*is_tx_desc_closed)(struct ieee80211_hw *hw,
2287 u8 hw_queue, u16 index);
2288 void (*tx_polling)(struct ieee80211_hw *hw, u8 hw_queue);
2289 void (*enable_hw_sec)(struct ieee80211_hw *hw);
2290 void (*set_key)(struct ieee80211_hw *hw, u32 key_index,
2291 u8 *macaddr, bool is_group, u8 enc_algo,
2292 bool is_wepkey, bool clear_all);
2293 void (*init_sw_leds)(struct ieee80211_hw *hw);
2294 void (*deinit_sw_leds)(struct ieee80211_hw *hw);
2295 u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2296 void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2297 u32 data);
2298 u32 (*get_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2299 u32 regaddr, u32 bitmask);
2300 void (*set_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2301 u32 regaddr, u32 bitmask, u32 data);
2302 void (*linked_set_reg)(struct ieee80211_hw *hw);
2303 void (*chk_switch_dmdp)(struct ieee80211_hw *hw);
2304 void (*dualmac_easy_concurrent)(struct ieee80211_hw *hw);
2305 void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw);
2306 bool (*phy_rf6052_config)(struct ieee80211_hw *hw);
2307 void (*phy_rf6052_set_cck_txpower)(struct ieee80211_hw *hw,
2308 u8 *powerlevel);
2309 void (*phy_rf6052_set_ofdm_txpower)(struct ieee80211_hw *hw,
2310 u8 *ppowerlevel, u8 channel);
2311 bool (*config_bb_with_headerfile)(struct ieee80211_hw *hw,
2312 u8 configtype);
2313 bool (*config_bb_with_pgheaderfile)(struct ieee80211_hw *hw,
2314 u8 configtype);
2315 void (*phy_lc_calibrate)(struct ieee80211_hw *hw, bool is2t);
2316 void (*phy_set_bw_mode_callback)(struct ieee80211_hw *hw);
2317 void (*dm_dynamic_txpower)(struct ieee80211_hw *hw);
2318 void (*c2h_command_handle)(struct ieee80211_hw *hw);
2319 void (*bt_wifi_media_status_notify)(struct ieee80211_hw *hw,
2320 bool mstate);
2321 void (*bt_coex_off_before_lps)(struct ieee80211_hw *hw);
2322 void (*fill_h2c_cmd)(struct ieee80211_hw *hw, u8 element_id,
2323 u32 cmd_len, u8 *p_cmdbuffer);
2324 void (*set_default_port_id_cmd)(struct ieee80211_hw *hw);
2325 bool (*get_btc_status)(void);
2326 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2327 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2328 struct rtl_wow_pattern *rtl_pattern,
2329 u8 index);
2330 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2331 void (*c2h_ra_report_handler)(struct ieee80211_hw *hw,
2332 u8 *cmd_buf, u8 cmd_len);
2333 };
2334
2335 struct rtl_intf_ops {
2336 /*com */
2337 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2338 int (*adapter_start)(struct ieee80211_hw *hw);
2339 void (*adapter_stop)(struct ieee80211_hw *hw);
2340 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2341 struct rtl_priv **buddy_priv);
2342
2343 int (*adapter_tx)(struct ieee80211_hw *hw,
2344 struct ieee80211_sta *sta,
2345 struct sk_buff *skb,
2346 struct rtl_tcb_desc *ptcb_desc);
2347 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2348 int (*reset_trx_ring)(struct ieee80211_hw *hw);
2349 bool (*waitq_insert)(struct ieee80211_hw *hw,
2350 struct ieee80211_sta *sta,
2351 struct sk_buff *skb);
2352
2353 /*pci */
2354 void (*disable_aspm)(struct ieee80211_hw *hw);
2355 void (*enable_aspm)(struct ieee80211_hw *hw);
2356
2357 /*usb */
2358 };
2359
2360 struct rtl_mod_params {
2361 /* default: 0,0 */
2362 u64 debug_mask;
2363 /* default: 0 = using hardware encryption */
2364 bool sw_crypto;
2365
2366 /* default: 0 = DBG_EMERG (0)*/
2367 int debug_level;
2368
2369 /* default: 1 = using no linked power save */
2370 bool inactiveps;
2371
2372 /* default: 1 = using linked sw power save */
2373 bool swctrl_lps;
2374
2375 /* default: 1 = using linked fw power save */
2376 bool fwctrl_lps;
2377
2378 /* default: 0 = not using MSI interrupts mode
2379 * submodules should set their own default value
2380 */
2381 bool msi_support;
2382
2383 /* default: 0 = dma 32 */
2384 bool dma64;
2385
2386 /* default: 1 = enable aspm */
2387 int aspm_support;
2388
2389 /* default 0: 1 means disable */
2390 bool disable_watchdog;
2391
2392 /* default 0: 1 means do not disable interrupts */
2393 bool int_clear;
2394
2395 /* select antenna */
2396 int ant_sel;
2397 };
2398
2399 struct rtl_hal_usbint_cfg {
2400 /* data - rx */
2401 u32 in_ep_num;
2402 u32 rx_urb_num;
2403 u32 rx_max_size;
2404
2405 /* op - rx */
2406 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2407 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2408 struct sk_buff_head *);
2409
2410 /* tx */
2411 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2412 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2413 struct sk_buff *);
2414 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2415 struct sk_buff_head *);
2416
2417 /* endpoint mapping */
2418 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2419 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2420 };
2421
2422 struct rtl_hal_cfg {
2423 u8 bar_id;
2424 bool write_readback;
2425 char *name;
2426 char *alt_fw_name;
2427 struct rtl_hal_ops *ops;
2428 struct rtl_mod_params *mod_params;
2429 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2430 enum rtl_spec_ver spec_ver;
2431
2432 /*this map used for some registers or vars
2433 * defined int HAL but used in MAIN
2434 */
2435 u32 maps[RTL_VAR_MAP_MAX];
2436
2437 };
2438
2439 struct rtl_locks {
2440 /* mutex */
2441 struct mutex conf_mutex;
2442 struct mutex ips_mutex; /* mutex for enter/leave IPS */
2443 struct mutex lps_mutex; /* mutex for enter/leave LPS */
2444
2445 /*spin lock */
2446 spinlock_t irq_th_lock;
2447 spinlock_t h2c_lock;
2448 spinlock_t rf_ps_lock;
2449 spinlock_t rf_lock;
2450 spinlock_t waitq_lock;
2451 spinlock_t entry_list_lock;
2452 spinlock_t usb_lock;
2453 spinlock_t c2hcmd_lock;
2454 spinlock_t scan_list_lock; /* lock for the scan list */
2455
2456 /*FW clock change */
2457 spinlock_t fw_ps_lock;
2458
2459 /*Dual mac*/
2460 spinlock_t cck_and_rw_pagea_lock;
2461
2462 spinlock_t iqk_lock;
2463 };
2464
2465 struct rtl_works {
2466 struct ieee80211_hw *hw;
2467
2468 /*timer */
2469 struct timer_list watchdog_timer;
2470 struct timer_list dualmac_easyconcurrent_retrytimer;
2471 struct timer_list fw_clockoff_timer;
2472 struct timer_list fast_antenna_training_timer;
2473 /*task */
2474 struct tasklet_struct irq_tasklet;
2475 struct tasklet_struct irq_prepare_bcn_tasklet;
2476
2477 /*work queue */
2478 struct workqueue_struct *rtl_wq;
2479 struct delayed_work watchdog_wq;
2480 struct delayed_work ips_nic_off_wq;
2481 struct delayed_work c2hcmd_wq;
2482
2483 /* For SW LPS */
2484 struct delayed_work ps_work;
2485 struct delayed_work ps_rfon_wq;
2486 struct delayed_work fwevt_wq;
2487
2488 struct work_struct lps_change_work;
2489 struct work_struct fill_h2c_cmd;
2490 };
2491
2492 struct rtl_debug {
2493 /* add for debug */
2494 struct dentry *debugfs_dir;
2495 char debugfs_name[20];
2496 };
2497
2498 #define MIMO_PS_STATIC 0
2499 #define MIMO_PS_DYNAMIC 1
2500 #define MIMO_PS_NOLIMIT 3
2501
2502 struct rtl_dualmac_easy_concurrent_ctl {
2503 enum band_type currentbandtype_backfordmdp;
2504 bool close_bbandrf_for_dmsp;
2505 bool change_to_dmdp;
2506 bool change_to_dmsp;
2507 bool switch_in_process;
2508 };
2509
2510 struct rtl_dmsp_ctl {
2511 bool activescan_for_slaveofdmsp;
2512 bool scan_for_anothermac_fordmsp;
2513 bool scan_for_itself_fordmsp;
2514 bool writedig_for_anothermacofdmsp;
2515 u32 curdigvalue_for_anothermacofdmsp;
2516 bool changecckpdstate_for_anothermacofdmsp;
2517 u8 curcckpdstate_for_anothermacofdmsp;
2518 bool changetxhighpowerlvl_for_anothermacofdmsp;
2519 u8 curtxhighlvl_for_anothermacofdmsp;
2520 long rssivalmin_for_anothermacofdmsp;
2521 };
2522
2523 struct ps_t {
2524 u8 pre_ccastate;
2525 u8 cur_ccasate;
2526 u8 pre_rfstate;
2527 u8 cur_rfstate;
2528 u8 initialize;
2529 long rssi_val_min;
2530 };
2531
2532 struct dig_t {
2533 u32 rssi_lowthresh;
2534 u32 rssi_highthresh;
2535 u32 fa_lowthresh;
2536 u32 fa_highthresh;
2537 long last_min_undec_pwdb_for_dm;
2538 long rssi_highpower_lowthresh;
2539 long rssi_highpower_highthresh;
2540 u32 recover_cnt;
2541 u32 pre_igvalue;
2542 u32 cur_igvalue;
2543 long rssi_val;
2544 u8 dig_enable_flag;
2545 u8 dig_ext_port_stage;
2546 u8 dig_algorithm;
2547 u8 dig_twoport_algorithm;
2548 u8 dig_dbgmode;
2549 u8 dig_slgorithm_switch;
2550 u8 cursta_cstate;
2551 u8 presta_cstate;
2552 u8 curmultista_cstate;
2553 u8 stop_dig;
2554 s8 back_val;
2555 s8 back_range_max;
2556 s8 back_range_min;
2557 u8 rx_gain_max;
2558 u8 rx_gain_min;
2559 u8 min_undec_pwdb_for_dm;
2560 u8 rssi_val_min;
2561 u8 pre_cck_cca_thres;
2562 u8 cur_cck_cca_thres;
2563 u8 pre_cck_pd_state;
2564 u8 cur_cck_pd_state;
2565 u8 pre_cck_fa_state;
2566 u8 cur_cck_fa_state;
2567 u8 pre_ccastate;
2568 u8 cur_ccasate;
2569 u8 large_fa_hit;
2570 u8 forbidden_igi;
2571 u8 dig_state;
2572 u8 dig_highpwrstate;
2573 u8 cur_sta_cstate;
2574 u8 pre_sta_cstate;
2575 u8 cur_ap_cstate;
2576 u8 pre_ap_cstate;
2577 u8 cur_pd_thstate;
2578 u8 pre_pd_thstate;
2579 u8 cur_cs_ratiostate;
2580 u8 pre_cs_ratiostate;
2581 u8 backoff_enable_flag;
2582 s8 backoffval_range_max;
2583 s8 backoffval_range_min;
2584 u8 dig_min_0;
2585 u8 dig_min_1;
2586 u8 bt30_cur_igi;
2587 bool media_connect_0;
2588 bool media_connect_1;
2589
2590 u32 antdiv_rssi_max;
2591 u32 rssi_max;
2592 };
2593
2594 struct rtl_global_var {
2595 /* from this list we can get
2596 * other adapter's rtl_priv
2597 */
2598 struct list_head glb_priv_list;
2599 spinlock_t glb_list_lock;
2600 };
2601
2602 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */
2603
2604 struct rtl_btc_info {
2605 u8 bt_type;
2606 u8 btcoexist;
2607 u8 ant_num;
2608 u8 single_ant_path;
2609
2610 u8 ap_num;
2611 bool in_4way;
2612 unsigned long in_4way_ts;
2613 };
2614
2615 struct bt_coexist_info {
2616 struct rtl_btc_ops *btc_ops;
2617 struct rtl_btc_info btc_info;
2618 /* btc context */
2619 void *btc_context;
2620 void *wifi_only_context;
2621 /* EEPROM BT info. */
2622 u8 eeprom_bt_coexist;
2623 u8 eeprom_bt_type;
2624 u8 eeprom_bt_ant_num;
2625 u8 eeprom_bt_ant_isol;
2626 u8 eeprom_bt_radio_shared;
2627
2628 u8 bt_coexistence;
2629 u8 bt_ant_num;
2630 u8 bt_coexist_type;
2631 u8 bt_state;
2632 u8 bt_cur_state; /* 0:on, 1:off */
2633 u8 bt_ant_isolation; /* 0:good, 1:bad */
2634 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2635 u8 bt_service;
2636 u8 bt_radio_shared_type;
2637 u8 bt_rfreg_origin_1e;
2638 u8 bt_rfreg_origin_1f;
2639 u8 bt_rssi_state;
2640 u32 ratio_tx;
2641 u32 ratio_pri;
2642 u32 bt_edca_ul;
2643 u32 bt_edca_dl;
2644
2645 bool init_set;
2646 bool bt_busy_traffic;
2647 bool bt_traffic_mode_set;
2648 bool bt_non_traffic_mode_set;
2649
2650 bool fw_coexist_all_off;
2651 bool sw_coexist_all_off;
2652 bool hw_coexist_all_off;
2653 u32 cstate;
2654 u32 previous_state;
2655 u32 cstate_h;
2656 u32 previous_state_h;
2657
2658 u8 bt_pre_rssi_state;
2659 u8 bt_pre_rssi_state1;
2660
2661 u8 reg_bt_iso;
2662 u8 reg_bt_sco;
2663 bool balance_on;
2664 u8 bt_active_zero_cnt;
2665 bool cur_bt_disabled;
2666 bool pre_bt_disabled;
2667
2668 u8 bt_profile_case;
2669 u8 bt_profile_action;
2670 bool bt_busy;
2671 bool hold_for_bt_operation;
2672 u8 lps_counter;
2673 };
2674
2675 struct rtl_btc_ops {
2676 void (*btc_init_variables)(struct rtl_priv *rtlpriv);
2677 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv);
2678 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv);
2679 void (*btc_init_hal_vars)(struct rtl_priv *rtlpriv);
2680 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv);
2681 void (*btc_init_hw_config)(struct rtl_priv *rtlpriv);
2682 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv);
2683 void (*btc_ips_notify)(struct rtl_priv *rtlpriv, u8 type);
2684 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2685 void (*btc_scan_notify)(struct rtl_priv *rtlpriv, u8 scantype);
2686 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv,
2687 u8 scantype);
2688 void (*btc_connect_notify)(struct rtl_priv *rtlpriv, u8 action);
2689 void (*btc_mediastatus_notify)(struct rtl_priv *rtlpriv,
2690 enum rt_media_status mstatus);
2691 void (*btc_periodical)(struct rtl_priv *rtlpriv);
2692 void (*btc_halt_notify)(struct rtl_priv *rtlpriv);
2693 void (*btc_btinfo_notify)(struct rtl_priv *rtlpriv,
2694 u8 *tmp_buf, u8 length);
2695 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv,
2696 u8 *tmp_buf, u8 length);
2697 bool (*btc_is_limited_dig)(struct rtl_priv *rtlpriv);
2698 bool (*btc_is_disable_edca_turbo)(struct rtl_priv *rtlpriv);
2699 bool (*btc_is_bt_disabled)(struct rtl_priv *rtlpriv);
2700 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2701 u8 pkt_type);
2702 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type,
2703 bool scanning);
2704 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv,
2705 u8 type, bool scanning);
2706 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv,
2707 struct seq_file *m);
2708 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
2709 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv);
2710 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv);
2711 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv);
2712 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg,
2713 u8 *ctrl_agg_size, u8 *agg_size);
2714 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
2715 };
2716
2717 struct proxim {
2718 bool proxim_on;
2719
2720 void *proximity_priv;
2721 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2722 struct sk_buff *skb);
2723 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2724 };
2725
2726 struct rtl_c2hcmd {
2727 struct list_head list;
2728 u8 tag;
2729 u8 len;
2730 u8 *val;
2731 };
2732
2733 struct rtl_bssid_entry {
2734 struct list_head list;
2735 u8 bssid[ETH_ALEN];
2736 u32 age;
2737 };
2738
2739 struct rtl_scan_list {
2740 int num;
2741 struct list_head list; /* sort by age */
2742 };
2743
2744 struct rtl_priv {
2745 struct ieee80211_hw *hw;
2746 struct completion firmware_loading_complete;
2747 struct list_head list;
2748 struct rtl_priv *buddy_priv;
2749 struct rtl_global_var *glb_var;
2750 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2751 struct rtl_dmsp_ctl dmsp_ctl;
2752 struct rtl_locks locks;
2753 struct rtl_works works;
2754 struct rtl_mac mac80211;
2755 struct rtl_hal rtlhal;
2756 struct rtl_regulatory regd;
2757 struct rtl_rfkill rfkill;
2758 struct rtl_io io;
2759 struct rtl_phy phy;
2760 struct rtl_dm dm;
2761 struct rtl_security sec;
2762 struct rtl_efuse efuse;
2763 struct rtl_led_ctl ledctl;
2764 struct rtl_tx_report tx_report;
2765 struct rtl_scan_list scan_list;
2766
2767 struct rtl_ps_ctl psc;
2768 struct rate_adaptive ra;
2769 struct dynamic_primary_cca primarycca;
2770 struct wireless_stats stats;
2771 struct rt_link_detect link_info;
2772 struct false_alarm_statistics falsealm_cnt;
2773
2774 struct rtl_rate_priv *rate_priv;
2775
2776 /* sta entry list for ap adhoc or mesh */
2777 struct list_head entry_list;
2778
2779 /* c2hcmd list for kthread level access */
2780 struct sk_buff_head c2hcmd_queue;
2781
2782 struct rtl_debug dbg;
2783 int max_fw_size;
2784
2785 /* hal_cfg : for diff cards
2786 * intf_ops : for diff interrface usb/pcie
2787 */
2788 struct rtl_hal_cfg *cfg;
2789 const struct rtl_intf_ops *intf_ops;
2790
2791 /* this var will be set by set_bit,
2792 * and was used to indicate status of
2793 * interface or hardware
2794 */
2795 unsigned long status;
2796
2797 /* tables for dm */
2798 struct dig_t dm_digtable;
2799 struct ps_t dm_pstable;
2800
2801 u32 reg_874;
2802 u32 reg_c70;
2803 u32 reg_85c;
2804 u32 reg_a74;
2805 bool reg_init; /* true if regs saved */
2806 bool bt_operation_on;
2807 __le32 *usb_data;
2808 int usb_data_index;
2809 bool initialized;
2810 bool enter_ps; /* true when entering PS */
2811 u8 rate_mask[5];
2812
2813 /* intel Proximity, should be alloc mem
2814 * in intel Proximity module and can only
2815 * be used in intel Proximity mode
2816 */
2817 struct proxim proximity;
2818
2819 /*for bt coexist use*/
2820 struct bt_coexist_info btcoexist;
2821
2822 /* separate 92ee from other ICs,
2823 * 92ee use new trx flow.
2824 */
2825 bool use_new_trx_flow;
2826
2827 #ifdef CONFIG_PM
2828 struct wiphy_wowlan_support wowlan;
2829 #endif
2830 /* This must be the last item so
2831 * that it points to the data allocated
2832 * beyond this structure like:
2833 * rtl_pci_priv or rtl_usb_priv
2834 */
2835 u8 priv[0] __aligned(sizeof(void *));
2836 };
2837
2838 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2839 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2840 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2841 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2842 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2843
2844 /* Bluetooth Co-existence Related */
2845
2846 enum bt_ant_num {
2847 ANT_X2 = 0,
2848 ANT_X1 = 1,
2849 };
2850
2851 enum bt_ant_path {
2852 ANT_MAIN = 0,
2853 ANT_AUX = 1,
2854 };
2855
2856 enum bt_co_type {
2857 BT_2WIRE = 0,
2858 BT_ISSC_3WIRE = 1,
2859 BT_ACCEL = 2,
2860 BT_CSR_BC4 = 3,
2861 BT_CSR_BC8 = 4,
2862 BT_RTL8756 = 5,
2863 BT_RTL8723A = 6,
2864 BT_RTL8821A = 7,
2865 BT_RTL8723B = 8,
2866 BT_RTL8192E = 9,
2867 BT_RTL8812A = 11,
2868 };
2869
2870 enum bt_cur_state {
2871 BT_OFF = 0,
2872 BT_ON = 1,
2873 };
2874
2875 enum bt_service_type {
2876 BT_SCO = 0,
2877 BT_A2DP = 1,
2878 BT_HID = 2,
2879 BT_HID_IDLE = 3,
2880 BT_SCAN = 4,
2881 BT_IDLE = 5,
2882 BT_OTHER_ACTION = 6,
2883 BT_BUSY = 7,
2884 BT_OTHERBUSY = 8,
2885 BT_PAN = 9,
2886 };
2887
2888 enum bt_radio_shared {
2889 BT_RADIO_SHARED = 0,
2890 BT_RADIO_INDIVIDUAL = 1,
2891 };
2892
2893 /****************************************
2894 * mem access macro define start
2895 * Call endian free function when
2896 * 1. Read/write packet content.
2897 * 2. Before write integer to IO.
2898 * 3. After read integer from IO.
2899 ****************************************/
2900
2901 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2902 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2903
2904 /* mem access macro define end */
2905
2906 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2907
2908 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2909 #define RTL_WATCH_DOG_TIME 2000
2910 #define MSECS(t) msecs_to_jiffies(t)
2911 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2912 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2913 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2914 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2915 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2916
2917 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2918 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2919 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2920 /*NIC halt, re-initialize hw parameters*/
2921 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2922 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2923 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2924 /*Always enable ASPM and Clock Req in initialization.*/
2925 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2926 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2927 #define RT_PS_LEVEL_ASPM BIT(7)
2928 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2929 #define RT_RF_LPS_DISALBE_2R BIT(30)
2930 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2931 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2932 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2933 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2934 (ppsc->cur_ps_level &= (~(_ps_flg)))
2935 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2936 (ppsc->cur_ps_level |= _ps_flg)
2937
2938 #define FILL_OCTET_STRING(_os, _octet, _len) \
2939 (_os).octet = (u8 *)(_octet); \
2940 (_os).length = (_len);
2941
2942 #define CP_MACADDR(des, src) \
2943 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2944 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2945 (des)[4] = (src)[4], (des)[5] = (src)[5])
2946
2947 #define LDPC_HT_ENABLE_RX BIT(0)
2948 #define LDPC_HT_ENABLE_TX BIT(1)
2949 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
2950 #define LDPC_HT_CAP_TX BIT(3)
2951
2952 #define STBC_HT_ENABLE_RX BIT(0)
2953 #define STBC_HT_ENABLE_TX BIT(1)
2954 #define STBC_HT_TEST_TX_ENABLE BIT(2)
2955 #define STBC_HT_CAP_TX BIT(3)
2956
2957 #define LDPC_VHT_ENABLE_RX BIT(0)
2958 #define LDPC_VHT_ENABLE_TX BIT(1)
2959 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
2960 #define LDPC_VHT_CAP_TX BIT(3)
2961
2962 #define STBC_VHT_ENABLE_RX BIT(0)
2963 #define STBC_VHT_ENABLE_TX BIT(1)
2964 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
2965 #define STBC_VHT_CAP_TX BIT(3)
2966
2967 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
2968
2969 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
2970
2971 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2972 {
2973 return rtlpriv->io.read8_sync(rtlpriv, addr);
2974 }
2975
2976 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2977 {
2978 return rtlpriv->io.read16_sync(rtlpriv, addr);
2979 }
2980
2981 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2982 {
2983 return rtlpriv->io.read32_sync(rtlpriv, addr);
2984 }
2985
2986 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2987 {
2988 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2989
2990 if (rtlpriv->cfg->write_readback)
2991 rtlpriv->io.read8_sync(rtlpriv, addr);
2992 }
2993
2994 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw,
2995 u32 addr, u32 val8)
2996 {
2997 struct rtl_priv *rtlpriv = rtl_priv(hw);
2998
2999 rtl_write_byte(rtlpriv, addr, (u8)val8);
3000 }
3001
3002 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
3003 {
3004 rtlpriv->io.write16_async(rtlpriv, addr, val16);
3005
3006 if (rtlpriv->cfg->write_readback)
3007 rtlpriv->io.read16_sync(rtlpriv, addr);
3008 }
3009
3010 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
3011 u32 addr, u32 val32)
3012 {
3013 rtlpriv->io.write32_async(rtlpriv, addr, val32);
3014
3015 if (rtlpriv->cfg->write_readback)
3016 rtlpriv->io.read32_sync(rtlpriv, addr);
3017 }
3018
3019 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
3020 u32 regaddr, u32 bitmask)
3021 {
3022 struct rtl_priv *rtlpriv = hw->priv;
3023
3024 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
3025 }
3026
3027 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
3028 u32 bitmask, u32 data)
3029 {
3030 struct rtl_priv *rtlpriv = hw->priv;
3031
3032 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
3033 }
3034
3035 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw,
3036 u32 regaddr, u32 data)
3037 {
3038 rtl_set_bbreg(hw, regaddr, 0xffffffff, data);
3039 }
3040
3041 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
3042 enum radio_path rfpath, u32 regaddr,
3043 u32 bitmask)
3044 {
3045 struct rtl_priv *rtlpriv = hw->priv;
3046
3047 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
3048 }
3049
3050 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
3051 enum radio_path rfpath, u32 regaddr,
3052 u32 bitmask, u32 data)
3053 {
3054 struct rtl_priv *rtlpriv = hw->priv;
3055
3056 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
3057 }
3058
3059 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
3060 {
3061 return (_HAL_STATE_STOP == rtlhal->state);
3062 }
3063
3064 static inline void set_hal_start(struct rtl_hal *rtlhal)
3065 {
3066 rtlhal->state = _HAL_STATE_START;
3067 }
3068
3069 static inline void set_hal_stop(struct rtl_hal *rtlhal)
3070 {
3071 rtlhal->state = _HAL_STATE_STOP;
3072 }
3073
3074 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
3075 {
3076 return rtlphy->rf_type;
3077 }
3078
3079 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3080 {
3081 return (struct ieee80211_hdr *)(skb->data);
3082 }
3083
3084 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3085 {
3086 return rtl_get_hdr(skb)->frame_control;
3087 }
3088
3089 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
3090 {
3091 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3092 }
3093
3094 static inline u16 rtl_get_tid(struct sk_buff *skb)
3095 {
3096 return rtl_get_tid_h(rtl_get_hdr(skb));
3097 }
3098
3099 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3100 struct ieee80211_vif *vif,
3101 const u8 *bssid)
3102 {
3103 return ieee80211_find_sta(vif, bssid);
3104 }
3105
3106 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3107 u8 *mac_addr)
3108 {
3109 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3110
3111 return ieee80211_find_sta(mac->vif, mac_addr);
3112 }
3113
3114 #endif
Linux with added FPC-III support