drivers/net/wireless/realtek/rtw88/phy.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /* Copyright(c) 2018-2019  Realtek Corporation
   3  */
   4
   5 #ifndef __RTW_PHY_H_
   6 #define __RTW_PHY_H_
   7
   8 #include "debug.h"
   9
  10 extern u8 rtw_cck_rates[];
  11 extern u8 rtw_ofdm_rates[];
  12 extern u8 rtw_ht_1s_rates[];
  13 extern u8 rtw_ht_2s_rates[];
  14 extern u8 rtw_vht_1s_rates[];
  15 extern u8 rtw_vht_2s_rates[];
  16 extern u8 *rtw_rate_section[];
  17 extern u8 rtw_rate_size[];
  18
  19 void rtw_phy_init(struct rtw_dev *rtwdev);
  20 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev);
  21 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num);
  22 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
  23                     u32 addr, u32 mask);
  24 u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
  25                          u32 addr, u32 mask);
  26 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
  27                                u32 addr, u32 mask, u32 data);
  28 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
  29                           u32 addr, u32 mask, u32 data);
  30 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
  31                               u32 addr, u32 mask, u32 data);
  32 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg);
  33 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
  34 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
  35 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
  36 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
  37                      u32 addr, u32 data);
  38 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
  39                      u32 addr, u32 data);
  40 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
  41                     u32 addr, u32 data);
  42 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
  43                     u32 addr, u32 data);
  44 void rtw_phy_init_tx_power(struct rtw_dev *rtwdev);
  45 void rtw_phy_load_tables(struct rtw_dev *rtwdev);
  46 u8 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate,
  47                               enum rtw_bandwidth bw, u8 channel, u8 regd);
  48 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel);
  49 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal);
  50 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal);
  51 void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path);
  52 bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal,
  53                                       u8 path);
  54 u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path);
  55 s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev,
  56                                struct rtw_swing_table *swing_table,
  57                                u8 tbl_path, u8 therm_path, u8 delta);
  58 bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev);
  59 void rtw_phy_config_swing_table(struct rtw_dev *rtwdev,
  60                                 struct rtw_swing_table *swing_table);
  61
  62 struct rtw_txpwr_lmt_cfg_pair {
  63         u8 regd;
  64         u8 band;
  65         u8 bw;
  66         u8 rs;
  67         u8 ch;
  68         s8 txpwr_lmt;
  69 };
  70
  71 struct rtw_phy_pg_cfg_pair {
  72         u32 band;
  73         u32 rf_path;
  74         u32 tx_num;
  75         u32 addr;
  76         u32 bitmask;
  77         u32 data;
  78 };
  79
  80 #define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path)   \
  81 const struct rtw_table name ## _tbl = {                 \
  82         .data = name,                                   \
  83         .size = ARRAY_SIZE(name),                       \
  84         .parse = rtw_parse_tbl_phy_cond,                \
  85         .do_cfg = cfg,                                  \
  86         .rf_path = path,                                \
  87 }
  88
  89 #define RTW_DECL_TABLE_PHY_COND(name, cfg)              \
  90         RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)
  91
  92 #define RTW_DECL_TABLE_RF_RADIO(name, path)             \
  93         RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path)
  94
  95 #define RTW_DECL_TABLE_BB_PG(name)                      \
  96 const struct rtw_table name ## _tbl = {                 \
  97         .data = name,                                   \
  98         .size = ARRAY_SIZE(name),                       \
  99         .parse = rtw_parse_tbl_bb_pg,                   \
 100 }
 101
 102 #define RTW_DECL_TABLE_TXPWR_LMT(name)                  \
 103 const struct rtw_table name ## _tbl = {                 \
 104         .data = name,                                   \
 105         .size = ARRAY_SIZE(name),                       \
 106         .parse = rtw_parse_tbl_txpwr_lmt,               \
 107 }
 108
 109 static inline const struct rtw_rfe_def *rtw_get_rfe_def(struct rtw_dev *rtwdev)
 110 {
 111         struct rtw_chip_info *chip = rtwdev->chip;
 112         struct rtw_efuse *efuse = &rtwdev->efuse;
 113         const struct rtw_rfe_def *rfe_def = NULL;
 114
 115         if (chip->rfe_defs_size == 0)
 116                 return NULL;
 117
 118         if (efuse->rfe_option < chip->rfe_defs_size)
 119                 rfe_def = &chip->rfe_defs[efuse->rfe_option];
 120
 121         rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option);
 122         return rfe_def;
 123 }
 124
 125 static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev)
 126 {
 127         const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
 128
 129         if (!rfe_def || !rfe_def->phy_pg_tbl || !rfe_def->txpwr_lmt_tbl) {
 130                 rtw_err(rtwdev, "rfe %d isn't supported\n",
 131                         rtwdev->efuse.rfe_option);
 132                 return -ENODEV;
 133         }
 134
 135         return 0;
 136 }
 137
 138 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi);
 139
 140 struct rtw_power_params {
 141         u8 pwr_base;
 142         s8 pwr_offset;
 143         s8 pwr_limit;
 144         s8 pwr_remnant;
 145 };
 146
 147 void
 148 rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path,
 149                         u8 rate, u8 bw, u8 ch, u8 regd,
 150                         struct rtw_power_params *pwr_param);
 151
 152 enum rtw_phy_cck_pd_lv {
 153         CCK_PD_LV0,
 154         CCK_PD_LV1,
 155         CCK_PD_LV2,
 156         CCK_PD_LV3,
 157         CCK_PD_LV4,
 158         CCK_PD_LV_MAX,
 159 };
 160
 161 #define MASKBYTE0               0xff
 162 #define MASKBYTE1               0xff00
 163 #define MASKBYTE2               0xff0000
 164 #define MASKBYTE3               0xff000000
 165 #define MASKHWORD               0xffff0000
 166 #define MASKLWORD               0x0000ffff
 167 #define MASKDWORD               0xffffffff
 168 #define RFREG_MASK              0xfffff
 169
 170 #define MASK7BITS               0x7f
 171 #define MASK12BITS              0xfff
 172 #define MASKH4BITS              0xf0000000
 173 #define MASK20BITS              0xfffff
 174 #define MASK24BITS              0xffffff
 175
 176 #define MASKH3BYTES             0xffffff00
 177 #define MASKL3BYTES             0x00ffffff
 178 #define MASKBYTE2HIGHNIBBLE     0x00f00000
 179 #define MASKBYTE3LOWNIBBLE      0x0f000000
 180 #define MASKL3BYTES             0x00ffffff
 181
 182 #define CCK_FA_AVG_RESET 0xffffffff
 183
 184 #define LSSI_READ_ADDR_MASK     0x7f800000
 185 #define LSSI_READ_EDGE_MASK     0x80000000
 186 #define LSSI_READ_DATA_MASK     0xfffff
 187
 188 #endif