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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / net / wireless / realtek / rtw88 / rtw8822c.c
blobdd560c28abb2f995d74212de1fc736a21901fb73
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #include <linux/module.h>
6 #include "main.h"
7 #include "coex.h"
8 #include "fw.h"
9 #include "tx.h"
10 #include "rx.h"
11 #include "phy.h"
12 #include "rtw8822c.h"
13 #include "rtw8822c_table.h"
14 #include "mac.h"
15 #include "reg.h"
16 #include "debug.h"
17 #include "util.h"
18 #include "bf.h"
19 #include "efuse.h"
20
21 #define IQK_DONE_8822C 0xaa
22
23 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
24 u8 rx_path, bool is_tx2_path);
25
26 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse,
27 struct rtw8822c_efuse *map)
28 {
29 ether_addr_copy(efuse->addr, map->e.mac_addr);
30 }
31
32 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
33 {
34 struct rtw_efuse *efuse = &rtwdev->efuse;
35 struct rtw8822c_efuse *map;
36 int i;
37
38 map = (struct rtw8822c_efuse *)log_map;
39
40 efuse->rfe_option = map->rfe_option;
41 efuse->rf_board_option = map->rf_board_option;
42 efuse->crystal_cap = map->xtal_k;
43 efuse->channel_plan = map->channel_plan;
44 efuse->country_code[0] = map->country_code[0];
45 efuse->country_code[1] = map->country_code[1];
46 efuse->bt_setting = map->rf_bt_setting;
47 efuse->regd = map->rf_board_option & 0x7;
48 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal;
49 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal;
50 efuse->thermal_meter_k =
51 (map->path_a_thermal + map->path_b_thermal) >> 1;
52 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf;
53
54 for (i = 0; i < 4; i++)
55 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
56
57 switch (rtw_hci_type(rtwdev)) {
58 case RTW_HCI_TYPE_PCIE:
59 rtw8822ce_efuse_parsing(efuse, map);
60 break;
61 default:
62 /* unsupported now */
63 return -ENOTSUPP;
64 }
65
66 return 0;
67 }
68
69 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre)
70 {
71 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
72 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON);
73 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
74 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON);
75
76 if (pre)
77 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
78 else
79 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
80 }
81
82 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev,
83 struct rtw_backup_info *backup,
84 struct rtw_backup_info *backup_rf)
85 {
86 u32 path, i;
87 u32 val;
88 u32 reg;
89 u32 rf_addr[DACK_RF_8822C] = {0x8f};
90 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110,
91 0x1c3c, 0x1c24, 0x1d70, 0x9b4,
92 0x1a00, 0x1a14, 0x1d58, 0x1c38,
93 0x1e24, 0x1e28, 0x1860, 0x4160};
94
95 for (i = 0; i < DACK_REG_8822C; i++) {
96 backup[i].len = 4;
97 backup[i].reg = addrs[i];
98 backup[i].val = rtw_read32(rtwdev, addrs[i]);
99 }
100
101 for (path = 0; path < DACK_PATH_8822C; path++) {
102 for (i = 0; i < DACK_RF_8822C; i++) {
103 reg = rf_addr[i];
104 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
105 backup_rf[path * i + i].reg = reg;
106 backup_rf[path * i + i].val = val;
107 }
108 }
109 }
110
111 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev,
112 struct rtw_backup_info *backup,
113 struct rtw_backup_info *backup_rf)
114 {
115 u32 path, i;
116 u32 val;
117 u32 reg;
118
119 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C);
120
121 for (path = 0; path < DACK_PATH_8822C; path++) {
122 for (i = 0; i < DACK_RF_8822C; i++) {
123 val = backup_rf[path * i + i].val;
124 reg = backup_rf[path * i + i].reg;
125 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
126 }
127 }
128 }
129
130 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value,
131 u32 *min, u32 *max)
132 {
133 if (value >= 0x200) {
134 if (*min >= 0x200) {
135 if (*min > value)
136 *min = value;
137 } else {
138 *min = value;
139 }
140 if (*max >= 0x200) {
141 if (*max < value)
142 *max = value;
143 }
144 } else {
145 if (*min < 0x200) {
146 if (*min > value)
147 *min = value;
148 }
149
150 if (*max >= 0x200) {
151 *max = value;
152 } else {
153 if (*max < value)
154 *max = value;
155 }
156 }
157 }
158
159 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2)
160 {
161 if (*v1 >= 0x200 && *v2 >= 0x200) {
162 if (*v1 > *v2)
163 swap(*v1, *v2);
164 } else if (*v1 < 0x200 && *v2 < 0x200) {
165 if (*v1 > *v2)
166 swap(*v1, *v2);
167 } else if (*v1 < 0x200 && *v2 >= 0x200) {
168 swap(*v1, *v2);
169 }
170 }
171
172 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
173 {
174 u32 i, j;
175
176 for (i = 0; i < DACK_SN_8822C - 1; i++) {
177 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) {
178 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]);
179 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]);
180 }
181 }
182 }
183
184 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val)
185 {
186 u32 p, m, t, i;
187
188 m = 0;
189 p = 0;
190 for (i = 10; i < DACK_SN_8822C - 10; i++) {
191 if (vec[i] > 0x200)
192 m = (0x400 - vec[i]) + m;
193 else
194 p = vec[i] + p;
195 }
196
197 if (p > m) {
198 t = p - m;
199 t = t / (DACK_SN_8822C - 20);
200 } else {
201 t = m - p;
202 t = t / (DACK_SN_8822C - 20);
203 if (t != 0x0)
204 t = 0x400 - t;
205 }
206
207 *val = t;
208 }
209
210 static u32 rtw8822c_get_path_write_addr(u8 path)
211 {
212 u32 base_addr;
213
214 switch (path) {
215 case RF_PATH_A:
216 base_addr = 0x1800;
217 break;
218 case RF_PATH_B:
219 base_addr = 0x4100;
220 break;
221 default:
222 WARN_ON(1);
223 return -1;
224 }
225
226 return base_addr;
227 }
228
229 static u32 rtw8822c_get_path_read_addr(u8 path)
230 {
231 u32 base_addr;
232
233 switch (path) {
234 case RF_PATH_A:
235 base_addr = 0x2800;
236 break;
237 case RF_PATH_B:
238 base_addr = 0x4500;
239 break;
240 default:
241 WARN_ON(1);
242 return -1;
243 }
244
245 return base_addr;
246 }
247
248 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value)
249 {
250 bool ret = true;
251
252 if ((value >= 0x200 && (0x400 - value) > 0x64) ||
253 (value < 0x200 && value > 0x64)) {
254 ret = false;
255 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n");
256 }
257
258 return ret;
259 }
260
261 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
262 {
263 u32 temp;
264 int i = 0, cnt = 0;
265
266 while (i < DACK_SN_8822C && cnt < 10000) {
267 cnt++;
268 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
269 iv[i] = (temp & 0x3ff000) >> 12;
270 qv[i] = temp & 0x3ff;
271
272 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) &&
273 rtw8822c_dac_iq_check(rtwdev, qv[i]))
274 i++;
275 }
276 }
277
278 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev,
279 u32 *iv, u32 *qv,
280 u32 *i_value, u32 *q_value)
281 {
282 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0;
283 u32 i_delta, q_delta;
284 u32 temp;
285 int i, cnt = 0;
286
287 do {
288 i_min = iv[0];
289 i_max = iv[0];
290 q_min = qv[0];
291 q_max = qv[0];
292 for (i = 0; i < DACK_SN_8822C; i++) {
293 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max);
294 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max);
295 }
296
297 if (i_max < 0x200 && i_min < 0x200)
298 i_delta = i_max - i_min;
299 else if (i_max >= 0x200 && i_min >= 0x200)
300 i_delta = i_max - i_min;
301 else
302 i_delta = i_max + (0x400 - i_min);
303
304 if (q_max < 0x200 && q_min < 0x200)
305 q_delta = q_max - q_min;
306 else if (q_max >= 0x200 && q_min >= 0x200)
307 q_delta = q_max - q_min;
308 else
309 q_delta = q_max + (0x400 - q_min);
310
311 rtw_dbg(rtwdev, RTW_DBG_RFK,
312 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n",
313 i_min, i_max, i_delta);
314 rtw_dbg(rtwdev, RTW_DBG_RFK,
315 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n",
316 q_min, q_max, q_delta);
317
318 rtw8822c_dac_iq_sort(rtwdev, iv, qv);
319
320 if (i_delta > 5 || q_delta > 5) {
321 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
322 iv[0] = (temp & 0x3ff000) >> 12;
323 qv[0] = temp & 0x3ff;
324 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
325 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12;
326 qv[DACK_SN_8822C - 1] = temp & 0x3ff;
327 } else {
328 break;
329 }
330 } while (cnt++ < 100);
331
332 rtw8822c_dac_iq_offset(rtwdev, iv, i_value);
333 rtw8822c_dac_iq_offset(rtwdev, qv, q_value);
334 }
335
336 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev,
337 u32 *i_value, u32 *q_value)
338 {
339 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C];
340 u32 rf_a, rf_b;
341
342 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
343 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
344
345 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
346 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
347
348 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv);
349 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value);
350 }
351
352 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev)
353 {
354 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
355 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
356 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
357 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
358 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
359 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
360 rtw_write32(rtwdev, 0x1b00, 0x00000008);
361 rtw_write8(rtwdev, 0x1bcc, 0x3f);
362 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
363 rtw_write8(rtwdev, 0x1bcc, 0x3f);
364 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
365 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
366 }
367
368 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev,
369 u8 path, u32 *adc_ic, u32 *adc_qc)
370 {
371 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
372 u32 ic = 0, qc = 0, temp = 0;
373 u32 base_addr;
374 u32 path_sel;
375 int i;
376
377 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path);
378
379 base_addr = rtw8822c_get_path_write_addr(path);
380 switch (path) {
381 case RF_PATH_A:
382 path_sel = 0xa0000;
383 break;
384 case RF_PATH_B:
385 path_sel = 0x80000;
386 break;
387 default:
388 WARN_ON(1);
389 return;
390 }
391
392 /* ADCK step1 */
393 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
394 if (path == RF_PATH_B)
395 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
396 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
397 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
398 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
399 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
400 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
401 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
402 for (i = 0; i < 10; i++) {
403 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i);
404 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
405 rtw_write32(rtwdev, 0x1c24, 0x00010002);
406 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
407 rtw_dbg(rtwdev, RTW_DBG_RFK,
408 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc);
409
410 /* compensation value */
411 if (ic != 0x0) {
412 ic = 0x400 - ic;
413 *adc_ic = ic;
414 }
415 if (qc != 0x0) {
416 qc = 0x400 - qc;
417 *adc_qc = qc;
418 }
419 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);
420 rtw_write32(rtwdev, base_addr + 0x68, temp);
421 dm_info->dack_adck[path] = temp;
422 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
423 base_addr + 0x68, temp);
424 /* check ADC DC offset */
425 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
426 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
427 rtw_dbg(rtwdev, RTW_DBG_RFK,
428 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc);
429 if (ic >= 0x200)
430 ic = 0x400 - ic;
431 if (qc >= 0x200)
432 qc = 0x400 - qc;
433 if (ic < 5 && qc < 5)
434 break;
435 }
436
437 /* ADCK step2 */
438 rtw_write32(rtwdev, 0x1c3c, 0x00000003);
439 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
440 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
441
442 /* release pull low switch on IQ path */
443 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
444 }
445
446 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path)
447 {
448 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
449 u32 base_addr;
450 u32 read_addr;
451
452 base_addr = rtw8822c_get_path_write_addr(path);
453 read_addr = rtw8822c_get_path_read_addr(path);
454
455 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
456 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
457 if (path == RF_PATH_A) {
458 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
459 rtw_write32(rtwdev, 0x1c38, 0xffffffff);
460 }
461 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
462 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
463 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
464 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
465 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
466 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
467 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
468 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
469 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
470 mdelay(2);
471 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
472 mdelay(2);
473 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
474 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
475 mdelay(1);
476 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
477 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
478 mdelay(20);
479 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
480 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
481 rtw_err(rtwdev, "failed to wait for dack ready\n");
482 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
483 mdelay(1);
484 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
485 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
486 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
487 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
488 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
489 }
490
491 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev,
492 u8 path, u32 *ic_out, u32 *qc_out)
493 {
494 u32 base_addr;
495 u32 ic, qc, ic_in, qc_in;
496
497 base_addr = rtw8822c_get_path_write_addr(path);
498 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
499 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
500 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
501 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
502
503 rtw_write32(rtwdev, 0x1b00, 0x00000008);
504 rtw_write8(rtwdev, 0x1bcc, 0x03f);
505 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
506 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
507 rtw_write32(rtwdev, 0x1c3c, 0x00088103);
508
509 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in);
510 ic = ic_in;
511 qc = qc_in;
512
513 /* compensation value */
514 if (ic != 0x0)
515 ic = 0x400 - ic;
516 if (qc != 0x0)
517 qc = 0x400 - qc;
518 if (ic < 0x300) {
519 ic = ic * 2 * 6 / 5;
520 ic = ic + 0x80;
521 } else {
522 ic = (0x400 - ic) * 2 * 6 / 5;
523 ic = 0x7f - ic;
524 }
525 if (qc < 0x300) {
526 qc = qc * 2 * 6 / 5;
527 qc = qc + 0x80;
528 } else {
529 qc = (0x400 - qc) * 2 * 6 / 5;
530 qc = 0x7f - qc;
531 }
532
533 *ic_out = ic;
534 *qc_out = qc;
535
536 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
537 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc);
538 }
539
540 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path,
541 u32 adc_ic, u32 adc_qc,
542 u32 *ic_in, u32 *qc_in,
543 u32 *i_out, u32 *q_out)
544 {
545 u32 base_addr;
546 u32 read_addr;
547 u32 ic, qc;
548 u32 temp;
549
550 base_addr = rtw8822c_get_path_write_addr(path);
551 read_addr = rtw8822c_get_path_read_addr(path);
552 ic = *ic_in;
553 qc = *qc_in;
554
555 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
556 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
557 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
558 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
559 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
560 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
561 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
562 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
563 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
564 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
565 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
566 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
567 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
568 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
569 mdelay(2);
570 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
571 mdelay(2);
572 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
573 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
574 mdelay(1);
575 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
576 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
577 mdelay(20);
578 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
579 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
580 rtw_err(rtwdev, "failed to write IQ vector to hardware\n");
581 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
582 mdelay(1);
583 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
584 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
585
586 /* check DAC DC offset */
587 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10);
588 rtw_write32(rtwdev, base_addr + 0x68, temp);
589 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
590 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
591 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
592 if (ic >= 0x10)
593 ic = ic - 0x10;
594 else
595 ic = 0x400 - (0x10 - ic);
596
597 if (qc >= 0x10)
598 qc = qc - 0x10;
599 else
600 qc = 0x400 - (0x10 - qc);
601
602 *i_out = ic;
603 *q_out = qc;
604
605 if (ic >= 0x200)
606 ic = 0x400 - ic;
607 if (qc >= 0x200)
608 qc = 0x400 - qc;
609
610 *ic_in = ic;
611 *qc_in = qc;
612
613 rtw_dbg(rtwdev, RTW_DBG_RFK,
614 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out);
615 }
616
617 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path)
618 {
619 u32 base_addr = rtw8822c_get_path_write_addr(path);
620
621 rtw_write32(rtwdev, base_addr + 0x68, 0x0);
622 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
623 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
624 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
625 }
626
627 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev,
628 u8 path, u8 vec, u32 w_addr, u32 r_addr)
629 {
630 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
631 u16 val;
632 u32 i;
633
634 if (WARN_ON(vec >= 2))
635 return;
636
637 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
638 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i);
639 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
640 dm_info->dack_msbk[path][vec][i] = val;
641 }
642 }
643
644 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path)
645 {
646 u32 w_off = 0x1c;
647 u32 r_off = 0x2c;
648 u32 w_addr, r_addr;
649
650 if (WARN_ON(path >= 2))
651 return;
652
653 /* backup I vector */
654 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0;
655 r_addr = rtw8822c_get_path_read_addr(path) + 0x10;
656 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
657
658 /* backup Q vector */
659 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
660 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off;
661 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr);
662 }
663
664 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev)
665 {
666 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
667 u8 val;
668
669 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
670 dm_info->dack_dck[RF_PATH_A][0][0] = val;
671 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
672 dm_info->dack_dck[RF_PATH_A][0][1] = val;
673 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
674 dm_info->dack_dck[RF_PATH_A][1][0] = val;
675 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
676 dm_info->dack_dck[RF_PATH_A][1][1] = val;
677
678 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
679 dm_info->dack_dck[RF_PATH_B][0][0] = val;
680 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
681 dm_info->dack_dck[RF_PATH_B][1][0] = val;
682 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
683 dm_info->dack_dck[RF_PATH_B][0][1] = val;
684 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
685 dm_info->dack_dck[RF_PATH_B][1][1] = val;
686 }
687
688 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev)
689 {
690 u32 temp[3];
691
692 temp[0] = rtw_read32(rtwdev, 0x1860);
693 temp[1] = rtw_read32(rtwdev, 0x4160);
694 temp[2] = rtw_read32(rtwdev, 0x9b4);
695
696 /* set clock */
697 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
698
699 /* backup path-A I/Q */
700 rtw_write32_clr(rtwdev, 0x1830, BIT(30));
701 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
702 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A);
703
704 /* backup path-B I/Q */
705 rtw_write32_clr(rtwdev, 0x4130, BIT(30));
706 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
707 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B);
708
709 rtw8822c_dac_cal_backup_dck(rtwdev);
710 rtw_write32_set(rtwdev, 0x1830, BIT(30));
711 rtw_write32_set(rtwdev, 0x4130, BIT(30));
712
713 rtw_write32(rtwdev, 0x1860, temp[0]);
714 rtw_write32(rtwdev, 0x4160, temp[1]);
715 rtw_write32(rtwdev, 0x9b4, temp[2]);
716 }
717
718 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev)
719 {
720 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
721 u8 val;
722
723 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19));
724 val = dm_info->dack_dck[RF_PATH_A][0][0];
725 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
726 val = dm_info->dack_dck[RF_PATH_A][0][1];
727 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
728
729 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19));
730 val = dm_info->dack_dck[RF_PATH_A][1][0];
731 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
732 val = dm_info->dack_dck[RF_PATH_A][1][1];
733 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
734
735 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19));
736 val = dm_info->dack_dck[RF_PATH_B][0][0];
737 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
738 val = dm_info->dack_dck[RF_PATH_B][0][1];
739 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
740
741 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19));
742 val = dm_info->dack_dck[RF_PATH_B][1][0];
743 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
744 val = dm_info->dack_dck[RF_PATH_B][1][1];
745 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
746 }
747
748 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev)
749 {
750 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
751
752 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0);
753 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0);
754 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0);
755 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0);
756
757 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0);
758 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
759 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1);
760 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1);
761
762 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0);
763 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
764 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1);
765 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1);
766
767 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0);
768 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0);
769 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0);
770 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0);
771
772 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0);
773 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0);
774 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1);
775 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1);
776
777 rtw8822c_dac_cal_restore_dck(rtwdev);
778
779 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7);
780 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7);
781 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7);
782 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7);
783
784 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1);
785 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1);
786
787 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0);
788 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0);
789 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0);
790 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0);
791
792 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0);
793 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0);
794 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1);
795 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1);
796
797 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1);
798 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1);
799 }
800
801 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev,
802 u32 target_addr, u32 toggle_addr)
803 {
804 u32 cnt = 0;
805
806 do {
807 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0);
808 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2);
809
810 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
811 return true;
812
813 } while (cnt++ < 100);
814
815 return false;
816 }
817
818 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path)
819 {
820 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
821 u32 w_off = 0x1c;
822 u32 r_off = 0x2c;
823 u32 w_i, r_i, w_q, r_q;
824 u32 value;
825 u32 i;
826
827 w_i = rtw8822c_get_path_write_addr(path) + 0xb0;
828 r_i = rtw8822c_get_path_read_addr(path) + 0x08;
829 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
830 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off;
831
832 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8))
833 return false;
834
835 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
836 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
837 value = dm_info->dack_msbk[path][0][i];
838 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value);
839 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i);
840 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1);
841 }
842
843 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
844
845 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8))
846 return false;
847
848 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
849 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
850 value = dm_info->dack_msbk[path][1][i];
851 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value);
852 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i);
853 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1);
854 }
855 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
856
857 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0);
858 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0);
859 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0);
860 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0);
861
862 return true;
863 }
864
865 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
866 {
867 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A))
868 return false;
869
870 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B))
871 return false;
872
873 return true;
874 }
875
876 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
877 {
878 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
879 u32 temp[3];
880
881 /* sample the first element for both path's IQ vector */
882 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 &&
883 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 &&
884 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 &&
885 dm_info->dack_msbk[RF_PATH_B][1][0] == 0)
886 return false;
887
888 temp[0] = rtw_read32(rtwdev, 0x1860);
889 temp[1] = rtw_read32(rtwdev, 0x4160);
890 temp[2] = rtw_read32(rtwdev, 0x9b4);
891
892 rtw8822c_dac_cal_restore_prepare(rtwdev);
893 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
894 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
895 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
896 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
897 return false;
898
899 if (!__rtw8822c_dac_cal_restore(rtwdev)) {
900 rtw_err(rtwdev, "failed to restore dack vectors\n");
901 return false;
902 }
903
904 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1);
905 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
906 rtw_write32(rtwdev, 0x1860, temp[0]);
907 rtw_write32(rtwdev, 0x4160, temp[1]);
908 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1);
909 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1);
910 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1);
911 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1);
912 rtw_write32(rtwdev, 0x9b4, temp[2]);
913
914 return true;
915 }
916
917 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev)
918 {
919 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C];
920 struct rtw_backup_info backup[DACK_REG_8822C];
921 u32 ic = 0, qc = 0, i;
922 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0;
923 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0;
924 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0;
925
926 if (rtw8822c_dac_cal_restore(rtwdev))
927 return;
928
929 /* not able to restore, do it */
930
931 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf);
932
933 rtw8822c_dac_bb_setting(rtwdev);
934
935 /* path-A */
936 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a);
937 for (i = 0; i < 10; i++) {
938 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A);
939 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc);
940 ic_a = ic;
941 qc_a = qc;
942
943 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a,
944 &ic, &qc, &i_a, &q_a);
945
946 if (ic < 5 && qc < 5)
947 break;
948 }
949 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A);
950
951 /* path-B */
952 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b);
953 for (i = 0; i < 10; i++) {
954 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B);
955 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc);
956 ic_b = ic;
957 qc_b = qc;
958
959 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b,
960 &ic, &qc, &i_b, &q_b);
961
962 if (ic < 5 && qc < 5)
963 break;
964 }
965 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B);
966
967 rtw_write32(rtwdev, 0x1b00, 0x00000008);
968 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
969 rtw_write8(rtwdev, 0x1bcc, 0x0);
970 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
971 rtw_write8(rtwdev, 0x1bcc, 0x0);
972
973 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf);
974
975 /* backup results to restore, saving a lot of time */
976 rtw8822c_dac_cal_backup(rtwdev);
977
978 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
979 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
980 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
981 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
982 }
983
984 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev)
985 {
986 u8 x2k_busy;
987
988 mdelay(1);
989 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15));
990 if (x2k_busy == 1) {
991 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440);
992 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D);
993 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440);
994 mdelay(1);
995 }
996 }
997
998 static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8])
999 {
1000 #define RF_SET_POWER_TRIM(_path, _seq, _idx) \
1001 do { \
1002 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \
1003 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \
1004 bb_gain[_path][_idx]); \
1005 } while (0)
1006 u8 path;
1007
1008 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1009 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1);
1010 RF_SET_POWER_TRIM(path, 0x0, 0);
1011 RF_SET_POWER_TRIM(path, 0x1, 1);
1012 RF_SET_POWER_TRIM(path, 0x2, 2);
1013 RF_SET_POWER_TRIM(path, 0x3, 2);
1014 RF_SET_POWER_TRIM(path, 0x4, 3);
1015 RF_SET_POWER_TRIM(path, 0x5, 4);
1016 RF_SET_POWER_TRIM(path, 0x6, 5);
1017 RF_SET_POWER_TRIM(path, 0x7, 6);
1018 RF_SET_POWER_TRIM(path, 0x8, 7);
1019 RF_SET_POWER_TRIM(path, 0x9, 3);
1020 RF_SET_POWER_TRIM(path, 0xa, 4);
1021 RF_SET_POWER_TRIM(path, 0xb, 5);
1022 RF_SET_POWER_TRIM(path, 0xc, 6);
1023 RF_SET_POWER_TRIM(path, 0xd, 7);
1024 RF_SET_POWER_TRIM(path, 0xe, 7);
1025 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0);
1026 }
1027 #undef RF_SET_POWER_TRIM
1028 }
1029
1030 static void rtw8822c_power_trim(struct rtw_dev *rtwdev)
1031 {
1032 u8 pg_pwr = 0xff, i, path, idx;
1033 s8 bb_gain[2][8] = {};
1034 u16 rf_efuse_2g[3] = {PPG_2GL_TXAB, PPG_2GM_TXAB, PPG_2GH_TXAB};
1035 u16 rf_efuse_5g[2][5] = {{PPG_5GL1_TXA, PPG_5GL2_TXA, PPG_5GM1_TXA,
1036 PPG_5GM2_TXA, PPG_5GH1_TXA},
1037 {PPG_5GL1_TXB, PPG_5GL2_TXB, PPG_5GM1_TXB,
1038 PPG_5GM2_TXB, PPG_5GH1_TXB} };
1039 bool set = false;
1040
1041 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) {
1042 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr);
1043 if (pg_pwr == EFUSE_READ_FAIL)
1044 continue;
1045 set = true;
1046 bb_gain[RF_PATH_A][i] = FIELD_GET(PPG_2G_A_MASK, pg_pwr);
1047 bb_gain[RF_PATH_B][i] = FIELD_GET(PPG_2G_B_MASK, pg_pwr);
1048 }
1049
1050 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) {
1051 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1052 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i],
1053 &pg_pwr);
1054 if (pg_pwr == EFUSE_READ_FAIL)
1055 continue;
1056 set = true;
1057 idx = i + ARRAY_SIZE(rf_efuse_2g);
1058 bb_gain[path][idx] = FIELD_GET(PPG_5G_MASK, pg_pwr);
1059 }
1060 }
1061 if (set)
1062 rtw8822c_set_power_trim(rtwdev, bb_gain);
1063
1064 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1065 }
1066
1067 static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev)
1068 {
1069 u16 rf_efuse[2] = {PPG_THERMAL_A, PPG_THERMAL_B};
1070 u8 pg_therm = 0xff, thermal[2] = {0}, path;
1071
1072 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1073 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm);
1074 if (pg_therm == EFUSE_READ_FAIL)
1075 return;
1076 /* Efuse value of BIT(0) shall be move to BIT(3), and the value
1077 * of BIT(1) to BIT(3) should be right shifted 1 bit.
1078 */
1079 thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm);
1080 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0));
1081 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]);
1082 }
1083 }
1084
1085 static void rtw8822c_pa_bias(struct rtw_dev *rtwdev)
1086 {
1087 u16 rf_efuse_2g[2] = {PPG_PABIAS_2GA, PPG_PABIAS_2GB};
1088 u16 rf_efuse_5g[2] = {PPG_PABIAS_5GA, PPG_PABIAS_5GB};
1089 u8 pg_pa_bias = 0xff, path;
1090
1091 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1092 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path],
1093 &pg_pa_bias);
1094 if (pg_pa_bias == EFUSE_READ_FAIL)
1095 return;
1096 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias);
1097 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_2G_MASK, pg_pa_bias);
1098 }
1099 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1100 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path],
1101 &pg_pa_bias);
1102 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias);
1103 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_5G_MASK, pg_pa_bias);
1104 }
1105 }
1106
1107 static void rtw8822c_rf_init(struct rtw_dev *rtwdev)
1108 {
1109 rtw8822c_rf_dac_cal(rtwdev);
1110 rtw8822c_rf_x2_check(rtwdev);
1111 rtw8822c_thermal_trim(rtwdev);
1112 rtw8822c_power_trim(rtwdev);
1113 rtw8822c_pa_bias(rtwdev);
1114 }
1115
1116 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev)
1117 {
1118 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1119 u8 path;
1120
1121 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) {
1122 dm_info->delta_power_index[path] = 0;
1123 ewma_thermal_init(&dm_info->avg_thermal[path]);
1124 dm_info->thermal_avg[path] = 0xff;
1125 }
1126
1127 dm_info->pwr_trk_triggered = false;
1128 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
1129 }
1130
1131 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev)
1132 {
1133 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1134 struct rtw_hal *hal = &rtwdev->hal;
1135 u8 crystal_cap;
1136 u8 cck_gi_u_bnd_msb = 0;
1137 u8 cck_gi_u_bnd_lsb = 0;
1138 u8 cck_gi_l_bnd_msb = 0;
1139 u8 cck_gi_l_bnd_lsb = 0;
1140 bool is_tx2_path;
1141
1142 /* power on BB/RF domain */
1143 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
1144 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
1145 rtw_write8_set(rtwdev, REG_RF_CTRL,
1146 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
1147 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
1148
1149 /* disable low rate DPD */
1150 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1151
1152 /* pre init before header files config */
1153 rtw8822c_header_file_init(rtwdev, true);
1154
1155 rtw_phy_load_tables(rtwdev);
1156
1157 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1158 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00,
1159 crystal_cap | (crystal_cap << 7));
1160
1161 /* post init after header files config */
1162 rtw8822c_header_file_init(rtwdev, false);
1163
1164 is_tx2_path = false;
1165 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
1166 is_tx2_path);
1167 rtw_phy_init(rtwdev);
1168
1169 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
1170 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
1171 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
1172 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
1173
1174 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb));
1175 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb));
1176
1177 rtw8822c_rf_init(rtwdev);
1178 rtw8822c_pwrtrack_init(rtwdev);
1179
1180 rtw_bf_phy_init(rtwdev);
1181 }
1182
1183 #define WLAN_TXQ_RPT_EN 0x1F
1184 #define WLAN_SLOT_TIME 0x09
1185 #define WLAN_PIFS_TIME 0x1C
1186 #define WLAN_SIFS_CCK_CONT_TX 0x0A
1187 #define WLAN_SIFS_OFDM_CONT_TX 0x0E
1188 #define WLAN_SIFS_CCK_TRX 0x0A
1189 #define WLAN_SIFS_OFDM_TRX 0x10
1190 #define WLAN_NAV_MAX 0xC8
1191 #define WLAN_RDG_NAV 0x05
1192 #define WLAN_TXOP_NAV 0x1B
1193 #define WLAN_CCK_RX_TSF 0x30
1194 #define WLAN_OFDM_RX_TSF 0x30
1195 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
1196 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
1197 #define WLAN_DRV_EARLY_INT 0x04
1198 #define WLAN_BCN_CTRL_CLT0 0x10
1199 #define WLAN_BCN_DMA_TIME 0x02
1200 #define WLAN_BCN_MAX_ERR 0xFF
1201 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A
1202 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10
1203 #define WLAN_SIFS_CCK_CTX 0x0A
1204 #define WLAN_SIFS_CCK_IRX 0x0A
1205 #define WLAN_SIFS_OFDM_CTX 0x0E
1206 #define WLAN_SIFS_OFDM_IRX 0x0E
1207 #define WLAN_EIFS_DUR_TUNE 0x40
1208 #define WLAN_EDCA_VO_PARAM 0x002FA226
1209 #define WLAN_EDCA_VI_PARAM 0x005EA328
1210 #define WLAN_EDCA_BE_PARAM 0x005EA42B
1211 #define WLAN_EDCA_BK_PARAM 0x0000A44F
1212
1213 #define WLAN_RX_FILTER0 0xFFFFFFFF
1214 #define WLAN_RX_FILTER2 0xFFFF
1215 #define WLAN_RCR_CFG 0xE400220E
1216 #define WLAN_RXPKT_MAX_SZ 12288
1217 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
1218
1219 #define WLAN_AMPDU_MAX_TIME 0x70
1220 #define WLAN_RTS_LEN_TH 0xFF
1221 #define WLAN_RTS_TX_TIME_TH 0x08
1222 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f
1223 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f
1224 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0
1225 #define FAST_EDCA_VO_TH 0x06
1226 #define FAST_EDCA_VI_TH 0x06
1227 #define FAST_EDCA_BE_TH 0x06
1228 #define FAST_EDCA_BK_TH 0x06
1229 #define WLAN_BAR_RETRY_LIMIT 0x01
1230 #define WLAN_BAR_ACK_TYPE 0x05
1231 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
1232 #define WLAN_RESP_TXRATE 0x84
1233 #define WLAN_ACK_TO 0x21
1234 #define WLAN_ACK_TO_CCK 0x6A
1235 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000
1236 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504
1237 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504
1238 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010
1239 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000
1240 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010
1241 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000
1242 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010
1243 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0
1244 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015
1245 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0
1246 #define WLAN_MULTI_ADDR 0xFFFFFFFF
1247
1248 #define WLAN_TX_FUNC_CFG1 0x30
1249 #define WLAN_TX_FUNC_CFG2 0x30
1250 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
1251 #define WLAN_MAC_OPT_LB_FUNC1 0x80
1252 #define WLAN_MAC_OPT_FUNC2 0x30810041
1253 #define WLAN_MAC_INT_MIG_CFG 0x33330000
1254
1255 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
1256 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
1257 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
1258 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
1259
1260 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \
1261 (WLAN_SIFS_OFDM_DUR_TUNE << 8))
1262
1263 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
1264 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
1265
1266 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
1267 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
1268
1269 #define MAC_CLK_SPEED 80 /* 80M */
1270 #define EFUSE_PCB_INFO_OFFSET 0xCA
1271
1272 static int rtw8822c_mac_init(struct rtw_dev *rtwdev)
1273 {
1274 u8 value8;
1275 u16 value16;
1276 u32 value32;
1277 u16 pre_txcnt;
1278
1279 /* txq control */
1280 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL);
1281 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2));
1282 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8);
1283 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
1284 /* sifs control */
1285 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE);
1286 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
1287 rtw_write16(rtwdev, REG_RESP_SIFS_CCK,
1288 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8);
1289 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM,
1290 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8);
1291 /* rate fallback control */
1292 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4);
1293 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8);
1294 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8);
1295 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0);
1296 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H);
1297 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1);
1298 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H);
1299 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4);
1300 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H);
1301 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5);
1302 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H);
1303 /* protocol configuration */
1304 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
1305 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
1306 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
1307 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
1308 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
1309 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
1310 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
1311 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
1312 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
1313 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
1314 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
1315 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
1316 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
1317 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
1318 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
1319 /* close BA parser */
1320 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN);
1321 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC);
1322
1323 /* EDCA configuration */
1324 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM);
1325 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM);
1326 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM);
1327 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM);
1328 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
1329 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
1330 rtw_write8_set(rtwdev, REG_RD_CTRL + 1,
1331 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE |
1332 BIT_DIS_STBC_CFE) >> 8);
1333
1334 /* MAC clock configuration */
1335 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL);
1336 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
1337 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
1338
1339 rtw_write8_set(rtwdev, REG_MISC_CTRL,
1340 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA);
1341 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
1342 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
1343 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
1344 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
1345 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
1346 /* Set beacon cotnrol - enable TSF and other related functions */
1347 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1348 /* Set send beacon related registers */
1349 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
1350 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
1351 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0);
1352 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
1353 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR);
1354
1355 /* WMAC configuration */
1356 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR);
1357 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR);
1358 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE);
1359 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO);
1360 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
1361 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE);
1362 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX);
1363 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE);
1364 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
1365 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
1366 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
1367 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
1368 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
1369 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
1370 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN);
1371 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
1372 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1);
1373
1374 /* init low power */
1375 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F;
1376 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) |
1377 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16;
1378 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16);
1379 value16 = 0;
1380 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1);
1381 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN
1382 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN
1383 | BIT_RXPSF_OFDMRST;
1384 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
1385 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);
1386 /* rx ignore configuration */
1387 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL);
1388 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST |
1389 BIT_RXPSF_CONT_ERRCHKEN);
1390 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07);
1391 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
1392
1393 /* Interrupt migration configuration */
1394 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG);
1395
1396 return 0;
1397 }
1398
1399 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable)
1400 {
1401 if (enable) {
1402 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1);
1403 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1);
1404 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1);
1405 } else {
1406 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0);
1407 }
1408 }
1409
1410 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
1411 {
1412 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
1413 #define RF18_BAND_2G (0)
1414 #define RF18_BAND_5G (BIT(16) | BIT(8))
1415 #define RF18_CHANNEL_MASK (MASKBYTE0)
1416 #define RF18_RFSI_MASK (BIT(18) | BIT(17))
1417 #define RF18_RFSI_GE_CH80 (BIT(17))
1418 #define RF18_RFSI_GT_CH140 (BIT(18))
1419 #define RF18_BW_MASK (BIT(13) | BIT(12))
1420 #define RF18_BW_20M (BIT(13) | BIT(12))
1421 #define RF18_BW_40M (BIT(13))
1422 #define RF18_BW_80M (BIT(12))
1423
1424 u32 rf_reg18 = 0;
1425 u32 rf_rxbb = 0;
1426
1427 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
1428
1429 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
1430 RF18_BW_MASK);
1431
1432 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G);
1433 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
1434 if (IS_CH_5G_BAND_4(channel))
1435 rf_reg18 |= RF18_RFSI_GT_CH140;
1436 else if (IS_CH_5G_BAND_3(channel))
1437 rf_reg18 |= RF18_RFSI_GE_CH80;
1438
1439 switch (bw) {
1440 case RTW_CHANNEL_WIDTH_5:
1441 case RTW_CHANNEL_WIDTH_10:
1442 case RTW_CHANNEL_WIDTH_20:
1443 default:
1444 rf_reg18 |= RF18_BW_20M;
1445 rf_rxbb = 0x18;
1446 break;
1447 case RTW_CHANNEL_WIDTH_40:
1448 /* RF bandwidth */
1449 rf_reg18 |= RF18_BW_40M;
1450 rf_rxbb = 0x10;
1451 break;
1452 case RTW_CHANNEL_WIDTH_80:
1453 rf_reg18 |= RF18_BW_80M;
1454 rf_rxbb = 0x8;
1455 break;
1456 }
1457
1458 rtw8822c_rstb_3wire(rtwdev, false);
1459
1460 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01);
1461 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12);
1462 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb);
1463 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00);
1464
1465 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01);
1466 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12);
1467 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb);
1468 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00);
1469
1470 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18);
1471 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18);
1472
1473 rtw8822c_rstb_3wire(rtwdev, true);
1474 }
1475
1476 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev)
1477 {
1478 u32 igi;
1479
1480 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
1481 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
1482 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
1483 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi);
1484 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi);
1485 }
1486
1487 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1488 u8 primary_ch_idx)
1489 {
1490 if (IS_CH_2G_BAND(channel)) {
1491 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1492 rtw_write32_set(rtwdev, REG_TXF4, BIT(20));
1493 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1494 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1495 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
1496
1497 switch (bw) {
1498 case RTW_CHANNEL_WIDTH_20:
1499 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
1500 0x5);
1501 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
1502 0x5);
1503 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1504 0x6);
1505 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1506 0x6);
1507 break;
1508 case RTW_CHANNEL_WIDTH_40:
1509 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
1510 0x4);
1511 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
1512 0x4);
1513 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1514 0x0);
1515 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1516 0x0);
1517 break;
1518 }
1519 if (channel == 13 || channel == 14)
1520 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
1521 else if (channel == 11 || channel == 12)
1522 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a);
1523 else
1524 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa);
1525 if (channel == 14) {
1526 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0);
1527 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1528 0x4962c931);
1529 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
1530 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b);
1531 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
1532 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0);
1533 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1534 0xff012455);
1535 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff);
1536 } else {
1537 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284);
1538 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1539 0x3e18fec8);
1540 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
1541 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4);
1542 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
1543 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD,
1544 0x00faf0de);
1545 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1546 0x00122344);
1547 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD,
1548 0x0fffffff);
1549 }
1550 if (channel == 13)
1551 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
1552 else
1553 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1);
1554 } else if (IS_CH_5G_BAND(channel)) {
1555 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1556 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1557 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1558 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20));
1559 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
1560 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
1561 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) {
1562 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1563 0x1);
1564 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1565 0x1);
1566 } else if (IS_CH_5G_BAND_3(channel)) {
1567 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1568 0x2);
1569 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1570 0x2);
1571 } else if (IS_CH_5G_BAND_4(channel)) {
1572 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1573 0x3);
1574 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1575 0x3);
1576 }
1577
1578 if (channel >= 36 && channel <= 51)
1579 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494);
1580 else if (channel >= 52 && channel <= 55)
1581 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493);
1582 else if (channel >= 56 && channel <= 111)
1583 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453);
1584 else if (channel >= 112 && channel <= 119)
1585 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452);
1586 else if (channel >= 120 && channel <= 172)
1587 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412);
1588 else if (channel >= 173 && channel <= 177)
1589 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411);
1590 }
1591
1592 switch (bw) {
1593 case RTW_CHANNEL_WIDTH_20:
1594 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B);
1595 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1596 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
1597 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
1598 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
1599 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1600 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1601 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1602 break;
1603 case RTW_CHANNEL_WIDTH_40:
1604 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4),
1605 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));
1606 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5);
1607 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1608 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1609 (primary_ch_idx | (primary_ch_idx << 4)));
1610 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1);
1611 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1612 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
1613 break;
1614 case RTW_CHANNEL_WIDTH_80:
1615 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
1616 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1617 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1618 (primary_ch_idx | (primary_ch_idx << 4)));
1619 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6);
1620 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
1621 break;
1622 case RTW_CHANNEL_WIDTH_5:
1623 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1624 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1625 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
1626 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
1627 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
1628 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1629 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1630 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1631 break;
1632 case RTW_CHANNEL_WIDTH_10:
1633 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1634 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1635 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
1636 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
1637 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
1638 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1639 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1640 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1641 break;
1642 }
1643 }
1644
1645 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1646 u8 primary_chan_idx)
1647 {
1648 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
1649 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
1650 rtw8822c_set_channel_rf(rtwdev, channel, bw);
1651 rtw8822c_toggle_igi(rtwdev);
1652 }
1653
1654 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1655 {
1656 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
1657 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0);
1658 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0);
1659 } else if (rx_path == BB_PATH_AB) {
1660 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1);
1661 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1);
1662 }
1663
1664 if (rx_path == BB_PATH_A)
1665 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0);
1666 else if (rx_path == BB_PATH_B)
1667 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5);
1668 else if (rx_path == BB_PATH_AB)
1669 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1);
1670 }
1671
1672 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1673 {
1674 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
1675 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0);
1676 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0);
1677 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0);
1678 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0);
1679 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0);
1680 } else if (rx_path == BB_PATH_AB) {
1681 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1);
1682 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1);
1683 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1);
1684 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1);
1685 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1);
1686 }
1687
1688 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path);
1689 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path);
1690 }
1691
1692 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1693 {
1694 rtw8822c_config_cck_rx_path(rtwdev, rx_path);
1695 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path);
1696 }
1697
1698 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1699 bool is_tx2_path)
1700 {
1701 if (tx_path == BB_PATH_A) {
1702 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1703 } else if (tx_path == BB_PATH_B) {
1704 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4);
1705 } else {
1706 if (is_tx2_path)
1707 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc);
1708 else
1709 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1710 }
1711 }
1712
1713 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1714 bool is_tx2_path)
1715 {
1716 if (tx_path == BB_PATH_A) {
1717 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11);
1718 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1719 } else if (tx_path == BB_PATH_B) {
1720 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12);
1721 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1722 } else {
1723 if (is_tx2_path) {
1724 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33);
1725 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404);
1726 } else {
1727 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31);
1728 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
1729 }
1730 }
1731 }
1732
1733 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1734 bool is_tx2_path)
1735 {
1736 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path);
1737 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path);
1738 }
1739
1740 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
1741 u8 rx_path, bool is_tx2_path)
1742 {
1743 if ((tx_path | rx_path) & BB_PATH_A)
1744 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312);
1745 else
1746 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111);
1747 if ((tx_path | rx_path) & BB_PATH_B)
1748 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312);
1749 else
1750 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111);
1751
1752 rtw8822c_config_rx_path(rtwdev, rx_path);
1753 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path);
1754
1755 rtw8822c_toggle_igi(rtwdev);
1756 }
1757
1758 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
1759 struct rtw_rx_pkt_stat *pkt_stat)
1760 {
1761 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1762 u8 l_bnd, u_bnd;
1763 u8 gain_a, gain_b;
1764 s8 rx_power[RTW_RF_PATH_MAX];
1765 s8 min_rx_power = -120;
1766 u8 rssi;
1767 int path;
1768
1769 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status);
1770 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status);
1771 l_bnd = dm_info->cck_gi_l_bnd;
1772 u_bnd = dm_info->cck_gi_u_bnd;
1773 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status);
1774 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status);
1775 if (gain_a < l_bnd)
1776 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1;
1777 else if (gain_a > u_bnd)
1778 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1;
1779 if (gain_b < l_bnd)
1780 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1;
1781 else if (gain_b > u_bnd)
1782 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1;
1783
1784 rx_power[RF_PATH_A] -= 110;
1785 rx_power[RF_PATH_B] -= 110;
1786
1787 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A];
1788 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B];
1789
1790 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
1791 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
1792 dm_info->rssi[path] = rssi;
1793 }
1794
1795 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
1796 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
1797 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
1798 min_rx_power);
1799 }
1800
1801 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
1802 struct rtw_rx_pkt_stat *pkt_stat)
1803 {
1804 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1805 u8 rxsc, bw;
1806 s8 min_rx_power = -120;
1807 s8 rx_evm;
1808 u8 evm_dbm = 0;
1809 u8 rssi;
1810 int path;
1811
1812 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
1813 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
1814 else
1815 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
1816
1817 if (rxsc >= 9 && rxsc <= 12)
1818 bw = RTW_CHANNEL_WIDTH_40;
1819 else if (rxsc >= 13)
1820 bw = RTW_CHANNEL_WIDTH_80;
1821 else
1822 bw = RTW_CHANNEL_WIDTH_20;
1823
1824 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
1825 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
1826 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
1827 pkt_stat->bw = bw;
1828 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
1829 pkt_stat->rx_power[RF_PATH_B],
1830 min_rx_power);
1831
1832 dm_info->curr_rx_rate = pkt_stat->rate;
1833
1834 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
1835 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status);
1836
1837 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
1838 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status);
1839
1840 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
1841 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status);
1842
1843 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
1844 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
1845 dm_info->rssi[path] = rssi;
1846 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
1847 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
1848
1849 rx_evm = pkt_stat->rx_evm[path];
1850
1851 if (rx_evm < 0) {
1852 if (rx_evm == S8_MIN)
1853 evm_dbm = 0;
1854 else
1855 evm_dbm = ((u8)-rx_evm >> 1);
1856 }
1857 dm_info->rx_evm_dbm[path] = evm_dbm;
1858 }
1859 }
1860
1861 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
1862 struct rtw_rx_pkt_stat *pkt_stat)
1863 {
1864 u8 page;
1865
1866 page = *phy_status & 0xf;
1867
1868 switch (page) {
1869 case 0:
1870 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
1871 break;
1872 case 1:
1873 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
1874 break;
1875 default:
1876 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
1877 return;
1878 }
1879 }
1880
1881 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
1882 struct rtw_rx_pkt_stat *pkt_stat,
1883 struct ieee80211_rx_status *rx_status)
1884 {
1885 struct ieee80211_hdr *hdr;
1886 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
1887 u8 *phy_status = NULL;
1888
1889 memset(pkt_stat, 0, sizeof(*pkt_stat));
1890
1891 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
1892 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
1893 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
1894 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
1895 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE;
1896 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
1897 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
1898 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
1899 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
1900 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
1901 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
1902 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
1903 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
1904
1905 /* drv_info_sz is in unit of 8-bytes */
1906 pkt_stat->drv_info_sz *= 8;
1907
1908 /* c2h cmd pkt's rx/phy status is not interested */
1909 if (pkt_stat->is_c2h)
1910 return;
1911
1912 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
1913 pkt_stat->drv_info_sz);
1914 if (pkt_stat->phy_status) {
1915 phy_status = rx_desc + desc_sz + pkt_stat->shift;
1916 query_phy_status(rtwdev, phy_status, pkt_stat);
1917 }
1918
1919 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
1920 }
1921
1922 static void
1923 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck,
1924 u8 *tx_pwr_ref_ofdm)
1925 {
1926 struct rtw_hal *hal = &rtwdev->hal;
1927 u32 txref_cck[2] = {0x18a0, 0x41a0};
1928 u32 txref_ofdm[2] = {0x18e8, 0x41e8};
1929 u8 path;
1930
1931 for (path = 0; path < hal->rf_path_num; path++) {
1932 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1933 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
1934 tx_pwr_ref_cck[path]);
1935 }
1936 for (path = 0; path < hal->rf_path_num; path++) {
1937 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1938 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
1939 tx_pwr_ref_ofdm[path]);
1940 }
1941 }
1942
1943 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate,
1944 s8 *diff_idx)
1945 {
1946 u32 offset_txagc = 0x3a00;
1947 u8 rate_idx = rate & 0xfc;
1948 u8 pwr_idx[4];
1949 u32 phy_pwr_idx;
1950 int i;
1951
1952 for (i = 0; i < 4; i++)
1953 pwr_idx[i] = diff_idx[i] & 0x7f;
1954
1955 phy_pwr_idx = pwr_idx[0] |
1956 (pwr_idx[1] << 8) |
1957 (pwr_idx[2] << 16) |
1958 (pwr_idx[3] << 24);
1959
1960 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0);
1961 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD,
1962 phy_pwr_idx);
1963 }
1964
1965 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev)
1966 {
1967 struct rtw_hal *hal = &rtwdev->hal;
1968 u8 rs, rate, j;
1969 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M],
1970 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]};
1971 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7],
1972 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]};
1973 s8 diff_a, diff_b;
1974 u8 pwr_a, pwr_b;
1975 s8 diff_idx[4];
1976
1977 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm);
1978 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
1979 for (j = 0; j < rtw_rate_size[rs]; j++) {
1980 rate = rtw_rate_section[rs][j];
1981 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate];
1982 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate];
1983 if (rs == 0) {
1984 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0];
1985 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1];
1986 } else {
1987 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0];
1988 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1];
1989 }
1990 diff_idx[rate % 4] = min(diff_a, diff_b);
1991 if (rate % 4 == 3)
1992 rtw8822c_set_tx_power_diff(rtwdev, rate - 3,
1993 diff_idx);
1994 }
1995 }
1996 }
1997
1998 static int rtw8822c_set_antenna(struct rtw_dev *rtwdev,
1999 u32 antenna_tx,
2000 u32 antenna_rx)
2001 {
2002 struct rtw_hal *hal = &rtwdev->hal;
2003
2004 switch (antenna_tx) {
2005 case BB_PATH_A:
2006 case BB_PATH_B:
2007 case BB_PATH_AB:
2008 break;
2009 default:
2010 rtw_info(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
2011 return -EINVAL;
2012 }
2013
2014 /* path B only is not available for RX */
2015 switch (antenna_rx) {
2016 case BB_PATH_A:
2017 case BB_PATH_AB:
2018 break;
2019 default:
2020 rtw_info(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
2021 return -EINVAL;
2022 }
2023
2024 hal->antenna_tx = antenna_tx;
2025 hal->antenna_rx = antenna_rx;
2026
2027 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
2028
2029 return 0;
2030 }
2031
2032 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
2033 {
2034 u8 ldo_pwr;
2035
2036 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC);
2037 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON;
2038 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr);
2039 }
2040
2041 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
2042 {
2043 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2044 u32 cck_enable;
2045 u32 cck_fa_cnt;
2046 u32 crc32_cnt;
2047 u32 cca32_cnt;
2048 u32 ofdm_fa_cnt;
2049 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5;
2050 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail,
2051 fast_fsync, crc8_fail_vhta, mcs_fail_vht;
2052
2053 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN;
2054 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT);
2055
2056 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1);
2057 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2);
2058 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3);
2059 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4);
2060 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5);
2061
2062 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1);
2063 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2);
2064 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2);
2065 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3);
2066 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4);
2067 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4);
2068 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5);
2069 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5);
2070
2071 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta +
2072 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail;
2073
2074 dm_info->cck_fa_cnt = cck_fa_cnt;
2075 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
2076 dm_info->total_fa_cnt = ofdm_fa_cnt;
2077 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
2078
2079 crc32_cnt = rtw_read32(rtwdev, 0x2c04);
2080 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
2081 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2082 crc32_cnt = rtw_read32(rtwdev, 0x2c14);
2083 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
2084 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2085 crc32_cnt = rtw_read32(rtwdev, 0x2c10);
2086 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
2087 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2088 crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
2089 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
2090 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2091
2092 cca32_cnt = rtw_read32(rtwdev, 0x2c08);
2093 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
2094 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
2095 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
2096 if (cck_enable)
2097 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
2098
2099 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
2100 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2);
2101 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
2102 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2);
2103
2104 /* disable rx clk gating to reset counters */
2105 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2106 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2107 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2108 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2109 }
2110
2111 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
2112 {
2113 struct rtw_iqk_para para = {0};
2114 u8 iqk_chk;
2115 int ret;
2116
2117 para.clear = 1;
2118 rtw_fw_do_iqk(rtwdev, &para);
2119
2120 ret = read_poll_timeout(rtw_read8, iqk_chk, iqk_chk == IQK_DONE_8822C,
2121 20000, 300000, false, rtwdev, REG_RPT_CIP);
2122 if (ret)
2123 rtw_warn(rtwdev, "failed to poll iqk status bit\n");
2124
2125 rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
2126 }
2127
2128 /* for coex */
2129 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev)
2130 {
2131 /* enable TBTT nterrupt */
2132 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2133
2134 /* BT report packet sample rate */
2135 /* 0x790[5:0]=0x5 */
2136 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
2137
2138 /* enable BT counter statistics */
2139 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
2140
2141 /* enable PTA (3-wire function form BT side) */
2142 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
2143 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
2144
2145 /* enable PTA (tx/rx signal form WiFi side) */
2146 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
2147 /* wl tx signal to PTA not case EDCCA */
2148 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
2149 /* GNT_BT=1 while select both */
2150 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
2151 /* BT_CCA = ~GNT_WL_BB, not or GNT_BT_BB, LTE_Rx */
2152 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL);
2153
2154 /* to avoid RF parameter error */
2155 rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000);
2156 }
2157
2158 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
2159 {
2160 struct rtw_coex *coex = &rtwdev->coex;
2161 struct rtw_coex_stat *coex_stat = &coex->stat;
2162 struct rtw_efuse *efuse = &rtwdev->efuse;
2163 u32 rf_0x1;
2164
2165 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode)
2166 return;
2167
2168 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode;
2169
2170 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun)
2171 rf_0x1 = 0x40021;
2172 else
2173 rf_0x1 = 0x40000;
2174
2175 /* BT at S1 for Shared-Ant */
2176 if (efuse->share_ant)
2177 rf_0x1 |= BIT(13);
2178
2179 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
2180
2181 /* WL-S0 2G RF TRX cannot be masked by GNT_BT
2182 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type
2183 * disable:0x1860[3] = 1, enable:0x1860[3] = 0
2184 *
2185 * enable "DAC off if GNT_WL = 0" for non-shared-antenna
2186 * disable 0x1c30[22] = 0,
2187 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1
2188 *
2189 * disable WL-S1 BB chage RF mode if GNT_BT
2190 * since RF TRx mask can do it
2191 */
2192 rtw_write8_mask(rtwdev, REG_ANAPAR + 2, BIT_ANAPAR_BTPS >> 16, 1);
2193 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 1, BIT_DAC_OFF_ENABLE, 0);
2194 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 3, BIT_DAC_OFF_ENABLE, 1);
2195 rtw_write8_mask(rtwdev, REG_IGN_GNTBT4, BIT_PI_IGNORE_GNT_BT, 1);
2196
2197 /* disable WL-S0 BB chage RF mode if wifi is at 5G,
2198 * or antenna path is separated
2199 */
2200 if (coex_stat->wl_coex_mode == COEX_WLINK_5G ||
2201 coex->under_5g || !efuse->share_ant) {
2202 if (coex_stat->kt_ver >= 3) {
2203 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
2204 BIT_PI_IGNORE_GNT_BT, 0);
2205 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
2206 BIT_NOMASK_TXBT_ENABLE, 1);
2207 } else {
2208 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
2209 BIT_PI_IGNORE_GNT_BT, 1);
2210 }
2211 } else {
2212 /* shared-antenna */
2213 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
2214 BIT_PI_IGNORE_GNT_BT, 0);
2215 if (coex_stat->kt_ver >= 3) {
2216 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
2217 BIT_NOMASK_TXBT_ENABLE, 0);
2218 }
2219 }
2220 }
2221
2222 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
2223 {
2224 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
2225 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
2226 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
2227 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
2228 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
2229 }
2230
2231 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
2232 {
2233 struct rtw_coex *coex = &rtwdev->coex;
2234 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
2235 struct rtw_efuse *efuse = &rtwdev->efuse;
2236
2237 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
2238 coex_rfe->ant_switch_polarity = 0;
2239 coex_rfe->ant_switch_exist = false;
2240 coex_rfe->ant_switch_with_bt = false;
2241 coex_rfe->ant_switch_diversity = false;
2242
2243 if (efuse->share_ant)
2244 coex_rfe->wlg_at_btg = true;
2245 else
2246 coex_rfe->wlg_at_btg = false;
2247
2248 /* disable LTE coex in wifi side */
2249 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
2250 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
2251 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
2252 }
2253
2254 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
2255 {
2256 struct rtw_coex *coex = &rtwdev->coex;
2257 struct rtw_coex_dm *coex_dm = &coex->dm;
2258
2259 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
2260 return;
2261
2262 coex_dm->cur_wl_pwr_lvl = wl_pwr;
2263 }
2264
2265 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
2266 {
2267 struct rtw_coex *coex = &rtwdev->coex;
2268 struct rtw_coex_dm *coex_dm = &coex->dm;
2269
2270 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
2271 return;
2272
2273 coex_dm->cur_wl_rx_low_gain_en = low_gain;
2274
2275 if (coex_dm->cur_wl_rx_low_gain_en) {
2276 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
2277
2278 /* set Rx filter corner RCK offset */
2279 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22);
2280 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36);
2281 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22);
2282 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36);
2283
2284 } else {
2285 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
2286
2287 /* set Rx filter corner RCK offset */
2288 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20);
2289 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0);
2290 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20);
2291 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0);
2292 }
2293 }
2294
2295 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev,
2296 struct rtw_vif *vif,
2297 struct rtw_bfee *bfee)
2298 {
2299 u8 csi_rsc = 0;
2300 u32 tmp6dc;
2301
2302 rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
2303
2304 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
2305 BIT_WMAC_USE_NDPARATE |
2306 (csi_rsc << 13);
2307 if (vif->net_type == RTW_NET_AP_MODE)
2308 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12));
2309 else
2310 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12));
2311
2312 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550);
2313 }
2314
2315 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev,
2316 struct rtw_vif *vif,
2317 struct rtw_bfee *bfee, bool enable)
2318 {
2319 if (enable)
2320 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee);
2321 else
2322 rtw_bf_remove_bfee_su(rtwdev, bfee);
2323 }
2324
2325 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
2326 struct rtw_vif *vif,
2327 struct rtw_bfee *bfee, bool enable)
2328 {
2329 if (enable)
2330 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
2331 else
2332 rtw_bf_remove_bfee_mu(rtwdev, bfee);
2333 }
2334
2335 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
2336 struct rtw_bfee *bfee, bool enable)
2337 {
2338 if (bfee->role == RTW_BFEE_SU)
2339 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
2340 else if (bfee->role == RTW_BFEE_MU)
2341 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
2342 else
2343 rtw_warn(rtwdev, "wrong bfee role\n");
2344 }
2345
2346 struct dpk_cfg_pair {
2347 u32 addr;
2348 u32 bitmask;
2349 u32 data;
2350 };
2351
2352 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
2353 const struct rtw_table *tbl)
2354 {
2355 const struct dpk_cfg_pair *p = tbl->data;
2356 const struct dpk_cfg_pair *end = p + tbl->size / 3;
2357
2358 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3);
2359
2360 for (; p < end; p++)
2361 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data);
2362 }
2363
2364 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k)
2365 {
2366 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2367
2368 if (is_before_k) {
2369 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
2370 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
2371 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1);
2372 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77);
2373 } else {
2374 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD,
2375 dpk_info->gnt_value);
2376 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
2377 }
2378 }
2379
2380 static void
2381 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num,
2382 struct rtw_backup_info *bckp)
2383 {
2384 rtw_restore_reg(rtwdev, bckp, reg_num);
2385 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2386 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4);
2387 }
2388
2389 static void
2390 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg,
2391 u32 reg_num, struct rtw_backup_info *bckp)
2392 {
2393 u32 i;
2394
2395 for (i = 0; i < reg_num; i++) {
2396 bckp[i].len = 4;
2397 bckp[i].reg = reg[i];
2398 bckp[i].val = rtw_read32(rtwdev, reg[i]);
2399 }
2400 }
2401
2402 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev,
2403 u32 *rf_reg,
2404 u32 rf_reg_bak[][2])
2405 {
2406 u32 i;
2407
2408 for (i = 0; i < DPK_RF_REG_NUM; i++) {
2409 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A,
2410 rf_reg[i], RFREG_MASK);
2411 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B,
2412 rf_reg[i], RFREG_MASK);
2413 }
2414 }
2415
2416 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev,
2417 u32 *rf_reg,
2418 u32 rf_reg_bak[][2])
2419 {
2420 u32 i;
2421
2422 for (i = 0; i < DPK_RF_REG_NUM; i++) {
2423 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK,
2424 rf_reg_bak[i][RF_PATH_A]);
2425 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK,
2426 rf_reg_bak[i][RF_PATH_B]);
2427 }
2428 }
2429
2430 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev)
2431 {
2432 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2433 u32 reg;
2434 u8 band_shift;
2435
2436 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
2437
2438 band_shift = FIELD_GET(BIT(16), reg);
2439 dpk_info->dpk_band = 1 << band_shift;
2440 dpk_info->dpk_ch = FIELD_GET(0xff, reg);
2441 dpk_info->dpk_bw = FIELD_GET(0x3000, reg);
2442 }
2443
2444 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path)
2445 {
2446 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
2447 udelay(5);
2448 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801);
2449 usleep_range(600, 610);
2450 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
2451 }
2452
2453 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path)
2454 {
2455 u16 dc_i, dc_q;
2456 u8 corr_idx;
2457
2458 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0);
2459 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
2460 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
2461
2462 if (dc_i & BIT(11))
2463 dc_i = 0x1000 - dc_i;
2464 if (dc_q & BIT(11))
2465 dc_q = 0x1000 - dc_q;
2466
2467 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2468 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
2469 rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
2470
2471 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65)
2472 return 1;
2473 else
2474 return 0;
2475
2476 }
2477
2478 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev)
2479 {
2480 u8 reg_a, reg_b;
2481 u16 count = 0;
2482
2483 rtw_write8(rtwdev, 0x522, 0xff);
2484 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2);
2485
2486 do {
2487 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000);
2488 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000);
2489 udelay(2);
2490 count++;
2491 } while ((reg_a == 2 || reg_b == 2) && count < 2500);
2492 }
2493
2494 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev)
2495 {
2496 rtw8822c_dpk_tx_pause(rtwdev);
2497 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl);
2498 }
2499
2500 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk)
2501 {
2502 if (is_do_dpk)
2503 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl);
2504 else
2505 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl);
2506 }
2507
2508 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev)
2509 {
2510 u8 path;
2511
2512 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
2513 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
2514 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
2515 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)
2516 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
2517 else
2518 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
2519 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);
2520 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);
2521 }
2522 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2523 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b);
2524 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347);
2525 }
2526
2527 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path)
2528 {
2529 u32 ori_txbb;
2530
2531 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017);
2532 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK);
2533
2534 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
2535 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
2536 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0);
2537 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb);
2538
2539 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {
2540 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1);
2541 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
2542 } else {
2543 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
2544 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6);
2545 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
2546 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0);
2547 }
2548
2549 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
2550 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
2551 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
2552
2553 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80)
2554 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2);
2555 else
2556 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
2557
2558 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1);
2559
2560 usleep_range(100, 110);
2561
2562 return ori_txbb & 0x1f;
2563 }
2564
2565 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path)
2566 {
2567 u16 cmd;
2568 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
2569
2570 switch (action) {
2571 case RTW_DPK_GAIN_LOSS:
2572 cmd = 0x14 + path;
2573 break;
2574 case RTW_DPK_DO_DPK:
2575 cmd = 0x16 + path + bw;
2576 break;
2577 case RTW_DPK_DPK_ON:
2578 cmd = 0x1a + path;
2579 break;
2580 case RTW_DPK_DAGC:
2581 cmd = 0x1c + path + bw;
2582 break;
2583 default:
2584 return 0;
2585 }
2586
2587 return (cmd << 8) | 0x48;
2588 }
2589
2590 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action)
2591 {
2592 u16 dpk_cmd;
2593 u8 result = 0;
2594
2595 rtw8822c_dpk_set_gnt_wl(rtwdev, true);
2596
2597 if (action == RTW_DPK_CAL_PWR) {
2598 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1);
2599 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0);
2600 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
2601 msleep(10);
2602 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) {
2603 result = 1;
2604 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
2605 }
2606 } else {
2607 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2608 0x8 | (path << 1));
2609 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
2610
2611 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path);
2612 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd);
2613 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1);
2614 msleep(10);
2615 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) {
2616 result = 1;
2617 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
2618 }
2619 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2620 0x8 | (path << 1));
2621 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
2622 }
2623
2624 rtw8822c_dpk_set_gnt_wl(rtwdev, false);
2625
2626 rtw_write8(rtwdev, 0x1b10, 0x0);
2627
2628 return result;
2629 }
2630
2631 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path)
2632 {
2633 u16 dgain;
2634
2635 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2636 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0);
2637
2638 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
2639
2640 return dgain;
2641 }
2642
2643 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path)
2644 {
2645 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
2646 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0);
2647 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
2648 udelay(15);
2649
2650 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e);
2651 }
2652
2653 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path)
2654 {
2655 u32 i_val, q_val;
2656
2657 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
2658 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
2659 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001);
2660 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
2661 rtw_write32(rtwdev, 0x1b4c, 0x00080000);
2662
2663 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD);
2664 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD);
2665
2666 if (i_val & BIT(15))
2667 i_val = 0x10000 - i_val;
2668 if (q_val & BIT(15))
2669 q_val = 0x10000 - q_val;
2670
2671 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
2672
2673 return i_val * i_val + q_val * q_val;
2674 }
2675
2676 static u32 rtw8822c_psd_log2base(u32 val)
2677 {
2678 u32 tmp, val_integerd_b, tindex;
2679 u32 result, val_fractiond_b;
2680 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174,
2681 151, 132, 115, 100, 86, 74, 62, 51,
2682 42, 32, 23, 15, 7, 0};
2683
2684 if (val == 0)
2685 return 0;
2686
2687 val_integerd_b = __fls(val) + 1;
2688
2689 tmp = (val * 100) / (1 << val_integerd_b);
2690 tindex = tmp / 5;
2691
2692 if (tindex >= ARRAY_SIZE(table_fraction))
2693 tindex = ARRAY_SIZE(table_fraction) - 1;
2694
2695 val_fractiond_b = table_fraction[tindex];
2696
2697 result = val_integerd_b * 100 - val_fractiond_b;
2698
2699 return result;
2700 }
2701
2702 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path)
2703 {
2704 u8 result;
2705
2706 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2707 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1);
2708 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000);
2709
2710 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0);
2711
2712 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
2713
2714 return result;
2715 }
2716
2717 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path,
2718 u8 limited_pga)
2719 {
2720 u8 result = 0;
2721 u16 dgain;
2722
2723 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
2724 dgain = rtw8822c_dpk_dgain_read(rtwdev, path);
2725
2726 if (dgain > 1535 && !limited_pga)
2727 return RTW_DPK_GAIN_LESS;
2728 else if (dgain < 768 && !limited_pga)
2729 return RTW_DPK_GAIN_LARGE;
2730 else
2731 return result;
2732 }
2733
2734 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path)
2735 {
2736 u32 loss, loss_db;
2737
2738 loss = rtw8822c_dpk_pas_read(rtwdev, path);
2739 if (loss < 0x4000000)
2740 return RTW_DPK_GL_LESS;
2741 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870;
2742
2743 if (loss_db > 1000)
2744 return RTW_DPK_GL_LARGE;
2745 else if (loss_db < 250)
2746 return RTW_DPK_GL_LESS;
2747 else
2748 return RTW_DPK_AGC_OUT;
2749 }
2750
2751 struct rtw8822c_dpk_data {
2752 u8 txbb;
2753 u8 pga;
2754 u8 limited_pga;
2755 u8 agc_cnt;
2756 bool loss_only;
2757 bool gain_only;
2758 u8 path;
2759 };
2760
2761 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev,
2762 struct rtw8822c_dpk_data *data)
2763 {
2764 u8 state;
2765
2766 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN,
2767 BIT_GAIN_TXBB);
2768 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC,
2769 BIT_RXAGC);
2770
2771 if (data->loss_only) {
2772 state = RTW_DPK_LOSS_CHECK;
2773 goto check_end;
2774 }
2775
2776 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path,
2777 data->limited_pga);
2778 if (state == RTW_DPK_GAIN_CHECK && data->gain_only)
2779 state = RTW_DPK_AGC_OUT;
2780 else if (state == RTW_DPK_GAIN_CHECK)
2781 state = RTW_DPK_LOSS_CHECK;
2782
2783 check_end:
2784 data->agc_cnt++;
2785 if (data->agc_cnt >= 6)
2786 state = RTW_DPK_AGC_OUT;
2787
2788 return state;
2789 }
2790
2791 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev,
2792 struct rtw8822c_dpk_data *data)
2793 {
2794 u8 pga = data->pga;
2795
2796 if (pga > 0xe)
2797 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
2798 else if (pga > 0xb && pga < 0xf)
2799 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
2800 else if (pga < 0xc)
2801 data->limited_pga = 1;
2802
2803 return RTW_DPK_GAIN_CHECK;
2804 }
2805
2806 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev,
2807 struct rtw8822c_dpk_data *data)
2808 {
2809 u8 pga = data->pga;
2810
2811 if (pga < 0xc)
2812 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
2813 else if (pga > 0xb && pga < 0xf)
2814 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
2815 else if (pga > 0xe)
2816 data->limited_pga = 1;
2817
2818 return RTW_DPK_GAIN_CHECK;
2819 }
2820
2821 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev,
2822 struct rtw8822c_dpk_data *data, u8 is_large)
2823 {
2824 u8 txbb_bound[] = {0x1f, 0};
2825
2826 if (data->txbb == txbb_bound[is_large])
2827 return RTW_DPK_AGC_OUT;
2828
2829 if (is_large == 1)
2830 data->txbb -= 2;
2831 else
2832 data->txbb += 3;
2833
2834 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb);
2835 data->limited_pga = 0;
2836
2837 return RTW_DPK_GAIN_CHECK;
2838 }
2839
2840 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev,
2841 struct rtw8822c_dpk_data *data)
2842 {
2843 return rtw8822c_gl_state(rtwdev, data, 1);
2844 }
2845
2846 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev,
2847 struct rtw8822c_dpk_data *data)
2848 {
2849 return rtw8822c_gl_state(rtwdev, data, 0);
2850 }
2851
2852 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev,
2853 struct rtw8822c_dpk_data *data)
2854 {
2855 u8 path = data->path;
2856 u8 state;
2857
2858 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS);
2859 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path);
2860
2861 return state;
2862 }
2863
2864 static u8 (*dpk_state[])(struct rtw_dev *rtwdev,
2865 struct rtw8822c_dpk_data *data) = {
2866 rtw8822c_gain_check_state, rtw8822c_gain_large_state,
2867 rtw8822c_gain_less_state, rtw8822c_gl_large_state,
2868 rtw8822c_gl_less_state, rtw8822c_loss_check_state };
2869
2870 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path,
2871 bool gain_only, bool loss_only)
2872 {
2873 struct rtw8822c_dpk_data data = {0};
2874 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data);
2875 u8 state = RTW_DPK_GAIN_CHECK;
2876
2877 data.loss_only = loss_only;
2878 data.gain_only = gain_only;
2879 data.path = path;
2880
2881 for (;;) {
2882 func = dpk_state[state];
2883 state = func(rtwdev, &data);
2884 if (state == RTW_DPK_AGC_OUT)
2885 break;
2886 }
2887
2888 return data.txbb;
2889 }
2890
2891 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev,
2892 u16 coef_i, u16 coef_q)
2893 {
2894 if (coef_i == 0x1000 || coef_i == 0x0fff ||
2895 coef_q == 0x1000 || coef_q == 0x0fff)
2896 return true;
2897
2898 return false;
2899 }
2900
2901 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev)
2902 {
2903 u32 reg = 0;
2904 u16 coef_i = 0, coef_q = 0;
2905
2906 reg = rtw_read32(rtwdev, REG_STAT_RPT);
2907
2908 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff;
2909 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff;
2910
2911 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1;
2912
2913 reg = (coef_i << 16) | coef_q;
2914
2915 return reg;
2916 }
2917
2918 static const u32 rtw8822c_dpk_get_coef_tbl[] = {
2919 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0,
2920 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0,
2921 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0,
2922 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0,
2923 };
2924
2925 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path)
2926 {
2927 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2928 int i;
2929
2930 for (i = 0; i < 20; i++) {
2931 rtw_write32(rtwdev, REG_RXSRAM_CTL,
2932 rtw8822c_dpk_get_coef_tbl[i]);
2933 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev);
2934 }
2935 }
2936
2937 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path)
2938 {
2939 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
2940
2941 if (path == RF_PATH_A) {
2942 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0);
2943 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080);
2944 } else if (path == RF_PATH_B) {
2945 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1);
2946 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080);
2947 }
2948
2949 rtw8822c_dpk_coef_tbl_apply(rtwdev, path);
2950 }
2951
2952 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path)
2953 {
2954 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2955 u8 addr, result = 1;
2956 u16 coef_i, coef_q;
2957
2958 for (addr = 0; addr < 20; addr++) {
2959 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]);
2960 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]);
2961
2962 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) {
2963 result = 0;
2964 break;
2965 }
2966 }
2967 return result;
2968 }
2969
2970 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result)
2971 {
2972 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2973 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64};
2974 u32 coef;
2975 u8 addr;
2976
2977 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
2978 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2979
2980 for (addr = 0; addr < 20; addr++) {
2981 if (result == 0) {
2982 if (addr == 3)
2983 coef = 0x04001fff;
2984 else
2985 coef = 0x00001fff;
2986 } else {
2987 coef = dpk_info->coef[path][addr];
2988 }
2989 rtw_write32(rtwdev, reg[path] + addr * 4, coef);
2990 }
2991 }
2992
2993 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc,
2994 u8 path, u8 result)
2995 {
2996 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2997
2998 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2999
3000 if (result)
3001 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6));
3002 else
3003 rtw_write8(rtwdev, REG_DPD_AGC, 0x00);
3004
3005 dpk_info->result[path] = result;
3006 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC);
3007
3008 rtw8822c_dpk_coef_write(rtwdev, path, result);
3009 }
3010
3011 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path)
3012 {
3013 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3014 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2;
3015
3016 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path);
3017 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC);
3018
3019 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3020 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3021 rtw8822c_dpk_dgain_read(rtwdev, path);
3022
3023 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) {
3024 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3025 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3026 rtw8822c_dpk_dc_corr_check(rtwdev, path);
3027 }
3028
3029 t1 = rtw8822c_dpk_thermal_read(rtwdev, path);
3030 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true);
3031 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path);
3032
3033 if (tx_bb < tx_agc_search)
3034 tx_bb = 0;
3035 else
3036 tx_bb = tx_bb - tx_agc_search;
3037
3038 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb);
3039
3040 tx_agc = ori_txagc - (ori_txbb - tx_bb);
3041
3042 t2 = rtw8822c_dpk_thermal_read(rtwdev, path);
3043
3044 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1);
3045
3046 return tx_agc;
3047 }
3048
3049 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path)
3050 {
3051 u8 result;
3052
3053 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK);
3054
3055 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3056
3057 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26));
3058
3059 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14);
3060
3061 rtw8822c_dpk_get_coef(rtwdev, path);
3062
3063 return result;
3064 }
3065
3066 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path)
3067 {
3068 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3069 u32 tmp_gs = 0;
3070
3071 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3072 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0);
3073 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3074 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3075 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1);
3076 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3077 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf);
3078
3079 if (path == RF_PATH_A) {
3080 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
3081 0x1066680);
3082 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1);
3083 } else {
3084 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
3085 0x1066680);
3086 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1);
3087 }
3088
3089 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) {
3090 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310);
3091 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310);
3092 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db);
3093 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db);
3094 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3095 rtw_write32(rtwdev, REG_DPD_CTL15,
3096 0x05020000 | (BIT(path) << 28));
3097 } else {
3098 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c);
3099 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c);
3100 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14);
3101 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14);
3102 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3103 rtw_write32(rtwdev, REG_DPD_CTL15,
3104 0x05020008 | (BIT(path) << 28));
3105 }
3106
3107 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path);
3108
3109 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR);
3110
3111 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0);
3112 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3113 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3114 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0);
3115 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3116
3117 if (path == RF_PATH_A)
3118 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b);
3119 else
3120 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b);
3121
3122 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3123
3124 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN);
3125 tmp_gs = (tmp_gs * 910) >> 10;
3126 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10);
3127
3128 if (path == RF_PATH_A)
3129 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs);
3130 else
3131 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs);
3132
3133 dpk_info->dpk_gs[path] = tmp_gs;
3134 }
3135
3136 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev)
3137 {
3138 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3139 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58};
3140 u32 i_scaling;
3141 u8 path;
3142
3143 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3144 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3145 rtw_write32(rtwdev, REG_NCTL0, 0x00001148);
3146 rtw_write32(rtwdev, REG_NCTL0, 0x00001149);
3147
3148 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55);
3149
3150 rtw_write8(rtwdev, 0x1b10, 0x0);
3151 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3152
3153 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3154 i_scaling = 0x16c00 / dpk_info->dpk_gs[path];
3155
3156 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD,
3157 i_scaling);
3158 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3159 GENMASK(31, 28), 0x9);
3160 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3161 GENMASK(31, 28), 0x1);
3162 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3163 GENMASK(31, 28), 0x0);
3164 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path],
3165 BIT(14), 0x0);
3166 }
3167 }
3168
3169 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path)
3170 {
3171 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3172
3173 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
3174
3175 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3176 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3177
3178 if (test_bit(path, dpk_info->dpk_path_ok))
3179 rtw8822c_dpk_cal_gs(rtwdev, path);
3180 }
3181
3182 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail,
3183 u32 dpk_txagc, u8 path)
3184 {
3185 bool result;
3186
3187 if (!is_fail) {
3188 if (rtw8822c_dpk_coef_read(rtwdev, path))
3189 result = true;
3190 else
3191 result = false;
3192 } else {
3193 result = false;
3194 }
3195
3196 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result);
3197
3198 return result;
3199 }
3200
3201 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev)
3202 {
3203 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3204 u8 path;
3205
3206 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3207 clear_bit(path, dpk_info->dpk_path_ok);
3208 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3209 0x8 | (path << 1));
3210 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0);
3211
3212 dpk_info->dpk_txagc[path] = 0;
3213 dpk_info->result[path] = 0;
3214 dpk_info->dpk_gs[path] = 0x5b;
3215 dpk_info->pre_pwsf[path] = 0;
3216 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev,
3217 path);
3218 }
3219 }
3220
3221 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path)
3222 {
3223 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3224 u32 dpk_txagc;
3225 u8 dpk_fail;
3226
3227 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path);
3228
3229 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path);
3230
3231 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path);
3232
3233 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path))
3234 rtw_err(rtwdev, "failed to do dpk calibration\n");
3235
3236 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path);
3237
3238 if (dpk_info->result[path])
3239 set_bit(path, dpk_info->dpk_path_ok);
3240 }
3241
3242 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev)
3243 {
3244 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A);
3245 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B);
3246 rtw8822c_dpk_on(rtwdev, RF_PATH_A);
3247 rtw8822c_dpk_on(rtwdev, RF_PATH_B);
3248 rtw8822c_dpk_cal_coef1(rtwdev);
3249 }
3250
3251 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev)
3252 {
3253 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3254 u32 mask = BIT(15) | BIT(14);
3255
3256 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3257
3258 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN,
3259 dpk_info->is_dpk_pwr_on);
3260 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN,
3261 dpk_info->is_dpk_pwr_on);
3262
3263 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) {
3264 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0);
3265 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]);
3266 }
3267 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) {
3268 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0);
3269 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]);
3270 }
3271 }
3272
3273 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev)
3274 {
3275 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3276 u8 path;
3277
3278 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) &&
3279 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) &&
3280 dpk_info->dpk_ch == 0)
3281 return;
3282
3283 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3284 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3285 0x8 | (path << 1));
3286 if (dpk_info->dpk_band == RTW_BAND_2G)
3287 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
3288 else
3289 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
3290
3291 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);
3292
3293 rtw8822c_dpk_coef_write(rtwdev, path,
3294 test_bit(path, dpk_info->dpk_path_ok));
3295
3296 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
3297
3298 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3299
3300 if (path == RF_PATH_A)
3301 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
3302 dpk_info->dpk_gs[path]);
3303 else
3304 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
3305 dpk_info->dpk_gs[path]);
3306 }
3307 rtw8822c_dpk_cal_coef1(rtwdev);
3308 }
3309
3310 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev)
3311 {
3312 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3313 u8 channel;
3314
3315 dpk_info->is_reload = false;
3316
3317 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff);
3318
3319 if (channel == dpk_info->dpk_ch) {
3320 rtw_dbg(rtwdev, RTW_DBG_RFK,
3321 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch);
3322 rtw8822c_dpk_reload_data(rtwdev);
3323 dpk_info->is_reload = true;
3324 }
3325
3326 return dpk_info->is_reload;
3327 }
3328
3329 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev)
3330 {
3331 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3332 struct rtw_backup_info bckp[DPK_BB_REG_NUM];
3333 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM];
3334 u32 bb_reg[DPK_BB_REG_NUM] = {
3335 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864,
3336 0x4164, 0x180c, 0x410c, 0x186c, 0x416c,
3337 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4};
3338 u32 rf_reg[DPK_RF_REG_NUM] = {
3339 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde};
3340 u8 path;
3341
3342 if (!dpk_info->is_dpk_pwr_on) {
3343 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n");
3344 return;
3345 } else if (rtw8822c_dpk_reload(rtwdev)) {
3346 return;
3347 }
3348
3349 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++)
3350 ewma_thermal_init(&dpk_info->avg_thermal[path]);
3351
3352 rtw8822c_dpk_information(rtwdev);
3353
3354 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp);
3355 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup);
3356
3357 rtw8822c_dpk_mac_bb_setting(rtwdev);
3358 rtw8822c_dpk_afe_setting(rtwdev, true);
3359 rtw8822c_dpk_pre_setting(rtwdev);
3360 rtw8822c_dpk_result_reset(rtwdev);
3361 rtw8822c_dpk_path_select(rtwdev);
3362 rtw8822c_dpk_afe_setting(rtwdev, false);
3363 rtw8822c_dpk_enable_disable(rtwdev);
3364
3365 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup);
3366 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
3367 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3368 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp);
3369 }
3370
3371 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev)
3372 {
3373 rtw8822c_do_iqk(rtwdev);
3374 rtw8822c_do_dpk(rtwdev);
3375 }
3376
3377 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev)
3378 {
3379 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3380 u8 path;
3381 u8 thermal_value[DPK_RF_PATH_NUM] = {0};
3382 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM];
3383
3384 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0)
3385 return;
3386
3387 for (path = 0; path < DPK_RF_PATH_NUM; path++) {
3388 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path);
3389 ewma_thermal_add(&dpk_info->avg_thermal[path],
3390 thermal_value[path]);
3391 thermal_value[path] =
3392 ewma_thermal_read(&dpk_info->avg_thermal[path]);
3393 delta_dpk[path] = dpk_info->thermal_dpk[path] -
3394 thermal_value[path];
3395 offset[path] = delta_dpk[path] -
3396 dpk_info->thermal_dpk_delta[path];
3397 offset[path] &= 0x7f;
3398
3399 if (offset[path] != dpk_info->pre_pwsf[path]) {
3400 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3401 0x8 | (path << 1));
3402 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0),
3403 offset[path]);
3404 dpk_info->pre_pwsf[path] = offset[path];
3405 }
3406 }
3407 }
3408
3409 static const struct rtw_phy_cck_pd_reg
3410 rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = {
3411 {
3412 {0x1ac8, 0x00ff, 0x1ad0, 0x01f},
3413 {0x1ac8, 0xff00, 0x1ad0, 0x3e0}
3414 },
3415 {
3416 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000},
3417 {0x1acc, 0xff00, 0x1ad0, 0x3E000000}
3418 },
3419 };
3420
3421 #define RTW_CCK_PD_MAX 255
3422 #define RTW_CCK_CS_MAX 31
3423 #define RTW_CCK_CS_ERR1 27
3424 #define RTW_CCK_CS_ERR2 29
3425 static void
3426 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev,
3427 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx)
3428 {
3429 u32 pd, cs;
3430
3431 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX))
3432 return;
3433
3434 pd = rtw_read32_mask(rtwdev,
3435 rtw8822c_cck_pd_reg[bw][nrx].reg_pd,
3436 rtw8822c_cck_pd_reg[bw][nrx].mask_pd);
3437 cs = rtw_read32_mask(rtwdev,
3438 rtw8822c_cck_pd_reg[bw][nrx].reg_cs,
3439 rtw8822c_cck_pd_reg[bw][nrx].mask_cs);
3440 pd += pd_diff;
3441 cs += cs_diff;
3442 if (pd > RTW_CCK_PD_MAX)
3443 pd = RTW_CCK_PD_MAX;
3444 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2)
3445 cs++;
3446 else if (cs > RTW_CCK_CS_MAX)
3447 cs = RTW_CCK_CS_MAX;
3448 rtw_write32_mask(rtwdev,
3449 rtw8822c_cck_pd_reg[bw][nrx].reg_pd,
3450 rtw8822c_cck_pd_reg[bw][nrx].mask_pd,
3451 pd);
3452 rtw_write32_mask(rtwdev,
3453 rtw8822c_cck_pd_reg[bw][nrx].reg_cs,
3454 rtw8822c_cck_pd_reg[bw][nrx].mask_cs,
3455 cs);
3456
3457 rtw_dbg(rtwdev, RTW_DBG_PHY,
3458 "is_linked=%d, bw=%d, nrx=%d, cs_ratio=0x%x, pd_th=0x%x\n",
3459 rtw_is_assoc(rtwdev), bw, nrx, cs, pd);
3460 }
3461
3462 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
3463 {
3464 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3465 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8};
3466 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4};
3467 u8 cur_lvl;
3468 u8 nrx, bw;
3469
3470 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000);
3471 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc);
3472
3473 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d) bw=%d nr=%d cck_fa_avg=%d\n",
3474 dm_info->cck_pd_lv[bw][nrx], new_lvl, bw, nrx,
3475 dm_info->cck_fa_avg);
3476
3477 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl)
3478 return;
3479
3480 cur_lvl = dm_info->cck_pd_lv[bw][nrx];
3481
3482 /* update cck pd info */
3483 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
3484
3485 rtw8822c_phy_cck_pd_set_reg(rtwdev,
3486 pd_lvl[new_lvl] - pd_lvl[cur_lvl],
3487 cs_lvl[new_lvl] - cs_lvl[cur_lvl],
3488 bw, nrx);
3489 dm_info->cck_pd_lv[bw][nrx] = new_lvl;
3490 }
3491
3492 #define PWR_TRACK_MASK 0x7f
3493 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path)
3494 {
3495 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3496
3497 switch (rf_path) {
3498 case RF_PATH_A:
3499 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK,
3500 dm_info->delta_power_index[rf_path]);
3501 break;
3502 case RF_PATH_B:
3503 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK,
3504 dm_info->delta_power_index[rf_path]);
3505 break;
3506 default:
3507 break;
3508 }
3509 }
3510
3511 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev,
3512 struct rtw_swing_table *swing_table,
3513 u8 path)
3514 {
3515 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3516 u8 thermal_value, delta;
3517
3518 if (rtwdev->efuse.thermal_meter[path] == 0xff)
3519 return;
3520
3521 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e);
3522
3523 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path);
3524
3525 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path);
3526
3527 dm_info->delta_power_index[path] =
3528 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path,
3529 delta);
3530
3531 rtw8822c_pwrtrack_set(rtwdev, path);
3532 }
3533
3534 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev)
3535 {
3536 struct rtw_swing_table swing_table;
3537 u8 i;
3538
3539 rtw_phy_config_swing_table(rtwdev, &swing_table);
3540
3541 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
3542 rtw8822c_pwr_track_path(rtwdev, &swing_table, i);
3543
3544 if (rtw_phy_pwrtrack_need_iqk(rtwdev))
3545 rtw8822c_do_iqk(rtwdev);
3546 }
3547
3548 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev)
3549 {
3550 struct rtw_efuse *efuse = &rtwdev->efuse;
3551 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3552
3553 if (efuse->power_track_type != 0)
3554 return;
3555
3556 if (!dm_info->pwr_trk_triggered) {
3557 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
3558 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00);
3559 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
3560
3561 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
3562 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00);
3563 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
3564
3565 dm_info->pwr_trk_triggered = true;
3566 return;
3567 }
3568
3569 __rtw8822c_pwr_track(rtwdev);
3570 dm_info->pwr_trk_triggered = false;
3571 }
3572
3573 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = {
3574 {0x0086,
3575 RTW_PWR_CUT_ALL_MSK,
3576 RTW_PWR_INTF_SDIO_MSK,
3577 RTW_PWR_ADDR_SDIO,
3578 RTW_PWR_CMD_WRITE, BIT(0), 0},
3579 {0x0086,
3580 RTW_PWR_CUT_ALL_MSK,
3581 RTW_PWR_INTF_SDIO_MSK,
3582 RTW_PWR_ADDR_SDIO,
3583 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
3584 {0x002E,
3585 RTW_PWR_CUT_ALL_MSK,
3586 RTW_PWR_INTF_ALL_MSK,
3587 RTW_PWR_ADDR_MAC,
3588 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3589 {0x002D,
3590 RTW_PWR_CUT_ALL_MSK,
3591 RTW_PWR_INTF_ALL_MSK,
3592 RTW_PWR_ADDR_MAC,
3593 RTW_PWR_CMD_WRITE, BIT(0), 0},
3594 {0x007F,
3595 RTW_PWR_CUT_ALL_MSK,
3596 RTW_PWR_INTF_ALL_MSK,
3597 RTW_PWR_ADDR_MAC,
3598 RTW_PWR_CMD_WRITE, BIT(7), 0},
3599 {0x004A,
3600 RTW_PWR_CUT_ALL_MSK,
3601 RTW_PWR_INTF_USB_MSK,
3602 RTW_PWR_ADDR_MAC,
3603 RTW_PWR_CMD_WRITE, BIT(0), 0},
3604 {0x0005,
3605 RTW_PWR_CUT_ALL_MSK,
3606 RTW_PWR_INTF_ALL_MSK,
3607 RTW_PWR_ADDR_MAC,
3608 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
3609 {0xFFFF,
3610 RTW_PWR_CUT_ALL_MSK,
3611 RTW_PWR_INTF_ALL_MSK,
3612 0,
3613 RTW_PWR_CMD_END, 0, 0},
3614 };
3615
3616 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = {
3617 {0x0000,
3618 RTW_PWR_CUT_ALL_MSK,
3619 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3620 RTW_PWR_ADDR_MAC,
3621 RTW_PWR_CMD_WRITE, BIT(5), 0},
3622 {0x0005,
3623 RTW_PWR_CUT_ALL_MSK,
3624 RTW_PWR_INTF_ALL_MSK,
3625 RTW_PWR_ADDR_MAC,
3626 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
3627 {0x0075,
3628 RTW_PWR_CUT_ALL_MSK,
3629 RTW_PWR_INTF_PCI_MSK,
3630 RTW_PWR_ADDR_MAC,
3631 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3632 {0x0006,
3633 RTW_PWR_CUT_ALL_MSK,
3634 RTW_PWR_INTF_ALL_MSK,
3635 RTW_PWR_ADDR_MAC,
3636 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
3637 {0x0075,
3638 RTW_PWR_CUT_ALL_MSK,
3639 RTW_PWR_INTF_PCI_MSK,
3640 RTW_PWR_ADDR_MAC,
3641 RTW_PWR_CMD_WRITE, BIT(0), 0},
3642 {0xFF1A,
3643 RTW_PWR_CUT_ALL_MSK,
3644 RTW_PWR_INTF_USB_MSK,
3645 RTW_PWR_ADDR_MAC,
3646 RTW_PWR_CMD_WRITE, 0xFF, 0},
3647 {0x002E,
3648 RTW_PWR_CUT_ALL_MSK,
3649 RTW_PWR_INTF_ALL_MSK,
3650 RTW_PWR_ADDR_MAC,
3651 RTW_PWR_CMD_WRITE, BIT(3), 0},
3652 {0x0006,
3653 RTW_PWR_CUT_ALL_MSK,
3654 RTW_PWR_INTF_ALL_MSK,
3655 RTW_PWR_ADDR_MAC,
3656 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3657 {0x0005,
3658 RTW_PWR_CUT_ALL_MSK,
3659 RTW_PWR_INTF_ALL_MSK,
3660 RTW_PWR_ADDR_MAC,
3661 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
3662 {0x1018,
3663 RTW_PWR_CUT_ALL_MSK,
3664 RTW_PWR_INTF_ALL_MSK,
3665 RTW_PWR_ADDR_MAC,
3666 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3667 {0x0005,
3668 RTW_PWR_CUT_ALL_MSK,
3669 RTW_PWR_INTF_ALL_MSK,
3670 RTW_PWR_ADDR_MAC,
3671 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3672 {0x0005,
3673 RTW_PWR_CUT_ALL_MSK,
3674 RTW_PWR_INTF_ALL_MSK,
3675 RTW_PWR_ADDR_MAC,
3676 RTW_PWR_CMD_POLLING, BIT(0), 0},
3677 {0x0074,
3678 RTW_PWR_CUT_ALL_MSK,
3679 RTW_PWR_INTF_PCI_MSK,
3680 RTW_PWR_ADDR_MAC,
3681 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
3682 {0x0071,
3683 RTW_PWR_CUT_ALL_MSK,
3684 RTW_PWR_INTF_PCI_MSK,
3685 RTW_PWR_ADDR_MAC,
3686 RTW_PWR_CMD_WRITE, BIT(4), 0},
3687 {0x0062,
3688 RTW_PWR_CUT_ALL_MSK,
3689 RTW_PWR_INTF_PCI_MSK,
3690 RTW_PWR_ADDR_MAC,
3691 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
3692 (BIT(7) | BIT(6) | BIT(5))},
3693 {0x0061,
3694 RTW_PWR_CUT_ALL_MSK,
3695 RTW_PWR_INTF_PCI_MSK,
3696 RTW_PWR_ADDR_MAC,
3697 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
3698 {0x001F,
3699 RTW_PWR_CUT_ALL_MSK,
3700 RTW_PWR_INTF_ALL_MSK,
3701 RTW_PWR_ADDR_MAC,
3702 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},
3703 {0x00EF,
3704 RTW_PWR_CUT_ALL_MSK,
3705 RTW_PWR_INTF_ALL_MSK,
3706 RTW_PWR_ADDR_MAC,
3707 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},
3708 {0x1045,
3709 RTW_PWR_CUT_ALL_MSK,
3710 RTW_PWR_INTF_ALL_MSK,
3711 RTW_PWR_ADDR_MAC,
3712 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
3713 {0x0010,
3714 RTW_PWR_CUT_ALL_MSK,
3715 RTW_PWR_INTF_ALL_MSK,
3716 RTW_PWR_ADDR_MAC,
3717 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3718 {0x1064,
3719 RTW_PWR_CUT_ALL_MSK,
3720 RTW_PWR_INTF_ALL_MSK,
3721 RTW_PWR_ADDR_MAC,
3722 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
3723 {0xFFFF,
3724 RTW_PWR_CUT_ALL_MSK,
3725 RTW_PWR_INTF_ALL_MSK,
3726 0,
3727 RTW_PWR_CMD_END, 0, 0},
3728 };
3729
3730 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = {
3731 {0x0093,
3732 RTW_PWR_CUT_ALL_MSK,
3733 RTW_PWR_INTF_ALL_MSK,
3734 RTW_PWR_ADDR_MAC,
3735 RTW_PWR_CMD_WRITE, BIT(3), 0},
3736 {0x001F,
3737 RTW_PWR_CUT_ALL_MSK,
3738 RTW_PWR_INTF_ALL_MSK,
3739 RTW_PWR_ADDR_MAC,
3740 RTW_PWR_CMD_WRITE, 0xFF, 0},
3741 {0x00EF,
3742 RTW_PWR_CUT_ALL_MSK,
3743 RTW_PWR_INTF_ALL_MSK,
3744 RTW_PWR_ADDR_MAC,
3745 RTW_PWR_CMD_WRITE, 0xFF, 0},
3746 {0x1045,
3747 RTW_PWR_CUT_ALL_MSK,
3748 RTW_PWR_INTF_ALL_MSK,
3749 RTW_PWR_ADDR_MAC,
3750 RTW_PWR_CMD_WRITE, BIT(4), 0},
3751 {0xFF1A,
3752 RTW_PWR_CUT_ALL_MSK,
3753 RTW_PWR_INTF_USB_MSK,
3754 RTW_PWR_ADDR_MAC,
3755 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
3756 {0x0049,
3757 RTW_PWR_CUT_ALL_MSK,
3758 RTW_PWR_INTF_ALL_MSK,
3759 RTW_PWR_ADDR_MAC,
3760 RTW_PWR_CMD_WRITE, BIT(1), 0},
3761 {0x0006,
3762 RTW_PWR_CUT_ALL_MSK,
3763 RTW_PWR_INTF_ALL_MSK,
3764 RTW_PWR_ADDR_MAC,
3765 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3766 {0x0002,
3767 RTW_PWR_CUT_ALL_MSK,
3768 RTW_PWR_INTF_ALL_MSK,
3769 RTW_PWR_ADDR_MAC,
3770 RTW_PWR_CMD_WRITE, BIT(1), 0},
3771 {0x0005,
3772 RTW_PWR_CUT_ALL_MSK,
3773 RTW_PWR_INTF_ALL_MSK,
3774 RTW_PWR_ADDR_MAC,
3775 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
3776 {0x0005,
3777 RTW_PWR_CUT_ALL_MSK,
3778 RTW_PWR_INTF_ALL_MSK,
3779 RTW_PWR_ADDR_MAC,
3780 RTW_PWR_CMD_POLLING, BIT(1), 0},
3781 {0x0000,
3782 RTW_PWR_CUT_ALL_MSK,
3783 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3784 RTW_PWR_ADDR_MAC,
3785 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
3786 {0xFFFF,
3787 RTW_PWR_CUT_ALL_MSK,
3788 RTW_PWR_INTF_ALL_MSK,
3789 0,
3790 RTW_PWR_CMD_END, 0, 0},
3791 };
3792
3793 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = {
3794 {0x0005,
3795 RTW_PWR_CUT_ALL_MSK,
3796 RTW_PWR_INTF_SDIO_MSK,
3797 RTW_PWR_ADDR_MAC,
3798 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
3799 {0x0007,
3800 RTW_PWR_CUT_ALL_MSK,
3801 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3802 RTW_PWR_ADDR_MAC,
3803 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
3804 {0x0067,
3805 RTW_PWR_CUT_ALL_MSK,
3806 RTW_PWR_INTF_ALL_MSK,
3807 RTW_PWR_ADDR_MAC,
3808 RTW_PWR_CMD_WRITE, BIT(5), 0},
3809 {0x004A,
3810 RTW_PWR_CUT_ALL_MSK,
3811 RTW_PWR_INTF_USB_MSK,
3812 RTW_PWR_ADDR_MAC,
3813 RTW_PWR_CMD_WRITE, BIT(0), 0},
3814 {0x0081,
3815 RTW_PWR_CUT_ALL_MSK,
3816 RTW_PWR_INTF_ALL_MSK,
3817 RTW_PWR_ADDR_MAC,
3818 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
3819 {0x0090,
3820 RTW_PWR_CUT_ALL_MSK,
3821 RTW_PWR_INTF_ALL_MSK,
3822 RTW_PWR_ADDR_MAC,
3823 RTW_PWR_CMD_WRITE, BIT(1), 0},
3824 {0x0092,
3825 RTW_PWR_CUT_ALL_MSK,
3826 RTW_PWR_INTF_PCI_MSK,
3827 RTW_PWR_ADDR_MAC,
3828 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
3829 {0x0093,
3830 RTW_PWR_CUT_ALL_MSK,
3831 RTW_PWR_INTF_PCI_MSK,
3832 RTW_PWR_ADDR_MAC,
3833 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
3834 {0x0005,
3835 RTW_PWR_CUT_ALL_MSK,
3836 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3837 RTW_PWR_ADDR_MAC,
3838 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
3839 {0x0005,
3840 RTW_PWR_CUT_ALL_MSK,
3841 RTW_PWR_INTF_PCI_MSK,
3842 RTW_PWR_ADDR_MAC,
3843 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3844 {0x0086,
3845 RTW_PWR_CUT_ALL_MSK,
3846 RTW_PWR_INTF_SDIO_MSK,
3847 RTW_PWR_ADDR_SDIO,
3848 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3849 {0xFFFF,
3850 RTW_PWR_CUT_ALL_MSK,
3851 RTW_PWR_INTF_ALL_MSK,
3852 0,
3853 RTW_PWR_CMD_END, 0, 0},
3854 };
3855
3856 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = {
3857 trans_carddis_to_cardemu_8822c,
3858 trans_cardemu_to_act_8822c,
3859 NULL
3860 };
3861
3862 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = {
3863 trans_act_to_cardemu_8822c,
3864 trans_cardemu_to_carddis_8822c,
3865 NULL
3866 };
3867
3868 static const struct rtw_intf_phy_para usb2_param_8822c[] = {
3869 {0xFFFF, 0x00,
3870 RTW_IP_SEL_PHY,
3871 RTW_INTF_PHY_CUT_ALL,
3872 RTW_INTF_PHY_PLATFORM_ALL},
3873 };
3874
3875 static const struct rtw_intf_phy_para usb3_param_8822c[] = {
3876 {0xFFFF, 0x0000,
3877 RTW_IP_SEL_PHY,
3878 RTW_INTF_PHY_CUT_ALL,
3879 RTW_INTF_PHY_PLATFORM_ALL},
3880 };
3881
3882 static const struct rtw_intf_phy_para pcie_gen1_param_8822c[] = {
3883 {0xFFFF, 0x0000,
3884 RTW_IP_SEL_PHY,
3885 RTW_INTF_PHY_CUT_ALL,
3886 RTW_INTF_PHY_PLATFORM_ALL},
3887 };
3888
3889 static const struct rtw_intf_phy_para pcie_gen2_param_8822c[] = {
3890 {0xFFFF, 0x0000,
3891 RTW_IP_SEL_PHY,
3892 RTW_INTF_PHY_CUT_ALL,
3893 RTW_INTF_PHY_PLATFORM_ALL},
3894 };
3895
3896 static const struct rtw_intf_phy_para_table phy_para_table_8822c = {
3897 .usb2_para = usb2_param_8822c,
3898 .usb3_para = usb3_param_8822c,
3899 .gen1_para = pcie_gen1_param_8822c,
3900 .gen2_para = pcie_gen2_param_8822c,
3901 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c),
3902 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c),
3903 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c),
3904 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c),
3905 };
3906
3907 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = {
3908 [0] = RTW_DEF_RFE(8822c, 0, 0),
3909 [1] = RTW_DEF_RFE(8822c, 0, 0),
3910 [2] = RTW_DEF_RFE(8822c, 0, 0),
3911 [5] = RTW_DEF_RFE(8822c, 0, 5),
3912 [6] = RTW_DEF_RFE(8822c, 0, 0),
3913 };
3914
3915 static const struct rtw_hw_reg rtw8822c_dig[] = {
3916 [0] = { .addr = 0x1d70, .mask = 0x7f },
3917 [1] = { .addr = 0x1d70, .mask = 0x7f00 },
3918 };
3919
3920 static const struct rtw_ltecoex_addr rtw8822c_ltecoex_addr = {
3921 .ctrl = LTECOEX_ACCESS_CTRL,
3922 .wdata = LTECOEX_WRITE_DATA,
3923 .rdata = LTECOEX_READ_DATA,
3924 };
3925
3926 static const struct rtw_page_table page_table_8822c[] = {
3927 {64, 64, 64, 64, 1},
3928 {64, 64, 64, 64, 1},
3929 {64, 64, 0, 0, 1},
3930 {64, 64, 64, 0, 1},
3931 {64, 64, 64, 64, 1},
3932 };
3933
3934 static const struct rtw_rqpn rqpn_table_8822c[] = {
3935 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3936 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3937 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3938 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3939 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3940 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3941 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3942 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
3943 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
3944 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3945 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3946 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
3947 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3948 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3949 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3950 };
3951
3952 static struct rtw_prioq_addrs prioq_addrs_8822c = {
3953 .prio[RTW_DMA_MAPPING_EXTRA] = {
3954 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
3955 },
3956 .prio[RTW_DMA_MAPPING_LOW] = {
3957 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
3958 },
3959 .prio[RTW_DMA_MAPPING_NORMAL] = {
3960 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
3961 },
3962 .prio[RTW_DMA_MAPPING_HIGH] = {
3963 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
3964 },
3965 .wsize = true,
3966 };
3967
3968 static struct rtw_chip_ops rtw8822c_ops = {
3969 .phy_set_param = rtw8822c_phy_set_param,
3970 .read_efuse = rtw8822c_read_efuse,
3971 .query_rx_desc = rtw8822c_query_rx_desc,
3972 .set_channel = rtw8822c_set_channel,
3973 .mac_init = rtw8822c_mac_init,
3974 .read_rf = rtw_phy_read_rf,
3975 .write_rf = rtw_phy_write_rf_reg_mix,
3976 .set_tx_power_index = rtw8822c_set_tx_power_index,
3977 .set_antenna = rtw8822c_set_antenna,
3978 .cfg_ldo25 = rtw8822c_cfg_ldo25,
3979 .false_alarm_statistics = rtw8822c_false_alarm_statistics,
3980 .dpk_track = rtw8822c_dpk_track,
3981 .phy_calibration = rtw8822c_phy_calibration,
3982 .cck_pd_set = rtw8822c_phy_cck_pd_set,
3983 .pwr_track = rtw8822c_pwr_track,
3984 .config_bfee = rtw8822c_bf_config_bfee,
3985 .set_gid_table = rtw_bf_set_gid_table,
3986 .cfg_csi_rate = rtw_bf_cfg_csi_rate,
3987
3988 .coex_set_init = rtw8822c_coex_cfg_init,
3989 .coex_set_ant_switch = NULL,
3990 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix,
3991 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug,
3992 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type,
3993 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power,
3994 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain,
3995 };
3996
3997 /* Shared-Antenna Coex Table */
3998 static const struct coex_table_para table_sant_8822c[] = {
3999 {0xffffffff, 0xffffffff}, /* case-0 */
4000 {0x55555555, 0x55555555},
4001 {0x66555555, 0x66555555},
4002 {0xaaaaaaaa, 0xaaaaaaaa},
4003 {0x5a5a5a5a, 0x5a5a5a5a},
4004 {0xfafafafa, 0xfafafafa}, /* case-5 */
4005 {0x6a5a5555, 0xaaaaaaaa},
4006 {0x6a5a56aa, 0x6a5a56aa},
4007 {0x6a5a5a5a, 0x6a5a5a5a},
4008 {0x66555555, 0x5a5a5a5a},
4009 {0x66555555, 0x6a5a5a5a}, /* case-10 */
4010 {0x66555555, 0x6a5a5aaa},
4011 {0x66555555, 0x5a5a5aaa},
4012 {0x66555555, 0x6aaa5aaa},
4013 {0x66555555, 0xaaaa5aaa},
4014 {0x66555555, 0xaaaaaaaa}, /* case-15 */
4015 {0xffff55ff, 0xfafafafa},
4016 {0xffff55ff, 0x6afa5afa},
4017 {0xaaffffaa, 0xfafafafa},
4018 {0xaa5555aa, 0x5a5a5a5a},
4019 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
4020 {0xaa5555aa, 0xaaaaaaaa},
4021 {0xffffffff, 0x5a5a5a5a},
4022 {0xffffffff, 0x5a5a5a5a},
4023 {0xffffffff, 0x55555555},
4024 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
4025 {0x55555555, 0x5a5a5a5a},
4026 {0x55555555, 0xaaaaaaaa},
4027 {0x55555555, 0x6a5a6a5a},
4028 {0x66556655, 0x66556655},
4029 {0x66556aaa, 0x6a5a6aaa}, /*case-30*/
4030 {0xffffffff, 0x5aaa5aaa},
4031 {0x56555555, 0x5a5a5aaa},
4032 };
4033
4034 /* Non-Shared-Antenna Coex Table */
4035 static const struct coex_table_para table_nsant_8822c[] = {
4036 {0xffffffff, 0xffffffff}, /* case-100 */
4037 {0x55555555, 0x55555555},
4038 {0x66555555, 0x66555555},
4039 {0xaaaaaaaa, 0xaaaaaaaa},
4040 {0x5a5a5a5a, 0x5a5a5a5a},
4041 {0xfafafafa, 0xfafafafa}, /* case-105 */
4042 {0x5afa5afa, 0x5afa5afa},
4043 {0x55555555, 0xfafafafa},
4044 {0x66555555, 0xfafafafa},
4045 {0x66555555, 0x5a5a5a5a},
4046 {0x66555555, 0x6a5a5a5a}, /* case-110 */
4047 {0x66555555, 0xaaaaaaaa},
4048 {0xffff55ff, 0xfafafafa},
4049 {0xffff55ff, 0x5afa5afa},
4050 {0xffff55ff, 0xaaaaaaaa},
4051 {0xffff55ff, 0xffff55ff}, /* case-115 */
4052 {0xaaffffaa, 0x5afa5afa},
4053 {0xaaffffaa, 0xaaaaaaaa},
4054 {0xffffffff, 0xfafafafa},
4055 {0xffffffff, 0x5afa5afa},
4056 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
4057 {0x55ff55ff, 0x5afa5afa},
4058 {0x55ff55ff, 0xaaaaaaaa},
4059 {0x55ff55ff, 0x55ff55ff}
4060 };
4061
4062 /* Shared-Antenna TDMA */
4063 static const struct coex_tdma_para tdma_sant_8822c[] = {
4064 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
4065 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
4066 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
4067 { {0x61, 0x30, 0x03, 0x11, 0x11} },
4068 { {0x61, 0x20, 0x03, 0x11, 0x11} },
4069 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
4070 { {0x61, 0x45, 0x03, 0x11, 0x10} },
4071 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
4072 { {0x61, 0x30, 0x03, 0x11, 0x10} },
4073 { {0x61, 0x20, 0x03, 0x11, 0x10} },
4074 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
4075 { {0x61, 0x08, 0x03, 0x11, 0x14} },
4076 { {0x61, 0x08, 0x03, 0x10, 0x14} },
4077 { {0x51, 0x08, 0x03, 0x10, 0x54} },
4078 { {0x51, 0x08, 0x03, 0x10, 0x55} },
4079 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
4080 { {0x51, 0x45, 0x03, 0x10, 0x50} },
4081 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
4082 { {0x51, 0x30, 0x03, 0x10, 0x50} },
4083 { {0x51, 0x20, 0x03, 0x10, 0x50} },
4084 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
4085 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
4086 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
4087 { {0x55, 0x08, 0x03, 0x10, 0x54} },
4088 { {0x65, 0x10, 0x03, 0x11, 0x10} },
4089 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
4090 { {0x51, 0x08, 0x03, 0x10, 0x50} },
4091 { {0x61, 0x08, 0x03, 0x11, 0x11} }
4092 };
4093
4094 /* Non-Shared-Antenna TDMA */
4095 static const struct coex_tdma_para tdma_nsant_8822c[] = {
4096 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
4097 { {0x61, 0x45, 0x03, 0x11, 0x11} },
4098 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
4099 { {0x61, 0x30, 0x03, 0x11, 0x11} },
4100 { {0x61, 0x20, 0x03, 0x11, 0x11} },
4101 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
4102 { {0x61, 0x45, 0x03, 0x11, 0x10} },
4103 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
4104 { {0x61, 0x30, 0x03, 0x11, 0x10} },
4105 { {0x61, 0x20, 0x03, 0x11, 0x10} },
4106 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
4107 { {0x61, 0x08, 0x03, 0x11, 0x14} },
4108 { {0x61, 0x08, 0x03, 0x10, 0x14} },
4109 { {0x51, 0x08, 0x03, 0x10, 0x54} },
4110 { {0x51, 0x08, 0x03, 0x10, 0x55} },
4111 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
4112 { {0x51, 0x45, 0x03, 0x10, 0x50} },
4113 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
4114 { {0x51, 0x30, 0x03, 0x10, 0x50} },
4115 { {0x51, 0x20, 0x03, 0x10, 0x50} },
4116 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
4117 { {0x51, 0x08, 0x03, 0x10, 0x50} }
4118 };
4119
4120 /* rssi in percentage % (dbm = % - 100) */
4121 static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30};
4122 static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25};
4123 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} };
4124
4125 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
4126 static const struct coex_rf_para rf_para_tx_8822c[] = {
4127 {0, 0, false, 7}, /* for normal */
4128 {0, 16, false, 7}, /* for WL-CPT */
4129 {8, 17, true, 4},
4130 {7, 18, true, 4},
4131 {6, 19, true, 4},
4132 {5, 20, true, 4}
4133 };
4134
4135 static const struct coex_rf_para rf_para_rx_8822c[] = {
4136 {0, 0, false, 7}, /* for normal */
4137 {0, 16, false, 7}, /* for WL-CPT */
4138 {3, 24, true, 5},
4139 {2, 26, true, 5},
4140 {1, 27, true, 5},
4141 {0, 28, true, 5}
4142 };
4143
4144 static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c));
4145
4146 static const u8
4147 rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
4148 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
4149 11, 12, 13, 14, 15, 16, 18, 19, 20, 21,
4150 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 },
4151 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
4152 11, 12, 13, 14, 15, 16, 18, 19, 20, 21,
4153 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 },
4154 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
4155 11, 12, 13, 14, 15, 16, 18, 19, 20, 21,
4156 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 },
4157 };
4158
4159 static const u8
4160 rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
4161 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4162 10, 10, 11, 12, 13, 14, 15, 16, 17, 18,
4163 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 },
4164 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4165 10, 10, 11, 12, 13, 14, 15, 16, 17, 18,
4166 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 },
4167 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4168 10, 10, 11, 12, 13, 14, 15, 16, 17, 18,
4169 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 },
4170 };
4171
4172 static const u8
4173 rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
4174 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
4175 11, 13, 14, 15, 16, 17, 18, 19, 20, 21,
4176 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 },
4177 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
4178 11, 13, 14, 15, 16, 17, 18, 19, 20, 21,
4179 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 },
4180 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
4181 11, 13, 14, 15, 16, 17, 18, 19, 20, 21,
4182 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 },
4183 };
4184
4185 static const u8
4186 rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
4187 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4188 10, 11, 12, 13, 14, 15, 16, 17, 18, 20,
4189 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 },
4190 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4191 10, 11, 12, 13, 14, 15, 16, 17, 18, 20,
4192 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 },
4193 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4194 10, 11, 12, 13, 14, 15, 16, 17, 18, 20,
4195 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 },
4196 };
4197
4198 static const u8 rtw8822c_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = {
4199 0, 1, 2, 3, 4, 4, 5, 6, 7, 8,
4200 9, 9, 10, 11, 12, 13, 14, 15, 15, 16,
4201 17, 18, 19, 20, 20, 21, 22, 23, 24, 25
4202 };
4203
4204 static const u8 rtw8822c_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = {
4205 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4206 10, 11, 12, 13, 14, 14, 15, 16, 17, 18,
4207 19, 20, 21, 22, 23, 24, 25, 26, 27, 28
4208 };
4209
4210 static const u8 rtw8822c_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = {
4211 0, 1, 2, 2, 3, 4, 4, 5, 6, 6,
4212 7, 8, 8, 9, 9, 10, 11, 11, 12, 13,
4213 13, 14, 15, 15, 16, 17, 17, 18, 19, 19
4214 };
4215
4216 static const u8 rtw8822c_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = {
4217 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4218 10, 11, 11, 12, 13, 14, 15, 16, 17, 18,
4219 19, 20, 21, 22, 23, 24, 25, 25, 26, 27
4220 };
4221
4222 static const u8 rtw8822c_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = {
4223 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
4224 9, 10, 11, 11, 12, 13, 14, 15, 16, 17,
4225 17, 18, 19, 20, 21, 22, 23, 23, 24, 25
4226 };
4227
4228 static const u8 rtw8822c_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = {
4229 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4230 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
4231 20, 21, 22, 23, 24, 25, 26, 27, 28, 29
4232 };
4233
4234 static const u8 rtw8822c_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = {
4235 0, 1, 2, 3, 3, 4, 5, 6, 6, 7,
4236 8, 9, 9, 10, 11, 12, 12, 13, 14, 15,
4237 15, 16, 17, 18, 18, 19, 20, 21, 21, 22
4238 };
4239
4240 static const u8 rtw8822c_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = {
4241 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
4242 9, 10, 11, 11, 12, 13, 14, 15, 16, 17,
4243 18, 18, 19, 20, 21, 22, 23, 24, 24, 25
4244 };
4245
4246 static const struct rtw_pwr_track_tbl rtw8822c_rtw_pwr_track_tbl = {
4247 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1],
4248 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2],
4249 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3],
4250 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1],
4251 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2],
4252 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3],
4253 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1],
4254 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2],
4255 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3],
4256 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1],
4257 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2],
4258 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3],
4259 .pwrtrk_2gb_n = rtw8822c_pwrtrk_2gb_n,
4260 .pwrtrk_2gb_p = rtw8822c_pwrtrk_2gb_p,
4261 .pwrtrk_2ga_n = rtw8822c_pwrtrk_2ga_n,
4262 .pwrtrk_2ga_p = rtw8822c_pwrtrk_2ga_p,
4263 .pwrtrk_2g_cckb_n = rtw8822c_pwrtrk_2g_cck_b_n,
4264 .pwrtrk_2g_cckb_p = rtw8822c_pwrtrk_2g_cck_b_p,
4265 .pwrtrk_2g_ccka_n = rtw8822c_pwrtrk_2g_cck_a_n,
4266 .pwrtrk_2g_ccka_p = rtw8822c_pwrtrk_2g_cck_a_p,
4267 };
4268
4269 #ifdef CONFIG_PM
4270 static const struct wiphy_wowlan_support rtw_wowlan_stub_8822c = {
4271 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_GTK_REKEY_FAILURE |
4272 WIPHY_WOWLAN_DISCONNECT | WIPHY_WOWLAN_SUPPORTS_GTK_REKEY |
4273 WIPHY_WOWLAN_NET_DETECT,
4274 .n_patterns = RTW_MAX_PATTERN_NUM,
4275 .pattern_max_len = RTW_MAX_PATTERN_SIZE,
4276 .pattern_min_len = 1,
4277 .max_nd_match_sets = 4,
4278 };
4279 #endif
4280
4281 static const struct rtw_reg_domain coex_info_hw_regs_8822c[] = {
4282 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8},
4283 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8},
4284 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8},
4285 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32},
4286 {0, 0, RTW_REG_DOMAIN_NL},
4287 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
4288 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
4289 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
4290 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
4291 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
4292 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
4293 {0, 0, RTW_REG_DOMAIN_NL},
4294 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
4295 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
4296 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
4297 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
4298 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
4299 {0, 0, RTW_REG_DOMAIN_NL},
4300 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
4301 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
4302 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
4303 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
4304 };
4305
4306 struct rtw_chip_info rtw8822c_hw_spec = {
4307 .ops = &rtw8822c_ops,
4308 .id = RTW_CHIP_TYPE_8822C,
4309 .fw_name = "rtw88/rtw8822c_fw.bin",
4310 .wlan_cpu = RTW_WCPU_11AC,
4311 .tx_pkt_desc_sz = 48,
4312 .tx_buf_desc_sz = 16,
4313 .rx_pkt_desc_sz = 24,
4314 .rx_buf_desc_sz = 8,
4315 .phy_efuse_size = 512,
4316 .log_efuse_size = 768,
4317 .ptct_efuse_size = 124,
4318 .txff_size = 262144,
4319 .rxff_size = 24576,
4320 .fw_rxff_size = 12288,
4321 .txgi_factor = 2,
4322 .is_pwr_by_rate_dec = false,
4323 .max_power_index = 0x7f,
4324 .csi_buf_pg_num = 50,
4325 .band = RTW_BAND_2G | RTW_BAND_5G,
4326 .page_size = 128,
4327 .dig_min = 0x20,
4328 .ht_supported = true,
4329 .vht_supported = true,
4330 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK) | BIT(LPS_DEEP_MODE_PG),
4331 .sys_func_en = 0xD8,
4332 .pwr_on_seq = card_enable_flow_8822c,
4333 .pwr_off_seq = card_disable_flow_8822c,
4334 .page_table = page_table_8822c,
4335 .rqpn_table = rqpn_table_8822c,
4336 .prioq_addrs = &prioq_addrs_8822c,
4337 .intf_table = &phy_para_table_8822c,
4338 .dig = rtw8822c_dig,
4339 .dig_cck = NULL,
4340 .rf_base_addr = {0x3c00, 0x4c00},
4341 .rf_sipi_addr = {0x1808, 0x4108},
4342 .ltecoex_addr = &rtw8822c_ltecoex_addr,
4343 .mac_tbl = &rtw8822c_mac_tbl,
4344 .agc_tbl = &rtw8822c_agc_tbl,
4345 .bb_tbl = &rtw8822c_bb_tbl,
4346 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl,
4347 .rf_tbl = {&rtw8822c_rf_b_tbl, &rtw8822c_rf_a_tbl},
4348 .rfe_defs = rtw8822c_rfe_defs,
4349 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs),
4350 .en_dis_dpd = true,
4351 .dpd_ratemask = DIS_DPD_RATEALL,
4352 .pwr_track_tbl = &rtw8822c_rtw_pwr_track_tbl,
4353 .iqk_threshold = 8,
4354 .bfer_su_max_num = 2,
4355 .bfer_mu_max_num = 1,
4356 .rx_ldpc = true,
4357
4358 #ifdef CONFIG_PM
4359 .wow_fw_name = "rtw88/rtw8822c_wow_fw.bin",
4360 .wowlan_stub = &rtw_wowlan_stub_8822c,
4361 .max_sched_scan_ssids = 4,
4362 #endif
4363 .coex_para_ver = 0x201029,
4364 .bt_desired_ver = 0x1c,
4365 .scbd_support = true,
4366 .new_scbd10_def = true,
4367 .ble_hid_profile_support = true,
4368 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
4369 .bt_rssi_type = COEX_BTRSSI_DBM,
4370 .ant_isolation = 15,
4371 .rssi_tolerance = 2,
4372 .wl_rssi_step = wl_rssi_step_8822c,
4373 .bt_rssi_step = bt_rssi_step_8822c,
4374 .table_sant_num = ARRAY_SIZE(table_sant_8822c),
4375 .table_sant = table_sant_8822c,
4376 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c),
4377 .table_nsant = table_nsant_8822c,
4378 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c),
4379 .tdma_sant = tdma_sant_8822c,
4380 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c),
4381 .tdma_nsant = tdma_nsant_8822c,
4382 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c),
4383 .wl_rf_para_tx = rf_para_tx_8822c,
4384 .wl_rf_para_rx = rf_para_rx_8822c,
4385 .bt_afh_span_bw20 = 0x24,
4386 .bt_afh_span_bw40 = 0x36,
4387 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c),
4388 .afh_5g = afh_5g_8822c,
4389
4390 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822c),
4391 .coex_info_hw_regs = coex_info_hw_regs_8822c,
4392
4393 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},
4394 };
4395 EXPORT_SYMBOL(rtw8822c_hw_spec);
4396
4397 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin");
4398 MODULE_FIRMWARE("rtw88/rtw8822c_wow_fw.bin");
4399
4400 MODULE_AUTHOR("Realtek Corporation");
4401 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822c driver");
4402 MODULE_LICENSE("Dual BSD/GPL");
Linux with added FPC-III support