1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
6 * Copyright (C) 2016 Marvell
8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/pci-ecam.h>
20 #include <linux/init.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/msi.h>
24 #include <linux/of_address.h>
25 #include <linux/of_gpio.h>
26 #include <linux/of_pci.h>
29 #include "../pci-bridge-emul.h"
31 /* PCIe core registers */
32 #define PCIE_CORE_DEV_ID_REG 0x0
33 #define PCIE_CORE_CMD_STATUS_REG 0x4
34 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
35 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
36 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
37 #define PCIE_CORE_DEV_REV_REG 0x8
38 #define PCIE_CORE_PCIEXP_CAP 0xc0
39 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
41 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
42 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
43 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
44 #define PCIE_CORE_INT_A_ASSERT_ENABLE 1
45 #define PCIE_CORE_INT_B_ASSERT_ENABLE 2
46 #define PCIE_CORE_INT_C_ASSERT_ENABLE 3
47 #define PCIE_CORE_INT_D_ASSERT_ENABLE 4
48 /* PIO registers base address and register offsets */
49 #define PIO_BASE_ADDR 0x4000
50 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
51 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
52 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
53 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
54 #define PIO_COMPLETION_STATUS_SHIFT 7
55 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
56 #define PIO_COMPLETION_STATUS_OK 0
57 #define PIO_COMPLETION_STATUS_UR 1
58 #define PIO_COMPLETION_STATUS_CRS 2
59 #define PIO_COMPLETION_STATUS_CA 4
60 #define PIO_NON_POSTED_REQ BIT(0)
61 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
62 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
63 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
64 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
65 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
66 #define PIO_START (PIO_BASE_ADDR + 0x1c)
67 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
68 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
70 /* Aardvark Control registers */
71 #define CONTROL_BASE_ADDR 0x4800
72 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
73 #define PCIE_GEN_SEL_MSK 0x3
74 #define PCIE_GEN_SEL_SHIFT 0x0
80 #define LANE_CNT_MSK 0x18
81 #define LANE_CNT_SHIFT 0x3
82 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
83 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
84 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
85 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
86 #define LINK_TRAINING_EN BIT(6)
87 #define LEGACY_INTA BIT(28)
88 #define LEGACY_INTB BIT(29)
89 #define LEGACY_INTC BIT(30)
90 #define LEGACY_INTD BIT(31)
91 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
92 #define HOT_RESET_GEN BIT(0)
93 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
94 #define PCIE_CORE_CTRL2_RESERVED 0x7
95 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
96 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
97 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
98 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
99 #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14)
100 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1)
101 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
102 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
103 #define PCIE_MSG_PM_PME_MASK BIT(7)
104 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
105 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
106 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
107 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
108 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
109 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
110 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
111 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
112 #define PCIE_ISR1_FLUSH BIT(5)
113 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
114 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
115 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
116 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
117 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
118 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
119 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
121 /* LMI registers base address and register offsets */
122 #define LMI_BASE_ADDR 0x6000
123 #define CFG_REG (LMI_BASE_ADDR + 0x0)
124 #define LTSSM_SHIFT 24
125 #define LTSSM_MASK 0x3f
126 #define LTSSM_L0 0x10
127 #define RC_BAR_CONFIG 0x300
129 /* PCIe core controller registers */
130 #define CTRL_CORE_BASE_ADDR 0x18000
131 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
132 #define CTRL_MODE_SHIFT 0x0
133 #define CTRL_MODE_MASK 0x1
134 #define PCIE_CORE_MODE_DIRECT 0x0
135 #define PCIE_CORE_MODE_COMMAND 0x1
137 /* PCIe Central Interrupts Registers */
138 #define CENTRAL_INT_BASE_ADDR 0x1b000
139 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
140 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
141 #define PCIE_IRQ_CMDQ_INT BIT(0)
142 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
143 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
144 #define PCIE_IRQ_DMA_INT BIT(4)
145 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
146 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
147 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
148 #define PCIE_IRQ_COMPQ_INT BIT(12)
149 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
150 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
151 #define PCIE_IRQ_CORE_INT BIT(16)
152 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
153 #define PCIE_IRQ_DPMU_INT BIT(18)
154 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
155 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
156 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
157 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
158 #define PCIE_IRQ_EP_STATUS BIT(23)
159 #define PCIE_IRQ_ALL_MASK 0xfff0fb
160 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
162 /* Transaction types */
163 #define PCIE_CONFIG_RD_TYPE0 0x8
164 #define PCIE_CONFIG_RD_TYPE1 0x9
165 #define PCIE_CONFIG_WR_TYPE0 0xa
166 #define PCIE_CONFIG_WR_TYPE1 0xb
168 #define PIO_RETRY_CNT 500
169 #define PIO_RETRY_DELAY 2 /* 2 us*/
171 #define LINK_WAIT_MAX_RETRIES 10
172 #define LINK_WAIT_USLEEP_MIN 90000
173 #define LINK_WAIT_USLEEP_MAX 100000
174 #define RETRAIN_WAIT_MAX_RETRIES 10
175 #define RETRAIN_WAIT_USLEEP_US 2000
177 #define MSI_IRQ_NUM 32
180 struct platform_device
*pdev
;
182 struct irq_domain
*irq_domain
;
183 struct irq_chip irq_chip
;
184 struct irq_domain
*msi_domain
;
185 struct irq_domain
*msi_inner_domain
;
186 struct irq_chip msi_bottom_irq_chip
;
187 struct irq_chip msi_irq_chip
;
188 struct msi_domain_info msi_domain_info
;
189 DECLARE_BITMAP(msi_used
, MSI_IRQ_NUM
);
190 struct mutex msi_used_lock
;
193 struct pci_bridge_emul bridge
;
194 struct gpio_desc
*reset_gpio
;
198 static inline void advk_writel(struct advk_pcie
*pcie
, u32 val
, u64 reg
)
200 writel(val
, pcie
->base
+ reg
);
203 static inline u32
advk_readl(struct advk_pcie
*pcie
, u64 reg
)
205 return readl(pcie
->base
+ reg
);
208 static inline u16
advk_read16(struct advk_pcie
*pcie
, u64 reg
)
210 return advk_readl(pcie
, (reg
& ~0x3)) >> ((reg
& 0x3) * 8);
213 static int advk_pcie_link_up(struct advk_pcie
*pcie
)
215 u32 val
, ltssm_state
;
217 val
= advk_readl(pcie
, CFG_REG
);
218 ltssm_state
= (val
>> LTSSM_SHIFT
) & LTSSM_MASK
;
219 return ltssm_state
>= LTSSM_L0
;
222 static int advk_pcie_wait_for_link(struct advk_pcie
*pcie
)
226 /* check if the link is up or not */
227 for (retries
= 0; retries
< LINK_WAIT_MAX_RETRIES
; retries
++) {
228 if (advk_pcie_link_up(pcie
))
231 usleep_range(LINK_WAIT_USLEEP_MIN
, LINK_WAIT_USLEEP_MAX
);
237 static void advk_pcie_wait_for_retrain(struct advk_pcie
*pcie
)
241 for (retries
= 0; retries
< RETRAIN_WAIT_MAX_RETRIES
; ++retries
) {
242 if (!advk_pcie_link_up(pcie
))
244 udelay(RETRAIN_WAIT_USLEEP_US
);
248 static void advk_pcie_issue_perst(struct advk_pcie
*pcie
)
252 if (!pcie
->reset_gpio
)
256 * As required by PCI Express spec (PCI Express Base Specification, REV.
257 * 4.0 PCI Express, February 19 2014, 6.6.1 Conventional Reset) a delay
258 * for at least 100ms after de-asserting PERST# signal is needed before
259 * link training is enabled. So ensure that link training is disabled
260 * prior de-asserting PERST# signal to fulfill that PCI Express spec
263 reg
= advk_readl(pcie
, PCIE_CORE_CTRL0_REG
);
264 reg
&= ~LINK_TRAINING_EN
;
265 advk_writel(pcie
, reg
, PCIE_CORE_CTRL0_REG
);
267 /* 10ms delay is needed for some cards */
268 dev_info(&pcie
->pdev
->dev
, "issuing PERST via reset GPIO for 10ms\n");
269 gpiod_set_value_cansleep(pcie
->reset_gpio
, 1);
270 usleep_range(10000, 11000);
271 gpiod_set_value_cansleep(pcie
->reset_gpio
, 0);
274 static int advk_pcie_train_at_gen(struct advk_pcie
*pcie
, int gen
)
279 /* Setup link speed */
280 reg
= advk_readl(pcie
, PCIE_CORE_CTRL0_REG
);
281 reg
&= ~PCIE_GEN_SEL_MSK
;
288 advk_writel(pcie
, reg
, PCIE_CORE_CTRL0_REG
);
291 * Enable link training. This is not needed in every call to this
292 * function, just once suffices, but it does not break anything either.
294 reg
= advk_readl(pcie
, PCIE_CORE_CTRL0_REG
);
295 reg
|= LINK_TRAINING_EN
;
296 advk_writel(pcie
, reg
, PCIE_CORE_CTRL0_REG
);
299 * Start link training immediately after enabling it.
300 * This solves problems for some buggy cards.
302 reg
= advk_readl(pcie
, PCIE_CORE_PCIEXP_CAP
+ PCI_EXP_LNKCTL
);
303 reg
|= PCI_EXP_LNKCTL_RL
;
304 advk_writel(pcie
, reg
, PCIE_CORE_PCIEXP_CAP
+ PCI_EXP_LNKCTL
);
306 ret
= advk_pcie_wait_for_link(pcie
);
310 reg
= advk_read16(pcie
, PCIE_CORE_PCIEXP_CAP
+ PCI_EXP_LNKSTA
);
311 neg_gen
= reg
& PCI_EXP_LNKSTA_CLS
;
316 static void advk_pcie_train_link(struct advk_pcie
*pcie
)
318 struct device
*dev
= &pcie
->pdev
->dev
;
319 int neg_gen
= -1, gen
;
322 * Reset PCIe card via PERST# signal. Some cards are not detected
323 * during link training when they are in some non-initial state.
325 advk_pcie_issue_perst(pcie
);
328 * PERST# signal could have been asserted by pinctrl subsystem before
329 * probe() callback has been called or issued explicitly by reset gpio
330 * function advk_pcie_issue_perst(), making the endpoint going into
331 * fundamental reset. As required by PCI Express spec a delay for at
332 * least 100ms after such a reset before link training is needed.
334 msleep(PCI_PM_D3COLD_WAIT
);
337 * Try link training at link gen specified by device tree property
338 * 'max-link-speed'. If this fails, iteratively train at lower gen.
340 for (gen
= pcie
->link_gen
; gen
> 0; --gen
) {
341 neg_gen
= advk_pcie_train_at_gen(pcie
, gen
);
350 * After successful training if negotiated gen is lower than requested,
351 * train again on negotiated gen. This solves some stability issues for
352 * some buggy gen1 cards.
356 neg_gen
= advk_pcie_train_at_gen(pcie
, gen
);
359 if (neg_gen
== gen
) {
360 dev_info(dev
, "link up at gen %i\n", gen
);
365 dev_err(dev
, "link never came up\n");
368 static void advk_pcie_setup_hw(struct advk_pcie
*pcie
)
373 reg
= advk_readl(pcie
, PCIE_CORE_REF_CLK_REG
);
374 reg
|= PCIE_CORE_REF_CLK_TX_ENABLE
;
375 advk_writel(pcie
, reg
, PCIE_CORE_REF_CLK_REG
);
377 /* Set to Direct mode */
378 reg
= advk_readl(pcie
, CTRL_CONFIG_REG
);
379 reg
&= ~(CTRL_MODE_MASK
<< CTRL_MODE_SHIFT
);
380 reg
|= ((PCIE_CORE_MODE_DIRECT
& CTRL_MODE_MASK
) << CTRL_MODE_SHIFT
);
381 advk_writel(pcie
, reg
, CTRL_CONFIG_REG
);
383 /* Set PCI global control register to RC mode */
384 reg
= advk_readl(pcie
, PCIE_CORE_CTRL0_REG
);
385 reg
|= (IS_RC_MSK
<< IS_RC_SHIFT
);
386 advk_writel(pcie
, reg
, PCIE_CORE_CTRL0_REG
);
388 /* Set Advanced Error Capabilities and Control PF0 register */
389 reg
= PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX
|
390 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN
|
391 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK
|
392 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV
;
393 advk_writel(pcie
, reg
, PCIE_CORE_ERR_CAPCTL_REG
);
395 /* Set PCIe Device Control register */
396 reg
= advk_readl(pcie
, PCIE_CORE_PCIEXP_CAP
+ PCI_EXP_DEVCTL
);
397 reg
&= ~PCI_EXP_DEVCTL_RELAX_EN
;
398 reg
&= ~PCI_EXP_DEVCTL_NOSNOOP_EN
;
399 reg
&= ~PCI_EXP_DEVCTL_READRQ
;
400 reg
|= PCI_EXP_DEVCTL_PAYLOAD
; /* Set max payload size */
401 reg
|= PCI_EXP_DEVCTL_READRQ_512B
;
402 advk_writel(pcie
, reg
, PCIE_CORE_PCIEXP_CAP
+ PCI_EXP_DEVCTL
);
404 /* Program PCIe Control 2 to disable strict ordering */
405 reg
= PCIE_CORE_CTRL2_RESERVED
|
406 PCIE_CORE_CTRL2_TD_ENABLE
;
407 advk_writel(pcie
, reg
, PCIE_CORE_CTRL2_REG
);
410 reg
= advk_readl(pcie
, PCIE_CORE_CTRL0_REG
);
411 reg
&= ~LANE_CNT_MSK
;
413 advk_writel(pcie
, reg
, PCIE_CORE_CTRL0_REG
);
416 reg
= advk_readl(pcie
, PCIE_CORE_CTRL2_REG
);
417 reg
|= PCIE_CORE_CTRL2_MSI_ENABLE
;
418 advk_writel(pcie
, reg
, PCIE_CORE_CTRL2_REG
);
420 /* Clear all interrupts */
421 advk_writel(pcie
, PCIE_ISR0_ALL_MASK
, PCIE_ISR0_REG
);
422 advk_writel(pcie
, PCIE_ISR1_ALL_MASK
, PCIE_ISR1_REG
);
423 advk_writel(pcie
, PCIE_IRQ_ALL_MASK
, HOST_CTRL_INT_STATUS_REG
);
425 /* Disable All ISR0/1 Sources */
426 reg
= PCIE_ISR0_ALL_MASK
;
427 reg
&= ~PCIE_ISR0_MSI_INT_PENDING
;
428 advk_writel(pcie
, reg
, PCIE_ISR0_MASK_REG
);
430 advk_writel(pcie
, PCIE_ISR1_ALL_MASK
, PCIE_ISR1_MASK_REG
);
432 /* Unmask all MSIs */
433 advk_writel(pcie
, 0, PCIE_MSI_MASK_REG
);
435 /* Enable summary interrupt for GIC SPI source */
436 reg
= PCIE_IRQ_ALL_MASK
& (~PCIE_IRQ_ENABLE_INTS_MASK
);
437 advk_writel(pcie
, reg
, HOST_CTRL_INT_MASK_REG
);
439 reg
= advk_readl(pcie
, PCIE_CORE_CTRL2_REG
);
440 reg
|= PCIE_CORE_CTRL2_OB_WIN_ENABLE
;
441 advk_writel(pcie
, reg
, PCIE_CORE_CTRL2_REG
);
443 /* Bypass the address window mapping for PIO */
444 reg
= advk_readl(pcie
, PIO_CTRL
);
445 reg
|= PIO_CTRL_ADDR_WIN_DISABLE
;
446 advk_writel(pcie
, reg
, PIO_CTRL
);
448 advk_pcie_train_link(pcie
);
451 * FIXME: The following register update is suspicious. This register is
452 * applicable only when the PCI controller is configured for Endpoint
453 * mode, not as a Root Complex. But apparently when this code is
454 * removed, some cards stop working. This should be investigated and
455 * a comment explaining this should be put here.
457 reg
= advk_readl(pcie
, PCIE_CORE_CMD_STATUS_REG
);
458 reg
|= PCIE_CORE_CMD_MEM_ACCESS_EN
|
459 PCIE_CORE_CMD_IO_ACCESS_EN
|
460 PCIE_CORE_CMD_MEM_IO_REQ_EN
;
461 advk_writel(pcie
, reg
, PCIE_CORE_CMD_STATUS_REG
);
464 static void advk_pcie_check_pio_status(struct advk_pcie
*pcie
)
466 struct device
*dev
= &pcie
->pdev
->dev
;
469 char *strcomp_status
, *str_posted
;
471 reg
= advk_readl(pcie
, PIO_STAT
);
472 status
= (reg
& PIO_COMPLETION_STATUS_MASK
) >>
473 PIO_COMPLETION_STATUS_SHIFT
;
479 case PIO_COMPLETION_STATUS_UR
:
480 strcomp_status
= "UR";
482 case PIO_COMPLETION_STATUS_CRS
:
483 strcomp_status
= "CRS";
485 case PIO_COMPLETION_STATUS_CA
:
486 strcomp_status
= "CA";
489 strcomp_status
= "Unknown";
493 if (reg
& PIO_NON_POSTED_REQ
)
494 str_posted
= "Non-posted";
496 str_posted
= "Posted";
498 dev_err(dev
, "%s PIO Response Status: %s, %#x @ %#x\n",
499 str_posted
, strcomp_status
, reg
, advk_readl(pcie
, PIO_ADDR_LS
));
502 static int advk_pcie_wait_pio(struct advk_pcie
*pcie
)
504 struct device
*dev
= &pcie
->pdev
->dev
;
507 for (i
= 0; i
< PIO_RETRY_CNT
; i
++) {
510 start
= advk_readl(pcie
, PIO_START
);
511 isr
= advk_readl(pcie
, PIO_ISR
);
514 udelay(PIO_RETRY_DELAY
);
517 dev_err(dev
, "config read/write timed out\n");
522 static pci_bridge_emul_read_status_t
523 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul
*bridge
,
526 struct advk_pcie
*pcie
= bridge
->data
;
531 *value
= PCI_EXP_SLTSTA_PDS
<< 16;
532 return PCI_BRIDGE_EMUL_HANDLED
;
534 case PCI_EXP_RTCTL
: {
535 u32 val
= advk_readl(pcie
, PCIE_ISR0_MASK_REG
);
536 *value
= (val
& PCIE_MSG_PM_PME_MASK
) ? 0 : PCI_EXP_RTCTL_PMEIE
;
537 return PCI_BRIDGE_EMUL_HANDLED
;
540 case PCI_EXP_RTSTA
: {
541 u32 isr0
= advk_readl(pcie
, PCIE_ISR0_REG
);
542 u32 msglog
= advk_readl(pcie
, PCIE_MSG_LOG_REG
);
543 *value
= (isr0
& PCIE_MSG_PM_PME_MASK
) << 16 | (msglog
>> 16);
544 return PCI_BRIDGE_EMUL_HANDLED
;
547 case PCI_EXP_LNKCTL
: {
548 /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */
549 u32 val
= advk_readl(pcie
, PCIE_CORE_PCIEXP_CAP
+ reg
) &
550 ~(PCI_EXP_LNKSTA_LT
<< 16);
551 if (!advk_pcie_link_up(pcie
))
552 val
|= (PCI_EXP_LNKSTA_LT
<< 16);
554 return PCI_BRIDGE_EMUL_HANDLED
;
557 case PCI_CAP_LIST_ID
:
561 *value
= advk_readl(pcie
, PCIE_CORE_PCIEXP_CAP
+ reg
);
562 return PCI_BRIDGE_EMUL_HANDLED
;
564 return PCI_BRIDGE_EMUL_NOT_HANDLED
;
570 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul
*bridge
,
571 int reg
, u32 old
, u32
new, u32 mask
)
573 struct advk_pcie
*pcie
= bridge
->data
;
577 advk_writel(pcie
, new, PCIE_CORE_PCIEXP_CAP
+ reg
);
581 advk_writel(pcie
, new, PCIE_CORE_PCIEXP_CAP
+ reg
);
582 if (new & PCI_EXP_LNKCTL_RL
)
583 advk_pcie_wait_for_retrain(pcie
);
586 case PCI_EXP_RTCTL
: {
587 /* Only mask/unmask PME interrupt */
588 u32 val
= advk_readl(pcie
, PCIE_ISR0_MASK_REG
) &
589 ~PCIE_MSG_PM_PME_MASK
;
590 if ((new & PCI_EXP_RTCTL_PMEIE
) == 0)
591 val
|= PCIE_MSG_PM_PME_MASK
;
592 advk_writel(pcie
, val
, PCIE_ISR0_MASK_REG
);
597 new = (new & PCI_EXP_RTSTA_PME
) >> 9;
598 advk_writel(pcie
, new, PCIE_ISR0_REG
);
606 static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops
= {
607 .read_pcie
= advk_pci_bridge_emul_pcie_conf_read
,
608 .write_pcie
= advk_pci_bridge_emul_pcie_conf_write
,
612 * Initialize the configuration space of the PCI-to-PCI bridge
613 * associated with the given PCIe interface.
615 static int advk_sw_pci_bridge_init(struct advk_pcie
*pcie
)
617 struct pci_bridge_emul
*bridge
= &pcie
->bridge
;
619 bridge
->conf
.vendor
=
620 cpu_to_le16(advk_readl(pcie
, PCIE_CORE_DEV_ID_REG
) & 0xffff);
621 bridge
->conf
.device
=
622 cpu_to_le16(advk_readl(pcie
, PCIE_CORE_DEV_ID_REG
) >> 16);
623 bridge
->conf
.class_revision
=
624 cpu_to_le32(advk_readl(pcie
, PCIE_CORE_DEV_REV_REG
) & 0xff);
626 /* Support 32 bits I/O addressing */
627 bridge
->conf
.iobase
= PCI_IO_RANGE_TYPE_32
;
628 bridge
->conf
.iolimit
= PCI_IO_RANGE_TYPE_32
;
630 /* Support 64 bits memory pref */
631 bridge
->conf
.pref_mem_base
= cpu_to_le16(PCI_PREF_RANGE_TYPE_64
);
632 bridge
->conf
.pref_mem_limit
= cpu_to_le16(PCI_PREF_RANGE_TYPE_64
);
634 /* Support interrupt A for MSI feature */
635 bridge
->conf
.intpin
= PCIE_CORE_INT_A_ASSERT_ENABLE
;
637 bridge
->has_pcie
= true;
639 bridge
->ops
= &advk_pci_bridge_emul_ops
;
641 return pci_bridge_emul_init(bridge
, 0);
644 static bool advk_pcie_valid_device(struct advk_pcie
*pcie
, struct pci_bus
*bus
,
647 if (pci_is_root_bus(bus
) && PCI_SLOT(devfn
) != 0)
651 * If the link goes down after we check for link-up, nothing bad
652 * happens but the config access times out.
654 if (!pci_is_root_bus(bus
) && !advk_pcie_link_up(pcie
))
660 static int advk_pcie_rd_conf(struct pci_bus
*bus
, u32 devfn
,
661 int where
, int size
, u32
*val
)
663 struct advk_pcie
*pcie
= bus
->sysdata
;
667 if (!advk_pcie_valid_device(pcie
, bus
, devfn
)) {
669 return PCIBIOS_DEVICE_NOT_FOUND
;
672 if (pci_is_root_bus(bus
))
673 return pci_bridge_emul_conf_read(&pcie
->bridge
, where
,
677 advk_writel(pcie
, 0, PIO_START
);
678 advk_writel(pcie
, 1, PIO_ISR
);
680 /* Program the control register */
681 reg
= advk_readl(pcie
, PIO_CTRL
);
682 reg
&= ~PIO_CTRL_TYPE_MASK
;
683 if (pci_is_root_bus(bus
->parent
))
684 reg
|= PCIE_CONFIG_RD_TYPE0
;
686 reg
|= PCIE_CONFIG_RD_TYPE1
;
687 advk_writel(pcie
, reg
, PIO_CTRL
);
689 /* Program the address registers */
690 reg
= ALIGN_DOWN(PCIE_ECAM_OFFSET(bus
->number
, devfn
, where
), 4);
691 advk_writel(pcie
, reg
, PIO_ADDR_LS
);
692 advk_writel(pcie
, 0, PIO_ADDR_MS
);
694 /* Program the data strobe */
695 advk_writel(pcie
, 0xf, PIO_WR_DATA_STRB
);
697 /* Start the transfer */
698 advk_writel(pcie
, 1, PIO_START
);
700 ret
= advk_pcie_wait_pio(pcie
);
703 return PCIBIOS_SET_FAILED
;
706 advk_pcie_check_pio_status(pcie
);
708 /* Get the read result */
709 *val
= advk_readl(pcie
, PIO_RD_DATA
);
711 *val
= (*val
>> (8 * (where
& 3))) & 0xff;
713 *val
= (*val
>> (8 * (where
& 3))) & 0xffff;
715 return PCIBIOS_SUCCESSFUL
;
718 static int advk_pcie_wr_conf(struct pci_bus
*bus
, u32 devfn
,
719 int where
, int size
, u32 val
)
721 struct advk_pcie
*pcie
= bus
->sysdata
;
723 u32 data_strobe
= 0x0;
727 if (!advk_pcie_valid_device(pcie
, bus
, devfn
))
728 return PCIBIOS_DEVICE_NOT_FOUND
;
730 if (pci_is_root_bus(bus
))
731 return pci_bridge_emul_conf_write(&pcie
->bridge
, where
,
735 return PCIBIOS_SET_FAILED
;
738 advk_writel(pcie
, 0, PIO_START
);
739 advk_writel(pcie
, 1, PIO_ISR
);
741 /* Program the control register */
742 reg
= advk_readl(pcie
, PIO_CTRL
);
743 reg
&= ~PIO_CTRL_TYPE_MASK
;
744 if (pci_is_root_bus(bus
->parent
))
745 reg
|= PCIE_CONFIG_WR_TYPE0
;
747 reg
|= PCIE_CONFIG_WR_TYPE1
;
748 advk_writel(pcie
, reg
, PIO_CTRL
);
750 /* Program the address registers */
751 reg
= ALIGN_DOWN(PCIE_ECAM_OFFSET(bus
->number
, devfn
, where
), 4);
752 advk_writel(pcie
, reg
, PIO_ADDR_LS
);
753 advk_writel(pcie
, 0, PIO_ADDR_MS
);
755 /* Calculate the write strobe */
756 offset
= where
& 0x3;
757 reg
= val
<< (8 * offset
);
758 data_strobe
= GENMASK(size
- 1, 0) << offset
;
760 /* Program the data register */
761 advk_writel(pcie
, reg
, PIO_WR_DATA
);
763 /* Program the data strobe */
764 advk_writel(pcie
, data_strobe
, PIO_WR_DATA_STRB
);
766 /* Start the transfer */
767 advk_writel(pcie
, 1, PIO_START
);
769 ret
= advk_pcie_wait_pio(pcie
);
771 return PCIBIOS_SET_FAILED
;
773 advk_pcie_check_pio_status(pcie
);
775 return PCIBIOS_SUCCESSFUL
;
778 static struct pci_ops advk_pcie_ops
= {
779 .read
= advk_pcie_rd_conf
,
780 .write
= advk_pcie_wr_conf
,
783 static void advk_msi_irq_compose_msi_msg(struct irq_data
*data
,
786 struct advk_pcie
*pcie
= irq_data_get_irq_chip_data(data
);
787 phys_addr_t msi_msg
= virt_to_phys(&pcie
->msi_msg
);
789 msg
->address_lo
= lower_32_bits(msi_msg
);
790 msg
->address_hi
= upper_32_bits(msi_msg
);
791 msg
->data
= data
->irq
;
794 static int advk_msi_set_affinity(struct irq_data
*irq_data
,
795 const struct cpumask
*mask
, bool force
)
800 static int advk_msi_irq_domain_alloc(struct irq_domain
*domain
,
802 unsigned int nr_irqs
, void *args
)
804 struct advk_pcie
*pcie
= domain
->host_data
;
807 mutex_lock(&pcie
->msi_used_lock
);
808 hwirq
= bitmap_find_next_zero_area(pcie
->msi_used
, MSI_IRQ_NUM
,
810 if (hwirq
>= MSI_IRQ_NUM
) {
811 mutex_unlock(&pcie
->msi_used_lock
);
815 bitmap_set(pcie
->msi_used
, hwirq
, nr_irqs
);
816 mutex_unlock(&pcie
->msi_used_lock
);
818 for (i
= 0; i
< nr_irqs
; i
++)
819 irq_domain_set_info(domain
, virq
+ i
, hwirq
+ i
,
820 &pcie
->msi_bottom_irq_chip
,
821 domain
->host_data
, handle_simple_irq
,
827 static void advk_msi_irq_domain_free(struct irq_domain
*domain
,
828 unsigned int virq
, unsigned int nr_irqs
)
830 struct irq_data
*d
= irq_domain_get_irq_data(domain
, virq
);
831 struct advk_pcie
*pcie
= domain
->host_data
;
833 mutex_lock(&pcie
->msi_used_lock
);
834 bitmap_clear(pcie
->msi_used
, d
->hwirq
, nr_irqs
);
835 mutex_unlock(&pcie
->msi_used_lock
);
838 static const struct irq_domain_ops advk_msi_domain_ops
= {
839 .alloc
= advk_msi_irq_domain_alloc
,
840 .free
= advk_msi_irq_domain_free
,
843 static void advk_pcie_irq_mask(struct irq_data
*d
)
845 struct advk_pcie
*pcie
= d
->domain
->host_data
;
846 irq_hw_number_t hwirq
= irqd_to_hwirq(d
);
849 mask
= advk_readl(pcie
, PCIE_ISR1_MASK_REG
);
850 mask
|= PCIE_ISR1_INTX_ASSERT(hwirq
);
851 advk_writel(pcie
, mask
, PCIE_ISR1_MASK_REG
);
854 static void advk_pcie_irq_unmask(struct irq_data
*d
)
856 struct advk_pcie
*pcie
= d
->domain
->host_data
;
857 irq_hw_number_t hwirq
= irqd_to_hwirq(d
);
860 mask
= advk_readl(pcie
, PCIE_ISR1_MASK_REG
);
861 mask
&= ~PCIE_ISR1_INTX_ASSERT(hwirq
);
862 advk_writel(pcie
, mask
, PCIE_ISR1_MASK_REG
);
865 static int advk_pcie_irq_map(struct irq_domain
*h
,
866 unsigned int virq
, irq_hw_number_t hwirq
)
868 struct advk_pcie
*pcie
= h
->host_data
;
870 advk_pcie_irq_mask(irq_get_irq_data(virq
));
871 irq_set_status_flags(virq
, IRQ_LEVEL
);
872 irq_set_chip_and_handler(virq
, &pcie
->irq_chip
,
874 irq_set_chip_data(virq
, pcie
);
879 static const struct irq_domain_ops advk_pcie_irq_domain_ops
= {
880 .map
= advk_pcie_irq_map
,
881 .xlate
= irq_domain_xlate_onecell
,
884 static int advk_pcie_init_msi_irq_domain(struct advk_pcie
*pcie
)
886 struct device
*dev
= &pcie
->pdev
->dev
;
887 struct device_node
*node
= dev
->of_node
;
888 struct irq_chip
*bottom_ic
, *msi_ic
;
889 struct msi_domain_info
*msi_di
;
890 phys_addr_t msi_msg_phys
;
892 mutex_init(&pcie
->msi_used_lock
);
894 bottom_ic
= &pcie
->msi_bottom_irq_chip
;
896 bottom_ic
->name
= "MSI";
897 bottom_ic
->irq_compose_msi_msg
= advk_msi_irq_compose_msi_msg
;
898 bottom_ic
->irq_set_affinity
= advk_msi_set_affinity
;
900 msi_ic
= &pcie
->msi_irq_chip
;
901 msi_ic
->name
= "advk-MSI";
903 msi_di
= &pcie
->msi_domain_info
;
904 msi_di
->flags
= MSI_FLAG_USE_DEF_DOM_OPS
| MSI_FLAG_USE_DEF_CHIP_OPS
|
905 MSI_FLAG_MULTI_PCI_MSI
;
906 msi_di
->chip
= msi_ic
;
908 msi_msg_phys
= virt_to_phys(&pcie
->msi_msg
);
910 advk_writel(pcie
, lower_32_bits(msi_msg_phys
),
911 PCIE_MSI_ADDR_LOW_REG
);
912 advk_writel(pcie
, upper_32_bits(msi_msg_phys
),
913 PCIE_MSI_ADDR_HIGH_REG
);
915 pcie
->msi_inner_domain
=
916 irq_domain_add_linear(NULL
, MSI_IRQ_NUM
,
917 &advk_msi_domain_ops
, pcie
);
918 if (!pcie
->msi_inner_domain
)
922 pci_msi_create_irq_domain(of_node_to_fwnode(node
),
923 msi_di
, pcie
->msi_inner_domain
);
924 if (!pcie
->msi_domain
) {
925 irq_domain_remove(pcie
->msi_inner_domain
);
932 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie
*pcie
)
934 irq_domain_remove(pcie
->msi_domain
);
935 irq_domain_remove(pcie
->msi_inner_domain
);
938 static int advk_pcie_init_irq_domain(struct advk_pcie
*pcie
)
940 struct device
*dev
= &pcie
->pdev
->dev
;
941 struct device_node
*node
= dev
->of_node
;
942 struct device_node
*pcie_intc_node
;
943 struct irq_chip
*irq_chip
;
946 pcie_intc_node
= of_get_next_child(node
, NULL
);
947 if (!pcie_intc_node
) {
948 dev_err(dev
, "No PCIe Intc node found\n");
952 irq_chip
= &pcie
->irq_chip
;
954 irq_chip
->name
= devm_kasprintf(dev
, GFP_KERNEL
, "%s-irq",
956 if (!irq_chip
->name
) {
961 irq_chip
->irq_mask
= advk_pcie_irq_mask
;
962 irq_chip
->irq_mask_ack
= advk_pcie_irq_mask
;
963 irq_chip
->irq_unmask
= advk_pcie_irq_unmask
;
966 irq_domain_add_linear(pcie_intc_node
, PCI_NUM_INTX
,
967 &advk_pcie_irq_domain_ops
, pcie
);
968 if (!pcie
->irq_domain
) {
969 dev_err(dev
, "Failed to get a INTx IRQ domain\n");
975 of_node_put(pcie_intc_node
);
979 static void advk_pcie_remove_irq_domain(struct advk_pcie
*pcie
)
981 irq_domain_remove(pcie
->irq_domain
);
984 static void advk_pcie_handle_msi(struct advk_pcie
*pcie
)
986 u32 msi_val
, msi_mask
, msi_status
, msi_idx
;
989 msi_mask
= advk_readl(pcie
, PCIE_MSI_MASK_REG
);
990 msi_val
= advk_readl(pcie
, PCIE_MSI_STATUS_REG
);
991 msi_status
= msi_val
& ~msi_mask
;
993 for (msi_idx
= 0; msi_idx
< MSI_IRQ_NUM
; msi_idx
++) {
994 if (!(BIT(msi_idx
) & msi_status
))
997 advk_writel(pcie
, BIT(msi_idx
), PCIE_MSI_STATUS_REG
);
998 msi_data
= advk_readl(pcie
, PCIE_MSI_PAYLOAD_REG
) & 0xFF;
999 generic_handle_irq(msi_data
);
1002 advk_writel(pcie
, PCIE_ISR0_MSI_INT_PENDING
,
1006 static void advk_pcie_handle_int(struct advk_pcie
*pcie
)
1008 u32 isr0_val
, isr0_mask
, isr0_status
;
1009 u32 isr1_val
, isr1_mask
, isr1_status
;
1012 isr0_val
= advk_readl(pcie
, PCIE_ISR0_REG
);
1013 isr0_mask
= advk_readl(pcie
, PCIE_ISR0_MASK_REG
);
1014 isr0_status
= isr0_val
& ((~isr0_mask
) & PCIE_ISR0_ALL_MASK
);
1016 isr1_val
= advk_readl(pcie
, PCIE_ISR1_REG
);
1017 isr1_mask
= advk_readl(pcie
, PCIE_ISR1_MASK_REG
);
1018 isr1_status
= isr1_val
& ((~isr1_mask
) & PCIE_ISR1_ALL_MASK
);
1020 if (!isr0_status
&& !isr1_status
) {
1021 advk_writel(pcie
, isr0_val
, PCIE_ISR0_REG
);
1022 advk_writel(pcie
, isr1_val
, PCIE_ISR1_REG
);
1026 /* Process MSI interrupts */
1027 if (isr0_status
& PCIE_ISR0_MSI_INT_PENDING
)
1028 advk_pcie_handle_msi(pcie
);
1030 /* Process legacy interrupts */
1031 for (i
= 0; i
< PCI_NUM_INTX
; i
++) {
1032 if (!(isr1_status
& PCIE_ISR1_INTX_ASSERT(i
)))
1035 advk_writel(pcie
, PCIE_ISR1_INTX_ASSERT(i
),
1038 virq
= irq_find_mapping(pcie
->irq_domain
, i
);
1039 generic_handle_irq(virq
);
1043 static irqreturn_t
advk_pcie_irq_handler(int irq
, void *arg
)
1045 struct advk_pcie
*pcie
= arg
;
1048 status
= advk_readl(pcie
, HOST_CTRL_INT_STATUS_REG
);
1049 if (!(status
& PCIE_IRQ_CORE_INT
))
1052 advk_pcie_handle_int(pcie
);
1054 /* Clear interrupt */
1055 advk_writel(pcie
, PCIE_IRQ_CORE_INT
, HOST_CTRL_INT_STATUS_REG
);
1060 static void __maybe_unused
advk_pcie_disable_phy(struct advk_pcie
*pcie
)
1062 phy_power_off(pcie
->phy
);
1063 phy_exit(pcie
->phy
);
1066 static int advk_pcie_enable_phy(struct advk_pcie
*pcie
)
1073 ret
= phy_init(pcie
->phy
);
1077 ret
= phy_set_mode(pcie
->phy
, PHY_MODE_PCIE
);
1079 phy_exit(pcie
->phy
);
1083 ret
= phy_power_on(pcie
->phy
);
1084 if (ret
== -EOPNOTSUPP
) {
1085 dev_warn(&pcie
->pdev
->dev
, "PHY unsupported by firmware\n");
1087 phy_exit(pcie
->phy
);
1094 static int advk_pcie_setup_phy(struct advk_pcie
*pcie
)
1096 struct device
*dev
= &pcie
->pdev
->dev
;
1097 struct device_node
*node
= dev
->of_node
;
1100 pcie
->phy
= devm_of_phy_get(dev
, node
, NULL
);
1101 if (IS_ERR(pcie
->phy
) && (PTR_ERR(pcie
->phy
) == -EPROBE_DEFER
))
1102 return PTR_ERR(pcie
->phy
);
1104 /* Old bindings miss the PHY handle */
1105 if (IS_ERR(pcie
->phy
)) {
1106 dev_warn(dev
, "PHY unavailable (%ld)\n", PTR_ERR(pcie
->phy
));
1111 ret
= advk_pcie_enable_phy(pcie
);
1113 dev_err(dev
, "Failed to initialize PHY (%d)\n", ret
);
1118 static int advk_pcie_probe(struct platform_device
*pdev
)
1120 struct device
*dev
= &pdev
->dev
;
1121 struct advk_pcie
*pcie
;
1122 struct pci_host_bridge
*bridge
;
1125 bridge
= devm_pci_alloc_host_bridge(dev
, sizeof(struct advk_pcie
));
1129 pcie
= pci_host_bridge_priv(bridge
);
1131 platform_set_drvdata(pdev
, pcie
);
1133 pcie
->base
= devm_platform_ioremap_resource(pdev
, 0);
1134 if (IS_ERR(pcie
->base
))
1135 return PTR_ERR(pcie
->base
);
1137 irq
= platform_get_irq(pdev
, 0);
1141 ret
= devm_request_irq(dev
, irq
, advk_pcie_irq_handler
,
1142 IRQF_SHARED
| IRQF_NO_THREAD
, "advk-pcie",
1145 dev_err(dev
, "Failed to register interrupt\n");
1149 pcie
->reset_gpio
= devm_gpiod_get_from_of_node(dev
, dev
->of_node
,
1153 ret
= PTR_ERR_OR_ZERO(pcie
->reset_gpio
);
1155 if (ret
== -ENOENT
) {
1156 pcie
->reset_gpio
= NULL
;
1158 if (ret
!= -EPROBE_DEFER
)
1159 dev_err(dev
, "Failed to get reset-gpio: %i\n",
1165 ret
= of_pci_get_max_link_speed(dev
->of_node
);
1166 if (ret
<= 0 || ret
> 3)
1169 pcie
->link_gen
= ret
;
1171 ret
= advk_pcie_setup_phy(pcie
);
1175 advk_pcie_setup_hw(pcie
);
1177 ret
= advk_sw_pci_bridge_init(pcie
);
1179 dev_err(dev
, "Failed to register emulated root PCI bridge\n");
1183 ret
= advk_pcie_init_irq_domain(pcie
);
1185 dev_err(dev
, "Failed to initialize irq\n");
1189 ret
= advk_pcie_init_msi_irq_domain(pcie
);
1191 dev_err(dev
, "Failed to initialize irq\n");
1192 advk_pcie_remove_irq_domain(pcie
);
1196 bridge
->sysdata
= pcie
;
1197 bridge
->ops
= &advk_pcie_ops
;
1199 ret
= pci_host_probe(bridge
);
1201 advk_pcie_remove_msi_irq_domain(pcie
);
1202 advk_pcie_remove_irq_domain(pcie
);
1209 static int advk_pcie_remove(struct platform_device
*pdev
)
1211 struct advk_pcie
*pcie
= platform_get_drvdata(pdev
);
1212 struct pci_host_bridge
*bridge
= pci_host_bridge_from_priv(pcie
);
1214 pci_lock_rescan_remove();
1215 pci_stop_root_bus(bridge
->bus
);
1216 pci_remove_root_bus(bridge
->bus
);
1217 pci_unlock_rescan_remove();
1219 advk_pcie_remove_msi_irq_domain(pcie
);
1220 advk_pcie_remove_irq_domain(pcie
);
1225 static const struct of_device_id advk_pcie_of_match_table
[] = {
1226 { .compatible
= "marvell,armada-3700-pcie", },
1229 MODULE_DEVICE_TABLE(of
, advk_pcie_of_match_table
);
1231 static struct platform_driver advk_pcie_driver
= {
1233 .name
= "advk-pcie",
1234 .of_match_table
= advk_pcie_of_match_table
,
1236 .probe
= advk_pcie_probe
,
1237 .remove
= advk_pcie_remove
,
1239 module_platform_driver(advk_pcie_driver
);
1241 MODULE_DESCRIPTION("Aardvark PCIe controller");
1242 MODULE_LICENSE("GPL v2");