drivers/pci/controller/pcie-altera.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright Altera Corporation (C) 2013-2015. All rights reserved
   4  *
   5  * Author: Ley Foon Tan <lftan@altera.com>
   6  * Description: Altera PCIe host controller driver
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/irqchip/chained_irq.h>
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/of_pci.h>
  18 #include <linux/pci.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/slab.h>
  21
  22 #include "../pci.h"
  23
  24 #define RP_TX_REG0                      0x2000
  25 #define RP_TX_REG1                      0x2004
  26 #define RP_TX_CNTRL                     0x2008
  27 #define RP_TX_EOP                       0x2
  28 #define RP_TX_SOP                       0x1
  29 #define RP_RXCPL_STATUS                 0x2010
  30 #define RP_RXCPL_EOP                    0x2
  31 #define RP_RXCPL_SOP                    0x1
  32 #define RP_RXCPL_REG0                   0x2014
  33 #define RP_RXCPL_REG1                   0x2018
  34 #define P2A_INT_STATUS                  0x3060
  35 #define P2A_INT_STS_ALL                 0xf
  36 #define P2A_INT_ENABLE                  0x3070
  37 #define P2A_INT_ENA_ALL                 0xf
  38 #define RP_LTSSM                        0x3c64
  39 #define RP_LTSSM_MASK                   0x1f
  40 #define LTSSM_L0                        0xf
  41
  42 #define S10_RP_TX_CNTRL                 0x2004
  43 #define S10_RP_RXCPL_REG                0x2008
  44 #define S10_RP_RXCPL_STATUS             0x200C
  45 #define S10_RP_CFG_ADDR(pcie, reg)      \
  46         (((pcie)->hip_base) + (reg) + (1 << 20))
  47 #define S10_RP_SECONDARY(pcie)          \
  48         readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
  49
  50 /* TLP configuration type 0 and 1 */
  51 #define TLP_FMTTYPE_CFGRD0              0x04    /* Configuration Read Type 0 */
  52 #define TLP_FMTTYPE_CFGWR0              0x44    /* Configuration Write Type 0 */
  53 #define TLP_FMTTYPE_CFGRD1              0x05    /* Configuration Read Type 1 */
  54 #define TLP_FMTTYPE_CFGWR1              0x45    /* Configuration Write Type 1 */
  55 #define TLP_PAYLOAD_SIZE                0x01
  56 #define TLP_READ_TAG                    0x1d
  57 #define TLP_WRITE_TAG                   0x10
  58 #define RP_DEVFN                        0
  59 #define TLP_REQ_ID(bus, devfn)          (((bus) << 8) | (devfn))
  60 #define TLP_CFG_DW0(pcie, cfg)          \
  61                 (((cfg) << 24) |        \
  62                   TLP_PAYLOAD_SIZE)
  63 #define TLP_CFG_DW1(pcie, tag, be)      \
  64         (((TLP_REQ_ID(pcie->root_bus_nr,  RP_DEVFN)) << 16) | (tag << 8) | (be))
  65 #define TLP_CFG_DW2(bus, devfn, offset) \
  66                                 (((bus) << 24) | ((devfn) << 16) | (offset))
  67 #define TLP_COMP_STATUS(s)              (((s) >> 13) & 7)
  68 #define TLP_BYTE_COUNT(s)               (((s) >> 0) & 0xfff)
  69 #define TLP_HDR_SIZE                    3
  70 #define TLP_LOOP                        500
  71
  72 #define LINK_UP_TIMEOUT                 HZ
  73 #define LINK_RETRAIN_TIMEOUT            HZ
  74
  75 #define DWORD_MASK                      3
  76
  77 #define S10_TLP_FMTTYPE_CFGRD0          0x05
  78 #define S10_TLP_FMTTYPE_CFGRD1          0x04
  79 #define S10_TLP_FMTTYPE_CFGWR0          0x45
  80 #define S10_TLP_FMTTYPE_CFGWR1          0x44
  81
  82 enum altera_pcie_version {
  83         ALTERA_PCIE_V1 = 0,
  84         ALTERA_PCIE_V2,
  85 };
  86
  87 struct altera_pcie {
  88         struct platform_device  *pdev;
  89         void __iomem            *cra_base;
  90         void __iomem            *hip_base;
  91         int                     irq;
  92         u8                      root_bus_nr;
  93         struct irq_domain       *irq_domain;
  94         struct resource         bus_range;
  95         const struct altera_pcie_data   *pcie_data;
  96 };
  97
  98 struct altera_pcie_ops {
  99         int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
 100         void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
 101                               u32 data, bool align);
 102         bool (*get_link_status)(struct altera_pcie *pcie);
 103         int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
 104                            int size, u32 *value);
 105         int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
 106                             int where, int size, u32 value);
 107 };
 108
 109 struct altera_pcie_data {
 110         const struct altera_pcie_ops *ops;
 111         enum altera_pcie_version version;
 112         u32 cap_offset;         /* PCIe capability structure register offset */
 113         u32 cfgrd0;
 114         u32 cfgrd1;
 115         u32 cfgwr0;
 116         u32 cfgwr1;
 117 };
 118
 119 struct tlp_rp_regpair_t {
 120         u32 ctrl;
 121         u32 reg0;
 122         u32 reg1;
 123 };
 124
 125 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
 126                               const u32 reg)
 127 {
 128         writel_relaxed(value, pcie->cra_base + reg);
 129 }
 130
 131 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
 132 {
 133         return readl_relaxed(pcie->cra_base + reg);
 134 }
 135
 136 static bool altera_pcie_link_up(struct altera_pcie *pcie)
 137 {
 138         return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
 139 }
 140
 141 static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
 142 {
 143         void __iomem *addr = S10_RP_CFG_ADDR(pcie,
 144                                    pcie->pcie_data->cap_offset +
 145                                    PCI_EXP_LNKSTA);
 146
 147         return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA);
 148 }
 149
 150 /*
 151  * Altera PCIe port uses BAR0 of RC's configuration space as the translation
 152  * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
 153  * using these registers, so it can be reached by DMA from EP devices.
 154  * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
 155  * from EP devices, eventually trigger interrupt to GIC.  The BAR0 of bridge
 156  * should be hidden during enumeration to avoid the sizing and resource
 157  * allocation by PCIe core.
 158  */
 159 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int  devfn,
 160                                     int offset)
 161 {
 162         if (pci_is_root_bus(bus) && (devfn == 0) &&
 163             (offset == PCI_BASE_ADDRESS_0))
 164                 return true;
 165
 166         return false;
 167 }
 168
 169 static void tlp_write_tx(struct altera_pcie *pcie,
 170                          struct tlp_rp_regpair_t *tlp_rp_regdata)
 171 {
 172         cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
 173         cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
 174         cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
 175 }
 176
 177 static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl)
 178 {
 179         cra_writel(pcie, reg0, RP_TX_REG0);
 180         cra_writel(pcie, ctrl, S10_RP_TX_CNTRL);
 181 }
 182
 183 static bool altera_pcie_valid_device(struct altera_pcie *pcie,
 184                                      struct pci_bus *bus, int dev)
 185 {
 186         /* If there is no link, then there is no device */
 187         if (bus->number != pcie->root_bus_nr) {
 188                 if (!pcie->pcie_data->ops->get_link_status(pcie))
 189                         return false;
 190         }
 191
 192         /* access only one slot on each root port */
 193         if (bus->number == pcie->root_bus_nr && dev > 0)
 194                 return false;
 195
 196         return true;
 197 }
 198
 199 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
 200 {
 201         int i;
 202         bool sop = false;
 203         u32 ctrl;
 204         u32 reg0, reg1;
 205         u32 comp_status = 1;
 206
 207         /*
 208          * Minimum 2 loops to read TLP headers and 1 loop to read data
 209          * payload.
 210          */
 211         for (i = 0; i < TLP_LOOP; i++) {
 212                 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
 213                 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
 214                         reg0 = cra_readl(pcie, RP_RXCPL_REG0);
 215                         reg1 = cra_readl(pcie, RP_RXCPL_REG1);
 216
 217                         if (ctrl & RP_RXCPL_SOP) {
 218                                 sop = true;
 219                                 comp_status = TLP_COMP_STATUS(reg1);
 220                         }
 221
 222                         if (ctrl & RP_RXCPL_EOP) {
 223                                 if (comp_status)
 224                                         return PCIBIOS_DEVICE_NOT_FOUND;
 225
 226                                 if (value)
 227                                         *value = reg0;
 228
 229                                 return PCIBIOS_SUCCESSFUL;
 230                         }
 231                 }
 232                 udelay(5);
 233         }
 234
 235         return PCIBIOS_DEVICE_NOT_FOUND;
 236 }
 237
 238 static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value)
 239 {
 240         u32 ctrl;
 241         u32 comp_status;
 242         u32 dw[4];
 243         u32 count;
 244         struct device *dev = &pcie->pdev->dev;
 245
 246         for (count = 0; count < TLP_LOOP; count++) {
 247                 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
 248                 if (ctrl & RP_RXCPL_SOP) {
 249                         /* Read first DW */
 250                         dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);
 251                         break;
 252                 }
 253
 254                 udelay(5);
 255         }
 256
 257         /* SOP detection failed, return error */
 258         if (count == TLP_LOOP)
 259                 return PCIBIOS_DEVICE_NOT_FOUND;
 260
 261         count = 1;
 262
 263         /* Poll for EOP */
 264         while (count < ARRAY_SIZE(dw)) {
 265                 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
 266                 dw[count++] = cra_readl(pcie, S10_RP_RXCPL_REG);
 267                 if (ctrl & RP_RXCPL_EOP) {
 268                         comp_status = TLP_COMP_STATUS(dw[1]);
 269                         if (comp_status)
 270                                 return PCIBIOS_DEVICE_NOT_FOUND;
 271
 272                         if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
 273                             count == 4)
 274                                 *value = dw[3];
 275
 276                         return PCIBIOS_SUCCESSFUL;
 277                 }
 278         }
 279
 280         dev_warn(dev, "Malformed TLP packet\n");
 281
 282         return PCIBIOS_DEVICE_NOT_FOUND;
 283 }
 284
 285 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
 286                              u32 data, bool align)
 287 {
 288         struct tlp_rp_regpair_t tlp_rp_regdata;
 289
 290         tlp_rp_regdata.reg0 = headers[0];
 291         tlp_rp_regdata.reg1 = headers[1];
 292         tlp_rp_regdata.ctrl = RP_TX_SOP;
 293         tlp_write_tx(pcie, &tlp_rp_regdata);
 294
 295         if (align) {
 296                 tlp_rp_regdata.reg0 = headers[2];
 297                 tlp_rp_regdata.reg1 = 0;
 298                 tlp_rp_regdata.ctrl = 0;
 299                 tlp_write_tx(pcie, &tlp_rp_regdata);
 300
 301                 tlp_rp_regdata.reg0 = data;
 302                 tlp_rp_regdata.reg1 = 0;
 303         } else {
 304                 tlp_rp_regdata.reg0 = headers[2];
 305                 tlp_rp_regdata.reg1 = data;
 306         }
 307
 308         tlp_rp_regdata.ctrl = RP_TX_EOP;
 309         tlp_write_tx(pcie, &tlp_rp_regdata);
 310 }
 311
 312 static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
 313                                  u32 data, bool dummy)
 314 {
 315         s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);
 316         s10_tlp_write_tx(pcie, headers[1], 0);
 317         s10_tlp_write_tx(pcie, headers[2], 0);
 318         s10_tlp_write_tx(pcie, data, RP_TX_EOP);
 319 }
 320
 321 static void get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn,
 322                            int where, u8 byte_en, bool read, u32 *headers)
 323 {
 324         u8 cfg;
 325         u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0;
 326         u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1;
 327         u8 tag = read ? TLP_READ_TAG : TLP_WRITE_TAG;
 328
 329         if (pcie->pcie_data->version == ALTERA_PCIE_V1)
 330                 cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1;
 331         else
 332                 cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1;
 333
 334         headers[0] = TLP_CFG_DW0(pcie, cfg);
 335         headers[1] = TLP_CFG_DW1(pcie, tag, byte_en);
 336         headers[2] = TLP_CFG_DW2(bus, devfn, where);
 337 }
 338
 339 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
 340                               int where, u8 byte_en, u32 *value)
 341 {
 342         u32 headers[TLP_HDR_SIZE];
 343
 344         get_tlp_header(pcie, bus, devfn, where, byte_en, true,
 345                        headers);
 346
 347         pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);
 348
 349         return pcie->pcie_data->ops->tlp_read_pkt(pcie, value);
 350 }
 351
 352 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
 353                                int where, u8 byte_en, u32 value)
 354 {
 355         u32 headers[TLP_HDR_SIZE];
 356         int ret;
 357
 358         get_tlp_header(pcie, bus, devfn, where, byte_en, false,
 359                        headers);
 360
 361         /* check alignment to Qword */
 362         if ((where & 0x7) == 0)
 363                 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
 364                                                     value, true);
 365         else
 366                 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,
 367                                                     value, false);
 368
 369         ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL);
 370         if (ret != PCIBIOS_SUCCESSFUL)
 371                 return ret;
 372
 373         /*
 374          * Monitor changes to PCI_PRIMARY_BUS register on root port
 375          * and update local copy of root bus number accordingly.
 376          */
 377         if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
 378                 pcie->root_bus_nr = (u8)(value);
 379
 380         return PCIBIOS_SUCCESSFUL;
 381 }
 382
 383 static int s10_rp_read_cfg(struct altera_pcie *pcie, int where,
 384                            int size, u32 *value)
 385 {
 386         void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
 387
 388         switch (size) {
 389         case 1:
 390                 *value = readb(addr);
 391                 break;
 392         case 2:
 393                 *value = readw(addr);
 394                 break;
 395         default:
 396                 *value = readl(addr);
 397                 break;
 398         }
 399
 400         return PCIBIOS_SUCCESSFUL;
 401 }
 402
 403 static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno,
 404                             int where, int size, u32 value)
 405 {
 406         void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);
 407
 408         switch (size) {
 409         case 1:
 410                 writeb(value, addr);
 411                 break;
 412         case 2:
 413                 writew(value, addr);
 414                 break;
 415         default:
 416                 writel(value, addr);
 417                 break;
 418         }
 419
 420         /*
 421          * Monitor changes to PCI_PRIMARY_BUS register on root port
 422          * and update local copy of root bus number accordingly.
 423          */
 424         if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)
 425                 pcie->root_bus_nr = value & 0xff;
 426
 427         return PCIBIOS_SUCCESSFUL;
 428 }
 429
 430 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
 431                                  unsigned int devfn, int where, int size,
 432                                  u32 *value)
 433 {
 434         int ret;
 435         u32 data;
 436         u8 byte_en;
 437
 438         if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg)
 439                 return pcie->pcie_data->ops->rp_read_cfg(pcie, where,
 440                                                          size, value);
 441
 442         switch (size) {
 443         case 1:
 444                 byte_en = 1 << (where & 3);
 445                 break;
 446         case 2:
 447                 byte_en = 3 << (where & 3);
 448                 break;
 449         default:
 450                 byte_en = 0xf;
 451                 break;
 452         }
 453
 454         ret = tlp_cfg_dword_read(pcie, busno, devfn,
 455                                  (where & ~DWORD_MASK), byte_en, &data);
 456         if (ret != PCIBIOS_SUCCESSFUL)
 457                 return ret;
 458
 459         switch (size) {
 460         case 1:
 461                 *value = (data >> (8 * (where & 0x3))) & 0xff;
 462                 break;
 463         case 2:
 464                 *value = (data >> (8 * (where & 0x2))) & 0xffff;
 465                 break;
 466         default:
 467                 *value = data;
 468                 break;
 469         }
 470
 471         return PCIBIOS_SUCCESSFUL;
 472 }
 473
 474 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
 475                                   unsigned int devfn, int where, int size,
 476                                   u32 value)
 477 {
 478         u32 data32;
 479         u32 shift = 8 * (where & 3);
 480         u8 byte_en;
 481
 482         if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg)
 483                 return pcie->pcie_data->ops->rp_write_cfg(pcie, busno,
 484                                                      where, size, value);
 485
 486         switch (size) {
 487         case 1:
 488                 data32 = (value & 0xff) << shift;
 489                 byte_en = 1 << (where & 3);
 490                 break;
 491         case 2:
 492                 data32 = (value & 0xffff) << shift;
 493                 byte_en = 3 << (where & 3);
 494                 break;
 495         default:
 496                 data32 = value;
 497                 byte_en = 0xf;
 498                 break;
 499         }
 500
 501         return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
 502                                    byte_en, data32);
 503 }
 504
 505 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
 506                                 int where, int size, u32 *value)
 507 {
 508         struct altera_pcie *pcie = bus->sysdata;
 509
 510         if (altera_pcie_hide_rc_bar(bus, devfn, where))
 511                 return PCIBIOS_BAD_REGISTER_NUMBER;
 512
 513         if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) {
 514                 *value = 0xffffffff;
 515                 return PCIBIOS_DEVICE_NOT_FOUND;
 516         }
 517
 518         return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
 519                                      value);
 520 }
 521
 522 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
 523                                  int where, int size, u32 value)
 524 {
 525         struct altera_pcie *pcie = bus->sysdata;
 526
 527         if (altera_pcie_hide_rc_bar(bus, devfn, where))
 528                 return PCIBIOS_BAD_REGISTER_NUMBER;
 529
 530         if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
 531                 return PCIBIOS_DEVICE_NOT_FOUND;
 532
 533         return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
 534                                      value);
 535 }
 536
 537 static struct pci_ops altera_pcie_ops = {
 538         .read = altera_pcie_cfg_read,
 539         .write = altera_pcie_cfg_write,
 540 };
 541
 542 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
 543                                 unsigned int devfn, int offset, u16 *value)
 544 {
 545         u32 data;
 546         int ret;
 547
 548         ret = _altera_pcie_cfg_read(pcie, busno, devfn,
 549                                     pcie->pcie_data->cap_offset + offset,
 550                                     sizeof(*value),
 551                                     &data);
 552         *value = data;
 553         return ret;
 554 }
 555
 556 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
 557                                  unsigned int devfn, int offset, u16 value)
 558 {
 559         return _altera_pcie_cfg_write(pcie, busno, devfn,
 560                                       pcie->pcie_data->cap_offset + offset,
 561                                       sizeof(value),
 562                                       value);
 563 }
 564
 565 static void altera_wait_link_retrain(struct altera_pcie *pcie)
 566 {
 567         struct device *dev = &pcie->pdev->dev;
 568         u16 reg16;
 569         unsigned long start_jiffies;
 570
 571         /* Wait for link training end. */
 572         start_jiffies = jiffies;
 573         for (;;) {
 574                 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 575                                      PCI_EXP_LNKSTA, &reg16);
 576                 if (!(reg16 & PCI_EXP_LNKSTA_LT))
 577                         break;
 578
 579                 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
 580                         dev_err(dev, "link retrain timeout\n");
 581                         break;
 582                 }
 583                 udelay(100);
 584         }
 585
 586         /* Wait for link is up */
 587         start_jiffies = jiffies;
 588         for (;;) {
 589                 if (pcie->pcie_data->ops->get_link_status(pcie))
 590                         break;
 591
 592                 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
 593                         dev_err(dev, "link up timeout\n");
 594                         break;
 595                 }
 596                 udelay(100);
 597         }
 598 }
 599
 600 static void altera_pcie_retrain(struct altera_pcie *pcie)
 601 {
 602         u16 linkcap, linkstat, linkctl;
 603
 604         if (!pcie->pcie_data->ops->get_link_status(pcie))
 605                 return;
 606
 607         /*
 608          * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
 609          * current speed is 2.5 GB/s.
 610          */
 611         altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
 612                              &linkcap);
 613         if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
 614                 return;
 615
 616         altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
 617                              &linkstat);
 618         if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
 619                 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 620                                      PCI_EXP_LNKCTL, &linkctl);
 621                 linkctl |= PCI_EXP_LNKCTL_RL;
 622                 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
 623                                       PCI_EXP_LNKCTL, linkctl);
 624
 625                 altera_wait_link_retrain(pcie);
 626         }
 627 }
 628
 629 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 630                                 irq_hw_number_t hwirq)
 631 {
 632         irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
 633         irq_set_chip_data(irq, domain->host_data);
 634         return 0;
 635 }
 636
 637 static const struct irq_domain_ops intx_domain_ops = {
 638         .map = altera_pcie_intx_map,
 639         .xlate = pci_irqd_intx_xlate,
 640 };
 641
 642 static void altera_pcie_isr(struct irq_desc *desc)
 643 {
 644         struct irq_chip *chip = irq_desc_get_chip(desc);
 645         struct altera_pcie *pcie;
 646         struct device *dev;
 647         unsigned long status;
 648         u32 bit;
 649         u32 virq;
 650
 651         chained_irq_enter(chip, desc);
 652         pcie = irq_desc_get_handler_data(desc);
 653         dev = &pcie->pdev->dev;
 654
 655         while ((status = cra_readl(pcie, P2A_INT_STATUS)
 656                 & P2A_INT_STS_ALL) != 0) {
 657                 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
 658                         /* clear interrupts */
 659                         cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
 660
 661                         virq = irq_find_mapping(pcie->irq_domain, bit);
 662                         if (virq)
 663                                 generic_handle_irq(virq);
 664                         else
 665                                 dev_err(dev, "unexpected IRQ, INT%d\n", bit);
 666                 }
 667         }
 668
 669         chained_irq_exit(chip, desc);
 670 }
 671
 672 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
 673 {
 674         struct device *dev = &pcie->pdev->dev;
 675         struct device_node *node = dev->of_node;
 676
 677         /* Setup INTx */
 678         pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
 679                                         &intx_domain_ops, pcie);
 680         if (!pcie->irq_domain) {
 681                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 682                 return -ENOMEM;
 683         }
 684
 685         return 0;
 686 }
 687
 688 static void altera_pcie_irq_teardown(struct altera_pcie *pcie)
 689 {
 690         irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
 691         irq_domain_remove(pcie->irq_domain);
 692         irq_dispose_mapping(pcie->irq);
 693 }
 694
 695 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
 696 {
 697         struct platform_device *pdev = pcie->pdev;
 698
 699         pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");
 700         if (IS_ERR(pcie->cra_base))
 701                 return PTR_ERR(pcie->cra_base);
 702
 703         if (pcie->pcie_data->version == ALTERA_PCIE_V2) {
 704                 pcie->hip_base =
 705                         devm_platform_ioremap_resource_byname(pdev, "Hip");
 706                 if (IS_ERR(pcie->hip_base))
 707                         return PTR_ERR(pcie->hip_base);
 708         }
 709
 710         /* setup IRQ */
 711         pcie->irq = platform_get_irq(pdev, 0);
 712         if (pcie->irq < 0)
 713                 return pcie->irq;
 714
 715         irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
 716         return 0;
 717 }
 718
 719 static void altera_pcie_host_init(struct altera_pcie *pcie)
 720 {
 721         altera_pcie_retrain(pcie);
 722 }
 723
 724 static const struct altera_pcie_ops altera_pcie_ops_1_0 = {
 725         .tlp_read_pkt = tlp_read_packet,
 726         .tlp_write_pkt = tlp_write_packet,
 727         .get_link_status = altera_pcie_link_up,
 728 };
 729
 730 static const struct altera_pcie_ops altera_pcie_ops_2_0 = {
 731         .tlp_read_pkt = s10_tlp_read_packet,
 732         .tlp_write_pkt = s10_tlp_write_packet,
 733         .get_link_status = s10_altera_pcie_link_up,
 734         .rp_read_cfg = s10_rp_read_cfg,
 735         .rp_write_cfg = s10_rp_write_cfg,
 736 };
 737
 738 static const struct altera_pcie_data altera_pcie_1_0_data = {
 739         .ops = &altera_pcie_ops_1_0,
 740         .cap_offset = 0x80,
 741         .version = ALTERA_PCIE_V1,
 742         .cfgrd0 = TLP_FMTTYPE_CFGRD0,
 743         .cfgrd1 = TLP_FMTTYPE_CFGRD1,
 744         .cfgwr0 = TLP_FMTTYPE_CFGWR0,
 745         .cfgwr1 = TLP_FMTTYPE_CFGWR1,
 746 };
 747
 748 static const struct altera_pcie_data altera_pcie_2_0_data = {
 749         .ops = &altera_pcie_ops_2_0,
 750         .version = ALTERA_PCIE_V2,
 751         .cap_offset = 0x70,
 752         .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0,
 753         .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1,
 754         .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0,
 755         .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1,
 756 };
 757
 758 static const struct of_device_id altera_pcie_of_match[] = {
 759         {.compatible = "altr,pcie-root-port-1.0",
 760          .data = &altera_pcie_1_0_data },
 761         {.compatible = "altr,pcie-root-port-2.0",
 762          .data = &altera_pcie_2_0_data },
 763         {},
 764 };
 765
 766 static int altera_pcie_probe(struct platform_device *pdev)
 767 {
 768         struct device *dev = &pdev->dev;
 769         struct altera_pcie *pcie;
 770         struct pci_host_bridge *bridge;
 771         int ret;
 772         const struct of_device_id *match;
 773
 774         bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
 775         if (!bridge)
 776                 return -ENOMEM;
 777
 778         pcie = pci_host_bridge_priv(bridge);
 779         pcie->pdev = pdev;
 780         platform_set_drvdata(pdev, pcie);
 781
 782         match = of_match_device(altera_pcie_of_match, &pdev->dev);
 783         if (!match)
 784                 return -ENODEV;
 785
 786         pcie->pcie_data = match->data;
 787
 788         ret = altera_pcie_parse_dt(pcie);
 789         if (ret) {
 790                 dev_err(dev, "Parsing DT failed\n");
 791                 return ret;
 792         }
 793
 794         ret = altera_pcie_init_irq_domain(pcie);
 795         if (ret) {
 796                 dev_err(dev, "Failed creating IRQ Domain\n");
 797                 return ret;
 798         }
 799
 800         /* clear all interrupts */
 801         cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
 802         /* enable all interrupts */
 803         cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
 804         altera_pcie_host_init(pcie);
 805
 806         bridge->sysdata = pcie;
 807         bridge->busnr = pcie->root_bus_nr;
 808         bridge->ops = &altera_pcie_ops;
 809
 810         return pci_host_probe(bridge);
 811 }
 812
 813 static int altera_pcie_remove(struct platform_device *pdev)
 814 {
 815         struct altera_pcie *pcie = platform_get_drvdata(pdev);
 816         struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
 817
 818         pci_stop_root_bus(bridge->bus);
 819         pci_remove_root_bus(bridge->bus);
 820         altera_pcie_irq_teardown(pcie);
 821
 822         return 0;
 823 }
 824
 825 static struct platform_driver altera_pcie_driver = {
 826         .probe          = altera_pcie_probe,
 827         .remove         = altera_pcie_remove,
 828         .driver = {
 829                 .name   = "altera-pcie",
 830                 .of_match_table = altera_pcie_of_match,
 831         },
 832 };
 833
 834 MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
 835 module_platform_driver(altera_pcie_driver);
 836 MODULE_LICENSE("GPL v2");