1 // SPDX-License-Identifier: GPL-2.0
3 * Volume Management Device driver
4 * Copyright (c) 2015, Intel Corporation.
7 #include <linux/device.h>
8 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/msi.h>
13 #include <linux/pci.h>
14 #include <linux/pci-ecam.h>
15 #include <linux/srcu.h>
16 #include <linux/rculist.h>
17 #include <linux/rcupdate.h>
19 #include <asm/irqdomain.h>
20 #include <asm/device.h>
27 #define PCI_REG_VMCAP 0x40
28 #define BUS_RESTRICT_CAP(vmcap) (vmcap & 0x1)
29 #define PCI_REG_VMCONFIG 0x44
30 #define BUS_RESTRICT_CFG(vmcfg) ((vmcfg >> 8) & 0x3)
31 #define PCI_REG_VMLOCK 0x70
32 #define MB2_SHADOW_EN(vmlock) (vmlock & 0x2)
34 #define MB2_SHADOW_OFFSET 0x2000
35 #define MB2_SHADOW_SIZE 16
39 * Device may contain registers which hint the physical location of the
40 * membars, in order to allow proper address translation during
41 * resource assignment to enable guest virtualization
43 VMD_FEAT_HAS_MEMBAR_SHADOW
= (1 << 0),
46 * Device may provide root port configuration information which limits
49 VMD_FEAT_HAS_BUS_RESTRICTIONS
= (1 << 1),
52 * Device contains physical location shadow registers in
53 * vendor-specific capability space
55 VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP
= (1 << 2),
58 * Device may use MSI-X vector 0 for software triggering and will not
59 * be used for MSI remapping
61 VMD_FEAT_OFFSET_FIRST_VECTOR
= (1 << 3),
65 * Lock for manipulating VMD IRQ lists.
67 static DEFINE_RAW_SPINLOCK(list_lock
);
70 * struct vmd_irq - private data to map driver IRQ to the VMD shared vector
71 * @node: list item for parent traversal.
72 * @irq: back pointer to parent.
73 * @enabled: true if driver enabled IRQ
74 * @virq: the virtual IRQ value provided to the requesting driver.
76 * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to
77 * a VMD IRQ using this structure.
80 struct list_head node
;
81 struct vmd_irq_list
*irq
;
87 * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector
88 * @irq_list: the list of irq's the VMD one demuxes to.
89 * @srcu: SRCU struct for local synchronization.
90 * @count: number of child IRQs assigned to this vector; used to track
94 struct list_head irq_list
;
95 struct srcu_struct srcu
;
103 void __iomem
*cfgbar
;
106 struct vmd_irq_list
*irqs
;
108 struct pci_sysdata sysdata
;
109 struct resource resources
[3];
110 struct irq_domain
*irq_domain
;
116 static inline struct vmd_dev
*vmd_from_bus(struct pci_bus
*bus
)
118 return container_of(bus
->sysdata
, struct vmd_dev
, sysdata
);
121 static inline unsigned int index_from_irqs(struct vmd_dev
*vmd
,
122 struct vmd_irq_list
*irqs
)
124 return irqs
- vmd
->irqs
;
128 * Drivers managing a device in a VMD domain allocate their own IRQs as before,
129 * but the MSI entry for the hardware it's driving will be programmed with a
130 * destination ID for the VMD MSI-X table. The VMD muxes interrupts in its
131 * domain into one of its own, and the VMD driver de-muxes these for the
132 * handlers sharing that VMD IRQ. The vmd irq_domain provides the operations
133 * and irq_chip to set this up.
135 static void vmd_compose_msi_msg(struct irq_data
*data
, struct msi_msg
*msg
)
137 struct vmd_irq
*vmdirq
= data
->chip_data
;
138 struct vmd_irq_list
*irq
= vmdirq
->irq
;
139 struct vmd_dev
*vmd
= irq_data_get_irq_handler_data(data
);
141 memset(msg
, 0, sizeof(*msg
));
142 msg
->address_hi
= X86_MSI_BASE_ADDRESS_HIGH
;
143 msg
->arch_addr_lo
.base_address
= X86_MSI_BASE_ADDRESS_LOW
;
144 msg
->arch_addr_lo
.destid_0_7
= index_from_irqs(vmd
, irq
);
148 * We rely on MSI_FLAG_USE_DEF_CHIP_OPS to set the IRQ mask/unmask ops.
150 static void vmd_irq_enable(struct irq_data
*data
)
152 struct vmd_irq
*vmdirq
= data
->chip_data
;
155 raw_spin_lock_irqsave(&list_lock
, flags
);
156 WARN_ON(vmdirq
->enabled
);
157 list_add_tail_rcu(&vmdirq
->node
, &vmdirq
->irq
->irq_list
);
158 vmdirq
->enabled
= true;
159 raw_spin_unlock_irqrestore(&list_lock
, flags
);
161 data
->chip
->irq_unmask(data
);
164 static void vmd_irq_disable(struct irq_data
*data
)
166 struct vmd_irq
*vmdirq
= data
->chip_data
;
169 data
->chip
->irq_mask(data
);
171 raw_spin_lock_irqsave(&list_lock
, flags
);
172 if (vmdirq
->enabled
) {
173 list_del_rcu(&vmdirq
->node
);
174 vmdirq
->enabled
= false;
176 raw_spin_unlock_irqrestore(&list_lock
, flags
);
180 * XXX: Stubbed until we develop acceptable way to not create conflicts with
181 * other devices sharing the same vector.
183 static int vmd_irq_set_affinity(struct irq_data
*data
,
184 const struct cpumask
*dest
, bool force
)
189 static struct irq_chip vmd_msi_controller
= {
191 .irq_enable
= vmd_irq_enable
,
192 .irq_disable
= vmd_irq_disable
,
193 .irq_compose_msi_msg
= vmd_compose_msi_msg
,
194 .irq_set_affinity
= vmd_irq_set_affinity
,
197 static irq_hw_number_t
vmd_get_hwirq(struct msi_domain_info
*info
,
198 msi_alloc_info_t
*arg
)
204 * XXX: We can be even smarter selecting the best IRQ once we solve the
207 static struct vmd_irq_list
*vmd_next_irq(struct vmd_dev
*vmd
, struct msi_desc
*desc
)
212 if (vmd
->msix_count
== 1 + vmd
->first_vec
)
213 return &vmd
->irqs
[vmd
->first_vec
];
216 * White list for fast-interrupt handlers. All others will share the
217 * "slow" interrupt vector.
219 switch (msi_desc_to_pci_dev(desc
)->class) {
220 case PCI_CLASS_STORAGE_EXPRESS
:
223 return &vmd
->irqs
[vmd
->first_vec
];
226 raw_spin_lock_irqsave(&list_lock
, flags
);
227 best
= vmd
->first_vec
+ 1;
228 for (i
= best
; i
< vmd
->msix_count
; i
++)
229 if (vmd
->irqs
[i
].count
< vmd
->irqs
[best
].count
)
231 vmd
->irqs
[best
].count
++;
232 raw_spin_unlock_irqrestore(&list_lock
, flags
);
234 return &vmd
->irqs
[best
];
237 static int vmd_msi_init(struct irq_domain
*domain
, struct msi_domain_info
*info
,
238 unsigned int virq
, irq_hw_number_t hwirq
,
239 msi_alloc_info_t
*arg
)
241 struct msi_desc
*desc
= arg
->desc
;
242 struct vmd_dev
*vmd
= vmd_from_bus(msi_desc_to_pci_dev(desc
)->bus
);
243 struct vmd_irq
*vmdirq
= kzalloc(sizeof(*vmdirq
), GFP_KERNEL
);
244 unsigned int index
, vector
;
249 INIT_LIST_HEAD(&vmdirq
->node
);
250 vmdirq
->irq
= vmd_next_irq(vmd
, desc
);
252 index
= index_from_irqs(vmd
, vmdirq
->irq
);
253 vector
= pci_irq_vector(vmd
->dev
, index
);
255 irq_domain_set_info(domain
, virq
, vector
, info
->chip
, vmdirq
,
256 handle_untracked_irq
, vmd
, NULL
);
260 static void vmd_msi_free(struct irq_domain
*domain
,
261 struct msi_domain_info
*info
, unsigned int virq
)
263 struct vmd_irq
*vmdirq
= irq_get_chip_data(virq
);
266 synchronize_srcu(&vmdirq
->irq
->srcu
);
268 /* XXX: Potential optimization to rebalance */
269 raw_spin_lock_irqsave(&list_lock
, flags
);
270 vmdirq
->irq
->count
--;
271 raw_spin_unlock_irqrestore(&list_lock
, flags
);
276 static int vmd_msi_prepare(struct irq_domain
*domain
, struct device
*dev
,
277 int nvec
, msi_alloc_info_t
*arg
)
279 struct pci_dev
*pdev
= to_pci_dev(dev
);
280 struct vmd_dev
*vmd
= vmd_from_bus(pdev
->bus
);
282 if (nvec
> vmd
->msix_count
)
283 return vmd
->msix_count
;
285 memset(arg
, 0, sizeof(*arg
));
289 static void vmd_set_desc(msi_alloc_info_t
*arg
, struct msi_desc
*desc
)
294 static struct msi_domain_ops vmd_msi_domain_ops
= {
295 .get_hwirq
= vmd_get_hwirq
,
296 .msi_init
= vmd_msi_init
,
297 .msi_free
= vmd_msi_free
,
298 .msi_prepare
= vmd_msi_prepare
,
299 .set_desc
= vmd_set_desc
,
302 static struct msi_domain_info vmd_msi_domain_info
= {
303 .flags
= MSI_FLAG_USE_DEF_DOM_OPS
| MSI_FLAG_USE_DEF_CHIP_OPS
|
305 .ops
= &vmd_msi_domain_ops
,
306 .chip
= &vmd_msi_controller
,
309 static int vmd_create_irq_domain(struct vmd_dev
*vmd
)
311 struct fwnode_handle
*fn
;
313 fn
= irq_domain_alloc_named_id_fwnode("VMD-MSI", vmd
->sysdata
.domain
);
317 vmd
->irq_domain
= pci_msi_create_irq_domain(fn
, &vmd_msi_domain_info
, NULL
);
318 if (!vmd
->irq_domain
) {
319 irq_domain_free_fwnode(fn
);
326 static void vmd_remove_irq_domain(struct vmd_dev
*vmd
)
328 if (vmd
->irq_domain
) {
329 struct fwnode_handle
*fn
= vmd
->irq_domain
->fwnode
;
331 irq_domain_remove(vmd
->irq_domain
);
332 irq_domain_free_fwnode(fn
);
336 static void __iomem
*vmd_cfg_addr(struct vmd_dev
*vmd
, struct pci_bus
*bus
,
337 unsigned int devfn
, int reg
, int len
)
339 unsigned int busnr_ecam
= bus
->number
- vmd
->busn_start
;
340 u32 offset
= PCIE_ECAM_OFFSET(busnr_ecam
, devfn
, reg
);
342 if (offset
+ len
>= resource_size(&vmd
->dev
->resource
[VMD_CFGBAR
]))
345 return vmd
->cfgbar
+ offset
;
349 * CPU may deadlock if config space is not serialized on some versions of this
350 * hardware, so all config space access is done under a spinlock.
352 static int vmd_pci_read(struct pci_bus
*bus
, unsigned int devfn
, int reg
,
355 struct vmd_dev
*vmd
= vmd_from_bus(bus
);
356 void __iomem
*addr
= vmd_cfg_addr(vmd
, bus
, devfn
, reg
, len
);
363 spin_lock_irqsave(&vmd
->cfg_lock
, flags
);
366 *value
= readb(addr
);
369 *value
= readw(addr
);
372 *value
= readl(addr
);
378 spin_unlock_irqrestore(&vmd
->cfg_lock
, flags
);
383 * VMD h/w converts non-posted config writes to posted memory writes. The
384 * read-back in this function forces the completion so it returns only after
385 * the config space was written, as expected.
387 static int vmd_pci_write(struct pci_bus
*bus
, unsigned int devfn
, int reg
,
390 struct vmd_dev
*vmd
= vmd_from_bus(bus
);
391 void __iomem
*addr
= vmd_cfg_addr(vmd
, bus
, devfn
, reg
, len
);
398 spin_lock_irqsave(&vmd
->cfg_lock
, flags
);
416 spin_unlock_irqrestore(&vmd
->cfg_lock
, flags
);
420 static struct pci_ops vmd_ops
= {
421 .read
= vmd_pci_read
,
422 .write
= vmd_pci_write
,
425 static void vmd_attach_resources(struct vmd_dev
*vmd
)
427 vmd
->dev
->resource
[VMD_MEMBAR1
].child
= &vmd
->resources
[1];
428 vmd
->dev
->resource
[VMD_MEMBAR2
].child
= &vmd
->resources
[2];
431 static void vmd_detach_resources(struct vmd_dev
*vmd
)
433 vmd
->dev
->resource
[VMD_MEMBAR1
].child
= NULL
;
434 vmd
->dev
->resource
[VMD_MEMBAR2
].child
= NULL
;
438 * VMD domains start at 0x10000 to not clash with ACPI _SEG domains.
439 * Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of which the lower
440 * 16 bits are the PCI Segment Group (domain) number. Other bits are
441 * currently reserved.
443 static int vmd_find_free_domain(void)
446 struct pci_bus
*bus
= NULL
;
448 while ((bus
= pci_find_next_bus(bus
)) != NULL
)
449 domain
= max_t(int, domain
, pci_domain_nr(bus
));
453 static int vmd_get_phys_offsets(struct vmd_dev
*vmd
, bool native_hint
,
454 resource_size_t
*offset1
,
455 resource_size_t
*offset2
)
457 struct pci_dev
*dev
= vmd
->dev
;
464 ret
= pci_read_config_dword(dev
, PCI_REG_VMLOCK
, &vmlock
);
465 if (ret
|| vmlock
== ~0)
468 if (MB2_SHADOW_EN(vmlock
)) {
469 void __iomem
*membar2
;
471 membar2
= pci_iomap(dev
, VMD_MEMBAR2
, 0);
474 phys1
= readq(membar2
+ MB2_SHADOW_OFFSET
);
475 phys2
= readq(membar2
+ MB2_SHADOW_OFFSET
+ 8);
476 pci_iounmap(dev
, membar2
);
480 /* Hypervisor-Emulated Vendor-Specific Capability */
481 int pos
= pci_find_capability(dev
, PCI_CAP_ID_VNDR
);
484 pci_read_config_dword(dev
, pos
+ 4, ®
);
487 if (pos
&& reg
== 0x53484457) {
488 pci_read_config_dword(dev
, pos
+ 8, ®
);
489 pci_read_config_dword(dev
, pos
+ 12, ®u
);
490 phys1
= (u64
) regu
<< 32 | reg
;
492 pci_read_config_dword(dev
, pos
+ 16, ®
);
493 pci_read_config_dword(dev
, pos
+ 20, ®u
);
494 phys2
= (u64
) regu
<< 32 | reg
;
499 *offset1
= dev
->resource
[VMD_MEMBAR1
].start
-
500 (phys1
& PCI_BASE_ADDRESS_MEM_MASK
);
501 *offset2
= dev
->resource
[VMD_MEMBAR2
].start
-
502 (phys2
& PCI_BASE_ADDRESS_MEM_MASK
);
507 static int vmd_get_bus_number_start(struct vmd_dev
*vmd
)
509 struct pci_dev
*dev
= vmd
->dev
;
512 pci_read_config_word(dev
, PCI_REG_VMCAP
, ®
);
513 if (BUS_RESTRICT_CAP(reg
)) {
514 pci_read_config_word(dev
, PCI_REG_VMCONFIG
, ®
);
516 switch (BUS_RESTRICT_CFG(reg
)) {
521 vmd
->busn_start
= 128;
524 vmd
->busn_start
= 224;
527 pci_err(dev
, "Unknown Bus Offset Setting (%d)\n",
528 BUS_RESTRICT_CFG(reg
));
536 static irqreturn_t
vmd_irq(int irq
, void *data
)
538 struct vmd_irq_list
*irqs
= data
;
539 struct vmd_irq
*vmdirq
;
542 idx
= srcu_read_lock(&irqs
->srcu
);
543 list_for_each_entry_rcu(vmdirq
, &irqs
->irq_list
, node
)
544 generic_handle_irq(vmdirq
->virq
);
545 srcu_read_unlock(&irqs
->srcu
, idx
);
550 static int vmd_alloc_irqs(struct vmd_dev
*vmd
)
552 struct pci_dev
*dev
= vmd
->dev
;
555 vmd
->msix_count
= pci_msix_vec_count(dev
);
556 if (vmd
->msix_count
< 0)
559 vmd
->msix_count
= pci_alloc_irq_vectors(dev
, vmd
->first_vec
+ 1,
560 vmd
->msix_count
, PCI_IRQ_MSIX
);
561 if (vmd
->msix_count
< 0)
562 return vmd
->msix_count
;
564 vmd
->irqs
= devm_kcalloc(&dev
->dev
, vmd
->msix_count
, sizeof(*vmd
->irqs
),
569 for (i
= 0; i
< vmd
->msix_count
; i
++) {
570 err
= init_srcu_struct(&vmd
->irqs
[i
].srcu
);
574 INIT_LIST_HEAD(&vmd
->irqs
[i
].irq_list
);
575 err
= devm_request_irq(&dev
->dev
, pci_irq_vector(dev
, i
),
576 vmd_irq
, IRQF_NO_THREAD
,
577 "vmd", &vmd
->irqs
[i
]);
585 static int vmd_enable_domain(struct vmd_dev
*vmd
, unsigned long features
)
587 struct pci_sysdata
*sd
= &vmd
->sysdata
;
588 struct resource
*res
;
591 LIST_HEAD(resources
);
592 resource_size_t offset
[2] = {0};
593 resource_size_t membar2_offset
= 0x2000;
594 struct pci_bus
*child
;
598 * Shadow registers may exist in certain VMD device ids which allow
599 * guests to correctly assign host physical addresses to the root ports
600 * and child devices. These registers will either return the host value
601 * or 0, depending on an enable bit in the VMD device.
603 if (features
& VMD_FEAT_HAS_MEMBAR_SHADOW
) {
604 membar2_offset
= MB2_SHADOW_OFFSET
+ MB2_SHADOW_SIZE
;
605 ret
= vmd_get_phys_offsets(vmd
, true, &offset
[0], &offset
[1]);
608 } else if (features
& VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP
) {
609 ret
= vmd_get_phys_offsets(vmd
, false, &offset
[0], &offset
[1]);
615 * Certain VMD devices may have a root port configuration option which
616 * limits the bus range to between 0-127, 128-255, or 224-255
618 if (features
& VMD_FEAT_HAS_BUS_RESTRICTIONS
) {
619 ret
= vmd_get_bus_number_start(vmd
);
624 res
= &vmd
->dev
->resource
[VMD_CFGBAR
];
625 vmd
->resources
[0] = (struct resource
) {
626 .name
= "VMD CFGBAR",
627 .start
= vmd
->busn_start
,
628 .end
= vmd
->busn_start
+ (resource_size(res
) >> 20) - 1,
629 .flags
= IORESOURCE_BUS
| IORESOURCE_PCI_FIXED
,
633 * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can
634 * put 32-bit resources in the window.
636 * There's no hardware reason why a 64-bit window *couldn't*
637 * contain a 32-bit resource, but pbus_size_mem() computes the
638 * bridge window size assuming a 64-bit window will contain no
639 * 32-bit resources. __pci_assign_resource() enforces that
640 * artificial restriction to make sure everything will fit.
642 * The only way we could use a 64-bit non-prefetchable MEMBAR is
643 * if its address is <4GB so that we can convert it to a 32-bit
644 * resource. To be visible to the host OS, all VMD endpoints must
645 * be initially configured by platform BIOS, which includes setting
646 * up these resources. We can assume the device is configured
647 * according to the platform needs.
649 res
= &vmd
->dev
->resource
[VMD_MEMBAR1
];
650 upper_bits
= upper_32_bits(res
->end
);
651 flags
= res
->flags
& ~IORESOURCE_SIZEALIGN
;
653 flags
&= ~IORESOURCE_MEM_64
;
654 vmd
->resources
[1] = (struct resource
) {
655 .name
= "VMD MEMBAR1",
662 res
= &vmd
->dev
->resource
[VMD_MEMBAR2
];
663 upper_bits
= upper_32_bits(res
->end
);
664 flags
= res
->flags
& ~IORESOURCE_SIZEALIGN
;
666 flags
&= ~IORESOURCE_MEM_64
;
667 vmd
->resources
[2] = (struct resource
) {
668 .name
= "VMD MEMBAR2",
669 .start
= res
->start
+ membar2_offset
,
675 sd
->vmd_dev
= vmd
->dev
;
676 sd
->domain
= vmd_find_free_domain();
680 sd
->node
= pcibus_to_node(vmd
->dev
->bus
);
682 ret
= vmd_create_irq_domain(vmd
);
687 * Override the irq domain bus token so the domain can be distinguished
688 * from a regular PCI/MSI domain.
690 irq_domain_update_bus_token(vmd
->irq_domain
, DOMAIN_BUS_VMD_MSI
);
692 pci_add_resource(&resources
, &vmd
->resources
[0]);
693 pci_add_resource_offset(&resources
, &vmd
->resources
[1], offset
[0]);
694 pci_add_resource_offset(&resources
, &vmd
->resources
[2], offset
[1]);
696 vmd
->bus
= pci_create_root_bus(&vmd
->dev
->dev
, vmd
->busn_start
,
697 &vmd_ops
, sd
, &resources
);
699 pci_free_resource_list(&resources
);
700 vmd_remove_irq_domain(vmd
);
704 vmd_attach_resources(vmd
);
706 dev_set_msi_domain(&vmd
->bus
->dev
, vmd
->irq_domain
);
708 pci_scan_child_bus(vmd
->bus
);
709 pci_assign_unassigned_bus_resources(vmd
->bus
);
712 * VMD root buses are virtual and don't return true on pci_is_pcie()
713 * and will fail pcie_bus_configure_settings() early. It can instead be
714 * run on each of the real root ports.
716 list_for_each_entry(child
, &vmd
->bus
->children
, node
)
717 pcie_bus_configure_settings(child
);
719 pci_bus_add_devices(vmd
->bus
);
721 WARN(sysfs_create_link(&vmd
->dev
->dev
.kobj
, &vmd
->bus
->dev
.kobj
,
722 "domain"), "Can't create symlink to domain\n");
726 static int vmd_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
)
728 unsigned long features
= (unsigned long) id
->driver_data
;
732 if (resource_size(&dev
->resource
[VMD_CFGBAR
]) < (1 << 20))
735 vmd
= devm_kzalloc(&dev
->dev
, sizeof(*vmd
), GFP_KERNEL
);
740 err
= pcim_enable_device(dev
);
744 vmd
->cfgbar
= pcim_iomap(dev
, VMD_CFGBAR
, 0);
749 if (dma_set_mask_and_coherent(&dev
->dev
, DMA_BIT_MASK(64)) &&
750 dma_set_mask_and_coherent(&dev
->dev
, DMA_BIT_MASK(32)))
753 if (features
& VMD_FEAT_OFFSET_FIRST_VECTOR
)
756 err
= vmd_alloc_irqs(vmd
);
760 spin_lock_init(&vmd
->cfg_lock
);
761 pci_set_drvdata(dev
, vmd
);
762 err
= vmd_enable_domain(vmd
, features
);
766 dev_info(&vmd
->dev
->dev
, "Bound to PCI domain %04x\n",
767 vmd
->sysdata
.domain
);
771 static void vmd_cleanup_srcu(struct vmd_dev
*vmd
)
775 for (i
= 0; i
< vmd
->msix_count
; i
++)
776 cleanup_srcu_struct(&vmd
->irqs
[i
].srcu
);
779 static void vmd_remove(struct pci_dev
*dev
)
781 struct vmd_dev
*vmd
= pci_get_drvdata(dev
);
783 sysfs_remove_link(&vmd
->dev
->dev
.kobj
, "domain");
784 pci_stop_root_bus(vmd
->bus
);
785 pci_remove_root_bus(vmd
->bus
);
786 vmd_cleanup_srcu(vmd
);
787 vmd_detach_resources(vmd
);
788 vmd_remove_irq_domain(vmd
);
791 #ifdef CONFIG_PM_SLEEP
792 static int vmd_suspend(struct device
*dev
)
794 struct pci_dev
*pdev
= to_pci_dev(dev
);
795 struct vmd_dev
*vmd
= pci_get_drvdata(pdev
);
798 for (i
= 0; i
< vmd
->msix_count
; i
++)
799 devm_free_irq(dev
, pci_irq_vector(pdev
, i
), &vmd
->irqs
[i
]);
804 static int vmd_resume(struct device
*dev
)
806 struct pci_dev
*pdev
= to_pci_dev(dev
);
807 struct vmd_dev
*vmd
= pci_get_drvdata(pdev
);
810 for (i
= 0; i
< vmd
->msix_count
; i
++) {
811 err
= devm_request_irq(dev
, pci_irq_vector(pdev
, i
),
812 vmd_irq
, IRQF_NO_THREAD
,
813 "vmd", &vmd
->irqs
[i
]);
821 static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops
, vmd_suspend
, vmd_resume
);
823 static const struct pci_device_id vmd_ids
[] = {
824 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_VMD_201D
),
825 .driver_data
= VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP
,},
826 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_VMD_28C0
),
827 .driver_data
= VMD_FEAT_HAS_MEMBAR_SHADOW
|
828 VMD_FEAT_HAS_BUS_RESTRICTIONS
,},
829 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x467f),
830 .driver_data
= VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP
|
831 VMD_FEAT_HAS_BUS_RESTRICTIONS
|
832 VMD_FEAT_OFFSET_FIRST_VECTOR
,},
833 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x4c3d),
834 .driver_data
= VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP
|
835 VMD_FEAT_HAS_BUS_RESTRICTIONS
|
836 VMD_FEAT_OFFSET_FIRST_VECTOR
,},
837 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_VMD_9A0B
),
838 .driver_data
= VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP
|
839 VMD_FEAT_HAS_BUS_RESTRICTIONS
|
840 VMD_FEAT_OFFSET_FIRST_VECTOR
,},
843 MODULE_DEVICE_TABLE(pci
, vmd_ids
);
845 static struct pci_driver vmd_drv
= {
849 .remove
= vmd_remove
,
851 .pm
= &vmd_dev_pm_ops
,
854 module_pci_driver(vmd_drv
);
856 MODULE_AUTHOR("Intel Corporation");
857 MODULE_LICENSE("GPL v2");
858 MODULE_VERSION("0.6");