drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  * Author: jitao.shi <jitao.shi@mediatek.com>
   5  */
   6
   7 #include "phy-mtk-mipi-dsi.h"
   8
   9 #define MIPITX_DSI_CON          0x00
  10 #define RG_DSI_LDOCORE_EN               BIT(0)
  11 #define RG_DSI_CKG_LDOOUT_EN            BIT(1)
  12 #define RG_DSI_BCLK_SEL                 (3 << 2)
  13 #define RG_DSI_LD_IDX_SEL               (7 << 4)
  14 #define RG_DSI_PHYCLK_SEL               (2 << 8)
  15 #define RG_DSI_DSICLK_FREQ_SEL          BIT(10)
  16 #define RG_DSI_LPTX_CLMP_EN             BIT(11)
  17
  18 #define MIPITX_DSI_CLOCK_LANE   0x04
  19 #define MIPITX_DSI_DATA_LANE0   0x08
  20 #define MIPITX_DSI_DATA_LANE1   0x0c
  21 #define MIPITX_DSI_DATA_LANE2   0x10
  22 #define MIPITX_DSI_DATA_LANE3   0x14
  23 #define RG_DSI_LNTx_LDOOUT_EN           BIT(0)
  24 #define RG_DSI_LNTx_CKLANE_EN           BIT(1)
  25 #define RG_DSI_LNTx_LPTX_IPLUS1         BIT(2)
  26 #define RG_DSI_LNTx_LPTX_IPLUS2         BIT(3)
  27 #define RG_DSI_LNTx_LPTX_IMINUS         BIT(4)
  28 #define RG_DSI_LNTx_LPCD_IPLUS          BIT(5)
  29 #define RG_DSI_LNTx_LPCD_IMINUS         BIT(6)
  30 #define RG_DSI_LNTx_RT_CODE             (0xf << 8)
  31
  32 #define MIPITX_DSI_TOP_CON      0x40
  33 #define RG_DSI_LNT_INTR_EN              BIT(0)
  34 #define RG_DSI_LNT_HS_BIAS_EN           BIT(1)
  35 #define RG_DSI_LNT_IMP_CAL_EN           BIT(2)
  36 #define RG_DSI_LNT_TESTMODE_EN          BIT(3)
  37 #define RG_DSI_LNT_IMP_CAL_CODE         (0xf << 4)
  38 #define RG_DSI_LNT_AIO_SEL              (7 << 8)
  39 #define RG_DSI_PAD_TIE_LOW_EN           BIT(11)
  40 #define RG_DSI_DEBUG_INPUT_EN           BIT(12)
  41 #define RG_DSI_PRESERVE                 (7 << 13)
  42
  43 #define MIPITX_DSI_BG_CON       0x44
  44 #define RG_DSI_BG_CORE_EN               BIT(0)
  45 #define RG_DSI_BG_CKEN                  BIT(1)
  46 #define RG_DSI_BG_DIV                   (0x3 << 2)
  47 #define RG_DSI_BG_FAST_CHARGE           BIT(4)
  48 #define RG_DSI_VOUT_MSK                 (0x3ffff << 5)
  49 #define RG_DSI_V12_SEL                  (7 << 5)
  50 #define RG_DSI_V10_SEL                  (7 << 8)
  51 #define RG_DSI_V072_SEL                 (7 << 11)
  52 #define RG_DSI_V04_SEL                  (7 << 14)
  53 #define RG_DSI_V032_SEL                 (7 << 17)
  54 #define RG_DSI_V02_SEL                  (7 << 20)
  55 #define RG_DSI_BG_R1_TRIM               (0xf << 24)
  56 #define RG_DSI_BG_R2_TRIM               (0xf << 28)
  57
  58 #define MIPITX_DSI_PLL_CON0     0x50
  59 #define RG_DSI_MPPLL_PLL_EN             BIT(0)
  60 #define RG_DSI_MPPLL_DIV_MSK            (0x1ff << 1)
  61 #define RG_DSI_MPPLL_PREDIV             (3 << 1)
  62 #define RG_DSI_MPPLL_TXDIV0             (3 << 3)
  63 #define RG_DSI_MPPLL_TXDIV1             (3 << 5)
  64 #define RG_DSI_MPPLL_POSDIV             (7 << 7)
  65 #define RG_DSI_MPPLL_MONVC_EN           BIT(10)
  66 #define RG_DSI_MPPLL_MONREF_EN          BIT(11)
  67 #define RG_DSI_MPPLL_VOD_EN             BIT(12)
  68
  69 #define MIPITX_DSI_PLL_CON1     0x54
  70 #define RG_DSI_MPPLL_SDM_FRA_EN         BIT(0)
  71 #define RG_DSI_MPPLL_SDM_SSC_PH_INIT    BIT(1)
  72 #define RG_DSI_MPPLL_SDM_SSC_EN         BIT(2)
  73 #define RG_DSI_MPPLL_SDM_SSC_PRD        (0xffff << 16)
  74
  75 #define MIPITX_DSI_PLL_CON2     0x58
  76
  77 #define MIPITX_DSI_PLL_TOP      0x64
  78 #define RG_DSI_MPPLL_PRESERVE           (0xff << 8)
  79
  80 #define MIPITX_DSI_PLL_PWR      0x68
  81 #define RG_DSI_MPPLL_SDM_PWR_ON         BIT(0)
  82 #define RG_DSI_MPPLL_SDM_ISO_EN         BIT(1)
  83 #define RG_DSI_MPPLL_SDM_PWR_ACK        BIT(8)
  84
  85 #define MIPITX_DSI_SW_CTRL      0x80
  86 #define SW_CTRL_EN                      BIT(0)
  87
  88 #define MIPITX_DSI_SW_CTRL_CON0 0x84
  89 #define SW_LNTC_LPTX_PRE_OE             BIT(0)
  90 #define SW_LNTC_LPTX_OE                 BIT(1)
  91 #define SW_LNTC_LPTX_P                  BIT(2)
  92 #define SW_LNTC_LPTX_N                  BIT(3)
  93 #define SW_LNTC_HSTX_PRE_OE             BIT(4)
  94 #define SW_LNTC_HSTX_OE                 BIT(5)
  95 #define SW_LNTC_HSTX_ZEROCLK            BIT(6)
  96 #define SW_LNT0_LPTX_PRE_OE             BIT(7)
  97 #define SW_LNT0_LPTX_OE                 BIT(8)
  98 #define SW_LNT0_LPTX_P                  BIT(9)
  99 #define SW_LNT0_LPTX_N                  BIT(10)
 100 #define SW_LNT0_HSTX_PRE_OE             BIT(11)
 101 #define SW_LNT0_HSTX_OE                 BIT(12)
 102 #define SW_LNT0_LPRX_EN                 BIT(13)
 103 #define SW_LNT1_LPTX_PRE_OE             BIT(14)
 104 #define SW_LNT1_LPTX_OE                 BIT(15)
 105 #define SW_LNT1_LPTX_P                  BIT(16)
 106 #define SW_LNT1_LPTX_N                  BIT(17)
 107 #define SW_LNT1_HSTX_PRE_OE             BIT(18)
 108 #define SW_LNT1_HSTX_OE                 BIT(19)
 109 #define SW_LNT2_LPTX_PRE_OE             BIT(20)
 110 #define SW_LNT2_LPTX_OE                 BIT(21)
 111 #define SW_LNT2_LPTX_P                  BIT(22)
 112 #define SW_LNT2_LPTX_N                  BIT(23)
 113 #define SW_LNT2_HSTX_PRE_OE             BIT(24)
 114 #define SW_LNT2_HSTX_OE                 BIT(25)
 115
 116 static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
 117 {
 118         struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
 119         u8 txdiv, txdiv0, txdiv1;
 120         u64 pcw;
 121
 122         dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate);
 123
 124         if (mipi_tx->data_rate >= 500000000) {
 125                 txdiv = 1;
 126                 txdiv0 = 0;
 127                 txdiv1 = 0;
 128         } else if (mipi_tx->data_rate >= 250000000) {
 129                 txdiv = 2;
 130                 txdiv0 = 1;
 131                 txdiv1 = 0;
 132         } else if (mipi_tx->data_rate >= 125000000) {
 133                 txdiv = 4;
 134                 txdiv0 = 2;
 135                 txdiv1 = 0;
 136         } else if (mipi_tx->data_rate > 62000000) {
 137                 txdiv = 8;
 138                 txdiv0 = 2;
 139                 txdiv1 = 1;
 140         } else if (mipi_tx->data_rate >= 50000000) {
 141                 txdiv = 16;
 142                 txdiv0 = 2;
 143                 txdiv1 = 2;
 144         } else {
 145                 return -EINVAL;
 146         }
 147
 148         mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON,
 149                                 RG_DSI_VOUT_MSK |
 150                                 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN,
 151                                 (4 << 20) | (4 << 17) | (4 << 14) |
 152                                 (4 << 11) | (4 << 8) | (4 << 5) |
 153                                 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
 154
 155         usleep_range(30, 100);
 156
 157         mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON,
 158                                 RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
 159                                 (8 << 4) | RG_DSI_LNT_HS_BIAS_EN);
 160
 161         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON,
 162                              RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
 163
 164         mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
 165                                 RG_DSI_MPPLL_SDM_PWR_ON |
 166                                 RG_DSI_MPPLL_SDM_ISO_EN,
 167                                 RG_DSI_MPPLL_SDM_PWR_ON);
 168
 169         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
 170                                RG_DSI_MPPLL_PLL_EN);
 171
 172         mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
 173                                 RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
 174                                 RG_DSI_MPPLL_PREDIV,
 175                                 (txdiv0 << 3) | (txdiv1 << 5));
 176
 177         /*
 178          * PLL PCW config
 179          * PCW bit 24~30 = integer part of pcw
 180          * PCW bit 0~23 = fractional part of pcw
 181          * pcw = data_Rate*4*txdiv/(Ref_clk*2);
 182          * Post DIV =4, so need data_Rate*4
 183          * Ref_clk is 26MHz
 184          */
 185         pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24,
 186                       26000000);
 187         writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2);
 188
 189         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
 190                              RG_DSI_MPPLL_SDM_FRA_EN);
 191
 192         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
 193
 194         usleep_range(20, 100);
 195
 196         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
 197                                RG_DSI_MPPLL_SDM_SSC_EN);
 198
 199         mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
 200                                 RG_DSI_MPPLL_PRESERVE,
 201                                 mipi_tx->driver_data->mppll_preserve);
 202
 203         return 0;
 204 }
 205
 206 static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
 207 {
 208         struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
 209
 210         dev_dbg(mipi_tx->dev, "unprepare\n");
 211
 212         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
 213                                RG_DSI_MPPLL_PLL_EN);
 214
 215         mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
 216                                 RG_DSI_MPPLL_PRESERVE, 0);
 217
 218         mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
 219                                 RG_DSI_MPPLL_SDM_ISO_EN |
 220                                 RG_DSI_MPPLL_SDM_PWR_ON,
 221                                 RG_DSI_MPPLL_SDM_ISO_EN);
 222
 223         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
 224                                RG_DSI_LNT_HS_BIAS_EN);
 225
 226         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON,
 227                                RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
 228
 229         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON,
 230                                RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
 231
 232         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
 233                                RG_DSI_MPPLL_DIV_MSK);
 234 }
 235
 236 static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 237                                        unsigned long *prate)
 238 {
 239         return clamp_val(rate, 50000000, 1250000000);
 240 }
 241
 242 static const struct clk_ops mtk_mipi_tx_pll_ops = {
 243         .prepare = mtk_mipi_tx_pll_prepare,
 244         .unprepare = mtk_mipi_tx_pll_unprepare,
 245         .round_rate = mtk_mipi_tx_pll_round_rate,
 246         .set_rate = mtk_mipi_tx_pll_set_rate,
 247         .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
 248 };
 249
 250 static void mtk_mipi_tx_power_on_signal(struct phy *phy)
 251 {
 252         struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
 253         u32 reg;
 254
 255         for (reg = MIPITX_DSI_CLOCK_LANE;
 256              reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
 257                 mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
 258
 259         mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
 260                                RG_DSI_PAD_TIE_LOW_EN);
 261 }
 262
 263 static void mtk_mipi_tx_power_off_signal(struct phy *phy)
 264 {
 265         struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
 266         u32 reg;
 267
 268         mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON,
 269                              RG_DSI_PAD_TIE_LOW_EN);
 270
 271         for (reg = MIPITX_DSI_CLOCK_LANE;
 272              reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
 273                 mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
 274 }
 275
 276 const struct mtk_mipitx_data mt2701_mipitx_data = {
 277         .mppll_preserve = (3 << 8),
 278         .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
 279         .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
 280         .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
 281 };
 282
 283 const struct mtk_mipitx_data mt8173_mipitx_data = {
 284         .mppll_preserve = (0 << 8),
 285         .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
 286         .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
 287         .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
 288 };