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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / pinctrl / actions / pinctrl-s700.c
blobfd00940a5799bc0cfeb18044d8e608e3b86672a3
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Actions Semi Owl S700 Pinctrl driver
4 *
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
7 *
8 * Author: Pathiban Nallathambi <pn@denx.de>
9 * Author: Saravanan Sekar <sravanhome@gmail.com>
10 */
11
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/pinctrl/pinctrl.h>
17 #include "pinctrl-owl.h"
18
19 /* Pinctrl registers offset */
20 #define MFCTL0 (0x0040)
21 #define MFCTL1 (0x0044)
22 #define MFCTL2 (0x0048)
23 #define MFCTL3 (0x004C)
24 #define PAD_PULLCTL0 (0x0060)
25 #define PAD_PULLCTL1 (0x0064)
26 #define PAD_PULLCTL2 (0x0068)
27 #define PAD_ST0 (0x006C)
28 #define PAD_ST1 (0x0070)
29 #define PAD_CTL (0x0074)
30 #define PAD_DRV0 (0x0080)
31 #define PAD_DRV1 (0x0084)
32 #define PAD_DRV2 (0x0088)
33
34 /*
35 * Most pins affected by the pinmux can also be GPIOs. Define these first.
36 * These must match how the GPIO driver names/numbers its pins.
37 */
38 #define _GPIOA(offset) (offset)
39 #define _GPIOB(offset) (32 + (offset))
40 #define _GPIOC(offset) (64 + (offset))
41 #define _GPIOD(offset) (96 + (offset))
42 #define _GPIOE(offset) (128 + (offset))
43
44 /* All non-GPIO pins follow */
45 #define NUM_GPIOS (_GPIOE(7) + 1)
46 #define _PIN(offset) (NUM_GPIOS + (offset))
47
48 /* Ethernet MAC */
49 #define ETH_TXD0 _GPIOA(14)
50 #define ETH_TXD1 _GPIOA(15)
51 #define ETH_TXD2 _GPIOE(4)
52 #define ETH_TXD3 _GPIOE(5)
53 #define ETH_TXEN _GPIOA(16)
54 #define ETH_RXER _GPIOA(17)
55 #define ETH_CRS_DV _GPIOA(18)
56 #define ETH_RXD1 _GPIOA(19)
57 #define ETH_RXD0 _GPIOA(20)
58 #define ETH_RXD2 _GPIOE(6)
59 #define ETH_RXD3 _GPIOE(7)
60 #define ETH_REF_CLK _GPIOA(21)
61 #define ETH_MDC _GPIOA(22)
62 #define ETH_MDIO _GPIOA(23)
63
64 /* SIRQ */
65 #define SIRQ0 _GPIOA(24)
66 #define SIRQ1 _GPIOA(25)
67 #define SIRQ2 _GPIOA(26)
68
69 /* I2S */
70 #define I2S_D0 _GPIOA(27)
71 #define I2S_BCLK0 _GPIOA(28)
72 #define I2S_LRCLK0 _GPIOA(29)
73 #define I2S_MCLK0 _GPIOA(30)
74 #define I2S_D1 _GPIOA(31)
75 #define I2S_BCLK1 _GPIOB(0)
76 #define I2S_LRCLK1 _GPIOB(1)
77 #define I2S_MCLK1 _GPIOB(2)
78
79 /* PCM1 */
80 #define PCM1_IN _GPIOD(28)
81 #define PCM1_CLK _GPIOD(29)
82 #define PCM1_SYNC _GPIOD(30)
83 #define PCM1_OUT _GPIOD(31)
84
85 /* KEY */
86 #define KS_IN0 _GPIOB(3)
87 #define KS_IN1 _GPIOB(4)
88 #define KS_IN2 _GPIOB(5)
89 #define KS_IN3 _GPIOB(6)
90 #define KS_OUT0 _GPIOB(7)
91 #define KS_OUT1 _GPIOB(8)
92 #define KS_OUT2 _GPIOB(9)
93
94 /* LVDS */
95 #define LVDS_OEP _GPIOB(10)
96 #define LVDS_OEN _GPIOB(11)
97 #define LVDS_ODP _GPIOB(12)
98 #define LVDS_ODN _GPIOB(13)
99 #define LVDS_OCP _GPIOB(14)
100 #define LVDS_OCN _GPIOB(15)
101 #define LVDS_OBP _GPIOB(16)
102 #define LVDS_OBN _GPIOB(17)
103 #define LVDS_OAP _GPIOB(18)
104 #define LVDS_OAN _GPIOB(19)
105 #define LVDS_EEP _GPIOB(20)
106 #define LVDS_EEN _GPIOB(21)
107 #define LVDS_EDP _GPIOB(22)
108 #define LVDS_EDN _GPIOB(23)
109 #define LVDS_ECP _GPIOB(24)
110 #define LVDS_ECN _GPIOB(25)
111 #define LVDS_EBP _GPIOB(26)
112 #define LVDS_EBN _GPIOB(27)
113 #define LVDS_EAP _GPIOB(28)
114 #define LVDS_EAN _GPIOB(29)
115 #define LCD0_D18 _GPIOB(30)
116 #define LCD0_D2 _GPIOB(31)
117
118 /* DSI */
119 #define DSI_DP3 _GPIOC(0)
120 #define DSI_DN3 _GPIOC(1)
121 #define DSI_DP1 _GPIOC(2)
122 #define DSI_DN1 _GPIOC(3)
123 #define DSI_CP _GPIOC(4)
124 #define DSI_CN _GPIOC(5)
125 #define DSI_DP0 _GPIOC(6)
126 #define DSI_DN0 _GPIOC(7)
127 #define DSI_DP2 _GPIOC(8)
128 #define DSI_DN2 _GPIOC(9)
129
130 /* SD */
131 #define SD0_D0 _GPIOC(10)
132 #define SD0_D1 _GPIOC(11)
133 #define SD0_D2 _GPIOC(12)
134 #define SD0_D3 _GPIOC(13)
135 #define SD0_D4 _GPIOC(14)
136 #define SD0_D5 _GPIOC(15)
137 #define SD0_D6 _GPIOC(16)
138 #define SD0_D7 _GPIOC(17)
139 #define SD0_CMD _GPIOC(18)
140 #define SD0_CLK _GPIOC(19)
141 #define SD1_CMD _GPIOC(20)
142 #define SD1_CLK _GPIOC(21)
143 #define SD1_D0 SD0_D4
144 #define SD1_D1 SD0_D5
145 #define SD1_D2 SD0_D6
146 #define SD1_D3 SD0_D7
147
148 /* SPI */
149 #define SPI0_SS _GPIOC(23)
150 #define SPI0_MISO _GPIOC(24)
151
152 /* UART for console */
153 #define UART0_RX _GPIOC(26)
154 #define UART0_TX _GPIOC(27)
155
156 /* UART for Bluetooth */
157 #define UART2_RX _GPIOD(18)
158 #define UART2_TX _GPIOD(19)
159 #define UART2_RTSB _GPIOD(20)
160 #define UART2_CTSB _GPIOD(21)
161
162 /* UART for 3G */
163 #define UART3_RX _GPIOD(22)
164 #define UART3_TX _GPIOD(23)
165 #define UART3_RTSB _GPIOD(24)
166 #define UART3_CTSB _GPIOD(25)
167
168 /* I2C */
169 #define I2C0_SCLK _GPIOC(28)
170 #define I2C0_SDATA _GPIOC(29)
171 #define I2C1_SCLK _GPIOE(0)
172 #define I2C1_SDATA _GPIOE(1)
173 #define I2C2_SCLK _GPIOE(2)
174 #define I2C2_SDATA _GPIOE(3)
175
176 /* CSI*/
177 #define CSI_DN0 _PIN(0)
178 #define CSI_DP0 _PIN(1)
179 #define CSI_DN1 _PIN(2)
180 #define CSI_DP1 _PIN(3)
181 #define CSI_CN _PIN(4)
182 #define CSI_CP _PIN(5)
183 #define CSI_DN2 _PIN(6)
184 #define CSI_DP2 _PIN(7)
185 #define CSI_DN3 _PIN(8)
186 #define CSI_DP3 _PIN(9)
187
188 /* Sensor */
189 #define SENSOR0_PCLK _GPIOC(31)
190 #define SENSOR0_CKOUT _GPIOD(10)
191
192 /* NAND (1.8v / 3.3v) */
193 #define DNAND_D0 _PIN(10)
194 #define DNAND_D1 _PIN(11)
195 #define DNAND_D2 _PIN(12)
196 #define DNAND_D3 _PIN(13)
197 #define DNAND_D4 _PIN(14)
198 #define DNAND_D5 _PIN(15)
199 #define DNAND_D6 _PIN(16)
200 #define DNAND_D7 _PIN(17)
201 #define DNAND_WRB _PIN(18)
202 #define DNAND_RDB _PIN(19)
203 #define DNAND_RDBN _PIN(20)
204 #define DNAND_DQS _GPIOA(12)
205 #define DNAND_DQSN _GPIOA(13)
206 #define DNAND_RB0 _PIN(21)
207 #define DNAND_ALE _GPIOD(12)
208 #define DNAND_CLE _GPIOD(13)
209 #define DNAND_CEB0 _GPIOD(14)
210 #define DNAND_CEB1 _GPIOD(15)
211 #define DNAND_CEB2 _GPIOD(16)
212 #define DNAND_CEB3 _GPIOD(17)
213
214 /* System */
215 #define PORB _PIN(22)
216 #define CLKO_25M _PIN(23)
217 #define BSEL _PIN(24)
218 #define PKG0 _PIN(25)
219 #define PKG1 _PIN(26)
220 #define PKG2 _PIN(27)
221 #define PKG3 _PIN(28)
222
223 #define _FIRSTPAD _GPIOA(0)
224 #define _LASTPAD PKG3
225 #define NUM_PADS (_PIN(28) + 1)
226
227 /* Pad names for the pinmux subsystem */
228 static const struct pinctrl_pin_desc s700_pads[] = {
229 PINCTRL_PIN(ETH_TXD0, "eth_txd0"),
230 PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
231 PINCTRL_PIN(ETH_TXD2, "eth_txd2"),
232 PINCTRL_PIN(ETH_TXD3, "eth_txd3"),
233 PINCTRL_PIN(ETH_TXEN, "eth_txen"),
234 PINCTRL_PIN(ETH_RXER, "eth_rxer"),
235 PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),
236 PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
237 PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),
238 PINCTRL_PIN(ETH_RXD2, "eth_rxd2"),
239 PINCTRL_PIN(ETH_RXD3, "eth_rxd3"),
240 PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),
241 PINCTRL_PIN(ETH_MDC, "eth_mdc"),
242 PINCTRL_PIN(ETH_MDIO, "eth_mdio"),
243 PINCTRL_PIN(SIRQ0, "sirq0"),
244 PINCTRL_PIN(SIRQ1, "sirq1"),
245 PINCTRL_PIN(SIRQ2, "sirq2"),
246 PINCTRL_PIN(I2S_D0, "i2s_d0"),
247 PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),
248 PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),
249 PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),
250 PINCTRL_PIN(I2S_D1, "i2s_d1"),
251 PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),
252 PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),
253 PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),
254 PINCTRL_PIN(PCM1_IN, "pcm1_in"),
255 PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),
256 PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),
257 PINCTRL_PIN(PCM1_OUT, "pcm1_out"),
258 PINCTRL_PIN(KS_IN0, "ks_in0"),
259 PINCTRL_PIN(KS_IN1, "ks_in1"),
260 PINCTRL_PIN(KS_IN2, "ks_in2"),
261 PINCTRL_PIN(KS_IN3, "ks_in3"),
262 PINCTRL_PIN(KS_OUT0, "ks_out0"),
263 PINCTRL_PIN(KS_OUT1, "ks_out1"),
264 PINCTRL_PIN(KS_OUT2, "ks_out2"),
265 PINCTRL_PIN(LVDS_OEP, "lvds_oep"),
266 PINCTRL_PIN(LVDS_OEN, "lvds_oen"),
267 PINCTRL_PIN(LVDS_ODP, "lvds_odp"),
268 PINCTRL_PIN(LVDS_ODN, "lvds_odn"),
269 PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),
270 PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),
271 PINCTRL_PIN(LVDS_OBP, "lvds_obp"),
272 PINCTRL_PIN(LVDS_OBN, "lvds_obn"),
273 PINCTRL_PIN(LVDS_OAP, "lvds_oap"),
274 PINCTRL_PIN(LVDS_OAN, "lvds_oan"),
275 PINCTRL_PIN(LVDS_EEP, "lvds_eep"),
276 PINCTRL_PIN(LVDS_EEN, "lvds_een"),
277 PINCTRL_PIN(LVDS_EDP, "lvds_edp"),
278 PINCTRL_PIN(LVDS_EDN, "lvds_edn"),
279 PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),
280 PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),
281 PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),
282 PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),
283 PINCTRL_PIN(LVDS_EAP, "lvds_eap"),
284 PINCTRL_PIN(LVDS_EAN, "lvds_ean"),
285 PINCTRL_PIN(LCD0_D18, "lcd0_d18"),
286 PINCTRL_PIN(LCD0_D2, "lcd0_d2"),
287 PINCTRL_PIN(DSI_DP3, "dsi_dp3"),
288 PINCTRL_PIN(DSI_DN3, "dsi_dn3"),
289 PINCTRL_PIN(DSI_DP1, "dsi_dp1"),
290 PINCTRL_PIN(DSI_DN1, "dsi_dn1"),
291 PINCTRL_PIN(DSI_CP, "dsi_cp"),
292 PINCTRL_PIN(DSI_CN, "dsi_cn"),
293 PINCTRL_PIN(DSI_DP0, "dsi_dp0"),
294 PINCTRL_PIN(DSI_DN0, "dsi_dn0"),
295 PINCTRL_PIN(DSI_DP2, "dsi_dp2"),
296 PINCTRL_PIN(DSI_DN2, "dsi_dn2"),
297 PINCTRL_PIN(SD0_D0, "sd0_d0"),
298 PINCTRL_PIN(SD0_D1, "sd0_d1"),
299 PINCTRL_PIN(SD0_D2, "sd0_d2"),
300 PINCTRL_PIN(SD0_D3, "sd0_d3"),
301 PINCTRL_PIN(SD1_D0, "sd1_d0"),
302 PINCTRL_PIN(SD1_D1, "sd1_d1"),
303 PINCTRL_PIN(SD1_D2, "sd1_d2"),
304 PINCTRL_PIN(SD1_D3, "sd1_d3"),
305 PINCTRL_PIN(SD0_CMD, "sd0_cmd"),
306 PINCTRL_PIN(SD0_CLK, "sd0_clk"),
307 PINCTRL_PIN(SD1_CMD, "sd1_cmd"),
308 PINCTRL_PIN(SD1_CLK, "sd1_clk"),
309 PINCTRL_PIN(SPI0_SS, "spi0_ss"),
310 PINCTRL_PIN(SPI0_MISO, "spi0_miso"),
311 PINCTRL_PIN(UART0_RX, "uart0_rx"),
312 PINCTRL_PIN(UART0_TX, "uart0_tx"),
313 PINCTRL_PIN(UART2_RX, "uart2_rx"),
314 PINCTRL_PIN(UART2_TX, "uart2_tx"),
315 PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),
316 PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),
317 PINCTRL_PIN(UART3_RX, "uart3_rx"),
318 PINCTRL_PIN(UART3_TX, "uart3_tx"),
319 PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),
320 PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),
321 PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),
322 PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),
323 PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),
324 PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),
325 PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),
326 PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),
327 PINCTRL_PIN(CSI_DN0, "csi_dn0"),
328 PINCTRL_PIN(CSI_DP0, "csi_dp0"),
329 PINCTRL_PIN(CSI_DN1, "csi_dn1"),
330 PINCTRL_PIN(CSI_DP1, "csi_dp1"),
331 PINCTRL_PIN(CSI_CN, "csi_cn"),
332 PINCTRL_PIN(CSI_CP, "csi_cp"),
333 PINCTRL_PIN(CSI_DN2, "csi_dn2"),
334 PINCTRL_PIN(CSI_DP2, "csi_dp2"),
335 PINCTRL_PIN(CSI_DN3, "csi_dn3"),
336 PINCTRL_PIN(CSI_DP3, "csi_dp3"),
337 PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),
338 PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),
339 PINCTRL_PIN(DNAND_D0, "dnand_d0"),
340 PINCTRL_PIN(DNAND_D1, "dnand_d1"),
341 PINCTRL_PIN(DNAND_D2, "dnand_d2"),
342 PINCTRL_PIN(DNAND_D3, "dnand_d3"),
343 PINCTRL_PIN(DNAND_D4, "dnand_d4"),
344 PINCTRL_PIN(DNAND_D5, "dnand_d5"),
345 PINCTRL_PIN(DNAND_D6, "dnand_d6"),
346 PINCTRL_PIN(DNAND_D7, "dnand_d7"),
347 PINCTRL_PIN(DNAND_WRB, "dnand_wrb"),
348 PINCTRL_PIN(DNAND_RDB, "dnand_rdb"),
349 PINCTRL_PIN(DNAND_RDBN, "dnand_rdbn"),
350 PINCTRL_PIN(DNAND_DQS, "dnand_dqs"),
351 PINCTRL_PIN(DNAND_DQSN, "dnand_dqsn"),
352 PINCTRL_PIN(DNAND_RB0, "dnand_rb0"),
353 PINCTRL_PIN(DNAND_ALE, "dnand_ale"),
354 PINCTRL_PIN(DNAND_CLE, "dnand_cle"),
355 PINCTRL_PIN(DNAND_CEB0, "dnand_ceb0"),
356 PINCTRL_PIN(DNAND_CEB1, "dnand_ceb1"),
357 PINCTRL_PIN(DNAND_CEB2, "dnand_ceb2"),
358 PINCTRL_PIN(DNAND_CEB3, "dnand_ceb3"),
359 PINCTRL_PIN(PORB, "porb"),
360 PINCTRL_PIN(CLKO_25M, "clko_25m"),
361 PINCTRL_PIN(BSEL, "bsel"),
362 PINCTRL_PIN(PKG0, "pkg0"),
363 PINCTRL_PIN(PKG1, "pkg1"),
364 PINCTRL_PIN(PKG2, "pkg2"),
365 PINCTRL_PIN(PKG3, "pkg3"),
366 };
367
368 enum s700_pinmux_functions {
369 S700_MUX_NOR,
370 S700_MUX_ETH_RGMII,
371 S700_MUX_ETH_SGMII,
372 S700_MUX_SPI0,
373 S700_MUX_SPI1,
374 S700_MUX_SPI2,
375 S700_MUX_SPI3,
376 S700_MUX_SENS0,
377 S700_MUX_SENS1,
378 S700_MUX_UART0,
379 S700_MUX_UART1,
380 S700_MUX_UART2,
381 S700_MUX_UART3,
382 S700_MUX_UART4,
383 S700_MUX_UART5,
384 S700_MUX_UART6,
385 S700_MUX_I2S0,
386 S700_MUX_I2S1,
387 S700_MUX_PCM1,
388 S700_MUX_PCM0,
389 S700_MUX_KS,
390 S700_MUX_JTAG,
391 S700_MUX_PWM0,
392 S700_MUX_PWM1,
393 S700_MUX_PWM2,
394 S700_MUX_PWM3,
395 S700_MUX_PWM4,
396 S700_MUX_PWM5,
397 S700_MUX_P0,
398 S700_MUX_SD0,
399 S700_MUX_SD1,
400 S700_MUX_SD2,
401 S700_MUX_I2C0,
402 S700_MUX_I2C1,
403 S700_MUX_I2C2,
404 S700_MUX_I2C3,
405 S700_MUX_DSI,
406 S700_MUX_LVDS,
407 S700_MUX_USB30,
408 S700_MUX_CLKO_25M,
409 S700_MUX_MIPI_CSI,
410 S700_MUX_NAND,
411 S700_MUX_SPDIF,
412 S700_MUX_SIRQ0,
413 S700_MUX_SIRQ1,
414 S700_MUX_SIRQ2,
415 S700_MUX_BT,
416 S700_MUX_LCD0,
417 S700_MUX_RESERVED,
418 };
419
420 /* mfp0_31_30 reserved */
421
422 /* rgmii_txd23 */
423 static unsigned int rgmii_txd23_mfp_pads[] = { ETH_TXD2, ETH_TXD3};
424 static unsigned int rgmii_txd23_mfp_funcs[] = { S700_MUX_ETH_RGMII,
425 S700_MUX_I2C1,
426 S700_MUX_UART3 };
427 /* rgmii_rxd2 */
428 static unsigned int rgmii_rxd2_mfp_pads[] = { ETH_RXD2 };
429 static unsigned int rgmii_rxd2_mfp_funcs[] = { S700_MUX_ETH_RGMII,
430 S700_MUX_PWM0,
431 S700_MUX_UART3 };
432 /* rgmii_rxd3 */
433 static unsigned int rgmii_rxd3_mfp_pads[] = { ETH_RXD3};
434 static unsigned int rgmii_rxd3_mfp_funcs[] = { S700_MUX_ETH_RGMII,
435 S700_MUX_PWM2,
436 S700_MUX_UART3 };
437 /* lcd0_d18 */
438 static unsigned int lcd0_d18_mfp_pads[] = { LCD0_D18 };
439 static unsigned int lcd0_d18_mfp_funcs[] = { S700_MUX_NOR,
440 S700_MUX_SENS1,
441 S700_MUX_PWM2,
442 S700_MUX_PWM4,
443 S700_MUX_LCD0 };
444 /* rgmii_txd01 */
445 static unsigned int rgmii_txd01_mfp_pads[] = { ETH_CRS_DV };
446 static unsigned int rgmii_txd01_mfp_funcs[] = { S700_MUX_ETH_RGMII,
447 S700_MUX_RESERVED,
448 S700_MUX_SPI2,
449 S700_MUX_UART4,
450 S700_MUX_PWM4 };
451 /* rgmii_txd0 */
452 static unsigned int rgmii_txd0_mfp_pads[] = { ETH_TXD0 };
453 static unsigned int rgmii_txd0_mfp_funcs[] = { S700_MUX_ETH_RGMII,
454 S700_MUX_ETH_SGMII,
455 S700_MUX_SPI2,
456 S700_MUX_UART6,
457 S700_MUX_PWM4 };
458 /* rgmii_txd1 */
459 static unsigned int rgmii_txd1_mfp_pads[] = { ETH_TXD1 };
460 static unsigned int rgmii_txd1_mfp_funcs[] = { S700_MUX_ETH_RGMII,
461 S700_MUX_ETH_SGMII,
462 S700_MUX_SPI2,
463 S700_MUX_UART6,
464 S700_MUX_PWM5 };
465 /* rgmii_txen */
466 static unsigned int rgmii_txen_mfp_pads[] = { ETH_TXEN };
467 static unsigned int rgmii_txen_mfp_funcs[] = { S700_MUX_ETH_RGMII,
468 S700_MUX_UART2,
469 S700_MUX_SPI3,
470 S700_MUX_PWM0 };
471 /* rgmii_rxen */
472 static unsigned int rgmii_rxen_mfp_pads[] = { ETH_RXER };
473 static unsigned int rgmii_rxen_mfp_funcs[] = { S700_MUX_ETH_RGMII,
474 S700_MUX_UART2,
475 S700_MUX_SPI3,
476 S700_MUX_PWM1 };
477 /* mfp0_12_11 reserved */
478 /* rgmii_rxd1*/
479 static unsigned int rgmii_rxd1_mfp_pads[] = { ETH_RXD1 };
480 static unsigned int rgmii_rxd1_mfp_funcs[] = { S700_MUX_ETH_RGMII,
481 S700_MUX_UART2,
482 S700_MUX_SPI3,
483 S700_MUX_PWM2,
484 S700_MUX_UART5,
485 S700_MUX_ETH_SGMII };
486 /* rgmii_rxd0 */
487 static unsigned int rgmii_rxd0_mfp_pads[] = { ETH_RXD0 };
488 static unsigned int rgmii_rxd0_mfp_funcs[] = { S700_MUX_ETH_RGMII,
489 S700_MUX_UART2,
490 S700_MUX_SPI3,
491 S700_MUX_PWM3,
492 S700_MUX_UART5,
493 S700_MUX_ETH_SGMII };
494 /* rgmii_ref_clk */
495 static unsigned int rgmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };
496 static unsigned int rgmii_ref_clk_mfp_funcs[] = { S700_MUX_ETH_RGMII,
497 S700_MUX_UART4,
498 S700_MUX_SPI2,
499 S700_MUX_RESERVED,
500 S700_MUX_ETH_SGMII };
501 /* i2s_d0 */
502 static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 };
503 static unsigned int i2s_d0_mfp_funcs[] = { S700_MUX_I2S0,
504 S700_MUX_NOR };
505 /* i2s_pcm1 */
506 static unsigned int i2s_pcm1_mfp_pads[] = { I2S_LRCLK0,
507 I2S_MCLK0 };
508 static unsigned int i2s_pcm1_mfp_funcs[] = { S700_MUX_I2S0,
509 S700_MUX_NOR,
510 S700_MUX_PCM1,
511 S700_MUX_BT };
512 /* i2s0_pcm0 */
513 static unsigned int i2s0_pcm0_mfp_pads[] = { I2S_BCLK0 };
514 static unsigned int i2s0_pcm0_mfp_funcs[] = { S700_MUX_I2S0,
515 S700_MUX_NOR,
516 S700_MUX_PCM0,
517 S700_MUX_BT };
518 /* i2s1_pcm0 */
519 static unsigned int i2s1_pcm0_mfp_pads[] = { I2S_BCLK1,
520 I2S_LRCLK1,
521 I2S_MCLK1 };
522
523 static unsigned int i2s1_pcm0_mfp_funcs[] = { S700_MUX_I2S1,
524 S700_MUX_NOR,
525 S700_MUX_PCM0,
526 S700_MUX_BT };
527 /* i2s_d1 */
528 static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 };
529 static unsigned int i2s_d1_mfp_funcs[] = { S700_MUX_I2S1,
530 S700_MUX_NOR };
531 /* ks_in2 */
532 static unsigned int ks_in2_mfp_pads[] = { KS_IN2 };
533 static unsigned int ks_in2_mfp_funcs[] = { S700_MUX_KS,
534 S700_MUX_JTAG,
535 S700_MUX_NOR,
536 S700_MUX_BT,
537 S700_MUX_PWM0,
538 S700_MUX_SENS1,
539 S700_MUX_PWM0,
540 S700_MUX_P0 };
541 /* ks_in1 */
542 static unsigned int ks_in1_mfp_pads[] = { KS_IN1 };
543 static unsigned int ks_in1_mfp_funcs[] = { S700_MUX_KS,
544 S700_MUX_JTAG,
545 S700_MUX_NOR,
546 S700_MUX_BT,
547 S700_MUX_PWM5,
548 S700_MUX_SENS1,
549 S700_MUX_PWM1,
550 S700_MUX_USB30 };
551 /* ks_in0 */
552 static unsigned int ks_in0_mfp_pads[] = { KS_IN0 };
553 static unsigned int ks_in0_mfp_funcs[] = { S700_MUX_KS,
554 S700_MUX_JTAG,
555 S700_MUX_NOR,
556 S700_MUX_BT,
557 S700_MUX_PWM4,
558 S700_MUX_SENS1,
559 S700_MUX_PWM4,
560 S700_MUX_P0 };
561 /* ks_in3 */
562 static unsigned int ks_in3_mfp_pads[] = { KS_IN3 };
563 static unsigned int ks_in3_mfp_funcs[] = { S700_MUX_KS,
564 S700_MUX_JTAG,
565 S700_MUX_NOR,
566 S700_MUX_PWM1,
567 S700_MUX_BT,
568 S700_MUX_SENS1 };
569 /* ks_out0 */
570 static unsigned int ks_out0_mfp_pads[] = { KS_OUT0 };
571 static unsigned int ks_out0_mfp_funcs[] = { S700_MUX_KS,
572 S700_MUX_UART5,
573 S700_MUX_NOR,
574 S700_MUX_PWM2,
575 S700_MUX_BT,
576 S700_MUX_SENS1,
577 S700_MUX_SD0,
578 S700_MUX_UART4 };
579
580 /* ks_out1 */
581 static unsigned int ks_out1_mfp_pads[] = { KS_OUT1 };
582 static unsigned int ks_out1_mfp_funcs[] = { S700_MUX_KS,
583 S700_MUX_JTAG,
584 S700_MUX_NOR,
585 S700_MUX_PWM3,
586 S700_MUX_BT,
587 S700_MUX_SENS1,
588 S700_MUX_SD0,
589 S700_MUX_UART4 };
590 /* ks_out2 */
591 static unsigned int ks_out2_mfp_pads[] = { KS_OUT2 };
592 static unsigned int ks_out2_mfp_funcs[] = { S700_MUX_SD0,
593 S700_MUX_KS,
594 S700_MUX_NOR,
595 S700_MUX_PWM2,
596 S700_MUX_UART5,
597 S700_MUX_SENS1,
598 S700_MUX_BT };
599 /* lvds_o_pn */
600 static unsigned int lvds_o_pn_mfp_pads[] = { LVDS_OEP,
601 LVDS_OEN,
602 LVDS_ODP,
603 LVDS_ODN,
604 LVDS_OCP,
605 LVDS_OCN,
606 LVDS_OBP,
607 LVDS_OBN,
608 LVDS_OAP,
609 LVDS_OAN };
610
611 static unsigned int lvds_o_pn_mfp_funcs[] = { S700_MUX_LVDS,
612 S700_MUX_BT,
613 S700_MUX_LCD0 };
614
615 /* dsi_dn0 */
616 static unsigned int dsi_dn0_mfp_pads[] = { DSI_DN0 };
617 static unsigned int dsi_dn0_mfp_funcs[] = { S700_MUX_DSI,
618 S700_MUX_UART2,
619 S700_MUX_SPI0 };
620 /* dsi_dp2 */
621 static unsigned int dsi_dp2_mfp_pads[] = { DSI_DP2 };
622 static unsigned int dsi_dp2_mfp_funcs[] = { S700_MUX_DSI,
623 S700_MUX_UART2,
624 S700_MUX_SPI0,
625 S700_MUX_SD1 };
626 /* lcd0_d2 */
627 static unsigned int lcd0_d2_mfp_pads[] = { LCD0_D2 };
628 static unsigned int lcd0_d2_mfp_funcs[] = { S700_MUX_NOR,
629 S700_MUX_SD0,
630 S700_MUX_RESERVED,
631 S700_MUX_PWM3,
632 S700_MUX_LCD0 };
633 /* dsi_dp3 */
634 static unsigned int dsi_dp3_mfp_pads[] = { DSI_DP3 };
635 static unsigned int dsi_dp3_mfp_funcs[] = { S700_MUX_DSI,
636 S700_MUX_SD0,
637 S700_MUX_SD1,
638 S700_MUX_LCD0 };
639 /* dsi_dn3 */
640 static unsigned int dsi_dn3_mfp_pads[] = { DSI_DN3 };
641 static unsigned int dsi_dn3_mfp_funcs[] = { S700_MUX_DSI,
642 S700_MUX_SD0,
643 S700_MUX_SD1,
644 S700_MUX_LCD0 };
645 /* dsi_dp0 */
646 static unsigned int dsi_dp0_mfp_pads[] = { DSI_DP0 };
647 static unsigned int dsi_dp0_mfp_funcs[] = { S700_MUX_DSI,
648 S700_MUX_RESERVED,
649 S700_MUX_SD0,
650 S700_MUX_UART2,
651 S700_MUX_SPI0 };
652 /* lvds_ee_pn */
653 static unsigned int lvds_ee_pn_mfp_pads[] = { LVDS_EEP,
654 LVDS_EEN };
655 static unsigned int lvds_ee_pn_mfp_funcs[] = { S700_MUX_LVDS,
656 S700_MUX_NOR,
657 S700_MUX_BT,
658 S700_MUX_LCD0 };
659 /* uart2_rx_tx */
660 static unsigned int uart2_rx_tx_mfp_pads[] = { UART2_RX,
661 UART2_TX };
662 static unsigned int uart2_rx_tx_mfp_funcs[] = { S700_MUX_UART2,
663 S700_MUX_NOR,
664 S700_MUX_SPI0,
665 S700_MUX_PCM0 };
666 /* spi0_i2c_pcm */
667 static unsigned int spi0_i2c_pcm_mfp_pads[] = { SPI0_SS,
668 SPI0_MISO };
669 static unsigned int spi0_i2c_pcm_mfp_funcs[] = { S700_MUX_SPI0,
670 S700_MUX_NOR,
671 S700_MUX_I2S1,
672 S700_MUX_PCM1,
673 S700_MUX_PCM0,
674 S700_MUX_I2C2 };
675 /* mfp2_31 reserved */
676
677 /* dsi_dnp1_cp_d2 */
678 static unsigned int dsi_dnp1_cp_d2_mfp_pads[] = { DSI_DP1,
679 DSI_CP,
680 DSI_CN };
681 static unsigned int dsi_dnp1_cp_d2_mfp_funcs[] = { S700_MUX_DSI,
682 S700_MUX_LCD0,
683 S700_MUX_RESERVED };
684 /* dsi_dnp1_cp_d17 */
685 static unsigned int dsi_dnp1_cp_d17_mfp_pads[] = { DSI_DP1,
686 DSI_CP,
687 DSI_CN };
688
689 static unsigned int dsi_dnp1_cp_d17_mfp_funcs[] = { S700_MUX_DSI,
690 S700_MUX_RESERVED,
691 S700_MUX_LCD0 };
692 /* lvds_e_pn */
693 static unsigned int lvds_e_pn_mfp_pads[] = { LVDS_EDP,
694 LVDS_EDN,
695 LVDS_ECP,
696 LVDS_ECN,
697 LVDS_EBP,
698 LVDS_EBN,
699 LVDS_EAP,
700 LVDS_EAN };
701
702 static unsigned int lvds_e_pn_mfp_funcs[] = { S700_MUX_LVDS,
703 S700_MUX_NOR,
704 S700_MUX_LCD0 };
705 /* dsi_dn2 */
706 static unsigned int dsi_dn2_mfp_pads[] = { DSI_DN2 };
707 static unsigned int dsi_dn2_mfp_funcs[] = { S700_MUX_DSI,
708 S700_MUX_RESERVED,
709 S700_MUX_SD1,
710 S700_MUX_UART2,
711 S700_MUX_SPI0 };
712 /* uart2_rtsb */
713 static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB };
714 static unsigned int uart2_rtsb_mfp_funcs[] = { S700_MUX_UART2,
715 S700_MUX_UART0 };
716
717 /* uart2_ctsb */
718 static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB };
719 static unsigned int uart2_ctsb_mfp_funcs[] = { S700_MUX_UART2,
720 S700_MUX_UART0 };
721 /* uart3_rtsb */
722 static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB };
723 static unsigned int uart3_rtsb_mfp_funcs[] = { S700_MUX_UART3,
724 S700_MUX_UART5 };
725
726 /* uart3_ctsb */
727 static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB };
728 static unsigned int uart3_ctsb_mfp_funcs[] = { S700_MUX_UART3,
729 S700_MUX_UART5 };
730 /* sd0_d0 */
731 static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 };
732 static unsigned int sd0_d0_mfp_funcs[] = { S700_MUX_SD0,
733 S700_MUX_NOR,
734 S700_MUX_RESERVED,
735 S700_MUX_JTAG,
736 S700_MUX_UART2,
737 S700_MUX_UART5 };
738 /* sd0_d1 */
739 static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 };
740 static unsigned int sd0_d1_mfp_funcs[] = { S700_MUX_SD0,
741 S700_MUX_NOR,
742 S700_MUX_RESERVED,
743 S700_MUX_RESERVED,
744 S700_MUX_UART2,
745 S700_MUX_UART5 };
746 /* sd0_d2_d3 */
747 static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2,
748 SD0_D3 };
749 static unsigned int sd0_d2_d3_mfp_funcs[] = { S700_MUX_SD0,
750 S700_MUX_NOR,
751 S700_MUX_RESERVED,
752 S700_MUX_JTAG,
753 S700_MUX_UART2,
754 S700_MUX_UART1 };
755
756 /* sd1_d0_d3 */
757 static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0,
758 SD1_D1,
759 SD1_D2,
760 SD1_D3 };
761 static unsigned int sd1_d0_d3_mfp_funcs[] = { S700_MUX_SD0,
762 S700_MUX_NOR,
763 S700_MUX_RESERVED,
764 S700_MUX_SD1 };
765
766 /* sd0_cmd */
767 static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD };
768 static unsigned int sd0_cmd_mfp_funcs[] = { S700_MUX_SD0,
769 S700_MUX_NOR,
770 S700_MUX_RESERVED,
771 S700_MUX_JTAG };
772 /* sd0_clk */
773 static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK };
774 static unsigned int sd0_clk_mfp_funcs[] = { S700_MUX_SD0,
775 S700_MUX_RESERVED,
776 S700_MUX_JTAG };
777 /* sd1_cmd */
778 static unsigned int sd1_cmd_mfp_pads[] = { SD1_CMD };
779 static unsigned int sd1_cmd_mfp_funcs[] = { S700_MUX_SD1,
780 S700_MUX_NOR };
781 /* uart0_rx */
782 static unsigned int uart0_rx_mfp_pads[] = { UART0_RX };
783 static unsigned int uart0_rx_mfp_funcs[] = { S700_MUX_UART0,
784 S700_MUX_UART2,
785 S700_MUX_SPI1,
786 S700_MUX_I2C0,
787 S700_MUX_PCM1,
788 S700_MUX_I2S1 };
789 /* dnand_data_wr1 reserved */
790
791 /* clko_25m */
792 static unsigned int clko_25m_mfp_pads[] = { CLKO_25M };
793 static unsigned int clko_25m_mfp_funcs[] = { S700_MUX_RESERVED,
794 S700_MUX_CLKO_25M };
795 /* csi_cn_cp */
796 static unsigned int csi_cn_cp_mfp_pads[] = { CSI_CN,
797 CSI_CP };
798 static unsigned int csi_cn_cp_mfp_funcs[] = { S700_MUX_MIPI_CSI,
799 S700_MUX_SENS0 };
800 /* dnand_acle_ce07_24 reserved */
801
802 /* sens0_ckout */
803 static unsigned int sens0_ckout_mfp_pads[] = { SENSOR0_CKOUT };
804 static unsigned int sens0_ckout_mfp_funcs[] = { S700_MUX_SENS0,
805 S700_MUX_NOR,
806 S700_MUX_SENS1,
807 S700_MUX_PWM1 };
808 /* uart0_tx */
809 static unsigned int uart0_tx_mfp_pads[] = { UART0_TX };
810 static unsigned int uart0_tx_mfp_funcs[] = { S700_MUX_UART0,
811 S700_MUX_UART2,
812 S700_MUX_SPI1,
813 S700_MUX_I2C0,
814 S700_MUX_SPDIF,
815 S700_MUX_PCM1,
816 S700_MUX_I2S1 };
817 /* i2c0_mfp */
818 static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK,
819 I2C0_SDATA };
820 static unsigned int i2c0_mfp_funcs[] = { S700_MUX_I2C0,
821 S700_MUX_UART2,
822 S700_MUX_I2C1,
823 S700_MUX_UART1,
824 S700_MUX_SPI1 };
825 /* csi_dn_dp */
826 static unsigned int csi_dn_dp_mfp_pads[] = { CSI_DN0,
827 CSI_DN1,
828 CSI_DN2,
829 CSI_DN3,
830 CSI_DP0,
831 CSI_DP1,
832 CSI_DP2,
833 CSI_DP3 };
834 static unsigned int csi_dn_dp_mfp_funcs[] = { S700_MUX_MIPI_CSI,
835 S700_MUX_SENS0 };
836 /* sen0_pclk */
837 static unsigned int sen0_pclk_mfp_pads[] = { SENSOR0_PCLK };
838 static unsigned int sen0_pclk_mfp_funcs[] = { S700_MUX_SENS0,
839 S700_MUX_NOR,
840 S700_MUX_PWM0 };
841 /* pcm1_in */
842 static unsigned int pcm1_in_mfp_pads[] = { PCM1_IN };
843 static unsigned int pcm1_in_mfp_funcs[] = { S700_MUX_PCM1,
844 S700_MUX_SENS1,
845 S700_MUX_BT,
846 S700_MUX_PWM4 };
847 /* pcm1_clk */
848 static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK };
849 static unsigned int pcm1_clk_mfp_funcs[] = { S700_MUX_PCM1,
850 S700_MUX_SENS1,
851 S700_MUX_BT,
852 S700_MUX_PWM5 };
853 /* pcm1_sync */
854 static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC };
855 static unsigned int pcm1_sync_mfp_funcs[] = { S700_MUX_PCM1,
856 S700_MUX_SENS1,
857 S700_MUX_BT,
858 S700_MUX_I2C3 };
859 /* pcm1_out */
860 static unsigned int pcm1_out_mfp_pads[] = { PCM1_OUT };
861 static unsigned int pcm1_out_mfp_funcs[] = { S700_MUX_PCM1,
862 S700_MUX_SENS1,
863 S700_MUX_BT,
864 S700_MUX_I2C3 };
865 /* dnand_data_wr */
866 static unsigned int dnand_data_wr_mfp_pads[] = { DNAND_D0,
867 DNAND_D1,
868 DNAND_D2,
869 DNAND_D3,
870 DNAND_D4,
871 DNAND_D5,
872 DNAND_D6,
873 DNAND_D7,
874 DNAND_RDB,
875 DNAND_RDBN };
876 static unsigned int dnand_data_wr_mfp_funcs[] = { S700_MUX_NAND,
877 S700_MUX_SD2 };
878 /* dnand_acle_ce0 */
879 static unsigned int dnand_acle_ce0_mfp_pads[] = { DNAND_ALE,
880 DNAND_CLE,
881 DNAND_CEB0,
882 DNAND_CEB1 };
883 static unsigned int dnand_acle_ce0_mfp_funcs[] = { S700_MUX_NAND,
884 S700_MUX_SPI2 };
885
886 /* nand_ceb2 */
887 static unsigned int nand_ceb2_mfp_pads[] = { DNAND_CEB2 };
888 static unsigned int nand_ceb2_mfp_funcs[] = { S700_MUX_NAND,
889 S700_MUX_PWM5 };
890 /* nand_ceb3 */
891 static unsigned int nand_ceb3_mfp_pads[] = { DNAND_CEB3 };
892 static unsigned int nand_ceb3_mfp_funcs[] = { S700_MUX_NAND,
893 S700_MUX_PWM4 };
894 /*****End MFP group data****************************/
895
896 /*****PADDRV group data****************************/
897
898 /*PAD_DRV0*/
899 static unsigned int sirq_drv_pads[] = { SIRQ0,
900 SIRQ1,
901 SIRQ2 };
902
903 static unsigned int rgmii_txd23_drv_pads[] = { ETH_TXD2,
904 ETH_TXD3 };
905
906 static unsigned int rgmii_rxd23_drv_pads[] = { ETH_RXD2,
907 ETH_RXD3 };
908
909 static unsigned int rgmii_txd01_txen_drv_pads[] = { ETH_TXD0,
910 ETH_TXD1,
911 ETH_TXEN };
912
913 static unsigned int rgmii_rxer_drv_pads[] = { ETH_RXER };
914
915 static unsigned int rgmii_crs_drv_pads[] = { ETH_CRS_DV };
916
917 static unsigned int rgmii_rxd10_drv_pads[] = { ETH_RXD0,
918 ETH_RXD1 };
919
920 static unsigned int rgmii_ref_clk_drv_pads[] = { ETH_REF_CLK };
921
922 static unsigned int smi_mdc_mdio_drv_pads[] = { ETH_MDC,
923 ETH_MDIO };
924
925 static unsigned int i2s_d0_drv_pads[] = { I2S_D0 };
926
927 static unsigned int i2s_bclk0_drv_pads[] = { I2S_BCLK0 };
928
929 static unsigned int i2s3_drv_pads[] = { I2S_LRCLK0,
930 I2S_MCLK0,
931 I2S_D1 };
932
933 static unsigned int i2s13_drv_pads[] = { I2S_BCLK1,
934 I2S_LRCLK1,
935 I2S_MCLK1 };
936
937 static unsigned int pcm1_drv_pads[] = { PCM1_IN,
938 PCM1_CLK,
939 PCM1_SYNC,
940 PCM1_OUT };
941
942 static unsigned int ks_in_drv_pads[] = { KS_IN0,
943 KS_IN1,
944 KS_IN2,
945 KS_IN3 };
946
947 /*PAD_DRV1*/
948 static unsigned int ks_out_drv_pads[] = { KS_OUT0,
949 KS_OUT1,
950 KS_OUT2 };
951
952 static unsigned int lvds_all_drv_pads[] = { LVDS_OEP,
953 LVDS_OEN,
954 LVDS_ODP,
955 LVDS_ODN,
956 LVDS_OCP,
957 LVDS_OCN,
958 LVDS_OBP,
959 LVDS_OBN,
960 LVDS_OAP,
961 LVDS_OAN,
962 LVDS_EEP,
963 LVDS_EEN,
964 LVDS_EDP,
965 LVDS_EDN,
966 LVDS_ECP,
967 LVDS_ECN,
968 LVDS_EBP,
969 LVDS_EBN,
970 LVDS_EAP,
971 LVDS_EAN };
972
973 static unsigned int lcd_d18_d2_drv_pads[] = { LCD0_D18,
974 LCD0_D2 };
975
976 static unsigned int dsi_all_drv_pads[] = { DSI_DP0,
977 DSI_DN0,
978 DSI_DP2,
979 DSI_DN2,
980 DSI_DP3,
981 DSI_DN3,
982 DSI_DP1,
983 DSI_DN1,
984 DSI_CP,
985 DSI_CN };
986
987 static unsigned int sd0_d0_d3_drv_pads[] = { SD0_D0,
988 SD0_D1,
989 SD0_D2,
990 SD0_D3 };
991
992 static unsigned int sd0_cmd_drv_pads[] = { SD0_CMD };
993
994 static unsigned int sd0_clk_drv_pads[] = { SD0_CLK };
995
996 static unsigned int spi0_all_drv_pads[] = { SPI0_SS,
997 SPI0_MISO };
998
999 /*PAD_DRV2*/
1000 static unsigned int uart0_rx_drv_pads[] = { UART0_RX };
1001
1002 static unsigned int uart0_tx_drv_pads[] = { UART0_TX };
1003
1004 static unsigned int uart2_all_drv_pads[] = { UART2_RX,
1005 UART2_TX,
1006 UART2_RTSB,
1007 UART2_CTSB };
1008
1009 static unsigned int i2c0_all_drv_pads[] = { I2C0_SCLK,
1010 I2C0_SDATA };
1011
1012 static unsigned int i2c12_all_drv_pads[] = { I2C1_SCLK,
1013 I2C1_SDATA,
1014 I2C2_SCLK,
1015 I2C2_SDATA };
1016
1017 static unsigned int sens0_pclk_drv_pads[] = { SENSOR0_PCLK };
1018
1019 static unsigned int sens0_ckout_drv_pads[] = { SENSOR0_CKOUT };
1020
1021 static unsigned int uart3_all_drv_pads[] = { UART3_RX,
1022 UART3_TX,
1023 UART3_RTSB,
1024 UART3_CTSB };
1025
1026 /* all pinctrl groups of S700 board */
1027 static const struct owl_pingroup s700_groups[] = {
1028 MUX_PG(rgmii_txd23_mfp, 0, 28, 2),
1029 MUX_PG(rgmii_rxd2_mfp, 0, 26, 2),
1030 MUX_PG(rgmii_rxd3_mfp, 0, 26, 2),
1031 MUX_PG(lcd0_d18_mfp, 0, 23, 3),
1032 MUX_PG(rgmii_txd01_mfp, 0, 20, 3),
1033 MUX_PG(rgmii_txd0_mfp, 0, 16, 3),
1034 MUX_PG(rgmii_txd1_mfp, 0, 16, 3),
1035 MUX_PG(rgmii_txen_mfp, 0, 13, 3),
1036 MUX_PG(rgmii_rxen_mfp, 0, 13, 3),
1037 MUX_PG(rgmii_rxd1_mfp, 0, 8, 3),
1038 MUX_PG(rgmii_rxd0_mfp, 0, 8, 3),
1039 MUX_PG(rgmii_ref_clk_mfp, 0, 6, 2),
1040 MUX_PG(i2s_d0_mfp, 0, 5, 1),
1041 MUX_PG(i2s_pcm1_mfp, 0, 3, 2),
1042 MUX_PG(i2s0_pcm0_mfp, 0, 1, 2),
1043 MUX_PG(i2s1_pcm0_mfp, 0, 1, 2),
1044 MUX_PG(i2s_d1_mfp, 0, 0, 1),
1045 MUX_PG(ks_in2_mfp, 1, 29, 3),
1046 MUX_PG(ks_in1_mfp, 1, 29, 3),
1047 MUX_PG(ks_in0_mfp, 1, 29, 3),
1048 MUX_PG(ks_in3_mfp, 1, 26, 3),
1049 MUX_PG(ks_out0_mfp, 1, 26, 3),
1050 MUX_PG(ks_out1_mfp, 1, 26, 3),
1051 MUX_PG(ks_out2_mfp, 1, 23, 3),
1052 MUX_PG(lvds_o_pn_mfp, 1, 21, 2),
1053 MUX_PG(dsi_dn0_mfp, 1, 19, 2),
1054 MUX_PG(dsi_dp2_mfp, 1, 17, 2),
1055 MUX_PG(lcd0_d2_mfp, 1, 14, 3),
1056 MUX_PG(dsi_dp3_mfp, 1, 12, 2),
1057 MUX_PG(dsi_dn3_mfp, 1, 10, 2),
1058 MUX_PG(dsi_dp0_mfp, 1, 7, 3),
1059 MUX_PG(lvds_ee_pn_mfp, 1, 5, 2),
1060 MUX_PG(uart2_rx_tx_mfp, 1, 3, 2),
1061 MUX_PG(spi0_i2c_pcm_mfp, 1, 0, 3),
1062 MUX_PG(dsi_dnp1_cp_d2_mfp, 2, 29, 2),
1063 MUX_PG(dsi_dnp1_cp_d17_mfp, 2, 29, 2),
1064 MUX_PG(lvds_e_pn_mfp, 2, 27, 2),
1065 MUX_PG(dsi_dn2_mfp, 2, 24, 3),
1066 MUX_PG(uart2_rtsb_mfp, 2, 23, 1),
1067 MUX_PG(uart2_ctsb_mfp, 2, 22, 1),
1068 MUX_PG(uart3_rtsb_mfp, 2, 21, 1),
1069 MUX_PG(uart3_ctsb_mfp, 2, 20, 1),
1070 MUX_PG(sd0_d0_mfp, 2, 17, 3),
1071 MUX_PG(sd0_d1_mfp, 2, 14, 3),
1072 MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),
1073 MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),
1074 MUX_PG(sd0_cmd_mfp, 2, 7, 2),
1075 MUX_PG(sd0_clk_mfp, 2, 5, 2),
1076 MUX_PG(sd1_cmd_mfp, 2, 3, 2),
1077 MUX_PG(uart0_rx_mfp, 2, 0, 3),
1078 MUX_PG(clko_25m_mfp, 3, 30, 1),
1079 MUX_PG(csi_cn_cp_mfp, 3, 28, 2),
1080 MUX_PG(sens0_ckout_mfp, 3, 22, 2),
1081 MUX_PG(uart0_tx_mfp, 3, 19, 3),
1082 MUX_PG(i2c0_mfp, 3, 16, 3),
1083 MUX_PG(csi_dn_dp_mfp, 3, 14, 2),
1084 MUX_PG(sen0_pclk_mfp, 3, 12, 2),
1085 MUX_PG(pcm1_in_mfp, 3, 10, 2),
1086 MUX_PG(pcm1_clk_mfp, 3, 8, 2),
1087 MUX_PG(pcm1_sync_mfp, 3, 6, 2),
1088 MUX_PG(pcm1_out_mfp, 3, 4, 2),
1089 MUX_PG(dnand_data_wr_mfp, 3, 3, 1),
1090 MUX_PG(dnand_acle_ce0_mfp, 3, 2, 1),
1091 MUX_PG(nand_ceb2_mfp, 3, 0, 2),
1092 MUX_PG(nand_ceb3_mfp, 3, 0, 2),
1093
1094 DRV_PG(sirq_drv, 0, 28, 2),
1095 DRV_PG(rgmii_txd23_drv, 0, 26, 2),
1096 DRV_PG(rgmii_rxd23_drv, 0, 24, 2),
1097 DRV_PG(rgmii_txd01_txen_drv, 0, 22, 2),
1098 DRV_PG(rgmii_rxer_drv, 0, 20, 2),
1099 DRV_PG(rgmii_crs_drv, 0, 18, 2),
1100 DRV_PG(rgmii_rxd10_drv, 0, 16, 2),
1101 DRV_PG(rgmii_ref_clk_drv, 0, 14, 2),
1102 DRV_PG(smi_mdc_mdio_drv, 0, 12, 2),
1103 DRV_PG(i2s_d0_drv, 0, 10, 2),
1104 DRV_PG(i2s_bclk0_drv, 0, 8, 2),
1105 DRV_PG(i2s3_drv, 0, 6, 2),
1106 DRV_PG(i2s13_drv, 0, 4, 2),
1107 DRV_PG(pcm1_drv, 0, 2, 2),
1108 DRV_PG(ks_in_drv, 0, 0, 2),
1109 DRV_PG(ks_out_drv, 1, 30, 2),
1110 DRV_PG(lvds_all_drv, 1, 28, 2),
1111 DRV_PG(lcd_d18_d2_drv, 1, 26, 2),
1112 DRV_PG(dsi_all_drv, 1, 24, 2),
1113 DRV_PG(sd0_d0_d3_drv, 1, 22, 2),
1114 DRV_PG(sd0_cmd_drv, 1, 18, 2),
1115 DRV_PG(sd0_clk_drv, 1, 16, 2),
1116 DRV_PG(spi0_all_drv, 1, 10, 2),
1117 DRV_PG(uart0_rx_drv, 2, 30, 2),
1118 DRV_PG(uart0_tx_drv, 2, 28, 2),
1119 DRV_PG(uart2_all_drv, 2, 26, 2),
1120 DRV_PG(i2c0_all_drv, 2, 23, 2),
1121 DRV_PG(i2c12_all_drv, 2, 21, 2),
1122 DRV_PG(sens0_pclk_drv, 2, 18, 2),
1123 DRV_PG(sens0_ckout_drv, 2, 12, 2),
1124 DRV_PG(uart3_all_drv, 2, 2, 2),
1125 };
1126
1127 static const char * const nor_groups[] = {
1128 "lcd0_d18_mfp",
1129 "i2s_d0_mfp",
1130 "i2s0_pcm0_mfp",
1131 "i2s1_pcm0_mfp",
1132 "i2s_d1_mfp",
1133 "ks_in2_mfp",
1134 "ks_in1_mfp",
1135 "ks_in0_mfp",
1136 "ks_in3_mfp",
1137 "ks_out0_mfp",
1138 "ks_out1_mfp",
1139 "ks_out2_mfp",
1140 "lcd0_d2_mfp",
1141 "lvds_ee_pn_mfp",
1142 "uart2_rx_tx_mfp",
1143 "spi0_i2c_pcm_mfp",
1144 "lvds_e_pn_mfp",
1145 "sd0_d0_mfp",
1146 "sd0_d1_mfp",
1147 "sd0_d2_d3_mfp",
1148 "sd1_d0_d3_mfp",
1149 "sd0_cmd_mfp",
1150 "sd1_cmd_mfp",
1151 "sens0_ckout_mfp",
1152 "sen0_pclk_mfp",
1153 };
1154
1155 static const char * const eth_rmii_groups[] = {
1156 "rgmii_txd23_mfp",
1157 "rgmii_rxd2_mfp",
1158 "rgmii_rxd3_mfp",
1159 "rgmii_txd01_mfp",
1160 "rgmii_txd0_mfp",
1161 "rgmii_txd1_mfp",
1162 "rgmii_txen_mfp",
1163 "rgmii_rxen_mfp",
1164 "rgmii_rxd1_mfp",
1165 "rgmii_rxd0_mfp",
1166 "rgmii_ref_clk_mfp",
1167 "eth_smi_dummy",
1168 };
1169
1170 static const char * const eth_smii_groups[] = {
1171 "rgmii_txd0_mfp",
1172 "rgmii_txd1_mfp",
1173 "rgmii_rxd0_mfp",
1174 "rgmii_rxd1_mfp",
1175 "rgmii_ref_clk_mfp",
1176 "eth_smi_dummy",
1177 };
1178
1179 static const char * const spi0_groups[] = {
1180 "dsi_dn0_mfp",
1181 "dsi_dp2_mfp",
1182 "dsi_dp0_mfp",
1183 "uart2_rx_tx_mfp",
1184 "spi0_i2c_pcm_mfp",
1185 "dsi_dn2_mfp",
1186 };
1187
1188 static const char * const spi1_groups[] = {
1189 "uart0_rx_mfp",
1190 "uart0_tx_mfp",
1191 "i2c0_mfp",
1192 };
1193
1194 static const char * const spi2_groups[] = {
1195 "rgmii_txd01_mfp",
1196 "rgmii_txd0_mfp",
1197 "rgmii_txd1_mfp",
1198 "rgmii_ref_clk_mfp",
1199 "dnand_acle_ce0_mfp",
1200 };
1201
1202 static const char * const spi3_groups[] = {
1203 "rgmii_txen_mfp",
1204 "rgmii_rxen_mfp",
1205 "rgmii_rxd1_mfp",
1206 "rgmii_rxd0_mfp",
1207 };
1208
1209 static const char * const sens0_groups[] = {
1210 "csi_cn_cp_mfp",
1211 "sens0_ckout_mfp",
1212 "csi_dn_dp_mfp",
1213 "sen0_pclk_mfp",
1214 };
1215
1216 static const char * const sens1_groups[] = {
1217 "lcd0_d18_mfp",
1218 "ks_in2_mfp",
1219 "ks_in1_mfp",
1220 "ks_in0_mfp",
1221 "ks_in3_mfp",
1222 "ks_out0_mfp",
1223 "ks_out1_mfp",
1224 "ks_out2_mfp",
1225 "sens0_ckout_mfp",
1226 "pcm1_in_mfp",
1227 "pcm1_clk_mfp",
1228 "pcm1_sync_mfp",
1229 "pcm1_out_mfp",
1230 };
1231
1232 static const char * const uart0_groups[] = {
1233 "uart2_rtsb_mfp",
1234 "uart2_ctsb_mfp",
1235 "uart0_rx_mfp",
1236 "uart0_tx_mfp",
1237 };
1238
1239 static const char * const uart1_groups[] = {
1240 "sd0_d2_d3_mfp",
1241 "i2c0_mfp",
1242 };
1243
1244 static const char * const uart2_groups[] = {
1245 "rgmii_txen_mfp",
1246 "rgmii_rxen_mfp",
1247 "rgmii_rxd1_mfp",
1248 "rgmii_rxd0_mfp",
1249 "dsi_dn0_mfp",
1250 "dsi_dp2_mfp",
1251 "dsi_dp0_mfp",
1252 "uart2_rx_tx_mfp",
1253 "dsi_dn2_mfp",
1254 "uart2_rtsb_mfp",
1255 "uart2_ctsb_mfp",
1256 "sd0_d0_mfp",
1257 "sd0_d1_mfp",
1258 "sd0_d2_d3_mfp",
1259 "uart0_rx_mfp",
1260 "uart0_tx_mfp",
1261 "i2c0_mfp",
1262 "uart2_dummy"
1263 };
1264
1265 static const char * const uart3_groups[] = {
1266 "rgmii_txd23_mfp",
1267 "rgmii_rxd2_mfp",
1268 "rgmii_rxd3_mfp",
1269 "uart3_rtsb_mfp",
1270 "uart3_ctsb_mfp",
1271 "uart3_dummy"
1272 };
1273
1274 static const char * const uart4_groups[] = {
1275 "rgmii_txd01_mfp",
1276 "rgmii_ref_clk_mfp",
1277 "ks_out0_mfp",
1278 "ks_out1_mfp",
1279 };
1280
1281 static const char * const uart5_groups[] = {
1282 "rgmii_rxd1_mfp",
1283 "rgmii_rxd0_mfp",
1284 "ks_out0_mfp",
1285 "ks_out2_mfp",
1286 "uart3_rtsb_mfp",
1287 "uart3_ctsb_mfp",
1288 "sd0_d0_mfp",
1289 "sd0_d1_mfp",
1290 };
1291
1292 static const char * const uart6_groups[] = {
1293 "rgmii_txd0_mfp",
1294 "rgmii_txd1_mfp",
1295 };
1296
1297 static const char * const i2s0_groups[] = {
1298 "i2s_d0_mfp",
1299 "i2s_pcm1_mfp",
1300 "i2s0_pcm0_mfp",
1301 };
1302
1303 static const char * const i2s1_groups[] = {
1304 "i2s1_pcm0_mfp",
1305 "i2s_d1_mfp",
1306 "i2s1_dummy",
1307 "spi0_i2c_pcm_mfp",
1308 "uart0_rx_mfp",
1309 "uart0_tx_mfp",
1310 };
1311
1312 static const char * const pcm1_groups[] = {
1313 "i2s_pcm1_mfp",
1314 "spi0_i2c_pcm_mfp",
1315 "uart0_rx_mfp",
1316 "uart0_tx_mfp",
1317 "pcm1_in_mfp",
1318 "pcm1_clk_mfp",
1319 "pcm1_sync_mfp",
1320 "pcm1_out_mfp",
1321 };
1322
1323 static const char * const pcm0_groups[] = {
1324 "i2s0_pcm0_mfp",
1325 "i2s1_pcm0_mfp",
1326 "uart2_rx_tx_mfp",
1327 "spi0_i2c_pcm_mfp",
1328 };
1329
1330 static const char * const ks_groups[] = {
1331 "ks_in2_mfp",
1332 "ks_in1_mfp",
1333 "ks_in0_mfp",
1334 "ks_in3_mfp",
1335 "ks_out0_mfp",
1336 "ks_out1_mfp",
1337 "ks_out2_mfp",
1338 };
1339
1340 static const char * const jtag_groups[] = {
1341 "ks_in2_mfp",
1342 "ks_in1_mfp",
1343 "ks_in0_mfp",
1344 "ks_in3_mfp",
1345 "ks_out1_mfp",
1346 "sd0_d0_mfp",
1347 "sd0_d2_d3_mfp",
1348 "sd0_cmd_mfp",
1349 "sd0_clk_mfp",
1350 };
1351
1352 static const char * const pwm0_groups[] = {
1353 "rgmii_rxd2_mfp",
1354 "rgmii_txen_mfp",
1355 "ks_in2_mfp",
1356 "sen0_pclk_mfp",
1357 };
1358
1359 static const char * const pwm1_groups[] = {
1360 "rgmii_rxen_mfp",
1361 "ks_in1_mfp",
1362 "ks_in3_mfp",
1363 "sens0_ckout_mfp",
1364 };
1365
1366 static const char * const pwm2_groups[] = {
1367 "lcd0_d18_mfp",
1368 "rgmii_rxd3_mfp",
1369 "rgmii_rxd1_mfp",
1370 "ks_out0_mfp",
1371 "ks_out2_mfp",
1372 };
1373
1374 static const char * const pwm3_groups[] = {
1375 "rgmii_rxd0_mfp",
1376 "ks_out1_mfp",
1377 "lcd0_d2_mfp",
1378 };
1379
1380 static const char * const pwm4_groups[] = {
1381 "lcd0_d18_mfp",
1382 "rgmii_txd01_mfp",
1383 "rgmii_txd0_mfp",
1384 "ks_in0_mfp",
1385 "pcm1_in_mfp",
1386 "nand_ceb3_mfp",
1387 };
1388
1389 static const char * const pwm5_groups[] = {
1390 "rgmii_txd1_mfp",
1391 "ks_in1_mfp",
1392 "pcm1_clk_mfp",
1393 "nand_ceb2_mfp",
1394 };
1395
1396 static const char * const p0_groups[] = {
1397 "ks_in2_mfp",
1398 "ks_in0_mfp",
1399 };
1400
1401 static const char * const sd0_groups[] = {
1402 "ks_out0_mfp",
1403 "ks_out1_mfp",
1404 "ks_out2_mfp",
1405 "lcd0_d2_mfp",
1406 "dsi_dp3_mfp",
1407 "dsi_dp0_mfp",
1408 "sd0_d0_mfp",
1409 "sd0_d1_mfp",
1410 "sd0_d2_d3_mfp",
1411 "sd1_d0_d3_mfp",
1412 "sd0_cmd_mfp",
1413 "sd0_clk_mfp",
1414 };
1415
1416 static const char * const sd1_groups[] = {
1417 "dsi_dp2_mfp",
1418 "mfp1_16_14_mfp",
1419 "lcd0_d2_mfp",
1420 "mfp1_16_14_d17_mfp",
1421 "dsi_dp3_mfp",
1422 "dsi_dn3_mfp",
1423 "dsi_dnp1_cp_d2_mfp",
1424 "dsi_dnp1_cp_d17_mfp",
1425 "dsi_dn2_mfp",
1426 "sd1_d0_d3_mfp",
1427 "sd1_cmd_mfp",
1428 "sd1_dummy",
1429 };
1430
1431 static const char * const sd2_groups[] = {
1432 "dnand_data_wr_mfp",
1433 };
1434
1435 static const char * const i2c0_groups[] = {
1436 "uart0_rx_mfp",
1437 "uart0_tx_mfp",
1438 "i2c0_mfp",
1439 };
1440
1441 static const char * const i2c1_groups[] = {
1442 "i2c0_mfp",
1443 "i2c1_dummy"
1444 };
1445
1446 static const char * const i2c2_groups[] = {
1447 "i2c2_dummy"
1448 };
1449
1450 static const char * const i2c3_groups[] = {
1451 "uart2_rx_tx_mfp",
1452 "pcm1_sync_mfp",
1453 "pcm1_out_mfp",
1454 };
1455
1456 static const char * const lvds_groups[] = {
1457 "lvds_o_pn_mfp",
1458 "lvds_ee_pn_mfp",
1459 "lvds_e_pn_mfp",
1460 };
1461
1462 static const char * const bt_groups[] = {
1463 "i2s_pcm1_mfp",
1464 "i2s0_pcm0_mfp",
1465 "i2s1_pcm0_mfp",
1466 "ks_in2_mfp",
1467 "ks_in1_mfp",
1468 "ks_in0_mfp",
1469 "ks_in3_mfp",
1470 "ks_out0_mfp",
1471 "ks_out1_mfp",
1472 "ks_out2_mfp",
1473 "lvds_o_pn_mfp",
1474 "lvds_ee_pn_mfp",
1475 "pcm1_in_mfp",
1476 "pcm1_clk_mfp",
1477 "pcm1_sync_mfp",
1478 "pcm1_out_mfp",
1479 };
1480
1481 static const char * const lcd0_groups[] = {
1482 "lcd0_d18_mfp",
1483 "lcd0_d2_mfp",
1484 "mfp1_16_14_d17_mfp",
1485 "lvds_o_pn_mfp",
1486 "dsi_dp3_mfp",
1487 "dsi_dn3_mfp",
1488 "lvds_ee_pn_mfp",
1489 "dsi_dnp1_cp_d2_mfp",
1490 "dsi_dnp1_cp_d17_mfp",
1491 "lvds_e_pn_mfp",
1492 };
1493
1494
1495 static const char * const usb30_groups[] = {
1496 "ks_in1_mfp",
1497 };
1498
1499 static const char * const clko_25m_groups[] = {
1500 "clko_25m_mfp",
1501 };
1502
1503 static const char * const mipi_csi_groups[] = {
1504 "csi_cn_cp_mfp",
1505 "csi_dn_dp_mfp",
1506 };
1507
1508 static const char * const dsi_groups[] = {
1509 "dsi_dn0_mfp",
1510 "dsi_dp2_mfp",
1511 "dsi_dp3_mfp",
1512 "dsi_dn3_mfp",
1513 "dsi_dp0_mfp",
1514 "dsi_dnp1_cp_d2_mfp",
1515 "dsi_dnp1_cp_d17_mfp",
1516 "dsi_dn2_mfp",
1517 "dsi_dummy",
1518 };
1519
1520 static const char * const nand_groups[] = {
1521 "dnand_data_wr_mfp",
1522 "dnand_acle_ce0_mfp",
1523 "nand_ceb2_mfp",
1524 "nand_ceb3_mfp",
1525 "nand_dummy",
1526 };
1527
1528 static const char * const spdif_groups[] = {
1529 "uart0_tx_mfp",
1530 };
1531
1532 static const char * const sirq0_groups[] = {
1533 "sirq0_dummy",
1534 };
1535
1536 static const char * const sirq1_groups[] = {
1537 "sirq1_dummy",
1538 };
1539
1540 static const char * const sirq2_groups[] = {
1541 "sirq2_dummy",
1542 };
1543
1544 static const struct owl_pinmux_func s700_functions[] = {
1545 [S700_MUX_NOR] = FUNCTION(nor),
1546 [S700_MUX_ETH_RGMII] = FUNCTION(eth_rmii),
1547 [S700_MUX_ETH_SGMII] = FUNCTION(eth_smii),
1548 [S700_MUX_SPI0] = FUNCTION(spi0),
1549 [S700_MUX_SPI1] = FUNCTION(spi1),
1550 [S700_MUX_SPI2] = FUNCTION(spi2),
1551 [S700_MUX_SPI3] = FUNCTION(spi3),
1552 [S700_MUX_SENS0] = FUNCTION(sens0),
1553 [S700_MUX_SENS1] = FUNCTION(sens1),
1554 [S700_MUX_UART0] = FUNCTION(uart0),
1555 [S700_MUX_UART1] = FUNCTION(uart1),
1556 [S700_MUX_UART2] = FUNCTION(uart2),
1557 [S700_MUX_UART3] = FUNCTION(uart3),
1558 [S700_MUX_UART4] = FUNCTION(uart4),
1559 [S700_MUX_UART5] = FUNCTION(uart5),
1560 [S700_MUX_UART6] = FUNCTION(uart6),
1561 [S700_MUX_I2S0] = FUNCTION(i2s0),
1562 [S700_MUX_I2S1] = FUNCTION(i2s1),
1563 [S700_MUX_PCM1] = FUNCTION(pcm1),
1564 [S700_MUX_PCM0] = FUNCTION(pcm0),
1565 [S700_MUX_KS] = FUNCTION(ks),
1566 [S700_MUX_JTAG] = FUNCTION(jtag),
1567 [S700_MUX_PWM0] = FUNCTION(pwm0),
1568 [S700_MUX_PWM1] = FUNCTION(pwm1),
1569 [S700_MUX_PWM2] = FUNCTION(pwm2),
1570 [S700_MUX_PWM3] = FUNCTION(pwm3),
1571 [S700_MUX_PWM4] = FUNCTION(pwm4),
1572 [S700_MUX_PWM5] = FUNCTION(pwm5),
1573 [S700_MUX_P0] = FUNCTION(p0),
1574 [S700_MUX_SD0] = FUNCTION(sd0),
1575 [S700_MUX_SD1] = FUNCTION(sd1),
1576 [S700_MUX_SD2] = FUNCTION(sd2),
1577 [S700_MUX_I2C0] = FUNCTION(i2c0),
1578 [S700_MUX_I2C1] = FUNCTION(i2c1),
1579 [S700_MUX_I2C2] = FUNCTION(i2c2),
1580 [S700_MUX_I2C3] = FUNCTION(i2c3),
1581 [S700_MUX_DSI] = FUNCTION(dsi),
1582 [S700_MUX_LVDS] = FUNCTION(lvds),
1583 [S700_MUX_USB30] = FUNCTION(usb30),
1584 [S700_MUX_CLKO_25M] = FUNCTION(clko_25m),
1585 [S700_MUX_MIPI_CSI] = FUNCTION(mipi_csi),
1586 [S700_MUX_NAND] = FUNCTION(nand),
1587 [S700_MUX_SPDIF] = FUNCTION(spdif),
1588 [S700_MUX_SIRQ0] = FUNCTION(sirq0),
1589 [S700_MUX_SIRQ1] = FUNCTION(sirq1),
1590 [S700_MUX_SIRQ2] = FUNCTION(sirq2),
1591 [S700_MUX_BT] = FUNCTION(bt),
1592 [S700_MUX_LCD0] = FUNCTION(lcd0),
1593 };
1594
1595 /* PAD_ST0 */
1596 static PAD_ST_CONF(UART2_TX, 0, 31, 1);
1597 static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);
1598 static PAD_ST_CONF(UART0_RX, 0, 29, 1);
1599 static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);
1600 static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);
1601 static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);
1602 static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);
1603 static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);
1604 static PAD_ST_CONF(DSI_DP0, 0, 16, 1);
1605 static PAD_ST_CONF(DSI_DN0, 0, 15, 1);
1606 static PAD_ST_CONF(UART0_TX, 0, 14, 1);
1607 static PAD_ST_CONF(SD0_CLK, 0, 12, 1);
1608 static PAD_ST_CONF(KS_IN0, 0, 11, 1);
1609 static PAD_ST_CONF(SENSOR0_PCLK, 0, 9, 1);
1610 static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);
1611 static PAD_ST_CONF(KS_OUT0, 0, 6, 1);
1612 static PAD_ST_CONF(KS_OUT1, 0, 5, 1);
1613 static PAD_ST_CONF(KS_OUT2, 0, 4, 1);
1614 static PAD_ST_CONF(ETH_TXD3, 0, 3, 1);
1615 static PAD_ST_CONF(ETH_TXD2, 0, 2, 1);
1616
1617 /* PAD_ST1 */
1618 static PAD_ST_CONF(DSI_DP2, 1, 31, 1);
1619 static PAD_ST_CONF(DSI_DN2, 1, 30, 1);
1620 static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);
1621 static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);
1622 static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);
1623 static PAD_ST_CONF(UART3_RX, 1, 25, 1);
1624 static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);
1625 static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);
1626 static PAD_ST_CONF(UART2_RX, 1, 22, 1);
1627 static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);
1628 static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
1629 static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);
1630 static PAD_ST_CONF(ETH_RXER, 1, 18, 1);
1631 static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
1632 static PAD_ST_CONF(LVDS_OAP, 1, 12, 1);
1633 static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);
1634 static PAD_ST_CONF(PCM1_IN, 1, 10, 1);
1635 static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);
1636 static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);
1637 static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);
1638 static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);
1639 static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);
1640
1641 static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);
1642 static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
1643 static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
1644 static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
1645
1646 /* PAD_PULLCTL0 */
1647 static PAD_PULLCTL_CONF(PCM1_SYNC, 0, 30, 1);
1648 static PAD_PULLCTL_CONF(PCM1_OUT, 0, 29, 1);
1649 static PAD_PULLCTL_CONF(KS_OUT2, 0, 28, 1);
1650 static PAD_PULLCTL_CONF(LCD0_D2, 0, 27, 1);
1651 static PAD_PULLCTL_CONF(DSI_DN3, 0, 26, 1);
1652 static PAD_PULLCTL_CONF(ETH_RXER, 0, 16, 1);
1653 static PAD_PULLCTL_CONF(SIRQ0, 0, 14, 2);
1654 static PAD_PULLCTL_CONF(SIRQ1, 0, 12, 2);
1655 static PAD_PULLCTL_CONF(SIRQ2, 0, 10, 2);
1656 static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 9, 1);
1657 static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 1);
1658 static PAD_PULLCTL_CONF(KS_IN0, 0, 7, 1);
1659 static PAD_PULLCTL_CONF(KS_IN1, 0, 6, 1);
1660 static PAD_PULLCTL_CONF(KS_IN2, 0, 5, 1);
1661 static PAD_PULLCTL_CONF(KS_IN3, 0, 4, 1);
1662 static PAD_PULLCTL_CONF(KS_OUT0, 0, 2, 1);
1663 static PAD_PULLCTL_CONF(KS_OUT1, 0, 1, 1);
1664 static PAD_PULLCTL_CONF(DSI_DP1, 0, 0, 1);
1665
1666 /* PAD_PULLCTL1 */
1667 static PAD_PULLCTL_CONF(SD0_D0, 1, 17, 1);
1668 static PAD_PULLCTL_CONF(SD0_D1, 1, 16, 1);
1669 static PAD_PULLCTL_CONF(SD0_D2, 1, 15, 1);
1670 static PAD_PULLCTL_CONF(SD0_D3, 1, 14, 1);
1671 static PAD_PULLCTL_CONF(SD0_CMD, 1, 13, 1);
1672 static PAD_PULLCTL_CONF(SD0_CLK, 1, 12, 1);
1673 static PAD_PULLCTL_CONF(UART0_RX, 1, 2, 1);
1674 static PAD_PULLCTL_CONF(UART0_TX, 1, 1, 1);
1675 static PAD_PULLCTL_CONF(CLKO_25M, 1, 0, 1);
1676
1677 /* PAD_PULLCTL2 */
1678 static PAD_PULLCTL_CONF(ETH_TXD2, 2, 18, 1);
1679 static PAD_PULLCTL_CONF(ETH_TXD3, 2, 17, 1);
1680 static PAD_PULLCTL_CONF(SPI0_SS, 2, 16, 1);
1681 static PAD_PULLCTL_CONF(SPI0_MISO, 2, 15, 1);
1682 static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 10, 1);
1683 static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 9, 1);
1684 static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1);
1685 static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1);
1686
1687 /* Pad info table for the pinmux subsystem */
1688 static const struct owl_padinfo s700_padinfo[NUM_PADS] = {
1689 [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
1690 [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
1691 [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
1692 [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),
1693 [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),
1694 [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
1695 [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),
1696 [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),
1697 [ETH_MDC] = PAD_INFO(ETH_MDC),
1698 [ETH_MDIO] = PAD_INFO(ETH_MDIO),
1699 [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),
1700 [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),
1701 [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),
1702 [I2S_D0] = PAD_INFO(I2S_D0),
1703 [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),
1704 [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),
1705 [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),
1706 [I2S_D1] = PAD_INFO(I2S_D1),
1707 [I2S_BCLK1] = PAD_INFO(I2S_BCLK1),
1708 [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),
1709 [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),
1710 [KS_IN0] = PAD_INFO_PULLCTL_ST(KS_IN0),
1711 [KS_IN1] = PAD_INFO_PULLCTL(KS_IN1),
1712 [KS_IN2] = PAD_INFO_PULLCTL(KS_IN2),
1713 [KS_IN3] = PAD_INFO_PULLCTL(KS_IN3),
1714 [KS_OUT0] = PAD_INFO_PULLCTL_ST(KS_OUT0),
1715 [KS_OUT1] = PAD_INFO_PULLCTL_ST(KS_OUT1),
1716 [KS_OUT2] = PAD_INFO_PULLCTL_ST(KS_OUT2),
1717 [LVDS_OEP] = PAD_INFO(LVDS_OEP),
1718 [LVDS_OEN] = PAD_INFO(LVDS_OEN),
1719 [LVDS_ODP] = PAD_INFO(LVDS_ODP),
1720 [LVDS_ODN] = PAD_INFO(LVDS_ODN),
1721 [LVDS_OCP] = PAD_INFO(LVDS_OCP),
1722 [LVDS_OCN] = PAD_INFO(LVDS_OCN),
1723 [LVDS_OBP] = PAD_INFO(LVDS_OBP),
1724 [LVDS_OBN] = PAD_INFO(LVDS_OBN),
1725 [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),
1726 [LVDS_OAN] = PAD_INFO(LVDS_OAN),
1727 [LVDS_EEP] = PAD_INFO(LVDS_EEP),
1728 [LVDS_EEN] = PAD_INFO(LVDS_EEN),
1729 [LVDS_EDP] = PAD_INFO(LVDS_EDP),
1730 [LVDS_EDN] = PAD_INFO(LVDS_EDN),
1731 [LVDS_ECP] = PAD_INFO(LVDS_ECP),
1732 [LVDS_ECN] = PAD_INFO(LVDS_ECN),
1733 [LVDS_EBP] = PAD_INFO(LVDS_EBP),
1734 [LVDS_EBN] = PAD_INFO(LVDS_EBN),
1735 [LVDS_EAP] = PAD_INFO(LVDS_EAP),
1736 [LVDS_EAN] = PAD_INFO(LVDS_EAN),
1737 [LCD0_D18] = PAD_INFO(LCD0_D18),
1738 [LCD0_D2] = PAD_INFO_PULLCTL(LCD0_D2),
1739 [DSI_DP3] = PAD_INFO(DSI_DP3),
1740 [DSI_DN3] = PAD_INFO_PULLCTL(DSI_DN3),
1741 [DSI_DP1] = PAD_INFO_PULLCTL(DSI_DP1),
1742 [DSI_DN1] = PAD_INFO(DSI_DN1),
1743 [DSI_DP0] = PAD_INFO_ST(DSI_DP0),
1744 [DSI_DN0] = PAD_INFO_ST(DSI_DN0),
1745 [DSI_DP2] = PAD_INFO_ST(DSI_DP2),
1746 [DSI_DN2] = PAD_INFO_ST(DSI_DN2),
1747 [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),
1748 [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),
1749 [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),
1750 [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),
1751 [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),
1752 [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),
1753 [SD1_CLK] = PAD_INFO(SD1_CLK),
1754 [SPI0_SS] = PAD_INFO_PULLCTL_ST(SPI0_SS),
1755 [SPI0_MISO] = PAD_INFO_PULLCTL_ST(SPI0_MISO),
1756 [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),
1757 [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),
1758 [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),
1759 [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),
1760 [SENSOR0_PCLK] = PAD_INFO_ST(SENSOR0_PCLK),
1761 [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),
1762 [DNAND_ALE] = PAD_INFO(DNAND_ALE),
1763 [DNAND_CLE] = PAD_INFO(DNAND_CLE),
1764 [DNAND_CEB0] = PAD_INFO(DNAND_CEB0),
1765 [DNAND_CEB1] = PAD_INFO(DNAND_CEB1),
1766 [DNAND_CEB2] = PAD_INFO(DNAND_CEB2),
1767 [DNAND_CEB3] = PAD_INFO(DNAND_CEB3),
1768 [UART2_RX] = PAD_INFO_ST(UART2_RX),
1769 [UART2_TX] = PAD_INFO_ST(UART2_TX),
1770 [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),
1771 [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),
1772 [UART3_RX] = PAD_INFO_ST(UART3_RX),
1773 [UART3_TX] = PAD_INFO(UART3_TX),
1774 [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),
1775 [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),
1776 [PCM1_IN] = PAD_INFO_ST(PCM1_IN),
1777 [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),
1778 [PCM1_SYNC] = PAD_INFO_PULLCTL_ST(PCM1_SYNC),
1779 [PCM1_OUT] = PAD_INFO_PULLCTL(PCM1_OUT),
1780 [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),
1781 [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),
1782 [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),
1783 [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),
1784 [CSI_DN0] = PAD_INFO(CSI_DN0),
1785 [CSI_DP0] = PAD_INFO(CSI_DP0),
1786 [CSI_DN1] = PAD_INFO(CSI_DN1),
1787 [CSI_DP1] = PAD_INFO(CSI_DP1),
1788 [CSI_CN] = PAD_INFO(CSI_CN),
1789 [CSI_CP] = PAD_INFO(CSI_CP),
1790 [CSI_DN2] = PAD_INFO(CSI_DN2),
1791 [CSI_DP2] = PAD_INFO(CSI_DP2),
1792 [CSI_DN3] = PAD_INFO(CSI_DN3),
1793 [CSI_DP3] = PAD_INFO(CSI_DP3),
1794 [DNAND_WRB] = PAD_INFO(DNAND_WRB),
1795 [DNAND_RDB] = PAD_INFO(DNAND_RDB),
1796 [DNAND_RB0] = PAD_INFO(DNAND_RB0),
1797 [PORB] = PAD_INFO(PORB),
1798 [CLKO_25M] = PAD_INFO_PULLCTL(CLKO_25M),
1799 [BSEL] = PAD_INFO(BSEL),
1800 [PKG0] = PAD_INFO(PKG0),
1801 [PKG1] = PAD_INFO(PKG1),
1802 [PKG2] = PAD_INFO(PKG2),
1803 [PKG3] = PAD_INFO(PKG3),
1804 [ETH_TXD2] = PAD_INFO_PULLCTL_ST(ETH_TXD2),
1805 [ETH_TXD3] = PAD_INFO_PULLCTL_ST(ETH_TXD3),
1806 };
1807
1808 static const struct owl_gpio_port s700_gpio_ports[] = {
1809 OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x230, 0),
1810 OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x204, 0x210, 0x214, 0x238, 1),
1811 OWL_GPIO_PORT(C, 0x0018, 32, 0x0, 0x4, 0x8, 0x204, 0x218, 0x21C, 0x240, 2),
1812 OWL_GPIO_PORT(D, 0x0024, 32, 0x0, 0x4, 0x8, 0x204, 0x220, 0x224, 0x248, 3),
1813 /* 0x24C (INTC_GPIOD_TYPE1) used to tweak the driver to handle generic */
1814 OWL_GPIO_PORT(E, 0x0030, 8, 0x0, 0x4, 0x8, 0x204, 0x228, 0x22C, 0x24C, 4),
1815 };
1816
1817 enum s700_pinconf_pull {
1818 OWL_PINCONF_PULL_DOWN,
1819 OWL_PINCONF_PULL_UP,
1820 };
1821
1822 static int s700_pad_pinconf_arg2val(const struct owl_padinfo *info,
1823 unsigned int param,
1824 u32 *arg)
1825 {
1826 switch (param) {
1827 case PIN_CONFIG_BIAS_PULL_DOWN:
1828 *arg = OWL_PINCONF_PULL_DOWN;
1829 break;
1830 case PIN_CONFIG_BIAS_PULL_UP:
1831 *arg = OWL_PINCONF_PULL_UP;
1832 break;
1833 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1834 *arg = (*arg >= 1 ? 1 : 0);
1835 break;
1836 default:
1837 return -ENOTSUPP;
1838 }
1839
1840 return 0;
1841 }
1842
1843 static int s700_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
1844 unsigned int param,
1845 u32 *arg)
1846 {
1847 switch (param) {
1848 case PIN_CONFIG_BIAS_PULL_DOWN:
1849 *arg = *arg == OWL_PINCONF_PULL_DOWN;
1850 break;
1851 case PIN_CONFIG_BIAS_PULL_UP:
1852 *arg = *arg == OWL_PINCONF_PULL_UP;
1853 break;
1854 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1855 *arg = *arg == 1;
1856 break;
1857 default:
1858 return -ENOTSUPP;
1859 }
1860
1861 return 0;
1862 }
1863
1864 static struct owl_pinctrl_soc_data s700_pinctrl_data = {
1865 .padinfo = s700_padinfo,
1866 .pins = (const struct pinctrl_pin_desc *)s700_pads,
1867 .npins = ARRAY_SIZE(s700_pads),
1868 .functions = s700_functions,
1869 .nfunctions = ARRAY_SIZE(s700_functions),
1870 .groups = s700_groups,
1871 .ngroups = ARRAY_SIZE(s700_groups),
1872 .ngpios = NUM_GPIOS,
1873 .ports = s700_gpio_ports,
1874 .nports = ARRAY_SIZE(s700_gpio_ports),
1875 .padctl_arg2val = s700_pad_pinconf_arg2val,
1876 .padctl_val2arg = s700_pad_pinconf_val2arg,
1877 };
1878
1879 static int s700_pinctrl_probe(struct platform_device *pdev)
1880 {
1881 return owl_pinctrl_probe(pdev, &s700_pinctrl_data);
1882 }
1883
1884 static const struct of_device_id s700_pinctrl_of_match[] = {
1885 { .compatible = "actions,s700-pinctrl", },
1886 {}
1887 };
1888
1889 static struct platform_driver s700_pinctrl_driver = {
1890 .probe = s700_pinctrl_probe,
1891 .driver = {
1892 .name = "pinctrl-s700",
1893 .of_match_table = of_match_ptr(s700_pinctrl_of_match),
1894 },
1895 };
1896
1897 static int __init s700_pinctrl_init(void)
1898 {
1899 return platform_driver_register(&s700_pinctrl_driver);
1900 }
1901 arch_initcall(s700_pinctrl_init);
1902
1903 static void __exit s700_pinctrl_exit(void)
1904 {
1905 platform_driver_unregister(&s700_pinctrl_driver);
1906 }
1907 module_exit(s700_pinctrl_exit);
1908
1909 MODULE_AUTHOR("Actions Semi Inc.");
1910 MODULE_DESCRIPTION("Actions Semi S700 Soc Pinctrl Driver");
1911 MODULE_LICENSE("GPL");
Linux with added FPC-III support