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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / pinctrl / intel / pinctrl-baytrail.c
blob394a421a19d588893d84223207df734ae53aca7a
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pinctrl GPIO driver for Intel Baytrail
4 *
5 * Copyright (c) 2012-2013, Intel Corporation
6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitops.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/property.h>
20 #include <linux/seq_file.h>
21
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26
27 #include "pinctrl-intel.h"
28
29 /* memory mapped register offsets */
30 #define BYT_CONF0_REG 0x000
31 #define BYT_CONF1_REG 0x004
32 #define BYT_VAL_REG 0x008
33 #define BYT_DFT_REG 0x00c
34 #define BYT_INT_STAT_REG 0x800
35 #define BYT_DEBOUNCE_REG 0x9d0
36
37 /* BYT_CONF0_REG register bits */
38 #define BYT_IODEN BIT(31)
39 #define BYT_DIRECT_IRQ_EN BIT(27)
40 #define BYT_TRIG_MASK GENMASK(26, 24)
41 #define BYT_TRIG_NEG BIT(26)
42 #define BYT_TRIG_POS BIT(25)
43 #define BYT_TRIG_LVL BIT(24)
44 #define BYT_DEBOUNCE_EN BIT(20)
45 #define BYT_GLITCH_FILTER_EN BIT(19)
46 #define BYT_GLITCH_F_SLOW_CLK BIT(17)
47 #define BYT_GLITCH_F_FAST_CLK BIT(16)
48 #define BYT_PULL_STR_SHIFT 9
49 #define BYT_PULL_STR_MASK GENMASK(10, 9)
50 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
51 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
52 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
53 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
54 #define BYT_PULL_ASSIGN_SHIFT 7
55 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)
56 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
57 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
58 #define BYT_PIN_MUX GENMASK(2, 0)
59
60 /* BYT_VAL_REG register bits */
61 #define BYT_DIR_MASK GENMASK(2, 1)
62 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
63 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
64 #define BYT_LEVEL BIT(0)
65
66 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
67 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
68
69 /* BYT_DEBOUNCE_REG bits */
70 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0)
71 #define BYT_DEBOUNCE_PULSE_375US 1
72 #define BYT_DEBOUNCE_PULSE_750US 2
73 #define BYT_DEBOUNCE_PULSE_1500US 3
74 #define BYT_DEBOUNCE_PULSE_3MS 4
75 #define BYT_DEBOUNCE_PULSE_6MS 5
76 #define BYT_DEBOUNCE_PULSE_12MS 6
77 #define BYT_DEBOUNCE_PULSE_24MS 7
78
79 #define BYT_NGPIO_SCORE 102
80 #define BYT_NGPIO_NCORE 28
81 #define BYT_NGPIO_SUS 44
82
83 #define BYT_SCORE_ACPI_UID "1"
84 #define BYT_NCORE_ACPI_UID "2"
85 #define BYT_SUS_ACPI_UID "3"
86
87 /*
88 * This is the function value most pins have for GPIO muxing. If the value
89 * differs from the default one, it must be explicitly mentioned. Otherwise, the
90 * pin control implementation will set the muxing value to default GPIO if it
91 * does not find a match for the requested function.
92 */
93 #define BYT_DEFAULT_GPIO_MUX 0
94 #define BYT_ALTER_GPIO_MUX 1
95
96 struct intel_pad_context {
97 u32 conf0;
98 u32 val;
99 };
100
101 #define COMMUNITY(p, n, map) \
102 { \
103 .pin_base = (p), \
104 .npins = (n), \
105 .pad_map = (map),\
106 }
107
108 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
109 static const struct pinctrl_pin_desc byt_score_pins[] = {
110 PINCTRL_PIN(0, "SATA_GP0"),
111 PINCTRL_PIN(1, "SATA_GP1"),
112 PINCTRL_PIN(2, "SATA_LED#"),
113 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
114 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
115 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
116 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
117 PINCTRL_PIN(7, "SD3_WP"),
118 PINCTRL_PIN(8, "HDA_RST"),
119 PINCTRL_PIN(9, "HDA_SYNC"),
120 PINCTRL_PIN(10, "HDA_CLK"),
121 PINCTRL_PIN(11, "HDA_SDO"),
122 PINCTRL_PIN(12, "HDA_SDI0"),
123 PINCTRL_PIN(13, "HDA_SDI1"),
124 PINCTRL_PIN(14, "GPIO_S0_SC14"),
125 PINCTRL_PIN(15, "GPIO_S0_SC15"),
126 PINCTRL_PIN(16, "MMC1_CLK"),
127 PINCTRL_PIN(17, "MMC1_D0"),
128 PINCTRL_PIN(18, "MMC1_D1"),
129 PINCTRL_PIN(19, "MMC1_D2"),
130 PINCTRL_PIN(20, "MMC1_D3"),
131 PINCTRL_PIN(21, "MMC1_D4"),
132 PINCTRL_PIN(22, "MMC1_D5"),
133 PINCTRL_PIN(23, "MMC1_D6"),
134 PINCTRL_PIN(24, "MMC1_D7"),
135 PINCTRL_PIN(25, "MMC1_CMD"),
136 PINCTRL_PIN(26, "MMC1_RST"),
137 PINCTRL_PIN(27, "SD2_CLK"),
138 PINCTRL_PIN(28, "SD2_D0"),
139 PINCTRL_PIN(29, "SD2_D1"),
140 PINCTRL_PIN(30, "SD2_D2"),
141 PINCTRL_PIN(31, "SD2_D3_CD"),
142 PINCTRL_PIN(32, "SD2_CMD"),
143 PINCTRL_PIN(33, "SD3_CLK"),
144 PINCTRL_PIN(34, "SD3_D0"),
145 PINCTRL_PIN(35, "SD3_D1"),
146 PINCTRL_PIN(36, "SD3_D2"),
147 PINCTRL_PIN(37, "SD3_D3"),
148 PINCTRL_PIN(38, "SD3_CD"),
149 PINCTRL_PIN(39, "SD3_CMD"),
150 PINCTRL_PIN(40, "SD3_1P8EN"),
151 PINCTRL_PIN(41, "SD3_PWREN#"),
152 PINCTRL_PIN(42, "ILB_LPC_AD0"),
153 PINCTRL_PIN(43, "ILB_LPC_AD1"),
154 PINCTRL_PIN(44, "ILB_LPC_AD2"),
155 PINCTRL_PIN(45, "ILB_LPC_AD3"),
156 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
157 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
158 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
159 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
160 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
161 PINCTRL_PIN(51, "PCU_SMB_DATA"),
162 PINCTRL_PIN(52, "PCU_SMB_CLK"),
163 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
164 PINCTRL_PIN(54, "ILB_8254_SPKR"),
165 PINCTRL_PIN(55, "GPIO_S0_SC55"),
166 PINCTRL_PIN(56, "GPIO_S0_SC56"),
167 PINCTRL_PIN(57, "GPIO_S0_SC57"),
168 PINCTRL_PIN(58, "GPIO_S0_SC58"),
169 PINCTRL_PIN(59, "GPIO_S0_SC59"),
170 PINCTRL_PIN(60, "GPIO_S0_SC60"),
171 PINCTRL_PIN(61, "GPIO_S0_SC61"),
172 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
173 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
174 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
175 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
176 PINCTRL_PIN(66, "SIO_SPI_CS"),
177 PINCTRL_PIN(67, "SIO_SPI_MISO"),
178 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
179 PINCTRL_PIN(69, "SIO_SPI_CLK"),
180 PINCTRL_PIN(70, "SIO_UART1_RXD"),
181 PINCTRL_PIN(71, "SIO_UART1_TXD"),
182 PINCTRL_PIN(72, "SIO_UART1_RTS"),
183 PINCTRL_PIN(73, "SIO_UART1_CTS"),
184 PINCTRL_PIN(74, "SIO_UART2_RXD"),
185 PINCTRL_PIN(75, "SIO_UART2_TXD"),
186 PINCTRL_PIN(76, "SIO_UART2_RTS"),
187 PINCTRL_PIN(77, "SIO_UART2_CTS"),
188 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
189 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
190 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
191 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
192 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
193 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
194 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
195 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
196 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
197 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
198 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
199 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
200 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
201 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
202 PINCTRL_PIN(92, "GPIO_S0_SC92"),
203 PINCTRL_PIN(93, "GPIO_S0_SC93"),
204 PINCTRL_PIN(94, "SIO_PWM0"),
205 PINCTRL_PIN(95, "SIO_PWM1"),
206 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
207 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
208 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
209 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
210 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
211 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
212 };
213
214 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
215 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
216 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
217 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
218 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
219 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
220 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
221 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
222 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
223 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
224 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
225 97, 100,
226 };
227
228 /* SCORE groups */
229 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
230 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
231
232 static const unsigned int byt_score_pwm0_pins[] = { 94 };
233 static const unsigned int byt_score_pwm1_pins[] = { 95 };
234
235 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
236
237 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
238 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
239 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
240 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
241 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
242 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
243 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
244
245 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
246 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
247 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
248
249 static const unsigned int byt_score_sdcard_pins[] = {
250 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
251 };
252 static const unsigned int byt_score_sdcard_mux_values[] = {
253 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
254 };
255
256 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
257
258 static const unsigned int byt_score_emmc_pins[] = {
259 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
260 };
261
262 static const unsigned int byt_score_ilb_lpc_pins[] = {
263 42, 43, 44, 45, 46, 47, 48, 49, 50,
264 };
265
266 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
267
268 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
269 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
270 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
271 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
272 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
273 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
274
275 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
276
277 static const struct intel_pingroup byt_score_groups[] = {
278 PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
279 PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
280 PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
281 PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
282 PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
283 PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
284 PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
285 PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
286 PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
287 PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
288 PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
289 PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
290 PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
291 PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
292 PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
293 PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
294 PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
295 PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
296 PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
297 PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
298 PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
299 PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
300 PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
301 PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
302 PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
303 PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
304 PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
305 };
306
307 static const char * const byt_score_uart_groups[] = {
308 "uart1_grp", "uart2_grp",
309 };
310 static const char * const byt_score_pwm_groups[] = {
311 "pwm0_grp", "pwm1_grp",
312 };
313 static const char * const byt_score_ssp_groups[] = {
314 "ssp0_grp", "ssp1_grp", "ssp2_grp",
315 };
316 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
317 static const char * const byt_score_i2c_groups[] = {
318 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
319 "i2c6_grp",
320 };
321 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
322 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
323 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
324 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
325 static const char * const byt_score_sata_groups[] = { "sata_grp" };
326 static const char * const byt_score_plt_clk_groups[] = {
327 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
328 "plt_clk4_grp", "plt_clk5_grp",
329 };
330 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
331 static const char * const byt_score_gpio_groups[] = {
332 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
333 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
334 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
335 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
336 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
337 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
338 };
339
340 static const struct intel_function byt_score_functions[] = {
341 FUNCTION("uart", byt_score_uart_groups),
342 FUNCTION("pwm", byt_score_pwm_groups),
343 FUNCTION("ssp", byt_score_ssp_groups),
344 FUNCTION("spi", byt_score_spi_groups),
345 FUNCTION("i2c", byt_score_i2c_groups),
346 FUNCTION("sdcard", byt_score_sdcard_groups),
347 FUNCTION("sdio", byt_score_sdio_groups),
348 FUNCTION("emmc", byt_score_emmc_groups),
349 FUNCTION("lpc", byt_score_lpc_groups),
350 FUNCTION("sata", byt_score_sata_groups),
351 FUNCTION("plt_clk", byt_score_plt_clk_groups),
352 FUNCTION("smbus", byt_score_smbus_groups),
353 FUNCTION("gpio", byt_score_gpio_groups),
354 };
355
356 static const struct intel_community byt_score_communities[] = {
357 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
358 };
359
360 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
361 .uid = BYT_SCORE_ACPI_UID,
362 .pins = byt_score_pins,
363 .npins = ARRAY_SIZE(byt_score_pins),
364 .groups = byt_score_groups,
365 .ngroups = ARRAY_SIZE(byt_score_groups),
366 .functions = byt_score_functions,
367 .nfunctions = ARRAY_SIZE(byt_score_functions),
368 .communities = byt_score_communities,
369 .ncommunities = ARRAY_SIZE(byt_score_communities),
370 };
371
372 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */
373 static const struct pinctrl_pin_desc byt_sus_pins[] = {
374 PINCTRL_PIN(0, "GPIO_S50"),
375 PINCTRL_PIN(1, "GPIO_S51"),
376 PINCTRL_PIN(2, "GPIO_S52"),
377 PINCTRL_PIN(3, "GPIO_S53"),
378 PINCTRL_PIN(4, "GPIO_S54"),
379 PINCTRL_PIN(5, "GPIO_S55"),
380 PINCTRL_PIN(6, "GPIO_S56"),
381 PINCTRL_PIN(7, "GPIO_S57"),
382 PINCTRL_PIN(8, "GPIO_S58"),
383 PINCTRL_PIN(9, "GPIO_S59"),
384 PINCTRL_PIN(10, "GPIO_S510"),
385 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
386 PINCTRL_PIN(12, "PMC_SUSCLK0"),
387 PINCTRL_PIN(13, "GPIO_S513"),
388 PINCTRL_PIN(14, "USB_ULPI_RST"),
389 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
390 PINCTRL_PIN(16, "PMC_PWRBTN"),
391 PINCTRL_PIN(17, "GPIO_S517"),
392 PINCTRL_PIN(18, "PMC_SUS_STAT"),
393 PINCTRL_PIN(19, "USB_OC0"),
394 PINCTRL_PIN(20, "USB_OC1"),
395 PINCTRL_PIN(21, "PCU_SPI_CS1"),
396 PINCTRL_PIN(22, "GPIO_S522"),
397 PINCTRL_PIN(23, "GPIO_S523"),
398 PINCTRL_PIN(24, "GPIO_S524"),
399 PINCTRL_PIN(25, "GPIO_S525"),
400 PINCTRL_PIN(26, "GPIO_S526"),
401 PINCTRL_PIN(27, "GPIO_S527"),
402 PINCTRL_PIN(28, "GPIO_S528"),
403 PINCTRL_PIN(29, "GPIO_S529"),
404 PINCTRL_PIN(30, "GPIO_S530"),
405 PINCTRL_PIN(31, "USB_ULPI_CLK"),
406 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
407 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
408 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
409 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
410 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
411 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
412 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
413 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
414 PINCTRL_PIN(40, "USB_ULPI_DIR"),
415 PINCTRL_PIN(41, "USB_ULPI_NXT"),
416 PINCTRL_PIN(42, "USB_ULPI_STP"),
417 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
418 };
419
420 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
421 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
422 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
423 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
424 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
425 52, 53, 59, 40,
426 };
427
428 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
429 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
430 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
431
432 static const unsigned int byt_sus_usb_ulpi_pins[] = {
433 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
434 };
435 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
436 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
437 };
438 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
439 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
440 };
441
442 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
443 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
444 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
445
446 static const struct intel_pingroup byt_sus_groups[] = {
447 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
448 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
449 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
450 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
451 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
452 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
453 };
454
455 static const char * const byt_sus_usb_groups[] = {
456 "usb_oc_grp", "usb_ulpi_grp",
457 };
458 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
459 static const char * const byt_sus_gpio_groups[] = {
460 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
461 };
462
463 static const struct intel_function byt_sus_functions[] = {
464 FUNCTION("usb", byt_sus_usb_groups),
465 FUNCTION("spi", byt_sus_spi_groups),
466 FUNCTION("gpio", byt_sus_gpio_groups),
467 };
468
469 static const struct intel_community byt_sus_communities[] = {
470 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
471 };
472
473 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
474 .uid = BYT_SUS_ACPI_UID,
475 .pins = byt_sus_pins,
476 .npins = ARRAY_SIZE(byt_sus_pins),
477 .groups = byt_sus_groups,
478 .ngroups = ARRAY_SIZE(byt_sus_groups),
479 .functions = byt_sus_functions,
480 .nfunctions = ARRAY_SIZE(byt_sus_functions),
481 .communities = byt_sus_communities,
482 .ncommunities = ARRAY_SIZE(byt_sus_communities),
483 };
484
485 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
486 PINCTRL_PIN(0, "HV_DDI0_HPD"),
487 PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"),
488 PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"),
489 PINCTRL_PIN(3, "PANEL0_VDDEN"),
490 PINCTRL_PIN(4, "PANEL0_BKLTEN"),
491 PINCTRL_PIN(5, "PANEL0_BKLTCTL"),
492 PINCTRL_PIN(6, "HV_DDI1_HPD"),
493 PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"),
494 PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"),
495 PINCTRL_PIN(9, "PANEL1_VDDEN"),
496 PINCTRL_PIN(10, "PANEL1_BKLTEN"),
497 PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
498 PINCTRL_PIN(12, "GP_INTD_DSI_TE1"),
499 PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"),
500 PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"),
501 PINCTRL_PIN(15, "GP_CAMERASB00"),
502 PINCTRL_PIN(16, "GP_CAMERASB01"),
503 PINCTRL_PIN(17, "GP_CAMERASB02"),
504 PINCTRL_PIN(18, "GP_CAMERASB03"),
505 PINCTRL_PIN(19, "GP_CAMERASB04"),
506 PINCTRL_PIN(20, "GP_CAMERASB05"),
507 PINCTRL_PIN(21, "GP_CAMERASB06"),
508 PINCTRL_PIN(22, "GP_CAMERASB07"),
509 PINCTRL_PIN(23, "GP_CAMERASB08"),
510 PINCTRL_PIN(24, "GP_CAMERASB09"),
511 PINCTRL_PIN(25, "GP_CAMERASB10"),
512 PINCTRL_PIN(26, "GP_CAMERASB11"),
513 PINCTRL_PIN(27, "GP_INTD_DSI_TE2"),
514 };
515
516 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
517 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
518 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
519 3, 6, 10, 13, 2, 5, 9, 7,
520 };
521
522 static const struct intel_community byt_ncore_communities[] = {
523 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
524 };
525
526 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
527 .uid = BYT_NCORE_ACPI_UID,
528 .pins = byt_ncore_pins,
529 .npins = ARRAY_SIZE(byt_ncore_pins),
530 .communities = byt_ncore_communities,
531 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
532 };
533
534 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
535 &byt_score_soc_data,
536 &byt_sus_soc_data,
537 &byt_ncore_soc_data,
538 NULL
539 };
540
541 static DEFINE_RAW_SPINLOCK(byt_lock);
542
543 static struct intel_community *byt_get_community(struct intel_pinctrl *vg,
544 unsigned int pin)
545 {
546 struct intel_community *comm;
547 int i;
548
549 for (i = 0; i < vg->ncommunities; i++) {
550 comm = vg->communities + i;
551 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
552 return comm;
553 }
554
555 return NULL;
556 }
557
558 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
559 int reg)
560 {
561 struct intel_community *comm = byt_get_community(vg, offset);
562 u32 reg_offset;
563
564 if (!comm)
565 return NULL;
566
567 offset -= comm->pin_base;
568 switch (reg) {
569 case BYT_INT_STAT_REG:
570 reg_offset = (offset / 32) * 4;
571 break;
572 case BYT_DEBOUNCE_REG:
573 reg_offset = 0;
574 break;
575 default:
576 reg_offset = comm->pad_map[offset] * 16;
577 break;
578 }
579
580 return comm->pad_regs + reg_offset + reg;
581 }
582
583 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
584 {
585 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
586
587 return vg->soc->ngroups;
588 }
589
590 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
591 unsigned int selector)
592 {
593 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
594
595 return vg->soc->groups[selector].name;
596 }
597
598 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
599 unsigned int selector,
600 const unsigned int **pins,
601 unsigned int *num_pins)
602 {
603 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
604
605 *pins = vg->soc->groups[selector].pins;
606 *num_pins = vg->soc->groups[selector].npins;
607
608 return 0;
609 }
610
611 static const struct pinctrl_ops byt_pinctrl_ops = {
612 .get_groups_count = byt_get_groups_count,
613 .get_group_name = byt_get_group_name,
614 .get_group_pins = byt_get_group_pins,
615 };
616
617 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
618 {
619 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
620
621 return vg->soc->nfunctions;
622 }
623
624 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
625 unsigned int selector)
626 {
627 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
628
629 return vg->soc->functions[selector].name;
630 }
631
632 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
633 unsigned int selector,
634 const char * const **groups,
635 unsigned int *num_groups)
636 {
637 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
638
639 *groups = vg->soc->functions[selector].groups;
640 *num_groups = vg->soc->functions[selector].ngroups;
641
642 return 0;
643 }
644
645 static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
646 const struct intel_pingroup group,
647 unsigned int func)
648 {
649 unsigned long flags;
650 int i;
651
652 raw_spin_lock_irqsave(&byt_lock, flags);
653
654 for (i = 0; i < group.npins; i++) {
655 void __iomem *padcfg0;
656 u32 value;
657
658 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
659 if (!padcfg0) {
660 dev_warn(vg->dev,
661 "Group %s, pin %i not muxed (no padcfg0)\n",
662 group.name, i);
663 continue;
664 }
665
666 value = readl(padcfg0);
667 value &= ~BYT_PIN_MUX;
668 value |= func;
669 writel(value, padcfg0);
670 }
671
672 raw_spin_unlock_irqrestore(&byt_lock, flags);
673 }
674
675 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
676 const struct intel_pingroup group,
677 const unsigned int *func)
678 {
679 unsigned long flags;
680 int i;
681
682 raw_spin_lock_irqsave(&byt_lock, flags);
683
684 for (i = 0; i < group.npins; i++) {
685 void __iomem *padcfg0;
686 u32 value;
687
688 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
689 if (!padcfg0) {
690 dev_warn(vg->dev,
691 "Group %s, pin %i not muxed (no padcfg0)\n",
692 group.name, i);
693 continue;
694 }
695
696 value = readl(padcfg0);
697 value &= ~BYT_PIN_MUX;
698 value |= func[i];
699 writel(value, padcfg0);
700 }
701
702 raw_spin_unlock_irqrestore(&byt_lock, flags);
703 }
704
705 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
706 unsigned int group_selector)
707 {
708 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
709 const struct intel_function func = vg->soc->functions[func_selector];
710 const struct intel_pingroup group = vg->soc->groups[group_selector];
711
712 if (group.modes)
713 byt_set_group_mixed_mux(vg, group, group.modes);
714 else if (!strcmp(func.name, "gpio"))
715 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
716 else
717 byt_set_group_simple_mux(vg, group, group.mode);
718
719 return 0;
720 }
721
722 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
723 {
724 /* SCORE pin 92-93 */
725 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
726 offset >= 92 && offset <= 93)
727 return BYT_ALTER_GPIO_MUX;
728
729 /* SUS pin 11-21 */
730 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
731 offset >= 11 && offset <= 21)
732 return BYT_ALTER_GPIO_MUX;
733
734 return BYT_DEFAULT_GPIO_MUX;
735 }
736
737 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
738 {
739 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
740 unsigned long flags;
741 u32 value;
742
743 raw_spin_lock_irqsave(&byt_lock, flags);
744 value = readl(reg);
745
746 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
747 if (value & BYT_DIRECT_IRQ_EN)
748 /* nothing to do */ ;
749 else
750 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
751
752 writel(value, reg);
753 raw_spin_unlock_irqrestore(&byt_lock, flags);
754 }
755
756 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
757 struct pinctrl_gpio_range *range,
758 unsigned int offset)
759 {
760 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
761 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
762 u32 value, gpio_mux;
763 unsigned long flags;
764
765 raw_spin_lock_irqsave(&byt_lock, flags);
766
767 /*
768 * In most cases, func pin mux 000 means GPIO function.
769 * But, some pins may have func pin mux 001 represents
770 * GPIO function.
771 *
772 * Because there are devices out there where some pins were not
773 * configured correctly we allow changing the mux value from
774 * request (but print out warning about that).
775 */
776 value = readl(reg) & BYT_PIN_MUX;
777 gpio_mux = byt_get_gpio_mux(vg, offset);
778 if (gpio_mux != value) {
779 value = readl(reg) & ~BYT_PIN_MUX;
780 value |= gpio_mux;
781 writel(value, reg);
782
783 dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
784 }
785
786 raw_spin_unlock_irqrestore(&byt_lock, flags);
787
788 pm_runtime_get(vg->dev);
789
790 return 0;
791 }
792
793 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
794 struct pinctrl_gpio_range *range,
795 unsigned int offset)
796 {
797 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
798
799 byt_gpio_clear_triggering(vg, offset);
800 pm_runtime_put(vg->dev);
801 }
802
803 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
804 unsigned int offset)
805 {
806 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
807
808 /*
809 * Before making any direction modifications, do a check if gpio is set
810 * for direct IRQ. On Bay Trail, setting GPIO to output does not make
811 * sense, so let's at least inform the caller before they shoot
812 * themselves in the foot.
813 */
814 if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
815 dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
816 }
817
818 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
819 struct pinctrl_gpio_range *range,
820 unsigned int offset,
821 bool input)
822 {
823 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
824 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
825 unsigned long flags;
826 u32 value;
827
828 raw_spin_lock_irqsave(&byt_lock, flags);
829
830 value = readl(val_reg);
831 value &= ~BYT_DIR_MASK;
832 if (input)
833 value |= BYT_OUTPUT_EN;
834 else
835 byt_gpio_direct_irq_check(vg, offset);
836
837 writel(value, val_reg);
838
839 raw_spin_unlock_irqrestore(&byt_lock, flags);
840
841 return 0;
842 }
843
844 static const struct pinmux_ops byt_pinmux_ops = {
845 .get_functions_count = byt_get_functions_count,
846 .get_function_name = byt_get_function_name,
847 .get_function_groups = byt_get_function_groups,
848 .set_mux = byt_set_mux,
849 .gpio_request_enable = byt_gpio_request_enable,
850 .gpio_disable_free = byt_gpio_disable_free,
851 .gpio_set_direction = byt_gpio_set_direction,
852 };
853
854 static void byt_get_pull_strength(u32 reg, u16 *strength)
855 {
856 switch (reg & BYT_PULL_STR_MASK) {
857 case BYT_PULL_STR_2K:
858 *strength = 2000;
859 break;
860 case BYT_PULL_STR_10K:
861 *strength = 10000;
862 break;
863 case BYT_PULL_STR_20K:
864 *strength = 20000;
865 break;
866 case BYT_PULL_STR_40K:
867 *strength = 40000;
868 break;
869 }
870 }
871
872 static int byt_set_pull_strength(u32 *reg, u16 strength)
873 {
874 *reg &= ~BYT_PULL_STR_MASK;
875
876 switch (strength) {
877 case 2000:
878 *reg |= BYT_PULL_STR_2K;
879 break;
880 case 10000:
881 *reg |= BYT_PULL_STR_10K;
882 break;
883 case 20000:
884 *reg |= BYT_PULL_STR_20K;
885 break;
886 case 40000:
887 *reg |= BYT_PULL_STR_40K;
888 break;
889 default:
890 return -EINVAL;
891 }
892
893 return 0;
894 }
895
896 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
897 unsigned long *config)
898 {
899 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
900 enum pin_config_param param = pinconf_to_config_param(*config);
901 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
902 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
903 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
904 unsigned long flags;
905 u32 conf, pull, val, debounce;
906 u16 arg = 0;
907
908 raw_spin_lock_irqsave(&byt_lock, flags);
909 conf = readl(conf_reg);
910 pull = conf & BYT_PULL_ASSIGN_MASK;
911 val = readl(val_reg);
912 raw_spin_unlock_irqrestore(&byt_lock, flags);
913
914 switch (param) {
915 case PIN_CONFIG_BIAS_DISABLE:
916 if (pull)
917 return -EINVAL;
918 break;
919 case PIN_CONFIG_BIAS_PULL_DOWN:
920 /* Pull assignment is only applicable in input mode */
921 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
922 return -EINVAL;
923
924 byt_get_pull_strength(conf, &arg);
925
926 break;
927 case PIN_CONFIG_BIAS_PULL_UP:
928 /* Pull assignment is only applicable in input mode */
929 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
930 return -EINVAL;
931
932 byt_get_pull_strength(conf, &arg);
933
934 break;
935 case PIN_CONFIG_INPUT_DEBOUNCE:
936 if (!(conf & BYT_DEBOUNCE_EN))
937 return -EINVAL;
938
939 raw_spin_lock_irqsave(&byt_lock, flags);
940 debounce = readl(db_reg);
941 raw_spin_unlock_irqrestore(&byt_lock, flags);
942
943 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
944 case BYT_DEBOUNCE_PULSE_375US:
945 arg = 375;
946 break;
947 case BYT_DEBOUNCE_PULSE_750US:
948 arg = 750;
949 break;
950 case BYT_DEBOUNCE_PULSE_1500US:
951 arg = 1500;
952 break;
953 case BYT_DEBOUNCE_PULSE_3MS:
954 arg = 3000;
955 break;
956 case BYT_DEBOUNCE_PULSE_6MS:
957 arg = 6000;
958 break;
959 case BYT_DEBOUNCE_PULSE_12MS:
960 arg = 12000;
961 break;
962 case BYT_DEBOUNCE_PULSE_24MS:
963 arg = 24000;
964 break;
965 default:
966 return -EINVAL;
967 }
968
969 break;
970 default:
971 return -ENOTSUPP;
972 }
973
974 *config = pinconf_to_config_packed(param, arg);
975
976 return 0;
977 }
978
979 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
980 unsigned int offset,
981 unsigned long *configs,
982 unsigned int num_configs)
983 {
984 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
985 unsigned int param, arg;
986 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
987 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
988 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
989 unsigned long flags;
990 u32 conf, val, debounce;
991 int i, ret = 0;
992
993 raw_spin_lock_irqsave(&byt_lock, flags);
994
995 conf = readl(conf_reg);
996 val = readl(val_reg);
997
998 for (i = 0; i < num_configs; i++) {
999 param = pinconf_to_config_param(configs[i]);
1000 arg = pinconf_to_config_argument(configs[i]);
1001
1002 switch (param) {
1003 case PIN_CONFIG_BIAS_DISABLE:
1004 conf &= ~BYT_PULL_ASSIGN_MASK;
1005 break;
1006 case PIN_CONFIG_BIAS_PULL_DOWN:
1007 /* Set default strength value in case none is given */
1008 if (arg == 1)
1009 arg = 2000;
1010
1011 /*
1012 * Pull assignment is only applicable in input mode. If
1013 * chip is not in input mode, set it and warn about it.
1014 */
1015 if (val & BYT_INPUT_EN) {
1016 val &= ~BYT_INPUT_EN;
1017 writel(val, val_reg);
1018 dev_warn(vg->dev,
1019 "pin %u forcibly set to input mode\n",
1020 offset);
1021 }
1022
1023 conf &= ~BYT_PULL_ASSIGN_MASK;
1024 conf |= BYT_PULL_ASSIGN_DOWN;
1025 ret = byt_set_pull_strength(&conf, arg);
1026
1027 break;
1028 case PIN_CONFIG_BIAS_PULL_UP:
1029 /* Set default strength value in case none is given */
1030 if (arg == 1)
1031 arg = 2000;
1032
1033 /*
1034 * Pull assignment is only applicable in input mode. If
1035 * chip is not in input mode, set it and warn about it.
1036 */
1037 if (val & BYT_INPUT_EN) {
1038 val &= ~BYT_INPUT_EN;
1039 writel(val, val_reg);
1040 dev_warn(vg->dev,
1041 "pin %u forcibly set to input mode\n",
1042 offset);
1043 }
1044
1045 conf &= ~BYT_PULL_ASSIGN_MASK;
1046 conf |= BYT_PULL_ASSIGN_UP;
1047 ret = byt_set_pull_strength(&conf, arg);
1048
1049 break;
1050 case PIN_CONFIG_INPUT_DEBOUNCE:
1051 debounce = readl(db_reg);
1052
1053 if (arg)
1054 conf |= BYT_DEBOUNCE_EN;
1055 else
1056 conf &= ~BYT_DEBOUNCE_EN;
1057
1058 switch (arg) {
1059 case 375:
1060 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1061 debounce |= BYT_DEBOUNCE_PULSE_375US;
1062 break;
1063 case 750:
1064 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1065 debounce |= BYT_DEBOUNCE_PULSE_750US;
1066 break;
1067 case 1500:
1068 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1069 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1070 break;
1071 case 3000:
1072 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1073 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1074 break;
1075 case 6000:
1076 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1077 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1078 break;
1079 case 12000:
1080 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1081 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1082 break;
1083 case 24000:
1084 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1085 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1086 break;
1087 default:
1088 if (arg)
1089 ret = -EINVAL;
1090 break;
1091 }
1092
1093 if (!ret)
1094 writel(debounce, db_reg);
1095 break;
1096 default:
1097 ret = -ENOTSUPP;
1098 }
1099
1100 if (ret)
1101 break;
1102 }
1103
1104 if (!ret)
1105 writel(conf, conf_reg);
1106
1107 raw_spin_unlock_irqrestore(&byt_lock, flags);
1108
1109 return ret;
1110 }
1111
1112 static const struct pinconf_ops byt_pinconf_ops = {
1113 .is_generic = true,
1114 .pin_config_get = byt_pin_config_get,
1115 .pin_config_set = byt_pin_config_set,
1116 };
1117
1118 static const struct pinctrl_desc byt_pinctrl_desc = {
1119 .pctlops = &byt_pinctrl_ops,
1120 .pmxops = &byt_pinmux_ops,
1121 .confops = &byt_pinconf_ops,
1122 .owner = THIS_MODULE,
1123 };
1124
1125 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1126 {
1127 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1128 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1129 unsigned long flags;
1130 u32 val;
1131
1132 raw_spin_lock_irqsave(&byt_lock, flags);
1133 val = readl(reg);
1134 raw_spin_unlock_irqrestore(&byt_lock, flags);
1135
1136 return !!(val & BYT_LEVEL);
1137 }
1138
1139 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1140 {
1141 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1142 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1143 unsigned long flags;
1144 u32 old_val;
1145
1146 if (!reg)
1147 return;
1148
1149 raw_spin_lock_irqsave(&byt_lock, flags);
1150 old_val = readl(reg);
1151 if (value)
1152 writel(old_val | BYT_LEVEL, reg);
1153 else
1154 writel(old_val & ~BYT_LEVEL, reg);
1155 raw_spin_unlock_irqrestore(&byt_lock, flags);
1156 }
1157
1158 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1159 {
1160 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1161 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1162 unsigned long flags;
1163 u32 value;
1164
1165 if (!reg)
1166 return -EINVAL;
1167
1168 raw_spin_lock_irqsave(&byt_lock, flags);
1169 value = readl(reg);
1170 raw_spin_unlock_irqrestore(&byt_lock, flags);
1171
1172 if (!(value & BYT_OUTPUT_EN))
1173 return GPIO_LINE_DIRECTION_OUT;
1174 if (!(value & BYT_INPUT_EN))
1175 return GPIO_LINE_DIRECTION_IN;
1176
1177 return -EINVAL;
1178 }
1179
1180 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1181 {
1182 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1183 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1184 unsigned long flags;
1185 u32 reg;
1186
1187 raw_spin_lock_irqsave(&byt_lock, flags);
1188
1189 reg = readl(val_reg);
1190 reg &= ~BYT_DIR_MASK;
1191 reg |= BYT_OUTPUT_EN;
1192 writel(reg, val_reg);
1193
1194 raw_spin_unlock_irqrestore(&byt_lock, flags);
1195 return 0;
1196 }
1197
1198 /*
1199 * Note despite the temptation this MUST NOT be converted into a call to
1200 * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
1201 * MUST be done as a single BYT_VAL_REG register write.
1202 * See the commit message of the commit adding this comment for details.
1203 */
1204 static int byt_gpio_direction_output(struct gpio_chip *chip,
1205 unsigned int offset, int value)
1206 {
1207 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1208 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1209 unsigned long flags;
1210 u32 reg;
1211
1212 raw_spin_lock_irqsave(&byt_lock, flags);
1213
1214 byt_gpio_direct_irq_check(vg, offset);
1215
1216 reg = readl(val_reg);
1217 reg &= ~BYT_DIR_MASK;
1218 if (value)
1219 reg |= BYT_LEVEL;
1220 else
1221 reg &= ~BYT_LEVEL;
1222
1223 writel(reg, val_reg);
1224
1225 raw_spin_unlock_irqrestore(&byt_lock, flags);
1226 return 0;
1227 }
1228
1229 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1230 {
1231 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1232 int i;
1233 u32 conf0, val;
1234
1235 for (i = 0; i < vg->soc->npins; i++) {
1236 const struct intel_community *comm;
1237 const char *pull_str = NULL;
1238 const char *pull = NULL;
1239 void __iomem *reg;
1240 unsigned long flags;
1241 const char *label;
1242 unsigned int pin;
1243
1244 raw_spin_lock_irqsave(&byt_lock, flags);
1245 pin = vg->soc->pins[i].number;
1246 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1247 if (!reg) {
1248 seq_printf(s,
1249 "Could not retrieve pin %i conf0 reg\n",
1250 pin);
1251 raw_spin_unlock_irqrestore(&byt_lock, flags);
1252 continue;
1253 }
1254 conf0 = readl(reg);
1255
1256 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1257 if (!reg) {
1258 seq_printf(s,
1259 "Could not retrieve pin %i val reg\n", pin);
1260 raw_spin_unlock_irqrestore(&byt_lock, flags);
1261 continue;
1262 }
1263 val = readl(reg);
1264 raw_spin_unlock_irqrestore(&byt_lock, flags);
1265
1266 comm = byt_get_community(vg, pin);
1267 if (!comm) {
1268 seq_printf(s,
1269 "Could not get community for pin %i\n", pin);
1270 continue;
1271 }
1272 label = gpiochip_is_requested(chip, i);
1273 if (!label)
1274 label = "Unrequested";
1275
1276 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1277 case BYT_PULL_ASSIGN_UP:
1278 pull = "up";
1279 break;
1280 case BYT_PULL_ASSIGN_DOWN:
1281 pull = "down";
1282 break;
1283 }
1284
1285 switch (conf0 & BYT_PULL_STR_MASK) {
1286 case BYT_PULL_STR_2K:
1287 pull_str = "2k";
1288 break;
1289 case BYT_PULL_STR_10K:
1290 pull_str = "10k";
1291 break;
1292 case BYT_PULL_STR_20K:
1293 pull_str = "20k";
1294 break;
1295 case BYT_PULL_STR_40K:
1296 pull_str = "40k";
1297 break;
1298 }
1299
1300 seq_printf(s,
1301 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1302 pin,
1303 label,
1304 val & BYT_INPUT_EN ? " " : "in",
1305 val & BYT_OUTPUT_EN ? " " : "out",
1306 val & BYT_LEVEL ? "hi" : "lo",
1307 comm->pad_map[i], comm->pad_map[i] * 16,
1308 conf0 & 0x7,
1309 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1310 conf0 & BYT_TRIG_POS ? " rise" : " ",
1311 conf0 & BYT_TRIG_LVL ? " level" : " ");
1312
1313 if (pull && pull_str)
1314 seq_printf(s, " %-4s %-3s", pull, pull_str);
1315 else
1316 seq_puts(s, " ");
1317
1318 if (conf0 & BYT_IODEN)
1319 seq_puts(s, " open-drain");
1320
1321 seq_puts(s, "\n");
1322 }
1323 }
1324
1325 static const struct gpio_chip byt_gpio_chip = {
1326 .owner = THIS_MODULE,
1327 .request = gpiochip_generic_request,
1328 .free = gpiochip_generic_free,
1329 .get_direction = byt_gpio_get_direction,
1330 .direction_input = byt_gpio_direction_input,
1331 .direction_output = byt_gpio_direction_output,
1332 .get = byt_gpio_get,
1333 .set = byt_gpio_set,
1334 .set_config = gpiochip_generic_config,
1335 .dbg_show = byt_gpio_dbg_show,
1336 };
1337
1338 static void byt_irq_ack(struct irq_data *d)
1339 {
1340 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1341 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1342 unsigned int offset = irqd_to_hwirq(d);
1343 void __iomem *reg;
1344
1345 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1346 if (!reg)
1347 return;
1348
1349 raw_spin_lock(&byt_lock);
1350 writel(BIT(offset % 32), reg);
1351 raw_spin_unlock(&byt_lock);
1352 }
1353
1354 static void byt_irq_mask(struct irq_data *d)
1355 {
1356 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1357 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1358
1359 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1360 }
1361
1362 static void byt_irq_unmask(struct irq_data *d)
1363 {
1364 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1365 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1366 unsigned int offset = irqd_to_hwirq(d);
1367 unsigned long flags;
1368 void __iomem *reg;
1369 u32 value;
1370
1371 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1372 if (!reg)
1373 return;
1374
1375 raw_spin_lock_irqsave(&byt_lock, flags);
1376 value = readl(reg);
1377
1378 switch (irqd_get_trigger_type(d)) {
1379 case IRQ_TYPE_LEVEL_HIGH:
1380 value |= BYT_TRIG_LVL;
1381 fallthrough;
1382 case IRQ_TYPE_EDGE_RISING:
1383 value |= BYT_TRIG_POS;
1384 break;
1385 case IRQ_TYPE_LEVEL_LOW:
1386 value |= BYT_TRIG_LVL;
1387 fallthrough;
1388 case IRQ_TYPE_EDGE_FALLING:
1389 value |= BYT_TRIG_NEG;
1390 break;
1391 case IRQ_TYPE_EDGE_BOTH:
1392 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1393 break;
1394 }
1395
1396 writel(value, reg);
1397
1398 raw_spin_unlock_irqrestore(&byt_lock, flags);
1399 }
1400
1401 static int byt_irq_type(struct irq_data *d, unsigned int type)
1402 {
1403 struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1404 u32 offset = irqd_to_hwirq(d);
1405 u32 value;
1406 unsigned long flags;
1407 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1408
1409 if (!reg || offset >= vg->chip.ngpio)
1410 return -EINVAL;
1411
1412 raw_spin_lock_irqsave(&byt_lock, flags);
1413 value = readl(reg);
1414
1415 WARN(value & BYT_DIRECT_IRQ_EN,
1416 "Bad pad config for io mode, force direct_irq_en bit clearing");
1417
1418 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1419 * are used to indicate high and low level triggering
1420 */
1421 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1422 BYT_TRIG_LVL);
1423 /* Enable glitch filtering */
1424 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1425 BYT_GLITCH_F_FAST_CLK;
1426
1427 writel(value, reg);
1428
1429 if (type & IRQ_TYPE_EDGE_BOTH)
1430 irq_set_handler_locked(d, handle_edge_irq);
1431 else if (type & IRQ_TYPE_LEVEL_MASK)
1432 irq_set_handler_locked(d, handle_level_irq);
1433
1434 raw_spin_unlock_irqrestore(&byt_lock, flags);
1435
1436 return 0;
1437 }
1438
1439 static void byt_gpio_irq_handler(struct irq_desc *desc)
1440 {
1441 struct irq_data *data = irq_desc_get_irq_data(desc);
1442 struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
1443 struct irq_chip *chip = irq_data_get_irq_chip(data);
1444 u32 base, pin;
1445 void __iomem *reg;
1446 unsigned long pending;
1447 unsigned int virq;
1448
1449 /* check from GPIO controller which pin triggered the interrupt */
1450 for (base = 0; base < vg->chip.ngpio; base += 32) {
1451 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1452
1453 if (!reg) {
1454 dev_warn(vg->dev,
1455 "Pin %i: could not retrieve interrupt status register\n",
1456 base);
1457 continue;
1458 }
1459
1460 raw_spin_lock(&byt_lock);
1461 pending = readl(reg);
1462 raw_spin_unlock(&byt_lock);
1463 for_each_set_bit(pin, &pending, 32) {
1464 virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
1465 generic_handle_irq(virq);
1466 }
1467 }
1468 chip->irq_eoi(data);
1469 }
1470
1471 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1472 unsigned long *valid_mask,
1473 unsigned int ngpios)
1474 {
1475 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1476 void __iomem *reg;
1477 u32 value;
1478 int i;
1479
1480 /*
1481 * Clear interrupt triggers for all pins that are GPIOs and
1482 * do not use direct IRQ mode. This will prevent spurious
1483 * interrupts from misconfigured pins.
1484 */
1485 for (i = 0; i < vg->soc->npins; i++) {
1486 unsigned int pin = vg->soc->pins[i].number;
1487
1488 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1489 if (!reg) {
1490 dev_warn(vg->dev,
1491 "Pin %i: could not retrieve conf0 register\n",
1492 i);
1493 continue;
1494 }
1495
1496 value = readl(reg);
1497 if (value & BYT_DIRECT_IRQ_EN) {
1498 clear_bit(i, valid_mask);
1499 dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i);
1500 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1501 byt_gpio_clear_triggering(vg, i);
1502 dev_dbg(vg->dev, "disabling GPIO %d\n", i);
1503 }
1504 }
1505 }
1506
1507 static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
1508 {
1509 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1510 void __iomem *reg;
1511 u32 base, value;
1512
1513 /* clear interrupt status trigger registers */
1514 for (base = 0; base < vg->soc->npins; base += 32) {
1515 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1516
1517 if (!reg) {
1518 dev_warn(vg->dev,
1519 "Pin %i: could not retrieve irq status reg\n",
1520 base);
1521 continue;
1522 }
1523
1524 writel(0xffffffff, reg);
1525 /* make sure trigger bits are cleared, if not then a pin
1526 might be misconfigured in bios */
1527 value = readl(reg);
1528 if (value)
1529 dev_err(vg->dev,
1530 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1531 base / 32, value);
1532 }
1533
1534 return 0;
1535 }
1536
1537 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1538 {
1539 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1540 struct device *dev = vg->dev;
1541 int ret;
1542
1543 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1544 if (ret)
1545 dev_err(dev, "failed to add GPIO pin range\n");
1546
1547 return ret;
1548 }
1549
1550 static int byt_gpio_probe(struct intel_pinctrl *vg)
1551 {
1552 struct platform_device *pdev = to_platform_device(vg->dev);
1553 struct gpio_chip *gc;
1554 int irq, ret;
1555
1556 /* Set up gpio chip */
1557 vg->chip = byt_gpio_chip;
1558 gc = &vg->chip;
1559 gc->label = dev_name(vg->dev);
1560 gc->base = -1;
1561 gc->can_sleep = false;
1562 gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1563 gc->parent = vg->dev;
1564 gc->ngpio = vg->soc->npins;
1565
1566 #ifdef CONFIG_PM_SLEEP
1567 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
1568 GFP_KERNEL);
1569 if (!vg->context.pads)
1570 return -ENOMEM;
1571 #endif
1572
1573 /* set up interrupts */
1574 irq = platform_get_irq_optional(pdev, 0);
1575 if (irq > 0) {
1576 struct gpio_irq_chip *girq;
1577
1578 vg->irqchip.name = "BYT-GPIO",
1579 vg->irqchip.irq_ack = byt_irq_ack,
1580 vg->irqchip.irq_mask = byt_irq_mask,
1581 vg->irqchip.irq_unmask = byt_irq_unmask,
1582 vg->irqchip.irq_set_type = byt_irq_type,
1583 vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE,
1584
1585 girq = &gc->irq;
1586 girq->chip = &vg->irqchip;
1587 girq->init_hw = byt_gpio_irq_init_hw;
1588 girq->init_valid_mask = byt_init_irq_valid_mask;
1589 girq->parent_handler = byt_gpio_irq_handler;
1590 girq->num_parents = 1;
1591 girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
1592 sizeof(*girq->parents), GFP_KERNEL);
1593 if (!girq->parents)
1594 return -ENOMEM;
1595 girq->parents[0] = irq;
1596 girq->default_type = IRQ_TYPE_NONE;
1597 girq->handler = handle_bad_irq;
1598 }
1599
1600 ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1601 if (ret) {
1602 dev_err(vg->dev, "failed adding byt-gpio chip\n");
1603 return ret;
1604 }
1605
1606 return ret;
1607 }
1608
1609 static int byt_set_soc_data(struct intel_pinctrl *vg,
1610 const struct intel_pinctrl_soc_data *soc)
1611 {
1612 struct platform_device *pdev = to_platform_device(vg->dev);
1613 int i;
1614
1615 vg->soc = soc;
1616
1617 vg->ncommunities = vg->soc->ncommunities;
1618 vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
1619 sizeof(*vg->communities), GFP_KERNEL);
1620 if (!vg->communities)
1621 return -ENOMEM;
1622
1623 for (i = 0; i < vg->soc->ncommunities; i++) {
1624 struct intel_community *comm = vg->communities + i;
1625
1626 *comm = vg->soc->communities[i];
1627
1628 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
1629 if (IS_ERR(comm->pad_regs))
1630 return PTR_ERR(comm->pad_regs);
1631 }
1632
1633 return 0;
1634 }
1635
1636 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1637 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1638 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1639 { }
1640 };
1641
1642 static int byt_pinctrl_probe(struct platform_device *pdev)
1643 {
1644 const struct intel_pinctrl_soc_data *soc_data;
1645 struct device *dev = &pdev->dev;
1646 struct intel_pinctrl *vg;
1647 int ret;
1648
1649 soc_data = intel_pinctrl_get_soc_data(pdev);
1650 if (IS_ERR(soc_data))
1651 return PTR_ERR(soc_data);
1652
1653 vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
1654 if (!vg)
1655 return -ENOMEM;
1656
1657 vg->dev = dev;
1658 ret = byt_set_soc_data(vg, soc_data);
1659 if (ret) {
1660 dev_err(dev, "failed to set soc data\n");
1661 return ret;
1662 }
1663
1664 vg->pctldesc = byt_pinctrl_desc;
1665 vg->pctldesc.name = dev_name(dev);
1666 vg->pctldesc.pins = vg->soc->pins;
1667 vg->pctldesc.npins = vg->soc->npins;
1668
1669 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1670 if (IS_ERR(vg->pctldev)) {
1671 dev_err(dev, "failed to register pinctrl driver\n");
1672 return PTR_ERR(vg->pctldev);
1673 }
1674
1675 ret = byt_gpio_probe(vg);
1676 if (ret)
1677 return ret;
1678
1679 platform_set_drvdata(pdev, vg);
1680 pm_runtime_enable(dev);
1681
1682 return 0;
1683 }
1684
1685 #ifdef CONFIG_PM_SLEEP
1686 static int byt_gpio_suspend(struct device *dev)
1687 {
1688 struct intel_pinctrl *vg = dev_get_drvdata(dev);
1689 unsigned long flags;
1690 int i;
1691
1692 raw_spin_lock_irqsave(&byt_lock, flags);
1693
1694 for (i = 0; i < vg->soc->npins; i++) {
1695 void __iomem *reg;
1696 u32 value;
1697 unsigned int pin = vg->soc->pins[i].number;
1698
1699 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1700 if (!reg) {
1701 dev_warn(vg->dev,
1702 "Pin %i: could not retrieve conf0 register\n",
1703 i);
1704 continue;
1705 }
1706 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1707 vg->context.pads[i].conf0 = value;
1708
1709 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1710 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1711 vg->context.pads[i].val = value;
1712 }
1713
1714 raw_spin_unlock_irqrestore(&byt_lock, flags);
1715 return 0;
1716 }
1717
1718 static int byt_gpio_resume(struct device *dev)
1719 {
1720 struct intel_pinctrl *vg = dev_get_drvdata(dev);
1721 unsigned long flags;
1722 int i;
1723
1724 raw_spin_lock_irqsave(&byt_lock, flags);
1725
1726 for (i = 0; i < vg->soc->npins; i++) {
1727 void __iomem *reg;
1728 u32 value;
1729 unsigned int pin = vg->soc->pins[i].number;
1730
1731 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1732 if (!reg) {
1733 dev_warn(vg->dev,
1734 "Pin %i: could not retrieve conf0 register\n",
1735 i);
1736 continue;
1737 }
1738 value = readl(reg);
1739 if ((value & BYT_CONF0_RESTORE_MASK) !=
1740 vg->context.pads[i].conf0) {
1741 value &= ~BYT_CONF0_RESTORE_MASK;
1742 value |= vg->context.pads[i].conf0;
1743 writel(value, reg);
1744 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1745 }
1746
1747 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1748 value = readl(reg);
1749 if ((value & BYT_VAL_RESTORE_MASK) !=
1750 vg->context.pads[i].val) {
1751 u32 v;
1752
1753 v = value & ~BYT_VAL_RESTORE_MASK;
1754 v |= vg->context.pads[i].val;
1755 if (v != value) {
1756 writel(v, reg);
1757 dev_dbg(dev, "restored pin %d val %#08x\n",
1758 i, v);
1759 }
1760 }
1761 }
1762
1763 raw_spin_unlock_irqrestore(&byt_lock, flags);
1764 return 0;
1765 }
1766 #endif
1767
1768 #ifdef CONFIG_PM
1769 static int byt_gpio_runtime_suspend(struct device *dev)
1770 {
1771 return 0;
1772 }
1773
1774 static int byt_gpio_runtime_resume(struct device *dev)
1775 {
1776 return 0;
1777 }
1778 #endif
1779
1780 static const struct dev_pm_ops byt_gpio_pm_ops = {
1781 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1782 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1783 NULL)
1784 };
1785
1786 static struct platform_driver byt_gpio_driver = {
1787 .probe = byt_pinctrl_probe,
1788 .driver = {
1789 .name = "byt_gpio",
1790 .pm = &byt_gpio_pm_ops,
1791 .acpi_match_table = byt_gpio_acpi_match,
1792 .suppress_bind_attrs = true,
1793 },
1794 };
1795
1796 static int __init byt_gpio_init(void)
1797 {
1798 return platform_driver_register(&byt_gpio_driver);
1799 }
1800 subsys_initcall(byt_gpio_init);
Linux with added FPC-III support