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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / pinctrl / intel / pinctrl-lynxpoint.c
blob0a48ca46ab59757bfcb795dfdc7571e12c66a785
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Intel Lynxpoint PCH pinctrl/GPIO driver
4 *
5 * Copyright (c) 2012, 2019, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Andy Shevchenko <andriy.shevchenko@linux.intel.com>
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/bitops.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26
27 #include "pinctrl-intel.h"
28
29 #define COMMUNITY(p, n) \
30 { \
31 .pin_base = (p), \
32 .npins = (n), \
33 }
34
35 static const struct pinctrl_pin_desc lptlp_pins[] = {
36 PINCTRL_PIN(0, "GP0_UART1_RXD"),
37 PINCTRL_PIN(1, "GP1_UART1_TXD"),
38 PINCTRL_PIN(2, "GP2_UART1_RTSB"),
39 PINCTRL_PIN(3, "GP3_UART1_CTSB"),
40 PINCTRL_PIN(4, "GP4_I2C0_SDA"),
41 PINCTRL_PIN(5, "GP5_I2C0_SCL"),
42 PINCTRL_PIN(6, "GP6_I2C1_SDA"),
43 PINCTRL_PIN(7, "GP7_I2C1_SCL"),
44 PINCTRL_PIN(8, "GP8"),
45 PINCTRL_PIN(9, "GP9"),
46 PINCTRL_PIN(10, "GP10"),
47 PINCTRL_PIN(11, "GP11_SMBALERTB"),
48 PINCTRL_PIN(12, "GP12_LANPHYPC"),
49 PINCTRL_PIN(13, "GP13"),
50 PINCTRL_PIN(14, "GP14"),
51 PINCTRL_PIN(15, "GP15"),
52 PINCTRL_PIN(16, "GP16_MGPIO9"),
53 PINCTRL_PIN(17, "GP17_MGPIO10"),
54 PINCTRL_PIN(18, "GP18_SRC0CLKRQB"),
55 PINCTRL_PIN(19, "GP19_SRC1CLKRQB"),
56 PINCTRL_PIN(20, "GP20_SRC2CLKRQB"),
57 PINCTRL_PIN(21, "GP21_SRC3CLKRQB"),
58 PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"),
59 PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"),
60 PINCTRL_PIN(24, "GP24_MGPIO0"),
61 PINCTRL_PIN(25, "GP25_USBWAKEOUTB"),
62 PINCTRL_PIN(26, "GP26_MGPIO5"),
63 PINCTRL_PIN(27, "GP27_MGPIO6"),
64 PINCTRL_PIN(28, "GP28_MGPIO7"),
65 PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"),
66 PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"),
67 PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"),
68 PINCTRL_PIN(32, "GP32_CLKRUNB"),
69 PINCTRL_PIN(33, "GP33_DEVSLP0"),
70 PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"),
71 PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"),
72 PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"),
73 PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"),
74 PINCTRL_PIN(38, "GP38_DEVSLP1"),
75 PINCTRL_PIN(39, "GP39_DEVSLP2"),
76 PINCTRL_PIN(40, "GP40_OC0B"),
77 PINCTRL_PIN(41, "GP41_OC1B"),
78 PINCTRL_PIN(42, "GP42_OC2B"),
79 PINCTRL_PIN(43, "GP43_OC3B"),
80 PINCTRL_PIN(44, "GP44"),
81 PINCTRL_PIN(45, "GP45_TMS2"),
82 PINCTRL_PIN(46, "GP46_TDO2"),
83 PINCTRL_PIN(47, "GP47"),
84 PINCTRL_PIN(48, "GP48"),
85 PINCTRL_PIN(49, "GP49"),
86 PINCTRL_PIN(50, "GP50"),
87 PINCTRL_PIN(51, "GP51_GSXDOUT"),
88 PINCTRL_PIN(52, "GP52_GSXSLOAD"),
89 PINCTRL_PIN(53, "GP53_GSXDIN"),
90 PINCTRL_PIN(54, "GP54_GSXSRESETB"),
91 PINCTRL_PIN(55, "GP55_GSXCLK"),
92 PINCTRL_PIN(56, "GP56"),
93 PINCTRL_PIN(57, "GP57"),
94 PINCTRL_PIN(58, "GP58"),
95 PINCTRL_PIN(59, "GP59"),
96 PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"),
97 PINCTRL_PIN(61, "GP61_SUS_STATB"),
98 PINCTRL_PIN(62, "GP62_SUSCLK"),
99 PINCTRL_PIN(63, "GP63_SLP_S5B"),
100 PINCTRL_PIN(64, "GP64_SDIO_CLK"),
101 PINCTRL_PIN(65, "GP65_SDIO_CMD"),
102 PINCTRL_PIN(66, "GP66_SDIO_D0"),
103 PINCTRL_PIN(67, "GP67_SDIO_D1"),
104 PINCTRL_PIN(68, "GP68_SDIO_D2"),
105 PINCTRL_PIN(69, "GP69_SDIO_D3"),
106 PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"),
107 PINCTRL_PIN(71, "GP71_MPHYPC"),
108 PINCTRL_PIN(72, "GP72_BATLOWB"),
109 PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"),
110 PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"),
111 PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"),
112 PINCTRL_PIN(76, "GP76_BMBUSYB"),
113 PINCTRL_PIN(77, "GP77_PIRQAB"),
114 PINCTRL_PIN(78, "GP78_PIRQBB"),
115 PINCTRL_PIN(79, "GP79_PIRQCB"),
116 PINCTRL_PIN(80, "GP80_PIRQDB"),
117 PINCTRL_PIN(81, "GP81_SPKR"),
118 PINCTRL_PIN(82, "GP82_RCINB"),
119 PINCTRL_PIN(83, "GP83_GSPI0_CSB"),
120 PINCTRL_PIN(84, "GP84_GSPI0_CLK"),
121 PINCTRL_PIN(85, "GP85_GSPI0_MISO"),
122 PINCTRL_PIN(86, "GP86_GSPI0_MOSI"),
123 PINCTRL_PIN(87, "GP87_GSPI1_CSB"),
124 PINCTRL_PIN(88, "GP88_GSPI1_CLK"),
125 PINCTRL_PIN(89, "GP89_GSPI1_MISO"),
126 PINCTRL_PIN(90, "GP90_GSPI1_MOSI"),
127 PINCTRL_PIN(91, "GP91_UART0_RXD"),
128 PINCTRL_PIN(92, "GP92_UART0_TXD"),
129 PINCTRL_PIN(93, "GP93_UART0_RTSB"),
130 PINCTRL_PIN(94, "GP94_UART0_CTSB"),
131 };
132
133 static const struct intel_community lptlp_communities[] = {
134 COMMUNITY(0, 95),
135 };
136
137 static const struct intel_pinctrl_soc_data lptlp_soc_data = {
138 .pins = lptlp_pins,
139 .npins = ARRAY_SIZE(lptlp_pins),
140 .communities = lptlp_communities,
141 .ncommunities = ARRAY_SIZE(lptlp_communities),
142 };
143
144 /* LynxPoint chipset has support for 95 GPIO pins */
145
146 #define LP_NUM_GPIO 95
147
148 /* Bitmapped register offsets */
149 #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
150 #define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */
151 #define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
152 #define LP_INT_STAT 0x80
153 #define LP_INT_ENABLE 0x90
154
155 /* Each pin has two 32 bit config registers, starting at 0x100 */
156 #define LP_CONFIG1 0x100
157 #define LP_CONFIG2 0x104
158
159 /* LP_CONFIG1 reg bits */
160 #define OUT_LVL_BIT BIT(31)
161 #define IN_LVL_BIT BIT(30)
162 #define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
163 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
164 #define DIR_BIT BIT(2) /* 0: Output, 1: Input */
165 #define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */
166 #define USE_SEL_NATIVE (0 << 0)
167 #define USE_SEL_GPIO (1 << 0)
168
169 /* LP_CONFIG2 reg bits */
170 #define GPINDIS_BIT BIT(2) /* disable input sensing */
171 #define GPIWP_MASK GENMASK(1, 0) /* weak pull options */
172 #define GPIWP_NONE 0 /* none */
173 #define GPIWP_DOWN 1 /* weak pull down */
174 #define GPIWP_UP 2 /* weak pull up */
175
176 /*
177 * Lynxpoint gpios are controlled through both bitmapped registers and
178 * per gpio specific registers. The bitmapped registers are in chunks of
179 * 3 x 32bit registers to cover all 95 GPIOs
180 *
181 * per gpio specific registers consist of two 32bit registers per gpio
182 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of
183 * 190 config registers.
184 *
185 * A simplified view of the register layout look like this:
186 *
187 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
188 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
189 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
190 * ...
191 * LP_INT_ENABLE[31:0] ...
192 * LP_INT_ENABLE[63:32] ...
193 * LP_INT_ENABLE[94:64] ...
194 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
195 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
196 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
197 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
198 * LP2_CONFIG1 (gpio 2) ...
199 * LP2_CONFIG2 (gpio 2) ...
200 * ...
201 * LP94_CONFIG1 (gpio 94) ...
202 * LP94_CONFIG2 (gpio 94) ...
203 *
204 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55.
205 */
206
207 static struct intel_community *lp_get_community(struct intel_pinctrl *lg,
208 unsigned int pin)
209 {
210 struct intel_community *comm;
211 int i;
212
213 for (i = 0; i < lg->ncommunities; i++) {
214 comm = &lg->communities[i];
215 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
216 return comm;
217 }
218
219 return NULL;
220 }
221
222 static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset,
223 int reg)
224 {
225 struct intel_pinctrl *lg = gpiochip_get_data(chip);
226 struct intel_community *comm;
227 int reg_offset;
228
229 comm = lp_get_community(lg, offset);
230 if (!comm)
231 return NULL;
232
233 offset -= comm->pin_base;
234
235 if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
236 /* per gpio specific config registers */
237 reg_offset = offset * 8;
238 else
239 /* bitmapped registers */
240 reg_offset = (offset / 32) * 4;
241
242 return comm->regs + reg_offset + reg;
243 }
244
245 static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin)
246 {
247 void __iomem *acpi_use;
248
249 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED);
250 if (!acpi_use)
251 return true;
252
253 return !(ioread32(acpi_use) & BIT(pin % 32));
254 }
255
256 static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset)
257 {
258 void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC);
259 u32 value;
260
261 value = ioread32(ioxapic_use);
262
263 if (offset >= 8 && offset <= 10)
264 return !!(value & BIT(offset - 8 + 0));
265 if (offset >= 13 && offset <= 14)
266 return !!(value & BIT(offset - 13 + 3));
267 if (offset >= 45 && offset <= 55)
268 return !!(value & BIT(offset - 45 + 5));
269
270 return false;
271 }
272
273 static int lp_get_groups_count(struct pinctrl_dev *pctldev)
274 {
275 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
276
277 return lg->soc->ngroups;
278 }
279
280 static const char *lp_get_group_name(struct pinctrl_dev *pctldev,
281 unsigned int selector)
282 {
283 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
284
285 return lg->soc->groups[selector].name;
286 }
287
288 static int lp_get_group_pins(struct pinctrl_dev *pctldev,
289 unsigned int selector,
290 const unsigned int **pins,
291 unsigned int *num_pins)
292 {
293 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
294
295 *pins = lg->soc->groups[selector].pins;
296 *num_pins = lg->soc->groups[selector].npins;
297
298 return 0;
299 }
300
301 static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
302 unsigned int pin)
303 {
304 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
305 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
306 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
307 u32 value, mode;
308
309 value = ioread32(reg);
310
311 mode = value & USE_SEL_MASK;
312 if (mode == USE_SEL_GPIO)
313 seq_puts(s, "GPIO ");
314 else
315 seq_printf(s, "mode %d ", mode);
316
317 seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2));
318
319 if (lp_gpio_acpi_use(lg, pin))
320 seq_puts(s, " [ACPI]");
321 }
322
323 static const struct pinctrl_ops lptlp_pinctrl_ops = {
324 .get_groups_count = lp_get_groups_count,
325 .get_group_name = lp_get_group_name,
326 .get_group_pins = lp_get_group_pins,
327 .pin_dbg_show = lp_pin_dbg_show,
328 };
329
330 static int lp_get_functions_count(struct pinctrl_dev *pctldev)
331 {
332 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
333
334 return lg->soc->nfunctions;
335 }
336
337 static const char *lp_get_function_name(struct pinctrl_dev *pctldev,
338 unsigned int selector)
339 {
340 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
341
342 return lg->soc->functions[selector].name;
343 }
344
345 static int lp_get_function_groups(struct pinctrl_dev *pctldev,
346 unsigned int selector,
347 const char * const **groups,
348 unsigned int *num_groups)
349 {
350 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
351
352 *groups = lg->soc->functions[selector].groups;
353 *num_groups = lg->soc->functions[selector].ngroups;
354
355 return 0;
356 }
357
358 static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
359 unsigned int function, unsigned int group)
360 {
361 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
362 const struct intel_pingroup *grp = &lg->soc->groups[group];
363 unsigned long flags;
364 int i;
365
366 raw_spin_lock_irqsave(&lg->lock, flags);
367
368 /* Now enable the mux setting for each pin in the group */
369 for (i = 0; i < grp->npins; i++) {
370 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1);
371 u32 value;
372
373 value = ioread32(reg);
374
375 value &= ~USE_SEL_MASK;
376 if (grp->modes)
377 value |= grp->modes[i];
378 else
379 value |= grp->mode;
380
381 iowrite32(value, reg);
382 }
383
384 raw_spin_unlock_irqrestore(&lg->lock, flags);
385
386 return 0;
387 }
388
389 static void lp_gpio_enable_input(void __iomem *reg)
390 {
391 iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg);
392 }
393
394 static void lp_gpio_disable_input(void __iomem *reg)
395 {
396 iowrite32(ioread32(reg) | GPINDIS_BIT, reg);
397 }
398
399 static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
400 struct pinctrl_gpio_range *range,
401 unsigned int pin)
402 {
403 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
404 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
405 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
406 unsigned long flags;
407 u32 value;
408
409 pm_runtime_get(lg->dev);
410
411 raw_spin_lock_irqsave(&lg->lock, flags);
412
413 /*
414 * Reconfigure pin to GPIO mode if needed and issue a warning,
415 * since we expect firmware to configure it properly.
416 */
417 value = ioread32(reg);
418 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) {
419 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg);
420 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin);
421 }
422
423 /* Enable input sensing */
424 lp_gpio_enable_input(conf2);
425
426 raw_spin_unlock_irqrestore(&lg->lock, flags);
427
428 return 0;
429 }
430
431 static void lp_gpio_disable_free(struct pinctrl_dev *pctldev,
432 struct pinctrl_gpio_range *range,
433 unsigned int pin)
434 {
435 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
436 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
437 unsigned long flags;
438
439 raw_spin_lock_irqsave(&lg->lock, flags);
440
441 /* Disable input sensing */
442 lp_gpio_disable_input(conf2);
443
444 raw_spin_unlock_irqrestore(&lg->lock, flags);
445
446 pm_runtime_put(lg->dev);
447 }
448
449 static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
450 struct pinctrl_gpio_range *range,
451 unsigned int pin, bool input)
452 {
453 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
454 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
455 unsigned long flags;
456 u32 value;
457
458 raw_spin_lock_irqsave(&lg->lock, flags);
459
460 value = ioread32(reg);
461 value &= ~DIR_BIT;
462 if (input) {
463 value |= DIR_BIT;
464 } else {
465 /*
466 * Before making any direction modifications, do a check if GPIO
467 * is set for direct IRQ. On Lynxpoint, setting GPIO to output
468 * does not make sense, so let's at least warn the caller before
469 * they shoot themselves in the foot.
470 */
471 WARN(lp_gpio_ioxapic_use(&lg->chip, pin),
472 "Potential Error: Setting GPIO to output with IOxAPIC redirection");
473 }
474 iowrite32(value, reg);
475
476 raw_spin_unlock_irqrestore(&lg->lock, flags);
477
478 return 0;
479 }
480
481 static const struct pinmux_ops lptlp_pinmux_ops = {
482 .get_functions_count = lp_get_functions_count,
483 .get_function_name = lp_get_function_name,
484 .get_function_groups = lp_get_function_groups,
485 .set_mux = lp_pinmux_set_mux,
486 .gpio_request_enable = lp_gpio_request_enable,
487 .gpio_disable_free = lp_gpio_disable_free,
488 .gpio_set_direction = lp_gpio_set_direction,
489 };
490
491 static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
492 unsigned long *config)
493 {
494 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
495 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
496 enum pin_config_param param = pinconf_to_config_param(*config);
497 unsigned long flags;
498 u32 value, pull;
499 u16 arg;
500
501 raw_spin_lock_irqsave(&lg->lock, flags);
502 value = ioread32(conf2);
503 raw_spin_unlock_irqrestore(&lg->lock, flags);
504
505 pull = value & GPIWP_MASK;
506
507 switch (param) {
508 case PIN_CONFIG_BIAS_DISABLE:
509 if (pull != GPIWP_NONE)
510 return -EINVAL;
511 arg = 0;
512 break;
513 case PIN_CONFIG_BIAS_PULL_DOWN:
514 if (pull != GPIWP_DOWN)
515 return -EINVAL;
516
517 arg = 1;
518 break;
519 case PIN_CONFIG_BIAS_PULL_UP:
520 if (pull != GPIWP_UP)
521 return -EINVAL;
522
523 arg = 1;
524 break;
525 default:
526 return -ENOTSUPP;
527 }
528
529 *config = pinconf_to_config_packed(param, arg);
530
531 return 0;
532 }
533
534 static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
535 unsigned long *configs, unsigned int num_configs)
536 {
537 struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
538 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
539 enum pin_config_param param;
540 unsigned long flags;
541 int i, ret = 0;
542 u32 value;
543
544 raw_spin_lock_irqsave(&lg->lock, flags);
545
546 value = ioread32(conf2);
547
548 for (i = 0; i < num_configs; i++) {
549 param = pinconf_to_config_param(configs[i]);
550
551 switch (param) {
552 case PIN_CONFIG_BIAS_DISABLE:
553 value &= ~GPIWP_MASK;
554 value |= GPIWP_NONE;
555 break;
556 case PIN_CONFIG_BIAS_PULL_DOWN:
557 value &= ~GPIWP_MASK;
558 value |= GPIWP_DOWN;
559 break;
560 case PIN_CONFIG_BIAS_PULL_UP:
561 value &= ~GPIWP_MASK;
562 value |= GPIWP_UP;
563 break;
564 default:
565 ret = -ENOTSUPP;
566 }
567
568 if (ret)
569 break;
570 }
571
572 if (!ret)
573 iowrite32(value, conf2);
574
575 raw_spin_unlock_irqrestore(&lg->lock, flags);
576
577 return ret;
578 }
579
580 static const struct pinconf_ops lptlp_pinconf_ops = {
581 .is_generic = true,
582 .pin_config_get = lp_pin_config_get,
583 .pin_config_set = lp_pin_config_set,
584 };
585
586 static const struct pinctrl_desc lptlp_pinctrl_desc = {
587 .pctlops = &lptlp_pinctrl_ops,
588 .pmxops = &lptlp_pinmux_ops,
589 .confops = &lptlp_pinconf_ops,
590 .owner = THIS_MODULE,
591 };
592
593 static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset)
594 {
595 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
596 return !!(ioread32(reg) & IN_LVL_BIT);
597 }
598
599 static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
600 {
601 struct intel_pinctrl *lg = gpiochip_get_data(chip);
602 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
603 unsigned long flags;
604
605 raw_spin_lock_irqsave(&lg->lock, flags);
606
607 if (value)
608 iowrite32(ioread32(reg) | OUT_LVL_BIT, reg);
609 else
610 iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg);
611
612 raw_spin_unlock_irqrestore(&lg->lock, flags);
613 }
614
615 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
616 {
617 return pinctrl_gpio_direction_input(chip->base + offset);
618 }
619
620 static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
621 int value)
622 {
623 lp_gpio_set(chip, offset, value);
624
625 return pinctrl_gpio_direction_output(chip->base + offset);
626 }
627
628 static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
629 {
630 void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
631
632 if (ioread32(reg) & DIR_BIT)
633 return GPIO_LINE_DIRECTION_IN;
634
635 return GPIO_LINE_DIRECTION_OUT;
636 }
637
638 static void lp_gpio_irq_handler(struct irq_desc *desc)
639 {
640 struct irq_data *data = irq_desc_get_irq_data(desc);
641 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
642 struct intel_pinctrl *lg = gpiochip_get_data(gc);
643 struct irq_chip *chip = irq_data_get_irq_chip(data);
644 void __iomem *reg, *ena;
645 unsigned long pending;
646 u32 base, pin;
647
648 /* check from GPIO controller which pin triggered the interrupt */
649 for (base = 0; base < lg->chip.ngpio; base += 32) {
650 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
651 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
652
653 /* Only interrupts that are enabled */
654 pending = ioread32(reg) & ioread32(ena);
655
656 for_each_set_bit(pin, &pending, 32) {
657 unsigned int irq;
658
659 irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
660 generic_handle_irq(irq);
661 }
662 }
663 chip->irq_eoi(data);
664 }
665
666 static void lp_irq_ack(struct irq_data *d)
667 {
668 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
669 struct intel_pinctrl *lg = gpiochip_get_data(gc);
670 u32 hwirq = irqd_to_hwirq(d);
671 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
672 unsigned long flags;
673
674 raw_spin_lock_irqsave(&lg->lock, flags);
675 iowrite32(BIT(hwirq % 32), reg);
676 raw_spin_unlock_irqrestore(&lg->lock, flags);
677 }
678
679 static void lp_irq_unmask(struct irq_data *d)
680 {
681 }
682
683 static void lp_irq_mask(struct irq_data *d)
684 {
685 }
686
687 static void lp_irq_enable(struct irq_data *d)
688 {
689 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
690 struct intel_pinctrl *lg = gpiochip_get_data(gc);
691 u32 hwirq = irqd_to_hwirq(d);
692 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
693 unsigned long flags;
694
695 raw_spin_lock_irqsave(&lg->lock, flags);
696 iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
697 raw_spin_unlock_irqrestore(&lg->lock, flags);
698 }
699
700 static void lp_irq_disable(struct irq_data *d)
701 {
702 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
703 struct intel_pinctrl *lg = gpiochip_get_data(gc);
704 u32 hwirq = irqd_to_hwirq(d);
705 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
706 unsigned long flags;
707
708 raw_spin_lock_irqsave(&lg->lock, flags);
709 iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
710 raw_spin_unlock_irqrestore(&lg->lock, flags);
711 }
712
713 static int lp_irq_set_type(struct irq_data *d, unsigned int type)
714 {
715 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
716 struct intel_pinctrl *lg = gpiochip_get_data(gc);
717 u32 hwirq = irqd_to_hwirq(d);
718 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
719 unsigned long flags;
720 u32 value;
721
722 if (hwirq >= lg->chip.ngpio)
723 return -EINVAL;
724
725 /* Fail if BIOS reserved pin for ACPI use */
726 if (lp_gpio_acpi_use(lg, hwirq)) {
727 dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq);
728 return -EBUSY;
729 }
730
731 raw_spin_lock_irqsave(&lg->lock, flags);
732 value = ioread32(reg);
733
734 /* set both TRIG_SEL and INV bits to 0 for rising edge */
735 if (type & IRQ_TYPE_EDGE_RISING)
736 value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
737
738 /* TRIG_SEL bit 0, INV bit 1 for falling edge */
739 if (type & IRQ_TYPE_EDGE_FALLING)
740 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
741
742 /* TRIG_SEL bit 1, INV bit 0 for level low */
743 if (type & IRQ_TYPE_LEVEL_LOW)
744 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
745
746 /* TRIG_SEL bit 1, INV bit 1 for level high */
747 if (type & IRQ_TYPE_LEVEL_HIGH)
748 value |= TRIG_SEL_BIT | INT_INV_BIT;
749
750 iowrite32(value, reg);
751
752 if (type & IRQ_TYPE_EDGE_BOTH)
753 irq_set_handler_locked(d, handle_edge_irq);
754 else if (type & IRQ_TYPE_LEVEL_MASK)
755 irq_set_handler_locked(d, handle_level_irq);
756
757 raw_spin_unlock_irqrestore(&lg->lock, flags);
758
759 return 0;
760 }
761
762 static struct irq_chip lp_irqchip = {
763 .name = "LP-GPIO",
764 .irq_ack = lp_irq_ack,
765 .irq_mask = lp_irq_mask,
766 .irq_unmask = lp_irq_unmask,
767 .irq_enable = lp_irq_enable,
768 .irq_disable = lp_irq_disable,
769 .irq_set_type = lp_irq_set_type,
770 .flags = IRQCHIP_SKIP_SET_WAKE,
771 };
772
773 static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
774 {
775 struct intel_pinctrl *lg = gpiochip_get_data(chip);
776 void __iomem *reg;
777 unsigned int base;
778
779 for (base = 0; base < lg->chip.ngpio; base += 32) {
780 /* disable gpio pin interrupts */
781 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
782 iowrite32(0, reg);
783 /* Clear interrupt status register */
784 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
785 iowrite32(0xffffffff, reg);
786 }
787
788 return 0;
789 }
790
791 static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
792 {
793 struct intel_pinctrl *lg = gpiochip_get_data(chip);
794 struct device *dev = lg->dev;
795 int ret;
796
797 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
798 if (ret)
799 dev_err(dev, "failed to add GPIO pin range\n");
800
801 return ret;
802 }
803
804 static int lp_gpio_probe(struct platform_device *pdev)
805 {
806 const struct intel_pinctrl_soc_data *soc;
807 struct intel_pinctrl *lg;
808 struct gpio_chip *gc;
809 struct device *dev = &pdev->dev;
810 struct resource *io_rc;
811 void __iomem *regs;
812 unsigned int i;
813 int irq, ret;
814
815 soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev);
816 if (!soc)
817 return -ENODEV;
818
819 lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL);
820 if (!lg)
821 return -ENOMEM;
822
823 lg->dev = dev;
824 lg->soc = soc;
825
826 lg->ncommunities = lg->soc->ncommunities;
827 lg->communities = devm_kcalloc(dev, lg->ncommunities,
828 sizeof(*lg->communities), GFP_KERNEL);
829 if (!lg->communities)
830 return -ENOMEM;
831
832 lg->pctldesc = lptlp_pinctrl_desc;
833 lg->pctldesc.name = dev_name(dev);
834 lg->pctldesc.pins = lg->soc->pins;
835 lg->pctldesc.npins = lg->soc->npins;
836
837 lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg);
838 if (IS_ERR(lg->pctldev)) {
839 dev_err(dev, "failed to register pinctrl driver\n");
840 return PTR_ERR(lg->pctldev);
841 }
842
843 platform_set_drvdata(pdev, lg);
844
845 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
846 if (!io_rc) {
847 dev_err(dev, "missing IO resources\n");
848 return -EINVAL;
849 }
850
851 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc));
852 if (!regs) {
853 dev_err(dev, "failed mapping IO region %pR\n", &io_rc);
854 return -EBUSY;
855 }
856
857 for (i = 0; i < lg->soc->ncommunities; i++) {
858 struct intel_community *comm = &lg->communities[i];
859
860 *comm = lg->soc->communities[i];
861
862 comm->regs = regs;
863 comm->pad_regs = regs + 0x100;
864 }
865
866 raw_spin_lock_init(&lg->lock);
867
868 gc = &lg->chip;
869 gc->label = dev_name(dev);
870 gc->owner = THIS_MODULE;
871 gc->request = gpiochip_generic_request;
872 gc->free = gpiochip_generic_free;
873 gc->direction_input = lp_gpio_direction_input;
874 gc->direction_output = lp_gpio_direction_output;
875 gc->get = lp_gpio_get;
876 gc->set = lp_gpio_set;
877 gc->set_config = gpiochip_generic_config;
878 gc->get_direction = lp_gpio_get_direction;
879 gc->base = -1;
880 gc->ngpio = LP_NUM_GPIO;
881 gc->can_sleep = false;
882 gc->add_pin_ranges = lp_gpio_add_pin_ranges;
883 gc->parent = dev;
884
885 /* set up interrupts */
886 irq = platform_get_irq_optional(pdev, 0);
887 if (irq > 0) {
888 struct gpio_irq_chip *girq;
889
890 girq = &gc->irq;
891 girq->chip = &lp_irqchip;
892 girq->init_hw = lp_gpio_irq_init_hw;
893 girq->parent_handler = lp_gpio_irq_handler;
894 girq->num_parents = 1;
895 girq->parents = devm_kcalloc(dev, girq->num_parents,
896 sizeof(*girq->parents),
897 GFP_KERNEL);
898 if (!girq->parents)
899 return -ENOMEM;
900 girq->parents[0] = irq;
901 girq->default_type = IRQ_TYPE_NONE;
902 girq->handler = handle_bad_irq;
903 }
904
905 ret = devm_gpiochip_add_data(dev, gc, lg);
906 if (ret) {
907 dev_err(dev, "failed adding lp-gpio chip\n");
908 return ret;
909 }
910
911 pm_runtime_enable(dev);
912
913 return 0;
914 }
915
916 static int lp_gpio_remove(struct platform_device *pdev)
917 {
918 pm_runtime_disable(&pdev->dev);
919 return 0;
920 }
921
922 static int lp_gpio_runtime_suspend(struct device *dev)
923 {
924 return 0;
925 }
926
927 static int lp_gpio_runtime_resume(struct device *dev)
928 {
929 return 0;
930 }
931
932 static int lp_gpio_resume(struct device *dev)
933 {
934 struct intel_pinctrl *lg = dev_get_drvdata(dev);
935 struct gpio_chip *chip = &lg->chip;
936 const char *dummy;
937 int i;
938
939 /* on some hardware suspend clears input sensing, re-enable it here */
940 for_each_requested_gpio(chip, i, dummy)
941 lp_gpio_enable_input(lp_gpio_reg(chip, i, LP_CONFIG2));
942
943 return 0;
944 }
945
946 static const struct dev_pm_ops lp_gpio_pm_ops = {
947 .runtime_suspend = lp_gpio_runtime_suspend,
948 .runtime_resume = lp_gpio_runtime_resume,
949 .resume = lp_gpio_resume,
950 };
951
952 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
953 { "INT33C7", (kernel_ulong_t)&lptlp_soc_data },
954 { "INT3437", (kernel_ulong_t)&lptlp_soc_data },
955 { }
956 };
957 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
958
959 static struct platform_driver lp_gpio_driver = {
960 .probe = lp_gpio_probe,
961 .remove = lp_gpio_remove,
962 .driver = {
963 .name = "lp_gpio",
964 .pm = &lp_gpio_pm_ops,
965 .acpi_match_table = lynxpoint_gpio_acpi_match,
966 },
967 };
968
969 static int __init lp_gpio_init(void)
970 {
971 return platform_driver_register(&lp_gpio_driver);
972 }
973 subsys_initcall(lp_gpio_init);
974
975 static void __exit lp_gpio_exit(void)
976 {
977 platform_driver_unregister(&lp_gpio_driver);
978 }
979 module_exit(lp_gpio_exit);
980
981 MODULE_AUTHOR("Mathias Nyman (Intel)");
982 MODULE_AUTHOR("Andy Shevchenko (Intel)");
983 MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver");
984 MODULE_LICENSE("GPL v2");
985 MODULE_ALIAS("platform:lp_gpio");
Linux with added FPC-III support