drivers/pinctrl/mediatek/pinctrl-mt2712.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
   5  *
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/pinctrl/pinctrl.h>
  13 #include <linux/regmap.h>
  14 #include <linux/pinctrl/pinconf-generic.h>
  15 #include <dt-bindings/pinctrl/mt65xx.h>
  16
  17 #include "pinctrl-mtk-common.h"
  18 #include "pinctrl-mtk-mt2712.h"
  19
  20 static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
  21         MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
  22         MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
  23         MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
  24         MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
  25         MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
  26         MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
  27
  28         MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
  29         MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
  30         MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
  31         MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
  32         MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
  33         MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
  34         MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
  35         MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
  36         MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
  37         MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
  38         MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
  39         MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
  40         MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
  41         MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
  42         MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
  43         MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
  44         MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
  45         MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
  46         MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
  47         MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
  48         MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
  49         MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
  50         MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
  51         MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
  52         MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
  53         MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
  54         MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
  55
  56         MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
  57         MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
  58         MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
  59         MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
  60         MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
  61         MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
  62         MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
  63         MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
  64
  65         MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
  66         MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
  67         MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
  68         MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
  69         MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
  70         MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
  71         MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
  72         MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
  73
  74         MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9),
  75         MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12),
  76         MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3),
  77         MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
  78         MTK_PIN_PUPD_SPEC_SR(139, 0xe70, 11, 10, 9),
  79         MTK_PIN_PUPD_SPEC_SR(140, 0xe70, 14, 13, 12),
  80         MTK_PIN_PUPD_SPEC_SR(141, 0xe60, 2, 1, 0),
  81         MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3)
  82 };
  83
  84 static int mt2712_spec_pull_set(struct regmap *regmap,
  85                                 unsigned int pin,
  86                                 unsigned char align,
  87                                 bool isup,
  88                                 unsigned int r1r0)
  89 {
  90         return mtk_pctrl_spec_pull_set_samereg(regmap, mt2712_spec_pupd,
  91                 ARRAY_SIZE(mt2712_spec_pupd), pin, align, isup, r1r0);
  92 }
  93
  94 static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
  95         MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
  96         MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0),
  97         MTK_PIN_IES_SMT_SPEC(8, 11, 0x900, 1),
  98         MTK_PIN_IES_SMT_SPEC(12, 12, 0x8d0, 6),
  99         MTK_PIN_IES_SMT_SPEC(13, 13, 0x8d0, 7),
 100         MTK_PIN_IES_SMT_SPEC(14, 14, 0x8d0, 6),
 101         MTK_PIN_IES_SMT_SPEC(15, 15, 0x8d0, 7),
 102         MTK_PIN_IES_SMT_SPEC(18, 23, 0x8d0, 1),
 103         MTK_PIN_IES_SMT_SPEC(24, 25, 0x8d0, 2),
 104         MTK_PIN_IES_SMT_SPEC(26, 26, 0x8d0, 3),
 105         MTK_PIN_IES_SMT_SPEC(27, 27, 0x8d0, 4),
 106         MTK_PIN_IES_SMT_SPEC(28, 29, 0x8d0, 3),
 107         MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 13),
 108         MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 13),
 109         MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 13),
 110         MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 13),
 111         MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 13),
 112         MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 13),
 113         MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 13),
 114         MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 13),
 115         MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 13),
 116         MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 13),
 117         MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 13),
 118         MTK_PIN_IES_SMT_SPEC(57, 62, 0x900, 3),
 119         MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 13),
 120         MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 13),
 121         MTK_PIN_IES_SMT_SPEC(67, 67, 0xc80, 13),
 122         MTK_PIN_IES_SMT_SPEC(68, 68, 0xca0, 13),
 123         MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 13),
 124         MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 13),
 125         MTK_PIN_IES_SMT_SPEC(71, 74, 0x8d0, 8),
 126         MTK_PIN_IES_SMT_SPEC(75, 77, 0x8d0, 9),
 127         MTK_PIN_IES_SMT_SPEC(78, 81, 0x8d0, 10),
 128         MTK_PIN_IES_SMT_SPEC(82, 88, 0x8d0, 9),
 129         MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 13),
 130         MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 13),
 131         MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 13),
 132         MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 13),
 133         MTK_PIN_IES_SMT_SPEC(97, 100, 0x8d0, 11),
 134         MTK_PIN_IES_SMT_SPEC(101, 104, 0x8d0, 12),
 135         MTK_PIN_IES_SMT_SPEC(105, 105, 0x8d0, 13),
 136         MTK_PIN_IES_SMT_SPEC(106, 106, 0x8d0, 14),
 137         MTK_PIN_IES_SMT_SPEC(107, 107, 0x8d0, 15),
 138         MTK_PIN_IES_SMT_SPEC(108, 108, 0x8e0, 0),
 139         MTK_PIN_IES_SMT_SPEC(109, 109, 0x8e0, 1),
 140         MTK_PIN_IES_SMT_SPEC(110, 110, 0x8e0, 2),
 141         MTK_PIN_IES_SMT_SPEC(111, 111, 0x8d0, 13),
 142         MTK_PIN_IES_SMT_SPEC(112, 112, 0x8d0, 14),
 143         MTK_PIN_IES_SMT_SPEC(113, 113, 0x8d0, 15),
 144         MTK_PIN_IES_SMT_SPEC(114, 114, 0x8e0, 0),
 145         MTK_PIN_IES_SMT_SPEC(115, 115, 0x8e0, 1),
 146         MTK_PIN_IES_SMT_SPEC(116, 116, 0x8e0, 2),
 147         MTK_PIN_IES_SMT_SPEC(117, 117, 0x8e0, 3),
 148         MTK_PIN_IES_SMT_SPEC(118, 118, 0x8e0, 4),
 149         MTK_PIN_IES_SMT_SPEC(119, 119, 0x8e0, 5),
 150         MTK_PIN_IES_SMT_SPEC(120, 120, 0x8e0, 3),
 151         MTK_PIN_IES_SMT_SPEC(121, 121, 0x8e0, 4),
 152         MTK_PIN_IES_SMT_SPEC(122, 122, 0x8e0, 5),
 153         MTK_PIN_IES_SMT_SPEC(123, 126, 0x8e0, 6),
 154         MTK_PIN_IES_SMT_SPEC(127, 130, 0x8e0, 7),
 155         MTK_PIN_IES_SMT_SPEC(131, 134, 0x8e0, 8),
 156         MTK_PIN_IES_SMT_SPEC(135, 142, 0x8d0, 1),
 157         MTK_PIN_IES_SMT_SPEC(143, 147, 0x8e0, 9),
 158         MTK_PIN_IES_SMT_SPEC(148, 152, 0x8e0, 10),
 159         MTK_PIN_IES_SMT_SPEC(153, 156, 0x8e0, 11),
 160         MTK_PIN_IES_SMT_SPEC(157, 160, 0x8e0, 12),
 161         MTK_PIN_IES_SMT_SPEC(161, 164, 0x8e0, 13),
 162         MTK_PIN_IES_SMT_SPEC(165, 168, 0x8e0, 14),
 163         MTK_PIN_IES_SMT_SPEC(169, 170, 0x8e0, 15),
 164         MTK_PIN_IES_SMT_SPEC(171, 172, 0x8f0, 0),
 165         MTK_PIN_IES_SMT_SPEC(173, 173, 0x8f0, 1),
 166         MTK_PIN_IES_SMT_SPEC(174, 175, 0x8f0, 2),
 167         MTK_PIN_IES_SMT_SPEC(176, 176, 0x8f0, 1),
 168         MTK_PIN_IES_SMT_SPEC(177, 177, 0x8f0, 3),
 169         MTK_PIN_IES_SMT_SPEC(178, 178, 0x8f0, 4),
 170         MTK_PIN_IES_SMT_SPEC(179, 179, 0x8f0, 3),
 171         MTK_PIN_IES_SMT_SPEC(180, 180, 0x8f0, 4),
 172         MTK_PIN_IES_SMT_SPEC(181, 181, 0x8f0, 5),
 173         MTK_PIN_IES_SMT_SPEC(182, 182, 0x8f0, 6),
 174         MTK_PIN_IES_SMT_SPEC(183, 183, 0x8f0, 5),
 175         MTK_PIN_IES_SMT_SPEC(184, 184, 0x8f0, 6),
 176         MTK_PIN_IES_SMT_SPEC(185, 186, 0x8f0, 7),
 177         MTK_PIN_IES_SMT_SPEC(187, 187, 0x8f0, 8),
 178         MTK_PIN_IES_SMT_SPEC(188, 188, 0x8f0, 9),
 179         MTK_PIN_IES_SMT_SPEC(189, 189, 0x8f0, 8),
 180         MTK_PIN_IES_SMT_SPEC(190, 190, 0x8f0, 9),
 181         MTK_PIN_IES_SMT_SPEC(191, 191, 0x8f0, 10),
 182         MTK_PIN_IES_SMT_SPEC(192, 192, 0x8f0, 11),
 183         MTK_PIN_IES_SMT_SPEC(193, 194, 0x8f0, 10),
 184         MTK_PIN_IES_SMT_SPEC(195, 195, 0x8f0, 11),
 185         MTK_PIN_IES_SMT_SPEC(196, 199, 0x8f0, 12),
 186         MTK_PIN_IES_SMT_SPEC(200, 203, 0x8f0, 13),
 187         MTK_PIN_IES_SMT_SPEC(204, 206, 0x8f0, 14),
 188         MTK_PIN_IES_SMT_SPEC(207, 209, 0x8f0, 15)
 189 };
 190
 191 static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = {
 192         MTK_PIN_IES_SMT_SPEC(0, 3, 0x8c0, 2),
 193         MTK_PIN_IES_SMT_SPEC(4, 7, 0x8c0, 0),
 194         MTK_PIN_IES_SMT_SPEC(8, 9, 0x8c0, 1),
 195         MTK_PIN_IES_SMT_SPEC(10, 11, 0x8c0, 4),
 196         MTK_PIN_IES_SMT_SPEC(12, 12, 0x890, 6),
 197         MTK_PIN_IES_SMT_SPEC(13, 13, 0x890, 7),
 198         MTK_PIN_IES_SMT_SPEC(14, 14, 0x890, 6),
 199         MTK_PIN_IES_SMT_SPEC(15, 15, 0x890, 7),
 200         MTK_PIN_IES_SMT_SPEC(18, 23, 0x890, 1),
 201         MTK_PIN_IES_SMT_SPEC(24, 25, 0x890, 2),
 202         MTK_PIN_IES_SMT_SPEC(26, 26, 0x890, 3),
 203         MTK_PIN_IES_SMT_SPEC(27, 27, 0x890, 4),
 204         MTK_PIN_IES_SMT_SPEC(28, 29, 0x890, 3),
 205         MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 14),
 206         MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 14),
 207         MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 14),
 208         MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 14),
 209         MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 14),
 210         MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 14),
 211         MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 14),
 212         MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 14),
 213         MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 14),
 214         MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 14),
 215         MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 14),
 216         MTK_PIN_IES_SMT_SPEC(57, 62, 0x8c0, 3),
 217         MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 14),
 218         MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 14),
 219         MTK_PIN_IES_SMT_SPEC(67, 68, 0xc80, 14),
 220         MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 14),
 221         MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 14),
 222         MTK_PIN_IES_SMT_SPEC(71, 74, 0x890, 8),
 223         MTK_PIN_IES_SMT_SPEC(75, 77, 0x890, 9),
 224         MTK_PIN_IES_SMT_SPEC(78, 81, 0x890, 10),
 225         MTK_PIN_IES_SMT_SPEC(82, 88, 0x890, 9),
 226         MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 14),
 227         MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 14),
 228         MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 14),
 229         MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 14),
 230         MTK_PIN_IES_SMT_SPEC(97, 100, 0x890, 11),
 231         MTK_PIN_IES_SMT_SPEC(101, 104, 0x890, 12),
 232         MTK_PIN_IES_SMT_SPEC(105, 105, 0x890, 13),
 233         MTK_PIN_IES_SMT_SPEC(106, 106, 0x890, 14),
 234         MTK_PIN_IES_SMT_SPEC(107, 107, 0x890, 15),
 235         MTK_PIN_IES_SMT_SPEC(108, 108, 0x8a0, 0),
 236         MTK_PIN_IES_SMT_SPEC(109, 109, 0x8a0, 1),
 237         MTK_PIN_IES_SMT_SPEC(110, 110, 0x8a0, 2),
 238         MTK_PIN_IES_SMT_SPEC(111, 111, 0x890, 13),
 239         MTK_PIN_IES_SMT_SPEC(112, 112, 0x890, 14),
 240         MTK_PIN_IES_SMT_SPEC(113, 113, 0x890, 15),
 241         MTK_PIN_IES_SMT_SPEC(114, 114, 0x8a0, 0),
 242         MTK_PIN_IES_SMT_SPEC(115, 115, 0x8a0, 1),
 243         MTK_PIN_IES_SMT_SPEC(116, 116, 0x8a0, 2),
 244         MTK_PIN_IES_SMT_SPEC(117, 117, 0x8a0, 3),
 245         MTK_PIN_IES_SMT_SPEC(118, 118, 0x8a0, 4),
 246         MTK_PIN_IES_SMT_SPEC(119, 119, 0x8a0, 5),
 247         MTK_PIN_IES_SMT_SPEC(120, 120, 0x8a0, 3),
 248         MTK_PIN_IES_SMT_SPEC(121, 121, 0x8a0, 4),
 249         MTK_PIN_IES_SMT_SPEC(122, 122, 0x8a0, 5),
 250         MTK_PIN_IES_SMT_SPEC(123, 126, 0x8a0, 6),
 251         MTK_PIN_IES_SMT_SPEC(127, 130, 0x8a0, 7),
 252         MTK_PIN_IES_SMT_SPEC(131, 135, 0x8a0, 8),
 253         MTK_PIN_IES_SMT_SPEC(136, 142, 0x890, 1),
 254         MTK_PIN_IES_SMT_SPEC(143, 147, 0x8a0, 9),
 255         MTK_PIN_IES_SMT_SPEC(148, 152, 0x8a0, 10),
 256         MTK_PIN_IES_SMT_SPEC(153, 156, 0x8a0, 11),
 257         MTK_PIN_IES_SMT_SPEC(157, 160, 0x8a0, 12),
 258         MTK_PIN_IES_SMT_SPEC(161, 164, 0x8a0, 13),
 259         MTK_PIN_IES_SMT_SPEC(165, 168, 0x8a0, 14),
 260         MTK_PIN_IES_SMT_SPEC(169, 170, 0x8a0, 15),
 261         MTK_PIN_IES_SMT_SPEC(171, 172, 0x8b0, 0),
 262         MTK_PIN_IES_SMT_SPEC(173, 173, 0x8b0, 1),
 263         MTK_PIN_IES_SMT_SPEC(174, 175, 0x8b0, 2),
 264         MTK_PIN_IES_SMT_SPEC(176, 176, 0x8b0, 1),
 265         MTK_PIN_IES_SMT_SPEC(177, 177, 0x8b0, 3),
 266         MTK_PIN_IES_SMT_SPEC(178, 178, 0x8b0, 4),
 267         MTK_PIN_IES_SMT_SPEC(179, 179, 0x8b0, 3),
 268         MTK_PIN_IES_SMT_SPEC(180, 180, 0x8b0, 4),
 269         MTK_PIN_IES_SMT_SPEC(181, 181, 0x8b0, 5),
 270         MTK_PIN_IES_SMT_SPEC(182, 182, 0x8b0, 6),
 271         MTK_PIN_IES_SMT_SPEC(183, 183, 0x8b0, 5),
 272         MTK_PIN_IES_SMT_SPEC(184, 184, 0x8b0, 6),
 273         MTK_PIN_IES_SMT_SPEC(185, 186, 0x8b0, 7),
 274         MTK_PIN_IES_SMT_SPEC(187, 187, 0x8b0, 8),
 275         MTK_PIN_IES_SMT_SPEC(188, 188, 0x8b0, 9),
 276         MTK_PIN_IES_SMT_SPEC(189, 189, 0x8b0, 8),
 277         MTK_PIN_IES_SMT_SPEC(190, 190, 0x8b0, 9),
 278         MTK_PIN_IES_SMT_SPEC(191, 191, 0x8b0, 10),
 279         MTK_PIN_IES_SMT_SPEC(192, 192, 0x8b0, 11),
 280         MTK_PIN_IES_SMT_SPEC(193, 194, 0x8b0, 10),
 281         MTK_PIN_IES_SMT_SPEC(195, 195, 0x8b0, 11),
 282         MTK_PIN_IES_SMT_SPEC(196, 199, 0x8b0, 12),
 283         MTK_PIN_IES_SMT_SPEC(200, 203, 0x8b0, 13),
 284         MTK_PIN_IES_SMT_SPEC(204, 206, 0x8b0, 14),
 285         MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15)
 286 };
 287
 288 static int mt2712_ies_smt_set(struct regmap *regmap, unsigned int pin,
 289                               unsigned char align,
 290                               int value, enum pin_config_param arg)
 291 {
 292         if (arg == PIN_CONFIG_INPUT_ENABLE)
 293                 return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_ies_set,
 294                         ARRAY_SIZE(mt2712_ies_set), pin, align, value);
 295         if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
 296                 return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_smt_set,
 297                         ARRAY_SIZE(mt2712_smt_set), pin, align, value);
 298         return -EINVAL;
 299 }
 300
 301 static const struct mtk_drv_group_desc mt2712_drv_grp[] =  {
 302         /* 0E4E8SR 4/8/12/16 */
 303         MTK_DRV_GRP(4, 16, 1, 2, 4),
 304         /* 0E2E4SR  2/4/6/8 */
 305         MTK_DRV_GRP(2, 8, 1, 2, 2),
 306         /* E8E4E2  2/4/6/8/10/12/14/16 */
 307         MTK_DRV_GRP(2, 16, 0, 2, 2)
 308 };
 309
 310 static const struct mtk_pin_drv_grp mt2712_pin_drv[] = {
 311         MTK_PIN_DRV_GRP(0, 0xc10, 4, 0),
 312         MTK_PIN_DRV_GRP(1, 0xc10, 4, 0),
 313         MTK_PIN_DRV_GRP(2, 0xc10, 4, 0),
 314         MTK_PIN_DRV_GRP(3, 0xc10, 4, 0),
 315
 316         MTK_PIN_DRV_GRP(4, 0xc00, 12, 0),
 317         MTK_PIN_DRV_GRP(5, 0xc00, 12, 0),
 318         MTK_PIN_DRV_GRP(6, 0xc00, 12, 0),
 319         MTK_PIN_DRV_GRP(7, 0xc00, 12, 0),
 320
 321         MTK_PIN_DRV_GRP(8, 0xc10, 0, 0),
 322         MTK_PIN_DRV_GRP(9, 0xc10, 0, 0),
 323         MTK_PIN_DRV_GRP(10, 0xc10, 0, 0),
 324         MTK_PIN_DRV_GRP(11, 0xc10, 0, 0),
 325
 326         MTK_PIN_DRV_GRP(12, 0xb60, 0, 0),
 327
 328         MTK_PIN_DRV_GRP(13, 0xb60, 4, 0),
 329
 330         MTK_PIN_DRV_GRP(14, 0xb60, 0, 0),
 331
 332         MTK_PIN_DRV_GRP(15, 0xb60, 4, 0),
 333
 334         MTK_PIN_DRV_GRP(18, 0xb40, 0, 1),
 335         MTK_PIN_DRV_GRP(19, 0xb40, 0, 1),
 336         MTK_PIN_DRV_GRP(20, 0xb40, 0, 1),
 337         MTK_PIN_DRV_GRP(21, 0xb40, 0, 1),
 338         MTK_PIN_DRV_GRP(22, 0xb40, 0, 1),
 339         MTK_PIN_DRV_GRP(23, 0xb40, 0, 1),
 340
 341         MTK_PIN_DRV_GRP(24, 0xb40, 4, 0),
 342
 343         MTK_PIN_DRV_GRP(25, 0xb40, 8, 0),
 344
 345         MTK_PIN_DRV_GRP(26, 0xb40, 12, 0),
 346
 347         MTK_PIN_DRV_GRP(27, 0xb50, 0, 0),
 348
 349         MTK_PIN_DRV_GRP(28, 0xb40, 12, 0),
 350         MTK_PIN_DRV_GRP(29, 0xb40, 12, 0),
 351
 352         MTK_PIN_DRV_GRP(30, 0xf50, 8, 2),
 353         MTK_PIN_DRV_GRP(31, 0xf50, 8, 2),
 354         MTK_PIN_DRV_GRP(32, 0xf50, 8, 2),
 355         MTK_PIN_DRV_GRP(33, 0xf50, 8, 2),
 356         MTK_PIN_DRV_GRP(34, 0xf50, 8, 2),
 357         MTK_PIN_DRV_GRP(35, 0xf50, 8, 2),
 358         MTK_PIN_DRV_GRP(36, 0xf50, 8, 2),
 359
 360         MTK_PIN_DRV_GRP(37, 0xc40, 8, 2),
 361
 362         MTK_PIN_DRV_GRP(38, 0xc60, 8, 2),
 363         MTK_PIN_DRV_GRP(39, 0xc60, 8, 2),
 364         MTK_PIN_DRV_GRP(40, 0xc60, 8, 2),
 365         MTK_PIN_DRV_GRP(41, 0xc60, 8, 2),
 366         MTK_PIN_DRV_GRP(42, 0xc60, 8, 2),
 367         MTK_PIN_DRV_GRP(43, 0xc60, 8, 2),
 368         MTK_PIN_DRV_GRP(44, 0xc60, 8, 2),
 369         MTK_PIN_DRV_GRP(45, 0xc60, 8, 2),
 370
 371         MTK_PIN_DRV_GRP(46, 0xc50, 8, 2),
 372
 373         MTK_PIN_DRV_GRP(47, 0xda0, 8, 2),
 374
 375         MTK_PIN_DRV_GRP(48, 0xd90, 8, 2),
 376
 377         MTK_PIN_DRV_GRP(49, 0xd60, 8, 2),
 378         MTK_PIN_DRV_GRP(50, 0xd60, 8, 2),
 379         MTK_PIN_DRV_GRP(51, 0xd60, 8, 2),
 380         MTK_PIN_DRV_GRP(52, 0xd60, 8, 2),
 381
 382         MTK_PIN_DRV_GRP(53, 0xd50, 8, 2),
 383
 384         MTK_PIN_DRV_GRP(54, 0xd80, 8, 2),
 385
 386         MTK_PIN_DRV_GRP(55, 0xe00, 8, 2),
 387
 388         MTK_PIN_DRV_GRP(56, 0xd40, 8, 2),
 389
 390         MTK_PIN_DRV_GRP(63, 0xc80, 8, 2),
 391
 392         MTK_PIN_DRV_GRP(64, 0xca0, 8, 2),
 393         MTK_PIN_DRV_GRP(65, 0xca0, 8, 2),
 394         MTK_PIN_DRV_GRP(66, 0xca0, 8, 2),
 395
 396         MTK_PIN_DRV_GRP(67, 0xcd0, 8, 2),
 397
 398         MTK_PIN_DRV_GRP(68, 0xca0, 8, 2),
 399
 400         MTK_PIN_DRV_GRP(69, 0xc90, 8, 2),
 401
 402         MTK_PIN_DRV_GRP(70, 0xcc0, 8, 2),
 403
 404         MTK_PIN_DRV_GRP(71, 0xb60, 8, 1),
 405         MTK_PIN_DRV_GRP(72, 0xb60, 8, 1),
 406         MTK_PIN_DRV_GRP(73, 0xb60, 8, 1),
 407         MTK_PIN_DRV_GRP(74, 0xb60, 8, 1),
 408
 409         MTK_PIN_DRV_GRP(75, 0xb60, 12, 1),
 410         MTK_PIN_DRV_GRP(76, 0xb60, 12, 1),
 411         MTK_PIN_DRV_GRP(77, 0xb60, 12, 1),
 412
 413         MTK_PIN_DRV_GRP(78, 0xb70, 0, 1),
 414         MTK_PIN_DRV_GRP(79, 0xb70, 0, 1),
 415         MTK_PIN_DRV_GRP(80, 0xb70, 0, 1),
 416         MTK_PIN_DRV_GRP(81, 0xb70, 0, 1),
 417
 418         MTK_PIN_DRV_GRP(82, 0xb60, 12, 1),
 419         MTK_PIN_DRV_GRP(83, 0xb60, 12, 1),
 420         MTK_PIN_DRV_GRP(84, 0xb60, 12, 1),
 421         MTK_PIN_DRV_GRP(85, 0xb60, 12, 1),
 422         MTK_PIN_DRV_GRP(86, 0xb60, 12, 1),
 423         MTK_PIN_DRV_GRP(87, 0xb60, 12, 1),
 424         MTK_PIN_DRV_GRP(88, 0xb60, 12, 1),
 425
 426         MTK_PIN_DRV_GRP(89, 0xce0, 8, 2),
 427
 428         MTK_PIN_DRV_GRP(90, 0xd00, 8, 2),
 429         MTK_PIN_DRV_GRP(91, 0xd00, 8, 2),
 430         MTK_PIN_DRV_GRP(92, 0xd00, 8, 2),
 431         MTK_PIN_DRV_GRP(93, 0xd00, 8, 2),
 432
 433         MTK_PIN_DRV_GRP(94, 0xd20, 8, 2),
 434
 435         MTK_PIN_DRV_GRP(95, 0xcf0, 8, 2),
 436
 437         MTK_PIN_DRV_GRP(96, 0xd30, 8, 2),
 438
 439         MTK_PIN_DRV_GRP(97, 0xb70, 4, 0),
 440         MTK_PIN_DRV_GRP(98, 0xb70, 4, 0),
 441         MTK_PIN_DRV_GRP(99, 0xb70, 4, 0),
 442         MTK_PIN_DRV_GRP(100, 0xb70, 4, 0),
 443
 444         MTK_PIN_DRV_GRP(101, 0xb70, 8, 0),
 445         MTK_PIN_DRV_GRP(102, 0xb70, 8, 0),
 446         MTK_PIN_DRV_GRP(103, 0xb70, 8, 0),
 447         MTK_PIN_DRV_GRP(104, 0xb70, 8, 0),
 448
 449         MTK_PIN_DRV_GRP(135, 0xb40, 0, 1),
 450         MTK_PIN_DRV_GRP(136, 0xb40, 0, 1),
 451         MTK_PIN_DRV_GRP(137, 0xb40, 0, 1),
 452         MTK_PIN_DRV_GRP(138, 0xb40, 0, 1),
 453         MTK_PIN_DRV_GRP(139, 0xb40, 0, 1),
 454         MTK_PIN_DRV_GRP(140, 0xb40, 0, 1),
 455         MTK_PIN_DRV_GRP(141, 0xb40, 0, 1),
 456         MTK_PIN_DRV_GRP(142, 0xb40, 0, 1),
 457
 458         MTK_PIN_DRV_GRP(143, 0xba0, 12, 0),
 459         MTK_PIN_DRV_GRP(144, 0xba0, 12, 0),
 460         MTK_PIN_DRV_GRP(145, 0xba0, 12, 0),
 461         MTK_PIN_DRV_GRP(146, 0xba0, 12, 0),
 462         MTK_PIN_DRV_GRP(147, 0xba0, 12, 0),
 463
 464         MTK_PIN_DRV_GRP(148, 0xbb0, 0, 0),
 465         MTK_PIN_DRV_GRP(149, 0xbb0, 0, 0),
 466         MTK_PIN_DRV_GRP(150, 0xbb0, 0, 0),
 467         MTK_PIN_DRV_GRP(151, 0xbb0, 0, 0),
 468         MTK_PIN_DRV_GRP(152, 0xbb0, 0, 0),
 469
 470         MTK_PIN_DRV_GRP(153, 0xbb0, 4, 0),
 471         MTK_PIN_DRV_GRP(154, 0xbb0, 4, 0),
 472         MTK_PIN_DRV_GRP(155, 0xbb0, 4, 0),
 473         MTK_PIN_DRV_GRP(156, 0xbb0, 4, 0),
 474
 475         MTK_PIN_DRV_GRP(157, 0xbb0, 8, 0),
 476         MTK_PIN_DRV_GRP(158, 0xbb0, 8, 0),
 477         MTK_PIN_DRV_GRP(159, 0xbb0, 8, 0),
 478         MTK_PIN_DRV_GRP(160, 0xbb0, 8, 0),
 479
 480         MTK_PIN_DRV_GRP(161, 0xbb0, 12, 0),
 481         MTK_PIN_DRV_GRP(162, 0xbb0, 12, 0),
 482         MTK_PIN_DRV_GRP(163, 0xbb0, 12, 0),
 483         MTK_PIN_DRV_GRP(164, 0xbb0, 12, 0),
 484
 485         MTK_PIN_DRV_GRP(165, 0xbc0, 0, 0),
 486         MTK_PIN_DRV_GRP(166, 0xbc0, 0, 0),
 487         MTK_PIN_DRV_GRP(167, 0xbc0, 0, 0),
 488         MTK_PIN_DRV_GRP(168, 0xbc0, 0, 0),
 489
 490         MTK_PIN_DRV_GRP(169, 0xbc0, 4, 0),
 491         MTK_PIN_DRV_GRP(170, 0xbc0, 4, 0),
 492
 493         MTK_PIN_DRV_GRP(171, 0xbc0, 8, 0),
 494         MTK_PIN_DRV_GRP(172, 0xbc0, 8, 0),
 495
 496         MTK_PIN_DRV_GRP(173, 0xbc0, 12, 0),
 497
 498         MTK_PIN_DRV_GRP(174, 0xbd0, 0, 0),
 499         MTK_PIN_DRV_GRP(175, 0xbd0, 0, 0),
 500
 501         MTK_PIN_DRV_GRP(176, 0xbc0, 12, 0),
 502
 503         MTK_PIN_DRV_GRP(177, 0xbd0, 4, 0),
 504
 505         MTK_PIN_DRV_GRP(178, 0xbd0, 8, 0),
 506
 507         MTK_PIN_DRV_GRP(179, 0xbd0, 4, 0),
 508
 509         MTK_PIN_DRV_GRP(180, 0xbd0, 8, 0),
 510
 511         MTK_PIN_DRV_GRP(181, 0xbd0, 12, 0),
 512
 513         MTK_PIN_DRV_GRP(182, 0xbe0, 0, 0),
 514
 515         MTK_PIN_DRV_GRP(183, 0xbd0, 12, 0),
 516
 517         MTK_PIN_DRV_GRP(184, 0xbe0, 0, 0),
 518
 519         MTK_PIN_DRV_GRP(185, 0xbe0, 4, 0),
 520
 521         MTK_PIN_DRV_GRP(186, 0xbe0, 8, 0),
 522
 523         MTK_PIN_DRV_GRP(187, 0xbe0, 12, 0),
 524
 525         MTK_PIN_DRV_GRP(188, 0xbf0, 0, 0),
 526
 527         MTK_PIN_DRV_GRP(189, 0xbe0, 12, 0),
 528
 529         MTK_PIN_DRV_GRP(190, 0xbf0, 0, 0),
 530
 531         MTK_PIN_DRV_GRP(191, 0xbf0, 4, 0),
 532
 533         MTK_PIN_DRV_GRP(192, 0xbf0, 8, 0),
 534
 535         MTK_PIN_DRV_GRP(193, 0xbf0, 4, 0),
 536         MTK_PIN_DRV_GRP(194, 0xbf0, 4, 0),
 537
 538         MTK_PIN_DRV_GRP(195, 0xbf0, 8, 0),
 539
 540         MTK_PIN_DRV_GRP(196, 0xbf0, 12, 0),
 541         MTK_PIN_DRV_GRP(197, 0xbf0, 12, 0),
 542         MTK_PIN_DRV_GRP(198, 0xbf0, 12, 0),
 543         MTK_PIN_DRV_GRP(199, 0xbf0, 12, 0),
 544
 545         MTK_PIN_DRV_GRP(200, 0xc00, 0, 0),
 546         MTK_PIN_DRV_GRP(201, 0xc00, 0, 0),
 547         MTK_PIN_DRV_GRP(202, 0xc00, 0, 0),
 548         MTK_PIN_DRV_GRP(203, 0xc00, 0, 0),
 549
 550         MTK_PIN_DRV_GRP(204, 0xc00, 4, 0),
 551         MTK_PIN_DRV_GRP(205, 0xc00, 4, 0),
 552         MTK_PIN_DRV_GRP(206, 0xc00, 4, 0),
 553
 554         MTK_PIN_DRV_GRP(207, 0xc00, 8, 0),
 555         MTK_PIN_DRV_GRP(208, 0xc00, 8, 0),
 556         MTK_PIN_DRV_GRP(209, 0xc00, 8, 0),
 557 };
 558
 559 static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
 560         .pins = mtk_pins_mt2712,
 561         .npins = ARRAY_SIZE(mtk_pins_mt2712),
 562         .grp_desc = mt2712_drv_grp,
 563         .n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
 564         .pin_drv_grp = mt2712_pin_drv,
 565         .n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
 566         .spec_pull_set = mt2712_spec_pull_set,
 567         .spec_ies_smt_set = mt2712_ies_smt_set,
 568         .dir_offset = 0x0000,
 569         .pullen_offset = 0x0100,
 570         .pullsel_offset = 0x0200,
 571         .dout_offset = 0x0300,
 572         .din_offset = 0x0400,
 573         .pinmux_offset = 0x0500,
 574         .type1_start = 210,
 575         .type1_end = 210,
 576         .port_shf = 4,
 577         .port_mask = 0xf,
 578         .port_align = 4,
 579         .eint_hw = {
 580                 .port_mask = 0xf,
 581                 .ports     = 8,
 582                 .ap_num    = 229,
 583                 .db_cnt    = 40,
 584         },
 585 };
 586
 587 static int mt2712_pinctrl_probe(struct platform_device *pdev)
 588 {
 589         return mtk_pctrl_init(pdev, &mt2712_pinctrl_data, NULL);
 590 }
 591
 592 static const struct of_device_id mt2712_pctrl_match[] = {
 593         {
 594                 .compatible = "mediatek,mt2712-pinctrl",
 595         },
 596         { }
 597 };
 598 MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
 599
 600 static struct platform_driver mtk_pinctrl_driver = {
 601         .probe = mt2712_pinctrl_probe,
 602         .driver = {
 603                 .name = "mediatek-mt2712-pinctrl",
 604                 .of_match_table = mt2712_pctrl_match,
 605                 .pm = &mtk_eint_pm_ops,
 606         },
 607 };
 608
 609 static int __init mtk_pinctrl_init(void)
 610 {
 611         return platform_driver_register(&mtk_pinctrl_driver);
 612 }
 613
 614 arch_initcall(mtk_pinctrl_init);