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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-amd.c
blob2d4acf21117cc5ce4fbabab577bf0ded2f4ca35b
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIO driver for AMD
4 *
5 * Copyright (c) 2014,2015 AMD Corporation.
6 * Authors: Ken Xue <Ken.Xue@amd.com>
7 * Wu, Jeff <Jeff.Wu@amd.com>
8 *
9 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
10 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
11 */
12
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
22 #include <linux/io.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
34
35 #include "core.h"
36 #include "pinctrl-utils.h"
37 #include "pinctrl-amd.h"
38
39 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
40 {
41 unsigned long flags;
42 u32 pin_reg;
43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
44
45 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
46 pin_reg = readl(gpio_dev->base + offset * 4);
47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
48
49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
50 return GPIO_LINE_DIRECTION_OUT;
51
52 return GPIO_LINE_DIRECTION_IN;
53 }
54
55 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
56 {
57 unsigned long flags;
58 u32 pin_reg;
59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
60
61 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
62 pin_reg = readl(gpio_dev->base + offset * 4);
63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
64 writel(pin_reg, gpio_dev->base + offset * 4);
65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
66
67 return 0;
68 }
69
70 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
71 int value)
72 {
73 u32 pin_reg;
74 unsigned long flags;
75 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
76
77 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
78 pin_reg = readl(gpio_dev->base + offset * 4);
79 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
80 if (value)
81 pin_reg |= BIT(OUTPUT_VALUE_OFF);
82 else
83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
84 writel(pin_reg, gpio_dev->base + offset * 4);
85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
86
87 return 0;
88 }
89
90 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
91 {
92 u32 pin_reg;
93 unsigned long flags;
94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
95
96 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
97 pin_reg = readl(gpio_dev->base + offset * 4);
98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
99
100 return !!(pin_reg & BIT(PIN_STS_OFF));
101 }
102
103 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
104 {
105 u32 pin_reg;
106 unsigned long flags;
107 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
108
109 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
110 pin_reg = readl(gpio_dev->base + offset * 4);
111 if (value)
112 pin_reg |= BIT(OUTPUT_VALUE_OFF);
113 else
114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
115 writel(pin_reg, gpio_dev->base + offset * 4);
116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
117 }
118
119 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
120 unsigned debounce)
121 {
122 u32 time;
123 u32 pin_reg;
124 int ret = 0;
125 unsigned long flags;
126 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
127
128 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
129 pin_reg = readl(gpio_dev->base + offset * 4);
130
131 if (debounce) {
132 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
133 pin_reg &= ~DB_TMR_OUT_MASK;
134 /*
135 Debounce Debounce Timer Max
136 TmrLarge TmrOutUnit Unit Debounce
137 Time
138 0 0 61 usec (2 RtcClk) 976 usec
139 0 1 244 usec (8 RtcClk) 3.9 msec
140 1 0 15.6 msec (512 RtcClk) 250 msec
141 1 1 62.5 msec (2048 RtcClk) 1 sec
142 */
143
144 if (debounce < 61) {
145 pin_reg |= 1;
146 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
147 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
148 } else if (debounce < 976) {
149 time = debounce / 61;
150 pin_reg |= time & DB_TMR_OUT_MASK;
151 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
152 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
153 } else if (debounce < 3900) {
154 time = debounce / 244;
155 pin_reg |= time & DB_TMR_OUT_MASK;
156 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 } else if (debounce < 250000) {
159 time = debounce / 15625;
160 pin_reg |= time & DB_TMR_OUT_MASK;
161 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
162 pin_reg |= BIT(DB_TMR_LARGE_OFF);
163 } else if (debounce < 1000000) {
164 time = debounce / 62500;
165 pin_reg |= time & DB_TMR_OUT_MASK;
166 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
167 pin_reg |= BIT(DB_TMR_LARGE_OFF);
168 } else {
169 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
170 ret = -EINVAL;
171 }
172 } else {
173 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
174 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
175 pin_reg &= ~DB_TMR_OUT_MASK;
176 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
177 }
178 writel(pin_reg, gpio_dev->base + offset * 4);
179 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
180
181 return ret;
182 }
183
184 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
185 unsigned long config)
186 {
187 u32 debounce;
188
189 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
190 return -ENOTSUPP;
191
192 debounce = pinconf_to_config_argument(config);
193 return amd_gpio_set_debounce(gc, offset, debounce);
194 }
195
196 #ifdef CONFIG_DEBUG_FS
197 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
198 {
199 u32 pin_reg;
200 u32 db_cntrl;
201 unsigned long flags;
202 unsigned int bank, i, pin_num;
203 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
204
205 bool tmr_out_unit;
206 unsigned int time;
207 unsigned int unit;
208 bool tmr_large;
209
210 char *level_trig;
211 char *active_level;
212 char *interrupt_enable;
213 char *interrupt_mask;
214 char *wake_cntrl0;
215 char *wake_cntrl1;
216 char *wake_cntrl2;
217 char *pin_sts;
218 char *pull_up_sel;
219 char *pull_up_enable;
220 char *pull_down_enable;
221 char *output_value;
222 char *output_enable;
223 char debounce_value[40];
224 char *debounce_enable;
225
226 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
227 seq_printf(s, "GPIO bank%d\t", bank);
228
229 switch (bank) {
230 case 0:
231 i = 0;
232 pin_num = AMD_GPIO_PINS_BANK0;
233 break;
234 case 1:
235 i = 64;
236 pin_num = AMD_GPIO_PINS_BANK1 + i;
237 break;
238 case 2:
239 i = 128;
240 pin_num = AMD_GPIO_PINS_BANK2 + i;
241 break;
242 case 3:
243 i = 192;
244 pin_num = AMD_GPIO_PINS_BANK3 + i;
245 break;
246 default:
247 /* Illegal bank number, ignore */
248 continue;
249 }
250 for (; i < pin_num; i++) {
251 seq_printf(s, "pin%d\t", i);
252 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
253 pin_reg = readl(gpio_dev->base + i * 4);
254 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
255
256 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
257 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
258 ACTIVE_LEVEL_MASK;
259 interrupt_enable = "interrupt is enabled|";
260
261 if (level == ACTIVE_LEVEL_HIGH)
262 active_level = "Active high|";
263 else if (level == ACTIVE_LEVEL_LOW)
264 active_level = "Active low|";
265 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
266 level == ACTIVE_LEVEL_BOTH)
267 active_level = "Active on both|";
268 else
269 active_level = "Unknown Active level|";
270
271 if (pin_reg & BIT(LEVEL_TRIG_OFF))
272 level_trig = "Level trigger|";
273 else
274 level_trig = "Edge trigger|";
275
276 } else {
277 interrupt_enable =
278 "interrupt is disabled|";
279 active_level = " ";
280 level_trig = " ";
281 }
282
283 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
284 interrupt_mask =
285 "interrupt is unmasked|";
286 else
287 interrupt_mask =
288 "interrupt is masked|";
289
290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
291 wake_cntrl0 = "enable wakeup in S0i3 state|";
292 else
293 wake_cntrl0 = "disable wakeup in S0i3 state|";
294
295 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
296 wake_cntrl1 = "enable wakeup in S3 state|";
297 else
298 wake_cntrl1 = "disable wakeup in S3 state|";
299
300 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
301 wake_cntrl2 = "enable wakeup in S4/S5 state|";
302 else
303 wake_cntrl2 = "disable wakeup in S4/S5 state|";
304
305 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
306 pull_up_enable = "pull-up is enabled|";
307 if (pin_reg & BIT(PULL_UP_SEL_OFF))
308 pull_up_sel = "8k pull-up|";
309 else
310 pull_up_sel = "4k pull-up|";
311 } else {
312 pull_up_enable = "pull-up is disabled|";
313 pull_up_sel = " ";
314 }
315
316 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
317 pull_down_enable = "pull-down is enabled|";
318 else
319 pull_down_enable = "Pull-down is disabled|";
320
321 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
322 pin_sts = " ";
323 output_enable = "output is enabled|";
324 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
325 output_value = "output is high|";
326 else
327 output_value = "output is low|";
328 } else {
329 output_enable = "output is disabled|";
330 output_value = " ";
331
332 if (pin_reg & BIT(PIN_STS_OFF))
333 pin_sts = "input is high|";
334 else
335 pin_sts = "input is low|";
336 }
337
338 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
339 if (db_cntrl) {
340 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
341 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
342 time = pin_reg & DB_TMR_OUT_MASK;
343 if (tmr_large) {
344 if (tmr_out_unit)
345 unit = 62500;
346 else
347 unit = 15625;
348 } else {
349 if (tmr_out_unit)
350 unit = 244;
351 else
352 unit = 61;
353 }
354 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
355 debounce_enable = "debouncing filter (high and low) enabled|";
356 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
357 debounce_enable = "debouncing filter (low) enabled|";
358 else
359 debounce_enable = "debouncing filter (high) enabled|";
360
361 snprintf(debounce_value, sizeof(debounce_value),
362 "debouncing timeout is %u (us)|", time * unit);
363 } else {
364 debounce_enable = "debouncing filter disabled|";
365 snprintf(debounce_value, sizeof(debounce_value), " ");
366 }
367
368 seq_printf(s, "%s %s %s %s %s %s\n"
369 " %s %s %s %s %s %s %s %s %s 0x%x\n",
370 level_trig, active_level, interrupt_enable,
371 interrupt_mask, wake_cntrl0, wake_cntrl1,
372 wake_cntrl2, pin_sts, pull_up_sel,
373 pull_up_enable, pull_down_enable,
374 output_value, output_enable,
375 debounce_enable, debounce_value, pin_reg);
376 }
377 }
378 }
379 #else
380 #define amd_gpio_dbg_show NULL
381 #endif
382
383 static void amd_gpio_irq_enable(struct irq_data *d)
384 {
385 u32 pin_reg;
386 unsigned long flags;
387 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
388 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
389
390 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
391 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
392 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
393 pin_reg |= BIT(INTERRUPT_MASK_OFF);
394 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
395 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
396 }
397
398 static void amd_gpio_irq_disable(struct irq_data *d)
399 {
400 u32 pin_reg;
401 unsigned long flags;
402 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
403 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
404
405 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
406 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
407 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
408 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
409 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
410 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
411 }
412
413 static void amd_gpio_irq_mask(struct irq_data *d)
414 {
415 u32 pin_reg;
416 unsigned long flags;
417 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
418 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
419
420 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
421 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
422 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
423 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
424 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
425 }
426
427 static void amd_gpio_irq_unmask(struct irq_data *d)
428 {
429 u32 pin_reg;
430 unsigned long flags;
431 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
432 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
433
434 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
435 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
436 pin_reg |= BIT(INTERRUPT_MASK_OFF);
437 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
438 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
439 }
440
441 static void amd_gpio_irq_eoi(struct irq_data *d)
442 {
443 u32 reg;
444 unsigned long flags;
445 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
446 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
447
448 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
449 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
450 reg |= EOI_MASK;
451 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
452 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
453 }
454
455 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
456 {
457 int ret = 0;
458 u32 pin_reg, pin_reg_irq_en, mask;
459 unsigned long flags;
460 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
461 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
462
463 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
464 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
465
466 switch (type & IRQ_TYPE_SENSE_MASK) {
467 case IRQ_TYPE_EDGE_RISING:
468 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
469 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
470 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
471 irq_set_handler_locked(d, handle_edge_irq);
472 break;
473
474 case IRQ_TYPE_EDGE_FALLING:
475 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
476 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
477 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
478 irq_set_handler_locked(d, handle_edge_irq);
479 break;
480
481 case IRQ_TYPE_EDGE_BOTH:
482 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
483 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
484 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
485 irq_set_handler_locked(d, handle_edge_irq);
486 break;
487
488 case IRQ_TYPE_LEVEL_HIGH:
489 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
490 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
491 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
492 irq_set_handler_locked(d, handle_level_irq);
493 break;
494
495 case IRQ_TYPE_LEVEL_LOW:
496 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
497 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
498 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
499 irq_set_handler_locked(d, handle_level_irq);
500 break;
501
502 case IRQ_TYPE_NONE:
503 break;
504
505 default:
506 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
507 ret = -EINVAL;
508 }
509
510 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
511 /*
512 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
513 * debounce registers of any GPIO will block wake/interrupt status
514 * generation for *all* GPIOs for a length of time that depends on
515 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
516 * INTERRUPT_ENABLE bit will read as 0.
517 *
518 * We temporarily enable irq for the GPIO whose configuration is
519 * changing, and then wait for it to read back as 1 to know when
520 * debounce has settled and then disable the irq again.
521 * We do this polling with the spinlock held to ensure other GPIO
522 * access routines do not read an incorrect value for the irq enable
523 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
524 * spurious irqs, and disable the irq again after polling.
525 */
526 mask = BIT(INTERRUPT_ENABLE_OFF);
527 pin_reg_irq_en = pin_reg;
528 pin_reg_irq_en |= mask;
529 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
530 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
531 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
532 continue;
533 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
534 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
535
536 return ret;
537 }
538
539 static void amd_irq_ack(struct irq_data *d)
540 {
541 /*
542 * based on HW design,there is no need to ack HW
543 * before handle current irq. But this routine is
544 * necessary for handle_edge_irq
545 */
546 }
547
548 static struct irq_chip amd_gpio_irqchip = {
549 .name = "amd_gpio",
550 .irq_ack = amd_irq_ack,
551 .irq_enable = amd_gpio_irq_enable,
552 .irq_disable = amd_gpio_irq_disable,
553 .irq_mask = amd_gpio_irq_mask,
554 .irq_unmask = amd_gpio_irq_unmask,
555 .irq_eoi = amd_gpio_irq_eoi,
556 .irq_set_type = amd_gpio_irq_set_type,
557 .flags = IRQCHIP_SKIP_SET_WAKE,
558 };
559
560 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
561
562 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
563 {
564 struct amd_gpio *gpio_dev = dev_id;
565 struct gpio_chip *gc = &gpio_dev->gc;
566 irqreturn_t ret = IRQ_NONE;
567 unsigned int i, irqnr;
568 unsigned long flags;
569 u32 __iomem *regs;
570 u32 regval;
571 u64 status, mask;
572
573 /* Read the wake status */
574 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
575 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
576 status <<= 32;
577 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
578 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
579
580 /* Bit 0-45 contain the relevant status bits */
581 status &= (1ULL << 46) - 1;
582 regs = gpio_dev->base;
583 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
584 if (!(status & mask))
585 continue;
586 status &= ~mask;
587
588 /* Each status bit covers four pins */
589 for (i = 0; i < 4; i++) {
590 regval = readl(regs + i);
591 if (!(regval & PIN_IRQ_PENDING) ||
592 !(regval & BIT(INTERRUPT_MASK_OFF)))
593 continue;
594 irq = irq_find_mapping(gc->irq.domain, irqnr + i);
595 if (irq != 0)
596 generic_handle_irq(irq);
597
598 /* Clear interrupt.
599 * We must read the pin register again, in case the
600 * value was changed while executing
601 * generic_handle_irq() above.
602 * If we didn't find a mapping for the interrupt,
603 * disable it in order to avoid a system hang caused
604 * by an interrupt storm.
605 */
606 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
607 regval = readl(regs + i);
608 if (irq == 0) {
609 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
610 dev_dbg(&gpio_dev->pdev->dev,
611 "Disabling spurious GPIO IRQ %d\n",
612 irqnr + i);
613 }
614 writel(regval, regs + i);
615 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
616 ret = IRQ_HANDLED;
617 }
618 }
619
620 /* Signal EOI to the GPIO unit */
621 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
622 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
623 regval |= EOI_MASK;
624 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
625 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
626
627 return ret;
628 }
629
630 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
631 {
632 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
633
634 return gpio_dev->ngroups;
635 }
636
637 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
638 unsigned group)
639 {
640 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
641
642 return gpio_dev->groups[group].name;
643 }
644
645 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
646 unsigned group,
647 const unsigned **pins,
648 unsigned *num_pins)
649 {
650 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
651
652 *pins = gpio_dev->groups[group].pins;
653 *num_pins = gpio_dev->groups[group].npins;
654 return 0;
655 }
656
657 static const struct pinctrl_ops amd_pinctrl_ops = {
658 .get_groups_count = amd_get_groups_count,
659 .get_group_name = amd_get_group_name,
660 .get_group_pins = amd_get_group_pins,
661 #ifdef CONFIG_OF
662 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
663 .dt_free_map = pinctrl_utils_free_map,
664 #endif
665 };
666
667 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
668 unsigned int pin,
669 unsigned long *config)
670 {
671 u32 pin_reg;
672 unsigned arg;
673 unsigned long flags;
674 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
675 enum pin_config_param param = pinconf_to_config_param(*config);
676
677 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
678 pin_reg = readl(gpio_dev->base + pin*4);
679 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
680 switch (param) {
681 case PIN_CONFIG_INPUT_DEBOUNCE:
682 arg = pin_reg & DB_TMR_OUT_MASK;
683 break;
684
685 case PIN_CONFIG_BIAS_PULL_DOWN:
686 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
687 break;
688
689 case PIN_CONFIG_BIAS_PULL_UP:
690 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
691 break;
692
693 case PIN_CONFIG_DRIVE_STRENGTH:
694 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
695 break;
696
697 default:
698 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
699 param);
700 return -ENOTSUPP;
701 }
702
703 *config = pinconf_to_config_packed(param, arg);
704
705 return 0;
706 }
707
708 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
709 unsigned long *configs, unsigned num_configs)
710 {
711 int i;
712 u32 arg;
713 int ret = 0;
714 u32 pin_reg;
715 unsigned long flags;
716 enum pin_config_param param;
717 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
718
719 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
720 for (i = 0; i < num_configs; i++) {
721 param = pinconf_to_config_param(configs[i]);
722 arg = pinconf_to_config_argument(configs[i]);
723 pin_reg = readl(gpio_dev->base + pin*4);
724
725 switch (param) {
726 case PIN_CONFIG_INPUT_DEBOUNCE:
727 pin_reg &= ~DB_TMR_OUT_MASK;
728 pin_reg |= arg & DB_TMR_OUT_MASK;
729 break;
730
731 case PIN_CONFIG_BIAS_PULL_DOWN:
732 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
733 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
734 break;
735
736 case PIN_CONFIG_BIAS_PULL_UP:
737 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
738 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
739 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
740 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
741 break;
742
743 case PIN_CONFIG_DRIVE_STRENGTH:
744 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
745 << DRV_STRENGTH_SEL_OFF);
746 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
747 << DRV_STRENGTH_SEL_OFF;
748 break;
749
750 default:
751 dev_err(&gpio_dev->pdev->dev,
752 "Invalid config param %04x\n", param);
753 ret = -ENOTSUPP;
754 }
755
756 writel(pin_reg, gpio_dev->base + pin*4);
757 }
758 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
759
760 return ret;
761 }
762
763 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
764 unsigned int group,
765 unsigned long *config)
766 {
767 const unsigned *pins;
768 unsigned npins;
769 int ret;
770
771 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
772 if (ret)
773 return ret;
774
775 if (amd_pinconf_get(pctldev, pins[0], config))
776 return -ENOTSUPP;
777
778 return 0;
779 }
780
781 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
782 unsigned group, unsigned long *configs,
783 unsigned num_configs)
784 {
785 const unsigned *pins;
786 unsigned npins;
787 int i, ret;
788
789 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
790 if (ret)
791 return ret;
792 for (i = 0; i < npins; i++) {
793 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
794 return -ENOTSUPP;
795 }
796 return 0;
797 }
798
799 static const struct pinconf_ops amd_pinconf_ops = {
800 .pin_config_get = amd_pinconf_get,
801 .pin_config_set = amd_pinconf_set,
802 .pin_config_group_get = amd_pinconf_group_get,
803 .pin_config_group_set = amd_pinconf_group_set,
804 };
805
806 #ifdef CONFIG_PM_SLEEP
807 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
808 {
809 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
810
811 if (!pd)
812 return false;
813
814 /*
815 * Only restore the pin if it is actually in use by the kernel (or
816 * by userspace).
817 */
818 if (pd->mux_owner || pd->gpio_owner ||
819 gpiochip_line_is_irq(&gpio_dev->gc, pin))
820 return true;
821
822 return false;
823 }
824
825 static int amd_gpio_suspend(struct device *dev)
826 {
827 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
828 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
829 int i;
830
831 for (i = 0; i < desc->npins; i++) {
832 int pin = desc->pins[i].number;
833
834 if (!amd_gpio_should_save(gpio_dev, pin))
835 continue;
836
837 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
838 }
839
840 return 0;
841 }
842
843 static int amd_gpio_resume(struct device *dev)
844 {
845 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
846 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
847 int i;
848
849 for (i = 0; i < desc->npins; i++) {
850 int pin = desc->pins[i].number;
851
852 if (!amd_gpio_should_save(gpio_dev, pin))
853 continue;
854
855 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
856 }
857
858 return 0;
859 }
860
861 static const struct dev_pm_ops amd_gpio_pm_ops = {
862 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
863 amd_gpio_resume)
864 };
865 #endif
866
867 static struct pinctrl_desc amd_pinctrl_desc = {
868 .pins = kerncz_pins,
869 .npins = ARRAY_SIZE(kerncz_pins),
870 .pctlops = &amd_pinctrl_ops,
871 .confops = &amd_pinconf_ops,
872 .owner = THIS_MODULE,
873 };
874
875 static int amd_gpio_probe(struct platform_device *pdev)
876 {
877 int ret = 0;
878 int irq_base;
879 struct resource *res;
880 struct amd_gpio *gpio_dev;
881 struct gpio_irq_chip *girq;
882
883 gpio_dev = devm_kzalloc(&pdev->dev,
884 sizeof(struct amd_gpio), GFP_KERNEL);
885 if (!gpio_dev)
886 return -ENOMEM;
887
888 raw_spin_lock_init(&gpio_dev->lock);
889
890 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
891 if (!res) {
892 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
893 return -EINVAL;
894 }
895
896 gpio_dev->base = devm_ioremap(&pdev->dev, res->start,
897 resource_size(res));
898 if (!gpio_dev->base)
899 return -ENOMEM;
900
901 irq_base = platform_get_irq(pdev, 0);
902 if (irq_base < 0)
903 return irq_base;
904
905 #ifdef CONFIG_PM_SLEEP
906 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
907 sizeof(*gpio_dev->saved_regs),
908 GFP_KERNEL);
909 if (!gpio_dev->saved_regs)
910 return -ENOMEM;
911 #endif
912
913 gpio_dev->pdev = pdev;
914 gpio_dev->gc.get_direction = amd_gpio_get_direction;
915 gpio_dev->gc.direction_input = amd_gpio_direction_input;
916 gpio_dev->gc.direction_output = amd_gpio_direction_output;
917 gpio_dev->gc.get = amd_gpio_get_value;
918 gpio_dev->gc.set = amd_gpio_set_value;
919 gpio_dev->gc.set_config = amd_gpio_set_config;
920 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
921
922 gpio_dev->gc.base = -1;
923 gpio_dev->gc.label = pdev->name;
924 gpio_dev->gc.owner = THIS_MODULE;
925 gpio_dev->gc.parent = &pdev->dev;
926 gpio_dev->gc.ngpio = resource_size(res) / 4;
927 #if defined(CONFIG_OF_GPIO)
928 gpio_dev->gc.of_node = pdev->dev.of_node;
929 #endif
930
931 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
932 gpio_dev->groups = kerncz_groups;
933 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
934
935 amd_pinctrl_desc.name = dev_name(&pdev->dev);
936 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
937 gpio_dev);
938 if (IS_ERR(gpio_dev->pctrl)) {
939 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
940 return PTR_ERR(gpio_dev->pctrl);
941 }
942
943 girq = &gpio_dev->gc.irq;
944 girq->chip = &amd_gpio_irqchip;
945 /* This will let us handle the parent IRQ in the driver */
946 girq->parent_handler = NULL;
947 girq->num_parents = 0;
948 girq->parents = NULL;
949 girq->default_type = IRQ_TYPE_NONE;
950 girq->handler = handle_simple_irq;
951
952 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
953 if (ret)
954 return ret;
955
956 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
957 0, 0, gpio_dev->gc.ngpio);
958 if (ret) {
959 dev_err(&pdev->dev, "Failed to add pin range\n");
960 goto out2;
961 }
962
963 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
964 IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
965 if (ret)
966 goto out2;
967
968 platform_set_drvdata(pdev, gpio_dev);
969
970 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
971 return ret;
972
973 out2:
974 gpiochip_remove(&gpio_dev->gc);
975
976 return ret;
977 }
978
979 static int amd_gpio_remove(struct platform_device *pdev)
980 {
981 struct amd_gpio *gpio_dev;
982
983 gpio_dev = platform_get_drvdata(pdev);
984
985 gpiochip_remove(&gpio_dev->gc);
986
987 return 0;
988 }
989
990 #ifdef CONFIG_ACPI
991 static const struct acpi_device_id amd_gpio_acpi_match[] = {
992 { "AMD0030", 0 },
993 { "AMDI0030", 0},
994 { },
995 };
996 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
997 #endif
998
999 static struct platform_driver amd_gpio_driver = {
1000 .driver = {
1001 .name = "amd_gpio",
1002 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
1003 #ifdef CONFIG_PM_SLEEP
1004 .pm = &amd_gpio_pm_ops,
1005 #endif
1006 },
1007 .probe = amd_gpio_probe,
1008 .remove = amd_gpio_remove,
1009 };
1010
1011 module_platform_driver(amd_gpio_driver);
1012
1013 MODULE_LICENSE("GPL v2");
1014 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1015 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux with added FPC-III support