1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91 pinctrl driver based on at91 pinmux core
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/init.h>
12 #include <linux/of_device.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/pinctrl/machine.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 /* Since we request GPIOs from ourself */
24 #include <linux/pinctrl/consumer.h>
26 #include "pinctrl-at91.h"
29 #define MAX_GPIO_BANKS 5
30 #define MAX_NB_GPIO_PER_BANK 32
32 struct at91_pinctrl_mux_ops
;
34 struct at91_gpio_chip
{
35 struct gpio_chip chip
;
36 struct pinctrl_gpio_range range
;
37 struct at91_gpio_chip
*next
; /* Bank sharing same clock */
38 int pioc_hwirq
; /* PIO bank interrupt identifier on AIC */
39 int pioc_virq
; /* PIO bank Linux virtual interrupt */
40 int pioc_idx
; /* PIO bank index */
41 void __iomem
*regbase
; /* PIO bank virtual address */
42 struct clk
*clock
; /* associated clock */
43 struct at91_pinctrl_mux_ops
*ops
; /* ops */
46 static struct at91_gpio_chip
*gpio_chips
[MAX_GPIO_BANKS
];
48 static int gpio_banks
;
50 #define PULL_UP (1 << 0)
51 #define MULTI_DRIVE (1 << 1)
52 #define DEGLITCH (1 << 2)
53 #define PULL_DOWN (1 << 3)
54 #define DIS_SCHMIT (1 << 4)
55 #define DRIVE_STRENGTH_SHIFT 5
56 #define DRIVE_STRENGTH_MASK 0x3
57 #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
58 #define OUTPUT (1 << 7)
59 #define OUTPUT_VAL_SHIFT 8
60 #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
61 #define SLEWRATE_SHIFT 9
62 #define SLEWRATE_MASK 0x1
63 #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
64 #define DEBOUNCE (1 << 16)
65 #define DEBOUNCE_VAL_SHIFT 17
66 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
69 * These defines will translated the dt binding settings to our internal
70 * settings. They are not necessarily the same value as the register setting.
71 * The actual drive strength current of low, medium and high must be looked up
72 * from the corresponding device datasheet. This value is different for pins
73 * that are even in the same banks. It is also dependent on VCC.
74 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
75 * strength when there is no dt config for it.
77 enum drive_strength_bit
{
78 DRIVE_STRENGTH_BIT_DEF
,
79 DRIVE_STRENGTH_BIT_LOW
,
80 DRIVE_STRENGTH_BIT_MED
,
81 DRIVE_STRENGTH_BIT_HI
,
84 #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
92 #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
95 * struct at91_pmx_func - describes AT91 pinmux functions
96 * @name: the name of this specific function
97 * @groups: corresponding pin groups
98 * @ngroups: the number of groups
100 struct at91_pmx_func
{
108 AT91_MUX_PERIPH_A
= 1,
109 AT91_MUX_PERIPH_B
= 2,
110 AT91_MUX_PERIPH_C
= 3,
111 AT91_MUX_PERIPH_D
= 4,
115 * struct at91_pmx_pin - describes an At91 pin mux
116 * @bank: the bank of the pin
117 * @pin: the pin number in the @bank
118 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
119 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
121 struct at91_pmx_pin
{
129 * struct at91_pin_group - describes an At91 pin group
130 * @name: the name of this specific pin group
131 * @pins_conf: the mux mode for each pin in this group. The size of this
132 * array is the same as pins.
133 * @pins: an array of discrete physical pins used in this group, taken
134 * from the driver-local pin enumeration space
135 * @npins: the number of pins in this group array, i.e. the number of
136 * elements in .pins so we can iterate over that array
138 struct at91_pin_group
{
140 struct at91_pmx_pin
*pins_conf
;
146 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
147 * on new IP with support for periph C and D the way to mux in
148 * periph A and B has changed
149 * So provide the right call back
150 * if not present means the IP does not support it
151 * @get_periph: return the periph mode configured
152 * @mux_A_periph: mux as periph A
153 * @mux_B_periph: mux as periph B
154 * @mux_C_periph: mux as periph C
155 * @mux_D_periph: mux as periph D
156 * @get_deglitch: get deglitch status
157 * @set_deglitch: enable/disable deglitch
158 * @get_debounce: get debounce status
159 * @set_debounce: enable/disable debounce
160 * @get_pulldown: get pulldown status
161 * @set_pulldown: enable/disable pulldown
162 * @get_schmitt_trig: get schmitt trigger status
163 * @disable_schmitt_trig: disable schmitt trigger
164 * @get_drivestrength: get driver strength
165 * @set_drivestrength: set driver strength
166 * @get_slewrate: get slew rate
167 * @set_slewrate: set slew rate
168 * @irq_type: return irq type
170 struct at91_pinctrl_mux_ops
{
171 enum at91_mux (*get_periph
)(void __iomem
*pio
, unsigned mask
);
172 void (*mux_A_periph
)(void __iomem
*pio
, unsigned mask
);
173 void (*mux_B_periph
)(void __iomem
*pio
, unsigned mask
);
174 void (*mux_C_periph
)(void __iomem
*pio
, unsigned mask
);
175 void (*mux_D_periph
)(void __iomem
*pio
, unsigned mask
);
176 bool (*get_deglitch
)(void __iomem
*pio
, unsigned pin
);
177 void (*set_deglitch
)(void __iomem
*pio
, unsigned mask
, bool is_on
);
178 bool (*get_debounce
)(void __iomem
*pio
, unsigned pin
, u32
*div
);
179 void (*set_debounce
)(void __iomem
*pio
, unsigned mask
, bool is_on
, u32 div
);
180 bool (*get_pulldown
)(void __iomem
*pio
, unsigned pin
);
181 void (*set_pulldown
)(void __iomem
*pio
, unsigned mask
, bool is_on
);
182 bool (*get_schmitt_trig
)(void __iomem
*pio
, unsigned pin
);
183 void (*disable_schmitt_trig
)(void __iomem
*pio
, unsigned mask
);
184 unsigned (*get_drivestrength
)(void __iomem
*pio
, unsigned pin
);
185 void (*set_drivestrength
)(void __iomem
*pio
, unsigned pin
,
187 unsigned (*get_slewrate
)(void __iomem
*pio
, unsigned pin
);
188 void (*set_slewrate
)(void __iomem
*pio
, unsigned pin
, u32 slewrate
);
190 int (*irq_type
)(struct irq_data
*d
, unsigned type
);
193 static int gpio_irq_type(struct irq_data
*d
, unsigned type
);
194 static int alt_gpio_irq_type(struct irq_data
*d
, unsigned type
);
196 struct at91_pinctrl
{
198 struct pinctrl_dev
*pctl
;
205 struct at91_pmx_func
*functions
;
208 struct at91_pin_group
*groups
;
211 struct at91_pinctrl_mux_ops
*ops
;
214 static inline const struct at91_pin_group
*at91_pinctrl_find_group_by_name(
215 const struct at91_pinctrl
*info
,
218 const struct at91_pin_group
*grp
= NULL
;
221 for (i
= 0; i
< info
->ngroups
; i
++) {
222 if (strcmp(info
->groups
[i
].name
, name
))
225 grp
= &info
->groups
[i
];
226 dev_dbg(info
->dev
, "%s: %d 0:%d\n", name
, grp
->npins
, grp
->pins
[0]);
233 static int at91_get_groups_count(struct pinctrl_dev
*pctldev
)
235 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
237 return info
->ngroups
;
240 static const char *at91_get_group_name(struct pinctrl_dev
*pctldev
,
243 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
245 return info
->groups
[selector
].name
;
248 static int at91_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned selector
,
249 const unsigned **pins
,
252 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
254 if (selector
>= info
->ngroups
)
257 *pins
= info
->groups
[selector
].pins
;
258 *npins
= info
->groups
[selector
].npins
;
263 static void at91_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
266 seq_printf(s
, "%s", dev_name(pctldev
->dev
));
269 static int at91_dt_node_to_map(struct pinctrl_dev
*pctldev
,
270 struct device_node
*np
,
271 struct pinctrl_map
**map
, unsigned *num_maps
)
273 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
274 const struct at91_pin_group
*grp
;
275 struct pinctrl_map
*new_map
;
276 struct device_node
*parent
;
281 * first find the group of this node and check if we need to create
282 * config maps for pins
284 grp
= at91_pinctrl_find_group_by_name(info
, np
->name
);
286 dev_err(info
->dev
, "unable to find group for node %pOFn\n",
291 map_num
+= grp
->npins
;
292 new_map
= devm_kcalloc(pctldev
->dev
, map_num
, sizeof(*new_map
),
301 parent
= of_get_parent(np
);
303 devm_kfree(pctldev
->dev
, new_map
);
306 new_map
[0].type
= PIN_MAP_TYPE_MUX_GROUP
;
307 new_map
[0].data
.mux
.function
= parent
->name
;
308 new_map
[0].data
.mux
.group
= np
->name
;
311 /* create config map */
313 for (i
= 0; i
< grp
->npins
; i
++) {
314 new_map
[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
315 new_map
[i
].data
.configs
.group_or_pin
=
316 pin_get_name(pctldev
, grp
->pins
[i
]);
317 new_map
[i
].data
.configs
.configs
= &grp
->pins_conf
[i
].conf
;
318 new_map
[i
].data
.configs
.num_configs
= 1;
321 dev_dbg(pctldev
->dev
, "maps: function %s group %s num %d\n",
322 (*map
)->data
.mux
.function
, (*map
)->data
.mux
.group
, map_num
);
327 static void at91_dt_free_map(struct pinctrl_dev
*pctldev
,
328 struct pinctrl_map
*map
, unsigned num_maps
)
332 static const struct pinctrl_ops at91_pctrl_ops
= {
333 .get_groups_count
= at91_get_groups_count
,
334 .get_group_name
= at91_get_group_name
,
335 .get_group_pins
= at91_get_group_pins
,
336 .pin_dbg_show
= at91_pin_dbg_show
,
337 .dt_node_to_map
= at91_dt_node_to_map
,
338 .dt_free_map
= at91_dt_free_map
,
341 static void __iomem
*pin_to_controller(struct at91_pinctrl
*info
,
344 if (!gpio_chips
[bank
])
347 return gpio_chips
[bank
]->regbase
;
350 static inline int pin_to_bank(unsigned pin
)
352 return pin
/= MAX_NB_GPIO_PER_BANK
;
355 static unsigned pin_to_mask(unsigned int pin
)
360 static unsigned two_bit_pin_value_shift_amount(unsigned int pin
)
362 /* return the shift value for a pin for "two bit" per pin registers,
363 * i.e. drive strength */
364 return 2*((pin
>= MAX_NB_GPIO_PER_BANK
/2)
365 ? pin
- MAX_NB_GPIO_PER_BANK
/2 : pin
);
368 static unsigned sama5d3_get_drive_register(unsigned int pin
)
370 /* drive strength is split between two registers
371 * with two bits per pin */
372 return (pin
>= MAX_NB_GPIO_PER_BANK
/2)
373 ? SAMA5D3_PIO_DRIVER2
: SAMA5D3_PIO_DRIVER1
;
376 static unsigned at91sam9x5_get_drive_register(unsigned int pin
)
378 /* drive strength is split between two registers
379 * with two bits per pin */
380 return (pin
>= MAX_NB_GPIO_PER_BANK
/2)
381 ? AT91SAM9X5_PIO_DRIVER2
: AT91SAM9X5_PIO_DRIVER1
;
384 static void at91_mux_disable_interrupt(void __iomem
*pio
, unsigned mask
)
386 writel_relaxed(mask
, pio
+ PIO_IDR
);
389 static unsigned at91_mux_get_pullup(void __iomem
*pio
, unsigned pin
)
391 return !((readl_relaxed(pio
+ PIO_PUSR
) >> pin
) & 0x1);
394 static void at91_mux_set_pullup(void __iomem
*pio
, unsigned mask
, bool on
)
397 writel_relaxed(mask
, pio
+ PIO_PPDDR
);
399 writel_relaxed(mask
, pio
+ (on
? PIO_PUER
: PIO_PUDR
));
402 static bool at91_mux_get_output(void __iomem
*pio
, unsigned int pin
, bool *val
)
404 *val
= (readl_relaxed(pio
+ PIO_ODSR
) >> pin
) & 0x1;
405 return (readl_relaxed(pio
+ PIO_OSR
) >> pin
) & 0x1;
408 static void at91_mux_set_output(void __iomem
*pio
, unsigned int mask
,
409 bool is_on
, bool val
)
411 writel_relaxed(mask
, pio
+ (val
? PIO_SODR
: PIO_CODR
));
412 writel_relaxed(mask
, pio
+ (is_on
? PIO_OER
: PIO_ODR
));
415 static unsigned at91_mux_get_multidrive(void __iomem
*pio
, unsigned pin
)
417 return (readl_relaxed(pio
+ PIO_MDSR
) >> pin
) & 0x1;
420 static void at91_mux_set_multidrive(void __iomem
*pio
, unsigned mask
, bool on
)
422 writel_relaxed(mask
, pio
+ (on
? PIO_MDER
: PIO_MDDR
));
425 static void at91_mux_set_A_periph(void __iomem
*pio
, unsigned mask
)
427 writel_relaxed(mask
, pio
+ PIO_ASR
);
430 static void at91_mux_set_B_periph(void __iomem
*pio
, unsigned mask
)
432 writel_relaxed(mask
, pio
+ PIO_BSR
);
435 static void at91_mux_pio3_set_A_periph(void __iomem
*pio
, unsigned mask
)
438 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) & ~mask
,
440 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) & ~mask
,
444 static void at91_mux_pio3_set_B_periph(void __iomem
*pio
, unsigned mask
)
446 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) | mask
,
448 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) & ~mask
,
452 static void at91_mux_pio3_set_C_periph(void __iomem
*pio
, unsigned mask
)
454 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) & ~mask
, pio
+ PIO_ABCDSR1
);
455 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) | mask
, pio
+ PIO_ABCDSR2
);
458 static void at91_mux_pio3_set_D_periph(void __iomem
*pio
, unsigned mask
)
460 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR1
) | mask
, pio
+ PIO_ABCDSR1
);
461 writel_relaxed(readl_relaxed(pio
+ PIO_ABCDSR2
) | mask
, pio
+ PIO_ABCDSR2
);
464 static enum at91_mux
at91_mux_pio3_get_periph(void __iomem
*pio
, unsigned mask
)
468 if (readl_relaxed(pio
+ PIO_PSR
) & mask
)
469 return AT91_MUX_GPIO
;
471 select
= !!(readl_relaxed(pio
+ PIO_ABCDSR1
) & mask
);
472 select
|= (!!(readl_relaxed(pio
+ PIO_ABCDSR2
) & mask
) << 1);
477 static enum at91_mux
at91_mux_get_periph(void __iomem
*pio
, unsigned mask
)
481 if (readl_relaxed(pio
+ PIO_PSR
) & mask
)
482 return AT91_MUX_GPIO
;
484 select
= readl_relaxed(pio
+ PIO_ABSR
) & mask
;
489 static bool at91_mux_get_deglitch(void __iomem
*pio
, unsigned pin
)
491 return (readl_relaxed(pio
+ PIO_IFSR
) >> pin
) & 0x1;
494 static void at91_mux_set_deglitch(void __iomem
*pio
, unsigned mask
, bool is_on
)
496 writel_relaxed(mask
, pio
+ (is_on
? PIO_IFER
: PIO_IFDR
));
499 static bool at91_mux_pio3_get_deglitch(void __iomem
*pio
, unsigned pin
)
501 if ((readl_relaxed(pio
+ PIO_IFSR
) >> pin
) & 0x1)
502 return !((readl_relaxed(pio
+ PIO_IFSCSR
) >> pin
) & 0x1);
507 static void at91_mux_pio3_set_deglitch(void __iomem
*pio
, unsigned mask
, bool is_on
)
510 writel_relaxed(mask
, pio
+ PIO_IFSCDR
);
511 at91_mux_set_deglitch(pio
, mask
, is_on
);
514 static bool at91_mux_pio3_get_debounce(void __iomem
*pio
, unsigned pin
, u32
*div
)
516 *div
= readl_relaxed(pio
+ PIO_SCDR
);
518 return ((readl_relaxed(pio
+ PIO_IFSR
) >> pin
) & 0x1) &&
519 ((readl_relaxed(pio
+ PIO_IFSCSR
) >> pin
) & 0x1);
522 static void at91_mux_pio3_set_debounce(void __iomem
*pio
, unsigned mask
,
526 writel_relaxed(mask
, pio
+ PIO_IFSCER
);
527 writel_relaxed(div
& PIO_SCDR_DIV
, pio
+ PIO_SCDR
);
528 writel_relaxed(mask
, pio
+ PIO_IFER
);
530 writel_relaxed(mask
, pio
+ PIO_IFSCDR
);
533 static bool at91_mux_pio3_get_pulldown(void __iomem
*pio
, unsigned pin
)
535 return !((readl_relaxed(pio
+ PIO_PPDSR
) >> pin
) & 0x1);
538 static void at91_mux_pio3_set_pulldown(void __iomem
*pio
, unsigned mask
, bool is_on
)
541 writel_relaxed(mask
, pio
+ PIO_PUDR
);
543 writel_relaxed(mask
, pio
+ (is_on
? PIO_PPDER
: PIO_PPDDR
));
546 static void at91_mux_pio3_disable_schmitt_trig(void __iomem
*pio
, unsigned mask
)
548 writel_relaxed(readl_relaxed(pio
+ PIO_SCHMITT
) | mask
, pio
+ PIO_SCHMITT
);
551 static bool at91_mux_pio3_get_schmitt_trig(void __iomem
*pio
, unsigned pin
)
553 return (readl_relaxed(pio
+ PIO_SCHMITT
) >> pin
) & 0x1;
556 static inline u32
read_drive_strength(void __iomem
*reg
, unsigned pin
)
558 unsigned tmp
= readl_relaxed(reg
);
560 tmp
= tmp
>> two_bit_pin_value_shift_amount(pin
);
562 return tmp
& DRIVE_STRENGTH_MASK
;
565 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem
*pio
,
568 unsigned tmp
= read_drive_strength(pio
+
569 sama5d3_get_drive_register(pin
), pin
);
571 /* SAMA5 strength is 1:1 with our defines,
572 * except 0 is equivalent to low per datasheet */
574 tmp
= DRIVE_STRENGTH_BIT_MSK(LOW
);
579 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem
*pio
,
582 unsigned tmp
= read_drive_strength(pio
+
583 at91sam9x5_get_drive_register(pin
), pin
);
585 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
586 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
587 tmp
= DRIVE_STRENGTH_BIT_MSK(HI
) - tmp
;
592 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem
*pio
,
595 unsigned tmp
= readl_relaxed(pio
+ SAM9X60_PIO_DRIVER1
);
598 return DRIVE_STRENGTH_BIT_HI
;
600 return DRIVE_STRENGTH_BIT_LOW
;
603 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem
*pio
, unsigned pin
)
605 unsigned tmp
= readl_relaxed(pio
+ SAM9X60_PIO_SLEWR
);
607 if ((tmp
& BIT(pin
)))
608 return SLEWRATE_BIT_ENA
;
610 return SLEWRATE_BIT_DIS
;
613 static void set_drive_strength(void __iomem
*reg
, unsigned pin
, u32 strength
)
615 unsigned tmp
= readl_relaxed(reg
);
616 unsigned shift
= two_bit_pin_value_shift_amount(pin
);
618 tmp
&= ~(DRIVE_STRENGTH_MASK
<< shift
);
619 tmp
|= strength
<< shift
;
621 writel_relaxed(tmp
, reg
);
624 static void at91_mux_sama5d3_set_drivestrength(void __iomem
*pio
, unsigned pin
,
627 /* do nothing if setting is zero */
631 /* strength is 1 to 1 with setting for SAMA5 */
632 set_drive_strength(pio
+ sama5d3_get_drive_register(pin
), pin
, setting
);
635 static void at91_mux_sam9x5_set_drivestrength(void __iomem
*pio
, unsigned pin
,
638 /* do nothing if setting is zero */
642 /* strength is inverse on SAM9x5s with our defines
643 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
644 setting
= DRIVE_STRENGTH_BIT_MSK(HI
) - setting
;
646 set_drive_strength(pio
+ at91sam9x5_get_drive_register(pin
), pin
,
650 static void at91_mux_sam9x60_set_drivestrength(void __iomem
*pio
, unsigned pin
,
655 if (setting
<= DRIVE_STRENGTH_BIT_DEF
||
656 setting
== DRIVE_STRENGTH_BIT_MED
||
657 setting
> DRIVE_STRENGTH_BIT_HI
)
660 tmp
= readl_relaxed(pio
+ SAM9X60_PIO_DRIVER1
);
662 /* Strength is 0: low, 1: hi */
663 if (setting
== DRIVE_STRENGTH_BIT_LOW
)
668 writel_relaxed(tmp
, pio
+ SAM9X60_PIO_DRIVER1
);
671 static void at91_mux_sam9x60_set_slewrate(void __iomem
*pio
, unsigned pin
,
676 if (setting
< SLEWRATE_BIT_ENA
|| setting
> SLEWRATE_BIT_DIS
)
679 tmp
= readl_relaxed(pio
+ SAM9X60_PIO_SLEWR
);
681 if (setting
== SLEWRATE_BIT_DIS
)
686 writel_relaxed(tmp
, pio
+ SAM9X60_PIO_SLEWR
);
689 static struct at91_pinctrl_mux_ops at91rm9200_ops
= {
690 .get_periph
= at91_mux_get_periph
,
691 .mux_A_periph
= at91_mux_set_A_periph
,
692 .mux_B_periph
= at91_mux_set_B_periph
,
693 .get_deglitch
= at91_mux_get_deglitch
,
694 .set_deglitch
= at91_mux_set_deglitch
,
695 .irq_type
= gpio_irq_type
,
698 static struct at91_pinctrl_mux_ops at91sam9x5_ops
= {
699 .get_periph
= at91_mux_pio3_get_periph
,
700 .mux_A_periph
= at91_mux_pio3_set_A_periph
,
701 .mux_B_periph
= at91_mux_pio3_set_B_periph
,
702 .mux_C_periph
= at91_mux_pio3_set_C_periph
,
703 .mux_D_periph
= at91_mux_pio3_set_D_periph
,
704 .get_deglitch
= at91_mux_pio3_get_deglitch
,
705 .set_deglitch
= at91_mux_pio3_set_deglitch
,
706 .get_debounce
= at91_mux_pio3_get_debounce
,
707 .set_debounce
= at91_mux_pio3_set_debounce
,
708 .get_pulldown
= at91_mux_pio3_get_pulldown
,
709 .set_pulldown
= at91_mux_pio3_set_pulldown
,
710 .get_schmitt_trig
= at91_mux_pio3_get_schmitt_trig
,
711 .disable_schmitt_trig
= at91_mux_pio3_disable_schmitt_trig
,
712 .get_drivestrength
= at91_mux_sam9x5_get_drivestrength
,
713 .set_drivestrength
= at91_mux_sam9x5_set_drivestrength
,
714 .irq_type
= alt_gpio_irq_type
,
717 static const struct at91_pinctrl_mux_ops sam9x60_ops
= {
718 .get_periph
= at91_mux_pio3_get_periph
,
719 .mux_A_periph
= at91_mux_pio3_set_A_periph
,
720 .mux_B_periph
= at91_mux_pio3_set_B_periph
,
721 .mux_C_periph
= at91_mux_pio3_set_C_periph
,
722 .mux_D_periph
= at91_mux_pio3_set_D_periph
,
723 .get_deglitch
= at91_mux_pio3_get_deglitch
,
724 .set_deglitch
= at91_mux_pio3_set_deglitch
,
725 .get_debounce
= at91_mux_pio3_get_debounce
,
726 .set_debounce
= at91_mux_pio3_set_debounce
,
727 .get_pulldown
= at91_mux_pio3_get_pulldown
,
728 .set_pulldown
= at91_mux_pio3_set_pulldown
,
729 .get_schmitt_trig
= at91_mux_pio3_get_schmitt_trig
,
730 .disable_schmitt_trig
= at91_mux_pio3_disable_schmitt_trig
,
731 .get_drivestrength
= at91_mux_sam9x60_get_drivestrength
,
732 .set_drivestrength
= at91_mux_sam9x60_set_drivestrength
,
733 .get_slewrate
= at91_mux_sam9x60_get_slewrate
,
734 .set_slewrate
= at91_mux_sam9x60_set_slewrate
,
735 .irq_type
= alt_gpio_irq_type
,
739 static struct at91_pinctrl_mux_ops sama5d3_ops
= {
740 .get_periph
= at91_mux_pio3_get_periph
,
741 .mux_A_periph
= at91_mux_pio3_set_A_periph
,
742 .mux_B_periph
= at91_mux_pio3_set_B_periph
,
743 .mux_C_periph
= at91_mux_pio3_set_C_periph
,
744 .mux_D_periph
= at91_mux_pio3_set_D_periph
,
745 .get_deglitch
= at91_mux_pio3_get_deglitch
,
746 .set_deglitch
= at91_mux_pio3_set_deglitch
,
747 .get_debounce
= at91_mux_pio3_get_debounce
,
748 .set_debounce
= at91_mux_pio3_set_debounce
,
749 .get_pulldown
= at91_mux_pio3_get_pulldown
,
750 .set_pulldown
= at91_mux_pio3_set_pulldown
,
751 .get_schmitt_trig
= at91_mux_pio3_get_schmitt_trig
,
752 .disable_schmitt_trig
= at91_mux_pio3_disable_schmitt_trig
,
753 .get_drivestrength
= at91_mux_sama5d3_get_drivestrength
,
754 .set_drivestrength
= at91_mux_sama5d3_set_drivestrength
,
755 .irq_type
= alt_gpio_irq_type
,
758 static void at91_pin_dbg(const struct device
*dev
, const struct at91_pmx_pin
*pin
)
761 dev_dbg(dev
, "pio%c%d configured as periph%c with conf = 0x%lx\n",
762 pin
->bank
+ 'A', pin
->pin
, pin
->mux
- 1 + 'A', pin
->conf
);
764 dev_dbg(dev
, "pio%c%d configured as gpio with conf = 0x%lx\n",
765 pin
->bank
+ 'A', pin
->pin
, pin
->conf
);
769 static int pin_check_config(struct at91_pinctrl
*info
, const char *name
,
770 int index
, const struct at91_pmx_pin
*pin
)
774 /* check if it's a valid config */
775 if (pin
->bank
>= gpio_banks
) {
776 dev_err(info
->dev
, "%s: pin conf %d bank_id %d >= nbanks %d\n",
777 name
, index
, pin
->bank
, gpio_banks
);
781 if (!gpio_chips
[pin
->bank
]) {
782 dev_err(info
->dev
, "%s: pin conf %d bank_id %d not enabled\n",
783 name
, index
, pin
->bank
);
787 if (pin
->pin
>= MAX_NB_GPIO_PER_BANK
) {
788 dev_err(info
->dev
, "%s: pin conf %d pin_bank_id %d >= %d\n",
789 name
, index
, pin
->pin
, MAX_NB_GPIO_PER_BANK
);
798 if (mux
>= info
->nmux
) {
799 dev_err(info
->dev
, "%s: pin conf %d mux_id %d >= nmux %d\n",
800 name
, index
, mux
, info
->nmux
);
804 if (!(info
->mux_mask
[pin
->bank
* info
->nmux
+ mux
] & 1 << pin
->pin
)) {
805 dev_err(info
->dev
, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
806 name
, index
, mux
, pin
->bank
+ 'A', pin
->pin
);
813 static void at91_mux_gpio_disable(void __iomem
*pio
, unsigned mask
)
815 writel_relaxed(mask
, pio
+ PIO_PDR
);
818 static void at91_mux_gpio_enable(void __iomem
*pio
, unsigned mask
, bool input
)
820 writel_relaxed(mask
, pio
+ PIO_PER
);
821 writel_relaxed(mask
, pio
+ (input
? PIO_ODR
: PIO_OER
));
824 static int at91_pmx_set(struct pinctrl_dev
*pctldev
, unsigned selector
,
827 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
828 const struct at91_pmx_pin
*pins_conf
= info
->groups
[group
].pins_conf
;
829 const struct at91_pmx_pin
*pin
;
830 uint32_t npins
= info
->groups
[group
].npins
;
835 dev_dbg(info
->dev
, "enable function %s group %s\n",
836 info
->functions
[selector
].name
, info
->groups
[group
].name
);
838 /* first check that all the pins of the group are valid with a valid
840 for (i
= 0; i
< npins
; i
++) {
842 ret
= pin_check_config(info
, info
->groups
[group
].name
, i
, pin
);
847 for (i
= 0; i
< npins
; i
++) {
849 at91_pin_dbg(info
->dev
, pin
);
850 pio
= pin_to_controller(info
, pin
->bank
);
855 mask
= pin_to_mask(pin
->pin
);
856 at91_mux_disable_interrupt(pio
, mask
);
859 at91_mux_gpio_enable(pio
, mask
, 1);
861 case AT91_MUX_PERIPH_A
:
862 info
->ops
->mux_A_periph(pio
, mask
);
864 case AT91_MUX_PERIPH_B
:
865 info
->ops
->mux_B_periph(pio
, mask
);
867 case AT91_MUX_PERIPH_C
:
868 if (!info
->ops
->mux_C_periph
)
870 info
->ops
->mux_C_periph(pio
, mask
);
872 case AT91_MUX_PERIPH_D
:
873 if (!info
->ops
->mux_D_periph
)
875 info
->ops
->mux_D_periph(pio
, mask
);
879 at91_mux_gpio_disable(pio
, mask
);
885 static int at91_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
887 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
889 return info
->nfunctions
;
892 static const char *at91_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
895 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
897 return info
->functions
[selector
].name
;
900 static int at91_pmx_get_groups(struct pinctrl_dev
*pctldev
, unsigned selector
,
901 const char * const **groups
,
902 unsigned * const num_groups
)
904 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
906 *groups
= info
->functions
[selector
].groups
;
907 *num_groups
= info
->functions
[selector
].ngroups
;
912 static int at91_gpio_request_enable(struct pinctrl_dev
*pctldev
,
913 struct pinctrl_gpio_range
*range
,
916 struct at91_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
917 struct at91_gpio_chip
*at91_chip
;
918 struct gpio_chip
*chip
;
922 dev_err(npct
->dev
, "invalid range\n");
926 dev_err(npct
->dev
, "missing GPIO chip in range\n");
930 at91_chip
= gpiochip_get_data(chip
);
932 dev_dbg(npct
->dev
, "enable pin %u as GPIO\n", offset
);
934 mask
= 1 << (offset
- chip
->base
);
936 dev_dbg(npct
->dev
, "enable pin %u as PIO%c%d 0x%x\n",
937 offset
, 'A' + range
->id
, offset
- chip
->base
, mask
);
939 writel_relaxed(mask
, at91_chip
->regbase
+ PIO_PER
);
944 static void at91_gpio_disable_free(struct pinctrl_dev
*pctldev
,
945 struct pinctrl_gpio_range
*range
,
948 struct at91_pinctrl
*npct
= pinctrl_dev_get_drvdata(pctldev
);
950 dev_dbg(npct
->dev
, "disable pin %u as GPIO\n", offset
);
951 /* Set the pin to some default state, GPIO is usually default */
954 static const struct pinmux_ops at91_pmx_ops
= {
955 .get_functions_count
= at91_pmx_get_funcs_count
,
956 .get_function_name
= at91_pmx_get_func_name
,
957 .get_function_groups
= at91_pmx_get_groups
,
958 .set_mux
= at91_pmx_set
,
959 .gpio_request_enable
= at91_gpio_request_enable
,
960 .gpio_disable_free
= at91_gpio_disable_free
,
963 static int at91_pinconf_get(struct pinctrl_dev
*pctldev
,
964 unsigned pin_id
, unsigned long *config
)
966 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
973 dev_dbg(info
->dev
, "%s:%d, pin_id=%d", __func__
, __LINE__
, pin_id
);
974 pio
= pin_to_controller(info
, pin_to_bank(pin_id
));
979 pin
= pin_id
% MAX_NB_GPIO_PER_BANK
;
981 if (at91_mux_get_multidrive(pio
, pin
))
982 *config
|= MULTI_DRIVE
;
984 if (at91_mux_get_pullup(pio
, pin
))
987 if (info
->ops
->get_deglitch
&& info
->ops
->get_deglitch(pio
, pin
))
989 if (info
->ops
->get_debounce
&& info
->ops
->get_debounce(pio
, pin
, &div
))
990 *config
|= DEBOUNCE
| (div
<< DEBOUNCE_VAL_SHIFT
);
991 if (info
->ops
->get_pulldown
&& info
->ops
->get_pulldown(pio
, pin
))
992 *config
|= PULL_DOWN
;
993 if (info
->ops
->get_schmitt_trig
&& info
->ops
->get_schmitt_trig(pio
, pin
))
994 *config
|= DIS_SCHMIT
;
995 if (info
->ops
->get_drivestrength
)
996 *config
|= (info
->ops
->get_drivestrength(pio
, pin
)
997 << DRIVE_STRENGTH_SHIFT
);
998 if (info
->ops
->get_slewrate
)
999 *config
|= (info
->ops
->get_slewrate(pio
, pin
) << SLEWRATE_SHIFT
);
1000 if (at91_mux_get_output(pio
, pin
, &out
))
1001 *config
|= OUTPUT
| (out
<< OUTPUT_VAL_SHIFT
);
1006 static int at91_pinconf_set(struct pinctrl_dev
*pctldev
,
1007 unsigned pin_id
, unsigned long *configs
,
1008 unsigned num_configs
)
1010 struct at91_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
1014 unsigned long config
;
1017 for (i
= 0; i
< num_configs
; i
++) {
1018 config
= configs
[i
];
1021 "%s:%d, pin_id=%d, config=0x%lx",
1022 __func__
, __LINE__
, pin_id
, config
);
1023 pio
= pin_to_controller(info
, pin_to_bank(pin_id
));
1028 pin
= pin_id
% MAX_NB_GPIO_PER_BANK
;
1029 mask
= pin_to_mask(pin
);
1031 if (config
& PULL_UP
&& config
& PULL_DOWN
)
1034 at91_mux_set_output(pio
, mask
, config
& OUTPUT
,
1035 (config
& OUTPUT_VAL
) >> OUTPUT_VAL_SHIFT
);
1036 at91_mux_set_pullup(pio
, mask
, config
& PULL_UP
);
1037 at91_mux_set_multidrive(pio
, mask
, config
& MULTI_DRIVE
);
1038 if (info
->ops
->set_deglitch
)
1039 info
->ops
->set_deglitch(pio
, mask
, config
& DEGLITCH
);
1040 if (info
->ops
->set_debounce
)
1041 info
->ops
->set_debounce(pio
, mask
, config
& DEBOUNCE
,
1042 (config
& DEBOUNCE_VAL
) >> DEBOUNCE_VAL_SHIFT
);
1043 if (info
->ops
->set_pulldown
)
1044 info
->ops
->set_pulldown(pio
, mask
, config
& PULL_DOWN
);
1045 if (info
->ops
->disable_schmitt_trig
&& config
& DIS_SCHMIT
)
1046 info
->ops
->disable_schmitt_trig(pio
, mask
);
1047 if (info
->ops
->set_drivestrength
)
1048 info
->ops
->set_drivestrength(pio
, pin
,
1049 (config
& DRIVE_STRENGTH
)
1050 >> DRIVE_STRENGTH_SHIFT
);
1051 if (info
->ops
->set_slewrate
)
1052 info
->ops
->set_slewrate(pio
, pin
,
1053 (config
& SLEWRATE
) >> SLEWRATE_SHIFT
);
1055 } /* for each config */
1060 #define DBG_SHOW_FLAG(flag) do { \
1061 if (config & flag) { \
1064 seq_puts(s, #flag); \
1069 #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
1070 if ((config & mask) == flag) { \
1073 seq_puts(s, #name); \
1078 static void at91_pinconf_dbg_show(struct pinctrl_dev
*pctldev
,
1079 struct seq_file
*s
, unsigned pin_id
)
1081 unsigned long config
;
1082 int val
, num_conf
= 0;
1084 at91_pinconf_get(pctldev
, pin_id
, &config
);
1086 DBG_SHOW_FLAG(MULTI_DRIVE
);
1087 DBG_SHOW_FLAG(PULL_UP
);
1088 DBG_SHOW_FLAG(PULL_DOWN
);
1089 DBG_SHOW_FLAG(DIS_SCHMIT
);
1090 DBG_SHOW_FLAG(DEGLITCH
);
1091 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH
, DRIVE_STRENGTH_BIT_MSK(LOW
),
1092 DRIVE_STRENGTH_LOW
);
1093 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH
, DRIVE_STRENGTH_BIT_MSK(MED
),
1094 DRIVE_STRENGTH_MED
);
1095 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH
, DRIVE_STRENGTH_BIT_MSK(HI
),
1097 DBG_SHOW_FLAG(SLEWRATE
);
1098 DBG_SHOW_FLAG(DEBOUNCE
);
1099 if (config
& DEBOUNCE
) {
1100 val
= config
>> DEBOUNCE_VAL_SHIFT
;
1101 seq_printf(s
, "(%d)", val
);
1107 static void at91_pinconf_group_dbg_show(struct pinctrl_dev
*pctldev
,
1108 struct seq_file
*s
, unsigned group
)
1112 static const struct pinconf_ops at91_pinconf_ops
= {
1113 .pin_config_get
= at91_pinconf_get
,
1114 .pin_config_set
= at91_pinconf_set
,
1115 .pin_config_dbg_show
= at91_pinconf_dbg_show
,
1116 .pin_config_group_dbg_show
= at91_pinconf_group_dbg_show
,
1119 static struct pinctrl_desc at91_pinctrl_desc
= {
1120 .pctlops
= &at91_pctrl_ops
,
1121 .pmxops
= &at91_pmx_ops
,
1122 .confops
= &at91_pinconf_ops
,
1123 .owner
= THIS_MODULE
,
1126 static const char *gpio_compat
= "atmel,at91rm9200-gpio";
1128 static void at91_pinctrl_child_count(struct at91_pinctrl
*info
,
1129 struct device_node
*np
)
1131 struct device_node
*child
;
1133 for_each_child_of_node(np
, child
) {
1134 if (of_device_is_compatible(child
, gpio_compat
)) {
1135 if (of_device_is_available(child
))
1136 info
->nactive_banks
++;
1139 info
->ngroups
+= of_get_child_count(child
);
1144 static int at91_pinctrl_mux_mask(struct at91_pinctrl
*info
,
1145 struct device_node
*np
)
1151 list
= of_get_property(np
, "atmel,mux-mask", &size
);
1153 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
1157 size
/= sizeof(*list
);
1158 if (!size
|| size
% gpio_banks
) {
1159 dev_err(info
->dev
, "wrong mux mask array should be by %d\n", gpio_banks
);
1162 info
->nmux
= size
/ gpio_banks
;
1164 info
->mux_mask
= devm_kcalloc(info
->dev
, size
, sizeof(u32
),
1166 if (!info
->mux_mask
)
1169 ret
= of_property_read_u32_array(np
, "atmel,mux-mask",
1170 info
->mux_mask
, size
);
1172 dev_err(info
->dev
, "can not read the mux-mask of %d\n", size
);
1176 static int at91_pinctrl_parse_groups(struct device_node
*np
,
1177 struct at91_pin_group
*grp
,
1178 struct at91_pinctrl
*info
, u32 index
)
1180 struct at91_pmx_pin
*pin
;
1185 dev_dbg(info
->dev
, "group(%d): %pOFn\n", index
, np
);
1187 /* Initialise group */
1188 grp
->name
= np
->name
;
1191 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1192 * do sanity check and calculate pins number
1194 list
= of_get_property(np
, "atmel,pins", &size
);
1195 /* we do not check return since it's safe node passed down */
1196 size
/= sizeof(*list
);
1197 if (!size
|| size
% 4) {
1198 dev_err(info
->dev
, "wrong pins number or pins and configs should be by 4\n");
1202 grp
->npins
= size
/ 4;
1203 pin
= grp
->pins_conf
= devm_kcalloc(info
->dev
,
1205 sizeof(struct at91_pmx_pin
),
1207 grp
->pins
= devm_kcalloc(info
->dev
, grp
->npins
, sizeof(unsigned int),
1209 if (!grp
->pins_conf
|| !grp
->pins
)
1212 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
1213 pin
->bank
= be32_to_cpu(*list
++);
1214 pin
->pin
= be32_to_cpu(*list
++);
1215 grp
->pins
[j
] = pin
->bank
* MAX_NB_GPIO_PER_BANK
+ pin
->pin
;
1216 pin
->mux
= be32_to_cpu(*list
++);
1217 pin
->conf
= be32_to_cpu(*list
++);
1219 at91_pin_dbg(info
->dev
, pin
);
1226 static int at91_pinctrl_parse_functions(struct device_node
*np
,
1227 struct at91_pinctrl
*info
, u32 index
)
1229 struct device_node
*child
;
1230 struct at91_pmx_func
*func
;
1231 struct at91_pin_group
*grp
;
1233 static u32 grp_index
;
1236 dev_dbg(info
->dev
, "parse function(%d): %pOFn\n", index
, np
);
1238 func
= &info
->functions
[index
];
1240 /* Initialise function */
1241 func
->name
= np
->name
;
1242 func
->ngroups
= of_get_child_count(np
);
1243 if (func
->ngroups
== 0) {
1244 dev_err(info
->dev
, "no groups defined\n");
1247 func
->groups
= devm_kcalloc(info
->dev
,
1248 func
->ngroups
, sizeof(char *), GFP_KERNEL
);
1252 for_each_child_of_node(np
, child
) {
1253 func
->groups
[i
] = child
->name
;
1254 grp
= &info
->groups
[grp_index
++];
1255 ret
= at91_pinctrl_parse_groups(child
, grp
, info
, i
++);
1265 static const struct of_device_id at91_pinctrl_of_match
[] = {
1266 { .compatible
= "atmel,sama5d3-pinctrl", .data
= &sama5d3_ops
},
1267 { .compatible
= "atmel,at91sam9x5-pinctrl", .data
= &at91sam9x5_ops
},
1268 { .compatible
= "atmel,at91rm9200-pinctrl", .data
= &at91rm9200_ops
},
1269 { .compatible
= "microchip,sam9x60-pinctrl", .data
= &sam9x60_ops
},
1273 static int at91_pinctrl_probe_dt(struct platform_device
*pdev
,
1274 struct at91_pinctrl
*info
)
1279 struct device_node
*np
= pdev
->dev
.of_node
;
1280 struct device_node
*child
;
1285 info
->dev
= &pdev
->dev
;
1286 info
->ops
= (struct at91_pinctrl_mux_ops
*)
1287 of_match_device(at91_pinctrl_of_match
, &pdev
->dev
)->data
;
1288 at91_pinctrl_child_count(info
, np
);
1290 if (gpio_banks
< 1) {
1291 dev_err(&pdev
->dev
, "you need to specify at least one gpio-controller\n");
1295 ret
= at91_pinctrl_mux_mask(info
, np
);
1299 dev_dbg(&pdev
->dev
, "nmux = %d\n", info
->nmux
);
1301 dev_dbg(&pdev
->dev
, "mux-mask\n");
1302 tmp
= info
->mux_mask
;
1303 for (i
= 0; i
< gpio_banks
; i
++) {
1304 for (j
= 0; j
< info
->nmux
; j
++, tmp
++) {
1305 dev_dbg(&pdev
->dev
, "%d:%d\t0x%x\n", i
, j
, tmp
[0]);
1309 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
1310 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
1311 info
->functions
= devm_kcalloc(&pdev
->dev
,
1313 sizeof(struct at91_pmx_func
),
1315 if (!info
->functions
)
1318 info
->groups
= devm_kcalloc(&pdev
->dev
,
1320 sizeof(struct at91_pin_group
),
1325 dev_dbg(&pdev
->dev
, "nbanks = %d\n", gpio_banks
);
1326 dev_dbg(&pdev
->dev
, "nfunctions = %d\n", info
->nfunctions
);
1327 dev_dbg(&pdev
->dev
, "ngroups = %d\n", info
->ngroups
);
1331 for_each_child_of_node(np
, child
) {
1332 if (of_device_is_compatible(child
, gpio_compat
))
1334 ret
= at91_pinctrl_parse_functions(child
, info
, i
++);
1336 dev_err(&pdev
->dev
, "failed to parse function\n");
1345 static int at91_pinctrl_probe(struct platform_device
*pdev
)
1347 struct at91_pinctrl
*info
;
1348 struct pinctrl_pin_desc
*pdesc
;
1349 int ret
, i
, j
, k
, ngpio_chips_enabled
= 0;
1351 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
1355 ret
= at91_pinctrl_probe_dt(pdev
, info
);
1360 * We need all the GPIO drivers to probe FIRST, or we will not be able
1361 * to obtain references to the struct gpio_chip * for them, and we
1362 * need this to proceed.
1364 for (i
= 0; i
< gpio_banks
; i
++)
1366 ngpio_chips_enabled
++;
1368 if (ngpio_chips_enabled
< info
->nactive_banks
) {
1369 dev_warn(&pdev
->dev
,
1370 "All GPIO chips are not registered yet (%d/%d)\n",
1371 ngpio_chips_enabled
, info
->nactive_banks
);
1372 devm_kfree(&pdev
->dev
, info
);
1373 return -EPROBE_DEFER
;
1376 at91_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
1377 at91_pinctrl_desc
.npins
= gpio_banks
* MAX_NB_GPIO_PER_BANK
;
1378 at91_pinctrl_desc
.pins
= pdesc
=
1379 devm_kcalloc(&pdev
->dev
,
1380 at91_pinctrl_desc
.npins
, sizeof(*pdesc
),
1383 if (!at91_pinctrl_desc
.pins
)
1386 for (i
= 0, k
= 0; i
< gpio_banks
; i
++) {
1387 for (j
= 0; j
< MAX_NB_GPIO_PER_BANK
; j
++, k
++) {
1389 pdesc
->name
= kasprintf(GFP_KERNEL
, "pio%c%d", i
+ 'A', j
);
1394 platform_set_drvdata(pdev
, info
);
1395 info
->pctl
= devm_pinctrl_register(&pdev
->dev
, &at91_pinctrl_desc
,
1398 if (IS_ERR(info
->pctl
)) {
1399 dev_err(&pdev
->dev
, "could not register AT91 pinctrl driver\n");
1400 return PTR_ERR(info
->pctl
);
1403 /* We will handle a range of GPIO pins */
1404 for (i
= 0; i
< gpio_banks
; i
++)
1406 pinctrl_add_gpio_range(info
->pctl
, &gpio_chips
[i
]->range
);
1408 dev_info(&pdev
->dev
, "initialized AT91 pinctrl driver\n");
1413 static int at91_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
1415 struct at91_gpio_chip
*at91_gpio
= gpiochip_get_data(chip
);
1416 void __iomem
*pio
= at91_gpio
->regbase
;
1417 unsigned mask
= 1 << offset
;
1420 osr
= readl_relaxed(pio
+ PIO_OSR
);
1422 return GPIO_LINE_DIRECTION_OUT
;
1424 return GPIO_LINE_DIRECTION_IN
;
1427 static int at91_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
1429 struct at91_gpio_chip
*at91_gpio
= gpiochip_get_data(chip
);
1430 void __iomem
*pio
= at91_gpio
->regbase
;
1431 unsigned mask
= 1 << offset
;
1433 writel_relaxed(mask
, pio
+ PIO_ODR
);
1437 static int at91_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1439 struct at91_gpio_chip
*at91_gpio
= gpiochip_get_data(chip
);
1440 void __iomem
*pio
= at91_gpio
->regbase
;
1441 unsigned mask
= 1 << offset
;
1444 pdsr
= readl_relaxed(pio
+ PIO_PDSR
);
1445 return (pdsr
& mask
) != 0;
1448 static void at91_gpio_set(struct gpio_chip
*chip
, unsigned offset
,
1451 struct at91_gpio_chip
*at91_gpio
= gpiochip_get_data(chip
);
1452 void __iomem
*pio
= at91_gpio
->regbase
;
1453 unsigned mask
= 1 << offset
;
1455 writel_relaxed(mask
, pio
+ (val
? PIO_SODR
: PIO_CODR
));
1458 static void at91_gpio_set_multiple(struct gpio_chip
*chip
,
1459 unsigned long *mask
, unsigned long *bits
)
1461 struct at91_gpio_chip
*at91_gpio
= gpiochip_get_data(chip
);
1462 void __iomem
*pio
= at91_gpio
->regbase
;
1464 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1465 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1466 uint32_t set_mask
= (*mask
& *bits
) & BITS_MASK(chip
->ngpio
);
1467 uint32_t clear_mask
= (*mask
& ~(*bits
)) & BITS_MASK(chip
->ngpio
);
1469 writel_relaxed(set_mask
, pio
+ PIO_SODR
);
1470 writel_relaxed(clear_mask
, pio
+ PIO_CODR
);
1473 static int at91_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
1476 struct at91_gpio_chip
*at91_gpio
= gpiochip_get_data(chip
);
1477 void __iomem
*pio
= at91_gpio
->regbase
;
1478 unsigned mask
= 1 << offset
;
1480 writel_relaxed(mask
, pio
+ (val
? PIO_SODR
: PIO_CODR
));
1481 writel_relaxed(mask
, pio
+ PIO_OER
);
1486 #ifdef CONFIG_DEBUG_FS
1487 static void at91_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
1491 struct at91_gpio_chip
*at91_gpio
= gpiochip_get_data(chip
);
1492 void __iomem
*pio
= at91_gpio
->regbase
;
1493 const char *gpio_label
;
1495 for_each_requested_gpio(chip
, i
, gpio_label
) {
1496 unsigned mask
= pin_to_mask(i
);
1498 mode
= at91_gpio
->ops
->get_periph(pio
, mask
);
1499 seq_printf(s
, "[%s] GPIO%s%d: ",
1500 gpio_label
, chip
->label
, i
);
1501 if (mode
== AT91_MUX_GPIO
) {
1502 seq_printf(s
, "[gpio] ");
1503 seq_printf(s
, "%s ",
1504 readl_relaxed(pio
+ PIO_OSR
) & mask
?
1505 "output" : "input");
1506 seq_printf(s
, "%s\n",
1507 readl_relaxed(pio
+ PIO_PDSR
) & mask
?
1510 seq_printf(s
, "[periph %c]\n",
1516 #define at91_gpio_dbg_show NULL
1519 /* Several AIC controller irqs are dispatched through this GPIO handler.
1520 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1521 * at91_set_gpio_input() then maybe enable its glitch filter.
1522 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1524 * First implementation always triggers on rising and falling edges
1525 * whereas the newer PIO3 can be additionally configured to trigger on
1526 * level, edge with any polarity.
1528 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1529 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1530 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1533 static void gpio_irq_mask(struct irq_data
*d
)
1535 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1536 void __iomem
*pio
= at91_gpio
->regbase
;
1537 unsigned mask
= 1 << d
->hwirq
;
1540 writel_relaxed(mask
, pio
+ PIO_IDR
);
1543 static void gpio_irq_unmask(struct irq_data
*d
)
1545 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1546 void __iomem
*pio
= at91_gpio
->regbase
;
1547 unsigned mask
= 1 << d
->hwirq
;
1550 writel_relaxed(mask
, pio
+ PIO_IER
);
1553 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
1557 case IRQ_TYPE_EDGE_BOTH
:
1564 /* Alternate irq type for PIO3 support */
1565 static int alt_gpio_irq_type(struct irq_data
*d
, unsigned type
)
1567 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1568 void __iomem
*pio
= at91_gpio
->regbase
;
1569 unsigned mask
= 1 << d
->hwirq
;
1572 case IRQ_TYPE_EDGE_RISING
:
1573 irq_set_handler_locked(d
, handle_simple_irq
);
1574 writel_relaxed(mask
, pio
+ PIO_ESR
);
1575 writel_relaxed(mask
, pio
+ PIO_REHLSR
);
1577 case IRQ_TYPE_EDGE_FALLING
:
1578 irq_set_handler_locked(d
, handle_simple_irq
);
1579 writel_relaxed(mask
, pio
+ PIO_ESR
);
1580 writel_relaxed(mask
, pio
+ PIO_FELLSR
);
1582 case IRQ_TYPE_LEVEL_LOW
:
1583 irq_set_handler_locked(d
, handle_level_irq
);
1584 writel_relaxed(mask
, pio
+ PIO_LSR
);
1585 writel_relaxed(mask
, pio
+ PIO_FELLSR
);
1587 case IRQ_TYPE_LEVEL_HIGH
:
1588 irq_set_handler_locked(d
, handle_level_irq
);
1589 writel_relaxed(mask
, pio
+ PIO_LSR
);
1590 writel_relaxed(mask
, pio
+ PIO_REHLSR
);
1592 case IRQ_TYPE_EDGE_BOTH
:
1594 * disable additional interrupt modes:
1595 * fall back to default behavior
1597 irq_set_handler_locked(d
, handle_simple_irq
);
1598 writel_relaxed(mask
, pio
+ PIO_AIMDR
);
1602 pr_warn("AT91: No type for GPIO irq offset %d\n", d
->irq
);
1606 /* enable additional interrupt modes */
1607 writel_relaxed(mask
, pio
+ PIO_AIMER
);
1612 static void gpio_irq_ack(struct irq_data
*d
)
1614 /* the interrupt is already cleared before by reading ISR */
1619 static u32 wakeups
[MAX_GPIO_BANKS
];
1620 static u32 backups
[MAX_GPIO_BANKS
];
1622 static int gpio_irq_set_wake(struct irq_data
*d
, unsigned state
)
1624 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
1625 unsigned bank
= at91_gpio
->pioc_idx
;
1626 unsigned mask
= 1 << d
->hwirq
;
1628 if (unlikely(bank
>= MAX_GPIO_BANKS
))
1632 wakeups
[bank
] |= mask
;
1634 wakeups
[bank
] &= ~mask
;
1636 irq_set_irq_wake(at91_gpio
->pioc_virq
, state
);
1641 void at91_pinctrl_gpio_suspend(void)
1645 for (i
= 0; i
< gpio_banks
; i
++) {
1651 pio
= gpio_chips
[i
]->regbase
;
1653 backups
[i
] = readl_relaxed(pio
+ PIO_IMR
);
1654 writel_relaxed(backups
[i
], pio
+ PIO_IDR
);
1655 writel_relaxed(wakeups
[i
], pio
+ PIO_IER
);
1658 clk_disable_unprepare(gpio_chips
[i
]->clock
);
1660 printk(KERN_DEBUG
"GPIO-%c may wake for %08x\n",
1665 void at91_pinctrl_gpio_resume(void)
1669 for (i
= 0; i
< gpio_banks
; i
++) {
1675 pio
= gpio_chips
[i
]->regbase
;
1678 clk_prepare_enable(gpio_chips
[i
]->clock
);
1680 writel_relaxed(wakeups
[i
], pio
+ PIO_IDR
);
1681 writel_relaxed(backups
[i
], pio
+ PIO_IER
);
1686 #define gpio_irq_set_wake NULL
1687 #endif /* CONFIG_PM */
1689 static void gpio_irq_handler(struct irq_desc
*desc
)
1691 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1692 struct gpio_chip
*gpio_chip
= irq_desc_get_handler_data(desc
);
1693 struct at91_gpio_chip
*at91_gpio
= gpiochip_get_data(gpio_chip
);
1694 void __iomem
*pio
= at91_gpio
->regbase
;
1698 chained_irq_enter(chip
, desc
);
1700 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1701 * When there are none pending, we're finished unless we need
1702 * to process multiple banks (like ID_PIOCDE on sam9263).
1704 isr
= readl_relaxed(pio
+ PIO_ISR
) & readl_relaxed(pio
+ PIO_IMR
);
1706 if (!at91_gpio
->next
)
1708 at91_gpio
= at91_gpio
->next
;
1709 pio
= at91_gpio
->regbase
;
1710 gpio_chip
= &at91_gpio
->chip
;
1714 for_each_set_bit(n
, &isr
, BITS_PER_LONG
) {
1715 generic_handle_irq(irq_find_mapping(
1716 gpio_chip
->irq
.domain
, n
));
1719 chained_irq_exit(chip
, desc
);
1720 /* now it may re-trigger */
1723 static int at91_gpio_of_irq_setup(struct platform_device
*pdev
,
1724 struct at91_gpio_chip
*at91_gpio
)
1726 struct gpio_chip
*gpiochip_prev
= NULL
;
1727 struct at91_gpio_chip
*prev
= NULL
;
1728 struct irq_data
*d
= irq_get_irq_data(at91_gpio
->pioc_virq
);
1729 struct irq_chip
*gpio_irqchip
;
1730 struct gpio_irq_chip
*girq
;
1733 gpio_irqchip
= devm_kzalloc(&pdev
->dev
, sizeof(*gpio_irqchip
),
1738 at91_gpio
->pioc_hwirq
= irqd_to_hwirq(d
);
1740 gpio_irqchip
->name
= "GPIO";
1741 gpio_irqchip
->irq_ack
= gpio_irq_ack
;
1742 gpio_irqchip
->irq_disable
= gpio_irq_mask
;
1743 gpio_irqchip
->irq_mask
= gpio_irq_mask
;
1744 gpio_irqchip
->irq_unmask
= gpio_irq_unmask
;
1745 gpio_irqchip
->irq_set_wake
= gpio_irq_set_wake
,
1746 gpio_irqchip
->irq_set_type
= at91_gpio
->ops
->irq_type
;
1748 /* Disable irqs of this PIO controller */
1749 writel_relaxed(~0, at91_gpio
->regbase
+ PIO_IDR
);
1752 * Let the generic code handle this edge IRQ, the the chained
1753 * handler will perform the actual work of handling the parent
1756 girq
= &at91_gpio
->chip
.irq
;
1757 girq
->chip
= gpio_irqchip
;
1758 girq
->default_type
= IRQ_TYPE_NONE
;
1759 girq
->handler
= handle_edge_irq
;
1762 * The top level handler handles one bank of GPIOs, except
1763 * on some SoC it can handle up to three...
1764 * We only set up the handler for the first of the list.
1766 gpiochip_prev
= irq_get_handler_data(at91_gpio
->pioc_virq
);
1767 if (!gpiochip_prev
) {
1768 girq
->parent_handler
= gpio_irq_handler
;
1769 girq
->num_parents
= 1;
1770 girq
->parents
= devm_kcalloc(&pdev
->dev
, 1,
1771 sizeof(*girq
->parents
),
1775 girq
->parents
[0] = at91_gpio
->pioc_virq
;
1779 prev
= gpiochip_get_data(gpiochip_prev
);
1780 /* we can only have 2 banks before */
1781 for (i
= 0; i
< 2; i
++) {
1785 prev
->next
= at91_gpio
;
1793 /* This structure is replicated for each GPIO block allocated at probe time */
1794 static const struct gpio_chip at91_gpio_template
= {
1795 .request
= gpiochip_generic_request
,
1796 .free
= gpiochip_generic_free
,
1797 .get_direction
= at91_gpio_get_direction
,
1798 .direction_input
= at91_gpio_direction_input
,
1799 .get
= at91_gpio_get
,
1800 .direction_output
= at91_gpio_direction_output
,
1801 .set
= at91_gpio_set
,
1802 .set_multiple
= at91_gpio_set_multiple
,
1803 .dbg_show
= at91_gpio_dbg_show
,
1805 .ngpio
= MAX_NB_GPIO_PER_BANK
,
1808 static const struct of_device_id at91_gpio_of_match
[] = {
1809 { .compatible
= "atmel,at91sam9x5-gpio", .data
= &at91sam9x5_ops
, },
1810 { .compatible
= "atmel,at91rm9200-gpio", .data
= &at91rm9200_ops
},
1811 { .compatible
= "microchip,sam9x60-gpio", .data
= &sam9x60_ops
},
1815 static int at91_gpio_probe(struct platform_device
*pdev
)
1817 struct device_node
*np
= pdev
->dev
.of_node
;
1818 struct at91_gpio_chip
*at91_chip
= NULL
;
1819 struct gpio_chip
*chip
;
1820 struct pinctrl_gpio_range
*range
;
1823 int alias_idx
= of_alias_get_id(np
, "gpio");
1827 BUG_ON(alias_idx
>= ARRAY_SIZE(gpio_chips
));
1828 if (gpio_chips
[alias_idx
]) {
1833 irq
= platform_get_irq(pdev
, 0);
1839 at91_chip
= devm_kzalloc(&pdev
->dev
, sizeof(*at91_chip
), GFP_KERNEL
);
1845 at91_chip
->regbase
= devm_platform_ioremap_resource(pdev
, 0);
1846 if (IS_ERR(at91_chip
->regbase
)) {
1847 ret
= PTR_ERR(at91_chip
->regbase
);
1851 at91_chip
->ops
= (struct at91_pinctrl_mux_ops
*)
1852 of_match_device(at91_gpio_of_match
, &pdev
->dev
)->data
;
1853 at91_chip
->pioc_virq
= irq
;
1854 at91_chip
->pioc_idx
= alias_idx
;
1856 at91_chip
->clock
= devm_clk_get(&pdev
->dev
, NULL
);
1857 if (IS_ERR(at91_chip
->clock
)) {
1858 dev_err(&pdev
->dev
, "failed to get clock, ignoring.\n");
1859 ret
= PTR_ERR(at91_chip
->clock
);
1863 ret
= clk_prepare_enable(at91_chip
->clock
);
1865 dev_err(&pdev
->dev
, "failed to prepare and enable clock, ignoring.\n");
1866 goto clk_enable_err
;
1869 at91_chip
->chip
= at91_gpio_template
;
1871 chip
= &at91_chip
->chip
;
1873 chip
->label
= dev_name(&pdev
->dev
);
1874 chip
->parent
= &pdev
->dev
;
1875 chip
->owner
= THIS_MODULE
;
1876 chip
->base
= alias_idx
* MAX_NB_GPIO_PER_BANK
;
1878 if (!of_property_read_u32(np
, "#gpio-lines", &ngpio
)) {
1879 if (ngpio
>= MAX_NB_GPIO_PER_BANK
)
1880 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1881 alias_idx
, MAX_NB_GPIO_PER_BANK
, MAX_NB_GPIO_PER_BANK
);
1883 chip
->ngpio
= ngpio
;
1886 names
= devm_kcalloc(&pdev
->dev
, chip
->ngpio
, sizeof(char *),
1891 goto clk_enable_err
;
1894 for (i
= 0; i
< chip
->ngpio
; i
++)
1895 names
[i
] = kasprintf(GFP_KERNEL
, "pio%c%d", alias_idx
+ 'A', i
);
1897 chip
->names
= (const char *const *)names
;
1899 range
= &at91_chip
->range
;
1900 range
->name
= chip
->label
;
1901 range
->id
= alias_idx
;
1902 range
->pin_base
= range
->base
= range
->id
* MAX_NB_GPIO_PER_BANK
;
1904 range
->npins
= chip
->ngpio
;
1907 ret
= at91_gpio_of_irq_setup(pdev
, at91_chip
);
1909 goto gpiochip_add_err
;
1911 ret
= gpiochip_add_data(chip
, at91_chip
);
1913 goto gpiochip_add_err
;
1915 gpio_chips
[alias_idx
] = at91_chip
;
1916 gpio_banks
= max(gpio_banks
, alias_idx
+ 1);
1918 dev_info(&pdev
->dev
, "at address %p\n", at91_chip
->regbase
);
1924 clk_disable_unprepare(at91_chip
->clock
);
1926 dev_err(&pdev
->dev
, "Failure %i for GPIO %i\n", ret
, alias_idx
);
1931 static struct platform_driver at91_gpio_driver
= {
1933 .name
= "gpio-at91",
1934 .of_match_table
= at91_gpio_of_match
,
1936 .probe
= at91_gpio_probe
,
1939 static struct platform_driver at91_pinctrl_driver
= {
1941 .name
= "pinctrl-at91",
1942 .of_match_table
= at91_pinctrl_of_match
,
1944 .probe
= at91_pinctrl_probe
,
1947 static struct platform_driver
* const drivers
[] = {
1949 &at91_pinctrl_driver
,
1952 static int __init
at91_pinctrl_init(void)
1954 return platform_register_drivers(drivers
, ARRAY_SIZE(drivers
));
1956 arch_initcall(at91_pinctrl_init
);