drivers/pinctrl/pinctrl-lantiq.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  linux/drivers/pinctrl/pinctrl-lantiq.h
   4  *  based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
   5  *
   6  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
   7  */
   8
   9 #ifndef __PINCTRL_LANTIQ_H
  10 #define __PINCTRL_LANTIQ_H
  11
  12 #include <linux/clkdev.h>
  13 #include <linux/pinctrl/pinctrl.h>
  14 #include <linux/pinctrl/pinconf.h>
  15 #include <linux/pinctrl/pinmux.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/pinctrl/machine.h>
  18
  19 #include "core.h"
  20
  21 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
  22
  23 #define LTQ_MAX_MUX             4
  24 #define MFPR_FUNC_MASK          0x3
  25
  26 #define LTQ_PINCONF_PACK(param, arg)            ((param) << 16 | (arg))
  27 #define LTQ_PINCONF_UNPACK_PARAM(conf)          ((conf) >> 16)
  28 #define LTQ_PINCONF_UNPACK_ARG(conf)            ((conf) & 0xffff)
  29
  30 enum ltq_pinconf_param {
  31         LTQ_PINCONF_PARAM_PULL,
  32         LTQ_PINCONF_PARAM_OPEN_DRAIN,
  33         LTQ_PINCONF_PARAM_DRIVE_CURRENT,
  34         LTQ_PINCONF_PARAM_SLEW_RATE,
  35         LTQ_PINCONF_PARAM_OUTPUT,
  36 };
  37
  38 struct ltq_cfg_param {
  39         const char *property;
  40         enum ltq_pinconf_param param;
  41 };
  42
  43 struct ltq_mfp_pin {
  44         const char *name;
  45         const unsigned int pin;
  46         const unsigned short func[LTQ_MAX_MUX];
  47 };
  48
  49 struct ltq_pin_group {
  50         const char *name;
  51         const unsigned mux;
  52         const unsigned *pins;
  53         const unsigned npins;
  54 };
  55
  56 struct ltq_pmx_func {
  57         const char *name;
  58         const char * const *groups;
  59         const unsigned num_groups;
  60 };
  61
  62 struct ltq_pinmux_info {
  63         struct device *dev;
  64         struct pinctrl_dev *pctrl;
  65
  66         /* we need to manage up to 5 pad controllers */
  67         void __iomem *membase[5];
  68
  69         /* the descriptor for the subsystem */
  70         struct pinctrl_desc *desc;
  71
  72         /* we expose our pads to the subsystem */
  73         struct pinctrl_pin_desc *pads;
  74
  75         /* the number of pads. this varies between socs */
  76         unsigned int num_pads;
  77
  78         /* these are our multifunction pins */
  79         const struct ltq_mfp_pin *mfp;
  80         unsigned int num_mfp;
  81
  82         /* a number of multifunction pins can be grouped together */
  83         const struct ltq_pin_group *grps;
  84         unsigned int num_grps;
  85
  86         /* a mapping between function string and id */
  87         const struct ltq_pmx_func *funcs;
  88         unsigned int num_funcs;
  89
  90         /* the pinconf options that we are able to read from the DT */
  91         const struct ltq_cfg_param *params;
  92         unsigned int num_params;
  93
  94         /* the pad controller can have a irq mapping  */
  95         const unsigned *exin;
  96         unsigned int num_exin;
  97
  98         /* we need 5 clocks max */
  99         struct clk *clk[5];
 100
 101         /* soc specific callback used to apply muxing */
 102         int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
 103 };
 104
 105 enum ltq_pin {
 106         GPIO0 = 0,
 107         GPIO1,
 108         GPIO2,
 109         GPIO3,
 110         GPIO4,
 111         GPIO5,
 112         GPIO6,
 113         GPIO7,
 114         GPIO8,
 115         GPIO9,
 116         GPIO10, /* 10 */
 117         GPIO11,
 118         GPIO12,
 119         GPIO13,
 120         GPIO14,
 121         GPIO15,
 122         GPIO16,
 123         GPIO17,
 124         GPIO18,
 125         GPIO19,
 126         GPIO20, /* 20 */
 127         GPIO21,
 128         GPIO22,
 129         GPIO23,
 130         GPIO24,
 131         GPIO25,
 132         GPIO26,
 133         GPIO27,
 134         GPIO28,
 135         GPIO29,
 136         GPIO30, /* 30 */
 137         GPIO31,
 138         GPIO32,
 139         GPIO33,
 140         GPIO34,
 141         GPIO35,
 142         GPIO36,
 143         GPIO37,
 144         GPIO38,
 145         GPIO39,
 146         GPIO40, /* 40 */
 147         GPIO41,
 148         GPIO42,
 149         GPIO43,
 150         GPIO44,
 151         GPIO45,
 152         GPIO46,
 153         GPIO47,
 154         GPIO48,
 155         GPIO49,
 156         GPIO50, /* 50 */
 157         GPIO51,
 158         GPIO52,
 159         GPIO53,
 160         GPIO54,
 161         GPIO55,
 162         GPIO56,
 163         GPIO57,
 164         GPIO58,
 165         GPIO59,
 166         GPIO60, /* 60 */
 167         GPIO61,
 168         GPIO62,
 169         GPIO63,
 170
 171         GPIO64,
 172         GPIO65,
 173         GPIO66,
 174         GPIO67,
 175         GPIO68,
 176         GPIO69,
 177         GPIO70,
 178         GPIO71,
 179         GPIO72,
 180         GPIO73,
 181         GPIO74,
 182         GPIO75,
 183         GPIO76,
 184         GPIO77,
 185         GPIO78,
 186         GPIO79,
 187         GPIO80,
 188         GPIO81,
 189         GPIO82,
 190         GPIO83,
 191         GPIO84,
 192         GPIO85,
 193         GPIO86,
 194         GPIO87,
 195         GPIO88,
 196 };
 197
 198 extern int ltq_pinctrl_register(struct platform_device *pdev,
 199                                    struct ltq_pinmux_info *info);
 200 extern int ltq_pinctrl_unregister(struct platform_device *pdev);
 201 #endif  /* __PINCTRL_LANTIQ_H */