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Merge tag 'block-5.11-2021-01-10' of git://git.kernel.dk/linux-block
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-st.c
blob7b8c7a0b13de09b483dd054e6cc47a47e0447349
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
4 * Authors:
5 * Srinivas Kandagatla <srinivas.kandagatla@st.com>
6 */
7
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/slab.h>
11 #include <linux/err.h>
12 #include <linux/io.h>
13 #include <linux/of.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_gpio.h> /* of_get_named_gpio() */
16 #include <linux/of_address.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/regmap.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/platform_device.h>
24 #include "core.h"
25
26 /* PIO Block registers */
27 /* PIO output */
28 #define REG_PIO_POUT 0x00
29 /* Set bits of POUT */
30 #define REG_PIO_SET_POUT 0x04
31 /* Clear bits of POUT */
32 #define REG_PIO_CLR_POUT 0x08
33 /* PIO input */
34 #define REG_PIO_PIN 0x10
35 /* PIO configuration */
36 #define REG_PIO_PC(n) (0x20 + (n) * 0x10)
37 /* Set bits of PC[2:0] */
38 #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10)
39 /* Clear bits of PC[2:0] */
40 #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10)
41 /* PIO input comparison */
42 #define REG_PIO_PCOMP 0x50
43 /* Set bits of PCOMP */
44 #define REG_PIO_SET_PCOMP 0x54
45 /* Clear bits of PCOMP */
46 #define REG_PIO_CLR_PCOMP 0x58
47 /* PIO input comparison mask */
48 #define REG_PIO_PMASK 0x60
49 /* Set bits of PMASK */
50 #define REG_PIO_SET_PMASK 0x64
51 /* Clear bits of PMASK */
52 #define REG_PIO_CLR_PMASK 0x68
53
54 #define ST_GPIO_DIRECTION_BIDIR 0x1
55 #define ST_GPIO_DIRECTION_OUT 0x2
56 #define ST_GPIO_DIRECTION_IN 0x4
57
58 /**
59 * Packed style retime configuration.
60 * There are two registers cfg0 and cfg1 in this style for each bank.
61 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
62 */
63 #define RT_P_CFGS_PER_BANK 2
64 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7)
65 #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23)
66 #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31)
67 #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7)
68 #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15)
69 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23)
70 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31)
71
72 /**
73 * Dedicated style retime Configuration register
74 * each register is dedicated per pin.
75 */
76 #define RT_D_CFGS_PER_BANK 8
77 #define RT_D_CFG_CLK_SHIFT 0
78 #define RT_D_CFG_CLK_MASK (0x3 << 0)
79 #define RT_D_CFG_CLKNOTDATA_SHIFT 2
80 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2)
81 #define RT_D_CFG_DELAY_SHIFT 3
82 #define RT_D_CFG_DELAY_MASK (0xf << 3)
83 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7
84 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)
85 #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8
86 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)
87 #define RT_D_CFG_INVERTCLK_SHIFT 9
88 #define RT_D_CFG_INVERTCLK_MASK BIT(9)
89 #define RT_D_CFG_RETIME_SHIFT 10
90 #define RT_D_CFG_RETIME_MASK BIT(10)
91
92 /*
93 * Pinconf is represented in an opaque unsigned long variable.
94 * Below is the bit allocation details for each possible configuration.
95 * All the bit fields can be encapsulated into four variables
96 * (direction, retime-type, retime-clk, retime-delay)
97 *
98 * +----------------+
99 *[31:28]| reserved-3 |
100 * +----------------+-------------
101 *[27] | oe | |
102 * +----------------+ v
103 *[26] | pu | [Direction ]
104 * +----------------+ ^
105 *[25] | od | |
106 * +----------------+-------------
107 *[24] | reserved-2 |
108 * +----------------+-------------
109 *[23] | retime | |
110 * +----------------+ |
111 *[22] | retime-invclk | |
112 * +----------------+ v
113 *[21] |retime-clknotdat| [Retime-type ]
114 * +----------------+ ^
115 *[20] | retime-de | |
116 * +----------------+-------------
117 *[19:18]| retime-clk |------>[Retime-Clk ]
118 * +----------------+
119 *[17:16]| reserved-1 |
120 * +----------------+
121 *[15..0]| retime-delay |------>[Retime Delay]
122 * +----------------+
123 */
124
125 #define ST_PINCONF_UNPACK(conf, param)\
126 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \
127 & ST_PINCONF_ ##param ##_MASK)
128
129 #define ST_PINCONF_PACK(conf, val, param) (conf |=\
130 ((val & ST_PINCONF_ ##param ##_MASK) << \
131 ST_PINCONF_ ##param ##_SHIFT))
132
133 /* Output enable */
134 #define ST_PINCONF_OE_MASK 0x1
135 #define ST_PINCONF_OE_SHIFT 27
136 #define ST_PINCONF_OE BIT(27)
137 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE)
138 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)
139
140 /* Pull Up */
141 #define ST_PINCONF_PU_MASK 0x1
142 #define ST_PINCONF_PU_SHIFT 26
143 #define ST_PINCONF_PU BIT(26)
144 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)
145 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)
146
147 /* Open Drain */
148 #define ST_PINCONF_OD_MASK 0x1
149 #define ST_PINCONF_OD_SHIFT 25
150 #define ST_PINCONF_OD BIT(25)
151 #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD)
152 #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD)
153
154 #define ST_PINCONF_RT_MASK 0x1
155 #define ST_PINCONF_RT_SHIFT 23
156 #define ST_PINCONF_RT BIT(23)
157 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
158 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
159
160 #define ST_PINCONF_RT_INVERTCLK_MASK 0x1
161 #define ST_PINCONF_RT_INVERTCLK_SHIFT 22
162 #define ST_PINCONF_RT_INVERTCLK BIT(22)
163 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
164 ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
165 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
166 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
167
168 #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1
169 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21
170 #define ST_PINCONF_RT_CLKNOTDATA BIT(21)
171 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \
172 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
173 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
174 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
175
176 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1
177 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20
178 #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20)
179 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
180 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
181 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
182 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
183
184 #define ST_PINCONF_RT_CLK_MASK 0x3
185 #define ST_PINCONF_RT_CLK_SHIFT 18
186 #define ST_PINCONF_RT_CLK BIT(18)
187 #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK)
188 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
189
190 /* RETIME_DELAY in Pico Secs */
191 #define ST_PINCONF_RT_DELAY_MASK 0xffff
192 #define ST_PINCONF_RT_DELAY_SHIFT 0
193 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
194 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \
195 ST_PINCONF_PACK(conf, val, RT_DELAY)
196
197 #define ST_GPIO_PINS_PER_BANK (8)
198 #define OF_GPIO_ARGS_MIN (4)
199 #define OF_RT_ARGS_MIN (2)
200
201 #define gpio_range_to_bank(chip) \
202 container_of(chip, struct st_gpio_bank, range)
203
204 #define pc_to_bank(pc) \
205 container_of(pc, struct st_gpio_bank, pc)
206
207 enum st_retime_style {
208 st_retime_style_none,
209 st_retime_style_packed,
210 st_retime_style_dedicated,
211 };
212
213 struct st_retime_dedicated {
214 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
215 };
216
217 struct st_retime_packed {
218 struct regmap_field *clk1notclk0;
219 struct regmap_field *delay_0;
220 struct regmap_field *delay_1;
221 struct regmap_field *invertclk;
222 struct regmap_field *retime;
223 struct regmap_field *clknotdata;
224 struct regmap_field *double_edge;
225 };
226
227 struct st_pio_control {
228 u32 rt_pin_mask;
229 struct regmap_field *alt, *oe, *pu, *od;
230 /* retiming */
231 union {
232 struct st_retime_packed rt_p;
233 struct st_retime_dedicated rt_d;
234 } rt;
235 };
236
237 struct st_pctl_data {
238 const enum st_retime_style rt_style;
239 const unsigned int *input_delays;
240 const int ninput_delays;
241 const unsigned int *output_delays;
242 const int noutput_delays;
243 /* register offset information */
244 const int alt, oe, pu, od, rt;
245 };
246
247 struct st_pinconf {
248 int pin;
249 const char *name;
250 unsigned long config;
251 int altfunc;
252 };
253
254 struct st_pmx_func {
255 const char *name;
256 const char **groups;
257 unsigned ngroups;
258 };
259
260 struct st_pctl_group {
261 const char *name;
262 unsigned int *pins;
263 unsigned npins;
264 struct st_pinconf *pin_conf;
265 };
266
267 /*
268 * Edge triggers are not supported at hardware level, it is supported by
269 * software by exploiting the level trigger support in hardware.
270 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
271 * of each gpio pin in a GPIO bank.
272 *
273 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
274 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
275 *
276 * bit allocation per pin is:
277 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
278 * --------------------------------------------------------
279 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
280 * --------------------------------------------------------
281 *
282 * A pin can have one of following the values in its edge configuration field.
283 *
284 * ------- ----------------------------
285 * [0-3] - Description
286 * ------- ----------------------------
287 * 0000 - No edge IRQ.
288 * 0001 - Falling edge IRQ.
289 * 0010 - Rising edge IRQ.
290 * 0011 - Rising and Falling edge IRQ.
291 * ------- ----------------------------
292 */
293
294 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
295 #define ST_IRQ_EDGE_MASK 0xf
296 #define ST_IRQ_EDGE_FALLING BIT(0)
297 #define ST_IRQ_EDGE_RISING BIT(1)
298 #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
299
300 #define ST_IRQ_RISING_EDGE_CONF(pin) \
301 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
302
303 #define ST_IRQ_FALLING_EDGE_CONF(pin) \
304 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
305
306 #define ST_IRQ_BOTH_EDGE_CONF(pin) \
307 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
308
309 #define ST_IRQ_EDGE_CONF(conf, pin) \
310 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
311
312 struct st_gpio_bank {
313 struct gpio_chip gpio_chip;
314 struct pinctrl_gpio_range range;
315 void __iomem *base;
316 struct st_pio_control pc;
317 unsigned long irq_edge_conf;
318 spinlock_t lock;
319 };
320
321 struct st_pinctrl {
322 struct device *dev;
323 struct pinctrl_dev *pctl;
324 struct st_gpio_bank *banks;
325 int nbanks;
326 struct st_pmx_func *functions;
327 int nfunctions;
328 struct st_pctl_group *groups;
329 int ngroups;
330 struct regmap *regmap;
331 const struct st_pctl_data *data;
332 void __iomem *irqmux_base;
333 };
334
335 /* SOC specific data */
336
337 static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250,
338 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
339
340 static const struct st_pctl_data stih407_data = {
341 .rt_style = st_retime_style_dedicated,
342 .input_delays = stih407_delays,
343 .ninput_delays = ARRAY_SIZE(stih407_delays),
344 .output_delays = stih407_delays,
345 .noutput_delays = ARRAY_SIZE(stih407_delays),
346 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
347 };
348
349 static const struct st_pctl_data stih407_flashdata = {
350 .rt_style = st_retime_style_none,
351 .input_delays = stih407_delays,
352 .ninput_delays = ARRAY_SIZE(stih407_delays),
353 .output_delays = stih407_delays,
354 .noutput_delays = ARRAY_SIZE(stih407_delays),
355 .alt = 0,
356 .oe = -1, /* Not Available */
357 .pu = -1, /* Not Available */
358 .od = 60,
359 .rt = 100,
360 };
361
362 static struct st_pio_control *st_get_pio_control(
363 struct pinctrl_dev *pctldev, int pin)
364 {
365 struct pinctrl_gpio_range *range =
366 pinctrl_find_gpio_range_from_pin(pctldev, pin);
367 struct st_gpio_bank *bank = gpio_range_to_bank(range);
368
369 return &bank->pc;
370 }
371
372 /* Low level functions.. */
373 static inline int st_gpio_bank(int gpio)
374 {
375 return gpio/ST_GPIO_PINS_PER_BANK;
376 }
377
378 static inline int st_gpio_pin(int gpio)
379 {
380 return gpio%ST_GPIO_PINS_PER_BANK;
381 }
382
383 static void st_pinconf_set_config(struct st_pio_control *pc,
384 int pin, unsigned long config)
385 {
386 struct regmap_field *output_enable = pc->oe;
387 struct regmap_field *pull_up = pc->pu;
388 struct regmap_field *open_drain = pc->od;
389 unsigned int oe_value, pu_value, od_value;
390 unsigned long mask = BIT(pin);
391
392 if (output_enable) {
393 regmap_field_read(output_enable, &oe_value);
394 oe_value &= ~mask;
395 if (config & ST_PINCONF_OE)
396 oe_value |= mask;
397 regmap_field_write(output_enable, oe_value);
398 }
399
400 if (pull_up) {
401 regmap_field_read(pull_up, &pu_value);
402 pu_value &= ~mask;
403 if (config & ST_PINCONF_PU)
404 pu_value |= mask;
405 regmap_field_write(pull_up, pu_value);
406 }
407
408 if (open_drain) {
409 regmap_field_read(open_drain, &od_value);
410 od_value &= ~mask;
411 if (config & ST_PINCONF_OD)
412 od_value |= mask;
413 regmap_field_write(open_drain, od_value);
414 }
415 }
416
417 static void st_pctl_set_function(struct st_pio_control *pc,
418 int pin_id, int function)
419 {
420 struct regmap_field *alt = pc->alt;
421 unsigned int val;
422 int pin = st_gpio_pin(pin_id);
423 int offset = pin * 4;
424
425 if (!alt)
426 return;
427
428 regmap_field_read(alt, &val);
429 val &= ~(0xf << offset);
430 val |= function << offset;
431 regmap_field_write(alt, val);
432 }
433
434 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
435 {
436 struct regmap_field *alt = pc->alt;
437 unsigned int val;
438 int offset = pin * 4;
439
440 if (!alt)
441 return 0;
442
443 regmap_field_read(alt, &val);
444
445 return (val >> offset) & 0xf;
446 }
447
448 static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
449 const struct st_pctl_data *data, unsigned long config)
450 {
451 const unsigned int *delay_times;
452 int num_delay_times, i, closest_index = -1;
453 unsigned int closest_divergence = UINT_MAX;
454
455 if (ST_PINCONF_UNPACK_OE(config)) {
456 delay_times = data->output_delays;
457 num_delay_times = data->noutput_delays;
458 } else {
459 delay_times = data->input_delays;
460 num_delay_times = data->ninput_delays;
461 }
462
463 for (i = 0; i < num_delay_times; i++) {
464 unsigned int divergence = abs(delay - delay_times[i]);
465
466 if (divergence == 0)
467 return i;
468
469 if (divergence < closest_divergence) {
470 closest_divergence = divergence;
471 closest_index = i;
472 }
473 }
474
475 pr_warn("Attempt to set delay %d, closest available %d\n",
476 delay, delay_times[closest_index]);
477
478 return closest_index;
479 }
480
481 static unsigned long st_pinconf_bit_to_delay(unsigned int index,
482 const struct st_pctl_data *data, unsigned long output)
483 {
484 const unsigned int *delay_times;
485 int num_delay_times;
486
487 if (output) {
488 delay_times = data->output_delays;
489 num_delay_times = data->noutput_delays;
490 } else {
491 delay_times = data->input_delays;
492 num_delay_times = data->ninput_delays;
493 }
494
495 if (index < num_delay_times) {
496 return delay_times[index];
497 } else {
498 pr_warn("Delay not found in/out delay list\n");
499 return 0;
500 }
501 }
502
503 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
504 int enable, int pin)
505 {
506 unsigned int val = 0;
507
508 regmap_field_read(field, &val);
509 if (enable)
510 val |= BIT(pin);
511 else
512 val &= ~BIT(pin);
513 regmap_field_write(field, val);
514 }
515
516 static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
517 struct st_pio_control *pc, unsigned long config, int pin)
518 {
519 const struct st_pctl_data *data = info->data;
520 struct st_retime_packed *rt_p = &pc->rt.rt_p;
521 unsigned int delay;
522
523 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
524 ST_PINCONF_UNPACK_RT_CLK(config), pin);
525
526 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
527 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);
528
529 st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
530 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);
531
532 st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
533 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);
534
535 st_regmap_field_bit_set_clear_pin(rt_p->retime,
536 ST_PINCONF_UNPACK_RT(config), pin);
537
538 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
539 data, config);
540 /* 2 bit delay, lsb */
541 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
542 /* 2 bit delay, msb */
543 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
544
545 }
546
547 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
548 struct st_pio_control *pc, unsigned long config, int pin)
549 {
550 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
551 int clk = ST_PINCONF_UNPACK_RT_CLK(config);
552 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
553 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
554 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config);
555 int retime = ST_PINCONF_UNPACK_RT(config);
556
557 unsigned long delay = st_pinconf_delay_to_bit(
558 ST_PINCONF_UNPACK_RT_DELAY(config),
559 info->data, config);
560 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
561
562 unsigned long retime_config =
563 ((clk) << RT_D_CFG_CLK_SHIFT) |
564 ((delay) << RT_D_CFG_DELAY_SHIFT) |
565 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
566 ((retime) << RT_D_CFG_RETIME_SHIFT) |
567 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
568 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
569 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);
570
571 regmap_field_write(rt_d->rt[pin], retime_config);
572 }
573
574 static void st_pinconf_get_direction(struct st_pio_control *pc,
575 int pin, unsigned long *config)
576 {
577 unsigned int oe_value, pu_value, od_value;
578
579 if (pc->oe) {
580 regmap_field_read(pc->oe, &oe_value);
581 if (oe_value & BIT(pin))
582 ST_PINCONF_PACK_OE(*config);
583 }
584
585 if (pc->pu) {
586 regmap_field_read(pc->pu, &pu_value);
587 if (pu_value & BIT(pin))
588 ST_PINCONF_PACK_PU(*config);
589 }
590
591 if (pc->od) {
592 regmap_field_read(pc->od, &od_value);
593 if (od_value & BIT(pin))
594 ST_PINCONF_PACK_OD(*config);
595 }
596 }
597
598 static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
599 struct st_pio_control *pc, int pin, unsigned long *config)
600 {
601 const struct st_pctl_data *data = info->data;
602 struct st_retime_packed *rt_p = &pc->rt.rt_p;
603 unsigned int delay_bits, delay, delay0, delay1, val;
604 int output = ST_PINCONF_UNPACK_OE(*config);
605
606 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
607 ST_PINCONF_PACK_RT(*config);
608
609 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
610 ST_PINCONF_PACK_RT_CLK(*config, 1);
611
612 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
613 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
614
615 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
616 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
617
618 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
619 ST_PINCONF_PACK_RT_INVERTCLK(*config);
620
621 regmap_field_read(rt_p->delay_0, &delay0);
622 regmap_field_read(rt_p->delay_1, &delay1);
623 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
624 (((delay0 & BIT(pin)) ? 1 : 0));
625 delay = st_pinconf_bit_to_delay(delay_bits, data, output);
626 ST_PINCONF_PACK_RT_DELAY(*config, delay);
627
628 return 0;
629 }
630
631 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
632 struct st_pio_control *pc, int pin, unsigned long *config)
633 {
634 unsigned int value;
635 unsigned long delay_bits, delay, rt_clk;
636 int output = ST_PINCONF_UNPACK_OE(*config);
637 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
638
639 regmap_field_read(rt_d->rt[pin], &value);
640
641 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
642 ST_PINCONF_PACK_RT_CLK(*config, rt_clk);
643
644 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
645 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output);
646 ST_PINCONF_PACK_RT_DELAY(*config, delay);
647
648 if (value & RT_D_CFG_CLKNOTDATA_MASK)
649 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
650
651 if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
652 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
653
654 if (value & RT_D_CFG_INVERTCLK_MASK)
655 ST_PINCONF_PACK_RT_INVERTCLK(*config);
656
657 if (value & RT_D_CFG_RETIME_MASK)
658 ST_PINCONF_PACK_RT(*config);
659
660 return 0;
661 }
662
663 /* GPIO related functions */
664
665 static inline void __st_gpio_set(struct st_gpio_bank *bank,
666 unsigned offset, int value)
667 {
668 if (value)
669 writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
670 else
671 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
672 }
673
674 static void st_gpio_direction(struct st_gpio_bank *bank,
675 unsigned int gpio, unsigned int direction)
676 {
677 int offset = st_gpio_pin(gpio);
678 int i = 0;
679 /**
680 * There are three configuration registers (PIOn_PC0, PIOn_PC1
681 * and PIOn_PC2) for each port. These are used to configure the
682 * PIO port pins. Each pin can be configured as an input, output,
683 * bidirectional, or alternative function pin. Three bits, one bit
684 * from each of the three registers, configure the corresponding bit of
685 * the port. Valid bit settings is:
686 *
687 * PC2 PC1 PC0 Direction.
688 * 0 0 0 [Input Weak pull-up]
689 * 0 0 or 1 1 [Bidirection]
690 * 0 1 0 [Output]
691 * 1 0 0 [Input]
692 *
693 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
694 * individually.
695 */
696 for (i = 0; i <= 2; i++) {
697 if (direction & BIT(i))
698 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
699 else
700 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
701 }
702 }
703
704 static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
705 {
706 struct st_gpio_bank *bank = gpiochip_get_data(chip);
707
708 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
709 }
710
711 static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
712 {
713 struct st_gpio_bank *bank = gpiochip_get_data(chip);
714 __st_gpio_set(bank, offset, value);
715 }
716
717 static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
718 {
719 pinctrl_gpio_direction_input(chip->base + offset);
720
721 return 0;
722 }
723
724 static int st_gpio_direction_output(struct gpio_chip *chip,
725 unsigned offset, int value)
726 {
727 struct st_gpio_bank *bank = gpiochip_get_data(chip);
728
729 __st_gpio_set(bank, offset, value);
730 pinctrl_gpio_direction_output(chip->base + offset);
731
732 return 0;
733 }
734
735 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
736 {
737 struct st_gpio_bank *bank = gpiochip_get_data(chip);
738 struct st_pio_control pc = bank->pc;
739 unsigned long config;
740 unsigned int direction = 0;
741 unsigned int function;
742 unsigned int value;
743 int i = 0;
744
745 /* Alternate function direction is handled by Pinctrl */
746 function = st_pctl_get_pin_function(&pc, offset);
747 if (function) {
748 st_pinconf_get_direction(&pc, offset, &config);
749 if (ST_PINCONF_UNPACK_OE(config))
750 return GPIO_LINE_DIRECTION_OUT;
751
752 return GPIO_LINE_DIRECTION_IN;
753 }
754
755 /*
756 * GPIO direction is handled differently
757 * - See st_gpio_direction() above for an explanation
758 */
759 for (i = 0; i <= 2; i++) {
760 value = readl(bank->base + REG_PIO_PC(i));
761 direction |= ((value >> offset) & 0x1) << i;
762 }
763
764 if (direction == ST_GPIO_DIRECTION_IN)
765 return GPIO_LINE_DIRECTION_IN;
766
767 return GPIO_LINE_DIRECTION_OUT;
768 }
769
770 /* Pinctrl Groups */
771 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
772 {
773 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
774
775 return info->ngroups;
776 }
777
778 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
779 unsigned selector)
780 {
781 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
782
783 return info->groups[selector].name;
784 }
785
786 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
787 unsigned selector, const unsigned **pins, unsigned *npins)
788 {
789 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
790
791 if (selector >= info->ngroups)
792 return -EINVAL;
793
794 *pins = info->groups[selector].pins;
795 *npins = info->groups[selector].npins;
796
797 return 0;
798 }
799
800 static inline const struct st_pctl_group *st_pctl_find_group_by_name(
801 const struct st_pinctrl *info, const char *name)
802 {
803 int i;
804
805 for (i = 0; i < info->ngroups; i++) {
806 if (!strcmp(info->groups[i].name, name))
807 return &info->groups[i];
808 }
809
810 return NULL;
811 }
812
813 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
814 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
815 {
816 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
817 const struct st_pctl_group *grp;
818 struct pinctrl_map *new_map;
819 struct device_node *parent;
820 int map_num, i;
821
822 grp = st_pctl_find_group_by_name(info, np->name);
823 if (!grp) {
824 dev_err(info->dev, "unable to find group for node %pOFn\n",
825 np);
826 return -EINVAL;
827 }
828
829 map_num = grp->npins + 1;
830 new_map = devm_kcalloc(pctldev->dev,
831 map_num, sizeof(*new_map), GFP_KERNEL);
832 if (!new_map)
833 return -ENOMEM;
834
835 parent = of_get_parent(np);
836 if (!parent) {
837 devm_kfree(pctldev->dev, new_map);
838 return -EINVAL;
839 }
840
841 *map = new_map;
842 *num_maps = map_num;
843 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
844 new_map[0].data.mux.function = parent->name;
845 new_map[0].data.mux.group = np->name;
846 of_node_put(parent);
847
848 /* create config map per pin */
849 new_map++;
850 for (i = 0; i < grp->npins; i++) {
851 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
852 new_map[i].data.configs.group_or_pin =
853 pin_get_name(pctldev, grp->pins[i]);
854 new_map[i].data.configs.configs = &grp->pin_conf[i].config;
855 new_map[i].data.configs.num_configs = 1;
856 }
857 dev_info(pctldev->dev, "maps: function %s group %s num %d\n",
858 (*map)->data.mux.function, grp->name, map_num);
859
860 return 0;
861 }
862
863 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
864 struct pinctrl_map *map, unsigned num_maps)
865 {
866 }
867
868 static const struct pinctrl_ops st_pctlops = {
869 .get_groups_count = st_pctl_get_groups_count,
870 .get_group_pins = st_pctl_get_group_pins,
871 .get_group_name = st_pctl_get_group_name,
872 .dt_node_to_map = st_pctl_dt_node_to_map,
873 .dt_free_map = st_pctl_dt_free_map,
874 };
875
876 /* Pinmux */
877 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
878 {
879 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
880
881 return info->nfunctions;
882 }
883
884 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
885 unsigned selector)
886 {
887 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
888
889 return info->functions[selector].name;
890 }
891
892 static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
893 unsigned selector, const char * const **grps, unsigned * const ngrps)
894 {
895 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
896 *grps = info->functions[selector].groups;
897 *ngrps = info->functions[selector].ngroups;
898
899 return 0;
900 }
901
902 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
903 unsigned group)
904 {
905 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
906 struct st_pinconf *conf = info->groups[group].pin_conf;
907 struct st_pio_control *pc;
908 int i;
909
910 for (i = 0; i < info->groups[group].npins; i++) {
911 pc = st_get_pio_control(pctldev, conf[i].pin);
912 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
913 }
914
915 return 0;
916 }
917
918 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
919 struct pinctrl_gpio_range *range, unsigned gpio,
920 bool input)
921 {
922 struct st_gpio_bank *bank = gpio_range_to_bank(range);
923 /*
924 * When a PIO bank is used in its primary function mode (altfunc = 0)
925 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
926 * for the primary PIO functions are driven by the related PIO block
927 */
928 st_pctl_set_function(&bank->pc, gpio, 0);
929 st_gpio_direction(bank, gpio, input ?
930 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);
931
932 return 0;
933 }
934
935 static const struct pinmux_ops st_pmxops = {
936 .get_functions_count = st_pmx_get_funcs_count,
937 .get_function_name = st_pmx_get_fname,
938 .get_function_groups = st_pmx_get_groups,
939 .set_mux = st_pmx_set_mux,
940 .gpio_set_direction = st_pmx_set_gpio_direction,
941 .strict = true,
942 };
943
944 /* Pinconf */
945 static void st_pinconf_get_retime(struct st_pinctrl *info,
946 struct st_pio_control *pc, int pin, unsigned long *config)
947 {
948 if (info->data->rt_style == st_retime_style_packed)
949 st_pinconf_get_retime_packed(info, pc, pin, config);
950 else if (info->data->rt_style == st_retime_style_dedicated)
951 if ((BIT(pin) & pc->rt_pin_mask))
952 st_pinconf_get_retime_dedicated(info, pc,
953 pin, config);
954 }
955
956 static void st_pinconf_set_retime(struct st_pinctrl *info,
957 struct st_pio_control *pc, int pin, unsigned long config)
958 {
959 if (info->data->rt_style == st_retime_style_packed)
960 st_pinconf_set_retime_packed(info, pc, config, pin);
961 else if (info->data->rt_style == st_retime_style_dedicated)
962 if ((BIT(pin) & pc->rt_pin_mask))
963 st_pinconf_set_retime_dedicated(info, pc,
964 config, pin);
965 }
966
967 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
968 unsigned long *configs, unsigned num_configs)
969 {
970 int pin = st_gpio_pin(pin_id);
971 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
972 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
973 int i;
974
975 for (i = 0; i < num_configs; i++) {
976 st_pinconf_set_config(pc, pin, configs[i]);
977 st_pinconf_set_retime(info, pc, pin, configs[i]);
978 } /* for each config */
979
980 return 0;
981 }
982
983 static int st_pinconf_get(struct pinctrl_dev *pctldev,
984 unsigned pin_id, unsigned long *config)
985 {
986 int pin = st_gpio_pin(pin_id);
987 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
988 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
989
990 *config = 0;
991 st_pinconf_get_direction(pc, pin, config);
992 st_pinconf_get_retime(info, pc, pin, config);
993
994 return 0;
995 }
996
997 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
998 struct seq_file *s, unsigned pin_id)
999 {
1000 struct st_pio_control *pc;
1001 unsigned long config;
1002 unsigned int function;
1003 int offset = st_gpio_pin(pin_id);
1004 char f[16];
1005 int oe;
1006
1007 mutex_unlock(&pctldev->mutex);
1008 pc = st_get_pio_control(pctldev, pin_id);
1009 st_pinconf_get(pctldev, pin_id, &config);
1010 mutex_lock(&pctldev->mutex);
1011
1012 function = st_pctl_get_pin_function(pc, offset);
1013 if (function)
1014 snprintf(f, 10, "Alt Fn %u", function);
1015 else
1016 snprintf(f, 5, "GPIO");
1017
1018 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset);
1019 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"
1020 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
1021 "de:%ld,rt-clk:%ld,rt-delay:%ld]",
1022 (oe == GPIO_LINE_DIRECTION_OUT),
1023 ST_PINCONF_UNPACK_PU(config),
1024 ST_PINCONF_UNPACK_OD(config),
1025 f,
1026 ST_PINCONF_UNPACK_RT(config),
1027 ST_PINCONF_UNPACK_RT_INVERTCLK(config),
1028 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
1029 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
1030 ST_PINCONF_UNPACK_RT_CLK(config),
1031 ST_PINCONF_UNPACK_RT_DELAY(config));
1032 }
1033
1034 static const struct pinconf_ops st_confops = {
1035 .pin_config_get = st_pinconf_get,
1036 .pin_config_set = st_pinconf_set,
1037 .pin_config_dbg_show = st_pinconf_dbg_show,
1038 };
1039
1040 static void st_pctl_dt_child_count(struct st_pinctrl *info,
1041 struct device_node *np)
1042 {
1043 struct device_node *child;
1044 for_each_child_of_node(np, child) {
1045 if (of_property_read_bool(child, "gpio-controller")) {
1046 info->nbanks++;
1047 } else {
1048 info->nfunctions++;
1049 info->ngroups += of_get_child_count(child);
1050 }
1051 }
1052 }
1053
1054 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,
1055 int bank, struct st_pio_control *pc)
1056 {
1057 struct device *dev = info->dev;
1058 struct regmap *rm = info->regmap;
1059 const struct st_pctl_data *data = info->data;
1060 /* 2 registers per bank */
1061 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
1062 struct st_retime_packed *rt_p = &pc->rt.rt_p;
1063 /* cfg0 */
1064 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);
1065 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);
1066 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);
1067 /* cfg1 */
1068 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);
1069 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);
1070 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);
1071 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);
1072
1073 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);
1074 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0);
1075 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);
1076 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);
1077 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);
1078 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);
1079 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);
1080
1081 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||
1082 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||
1083 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||
1084 IS_ERR(rt_p->double_edge))
1085 return -EINVAL;
1086
1087 return 0;
1088 }
1089
1090 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,
1091 int bank, struct st_pio_control *pc)
1092 {
1093 struct device *dev = info->dev;
1094 struct regmap *rm = info->regmap;
1095 const struct st_pctl_data *data = info->data;
1096 /* 8 registers per bank */
1097 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
1098 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
1099 unsigned int j;
1100 u32 pin_mask = pc->rt_pin_mask;
1101
1102 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {
1103 if (BIT(j) & pin_mask) {
1104 struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
1105 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);
1106 if (IS_ERR(rt_d->rt[j]))
1107 return -EINVAL;
1108 reg_offset += 4;
1109 }
1110 }
1111 return 0;
1112 }
1113
1114 static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
1115 int bank, struct st_pio_control *pc)
1116 {
1117 const struct st_pctl_data *data = info->data;
1118 if (data->rt_style == st_retime_style_packed)
1119 return st_pctl_dt_setup_retime_packed(info, bank, pc);
1120 else if (data->rt_style == st_retime_style_dedicated)
1121 return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
1122
1123 return -EINVAL;
1124 }
1125
1126
1127 static struct regmap_field *st_pc_get_value(struct device *dev,
1128 struct regmap *regmap, int bank,
1129 int data, int lsb, int msb)
1130 {
1131 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
1132
1133 if (data < 0)
1134 return NULL;
1135
1136 return devm_regmap_field_alloc(dev, regmap, reg);
1137 }
1138
1139 static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
1140 struct device_node *np)
1141 {
1142 const struct st_pctl_data *data = info->data;
1143 /**
1144 * For a given shared register like OE/PU/OD, there are 8 bits per bank
1145 * 0:7 belongs to bank0, 8:15 belongs to bank1 ...
1146 * So each register is shared across 4 banks.
1147 */
1148 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
1149 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
1150 struct st_pio_control *pc = &info->banks[bank].pc;
1151 struct device *dev = info->dev;
1152 struct regmap *regmap = info->regmap;
1153
1154 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
1155 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
1156 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
1157 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
1158
1159 /* retime avaiable for all pins by default */
1160 pc->rt_pin_mask = 0xff;
1161 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
1162 st_pctl_dt_setup_retime(info, bank, pc);
1163
1164 return;
1165 }
1166
1167 /*
1168 * Each pin is represented in of the below forms.
1169 * <bank offset mux direction rt_type rt_delay rt_clk>
1170 */
1171 static int st_pctl_dt_parse_groups(struct device_node *np,
1172 struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
1173 {
1174 /* bank pad direction val altfunction */
1175 const __be32 *list;
1176 struct property *pp;
1177 struct st_pinconf *conf;
1178 struct device_node *pins;
1179 int i = 0, npins = 0, nr_props, ret = 0;
1180
1181 pins = of_get_child_by_name(np, "st,pins");
1182 if (!pins)
1183 return -ENODATA;
1184
1185 for_each_property_of_node(pins, pp) {
1186 /* Skip those we do not want to proceed */
1187 if (!strcmp(pp->name, "name"))
1188 continue;
1189
1190 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {
1191 npins++;
1192 } else {
1193 pr_warn("Invalid st,pins in %pOFn node\n", np);
1194 ret = -EINVAL;
1195 goto out_put_node;
1196 }
1197 }
1198
1199 grp->npins = npins;
1200 grp->name = np->name;
1201 grp->pins = devm_kcalloc(info->dev, npins, sizeof(u32), GFP_KERNEL);
1202 grp->pin_conf = devm_kcalloc(info->dev,
1203 npins, sizeof(*conf), GFP_KERNEL);
1204
1205 if (!grp->pins || !grp->pin_conf) {
1206 ret = -ENOMEM;
1207 goto out_put_node;
1208 }
1209
1210 /* <bank offset mux direction rt_type rt_delay rt_clk> */
1211 for_each_property_of_node(pins, pp) {
1212 if (!strcmp(pp->name, "name"))
1213 continue;
1214 nr_props = pp->length/sizeof(u32);
1215 list = pp->value;
1216 conf = &grp->pin_conf[i];
1217
1218 /* bank & offset */
1219 be32_to_cpup(list++);
1220 be32_to_cpup(list++);
1221 conf->pin = of_get_named_gpio(pins, pp->name, 0);
1222 conf->name = pp->name;
1223 grp->pins[i] = conf->pin;
1224 /* mux */
1225 conf->altfunc = be32_to_cpup(list++);
1226 conf->config = 0;
1227 /* direction */
1228 conf->config |= be32_to_cpup(list++);
1229 /* rt_type rt_delay rt_clk */
1230 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
1231 /* rt_type */
1232 conf->config |= be32_to_cpup(list++);
1233 /* rt_delay */
1234 conf->config |= be32_to_cpup(list++);
1235 /* rt_clk */
1236 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
1237 conf->config |= be32_to_cpup(list++);
1238 }
1239 i++;
1240 }
1241
1242 out_put_node:
1243 of_node_put(pins);
1244
1245 return ret;
1246 }
1247
1248 static int st_pctl_parse_functions(struct device_node *np,
1249 struct st_pinctrl *info, u32 index, int *grp_index)
1250 {
1251 struct device_node *child;
1252 struct st_pmx_func *func;
1253 struct st_pctl_group *grp;
1254 int ret, i;
1255
1256 func = &info->functions[index];
1257 func->name = np->name;
1258 func->ngroups = of_get_child_count(np);
1259 if (func->ngroups == 0) {
1260 dev_err(info->dev, "No groups defined\n");
1261 return -EINVAL;
1262 }
1263 func->groups = devm_kcalloc(info->dev,
1264 func->ngroups, sizeof(char *), GFP_KERNEL);
1265 if (!func->groups)
1266 return -ENOMEM;
1267
1268 i = 0;
1269 for_each_child_of_node(np, child) {
1270 func->groups[i] = child->name;
1271 grp = &info->groups[*grp_index];
1272 *grp_index += 1;
1273 ret = st_pctl_dt_parse_groups(child, grp, info, i++);
1274 if (ret) {
1275 of_node_put(child);
1276 return ret;
1277 }
1278 }
1279 dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n",
1280 index, func->name, func->ngroups);
1281
1282 return 0;
1283 }
1284
1285 static void st_gpio_irq_mask(struct irq_data *d)
1286 {
1287 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1288 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1289
1290 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
1291 }
1292
1293 static void st_gpio_irq_unmask(struct irq_data *d)
1294 {
1295 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1296 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1297
1298 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
1299 }
1300
1301 static int st_gpio_irq_request_resources(struct irq_data *d)
1302 {
1303 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1304
1305 st_gpio_direction_input(gc, d->hwirq);
1306
1307 return gpiochip_lock_as_irq(gc, d->hwirq);
1308 }
1309
1310 static void st_gpio_irq_release_resources(struct irq_data *d)
1311 {
1312 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1313
1314 gpiochip_unlock_as_irq(gc, d->hwirq);
1315 }
1316
1317 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
1318 {
1319 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1320 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1321 unsigned long flags;
1322 int comp, pin = d->hwirq;
1323 u32 val;
1324 u32 pin_edge_conf = 0;
1325
1326 switch (type) {
1327 case IRQ_TYPE_LEVEL_HIGH:
1328 comp = 0;
1329 break;
1330 case IRQ_TYPE_EDGE_FALLING:
1331 comp = 0;
1332 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
1333 break;
1334 case IRQ_TYPE_LEVEL_LOW:
1335 comp = 1;
1336 break;
1337 case IRQ_TYPE_EDGE_RISING:
1338 comp = 1;
1339 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
1340 break;
1341 case IRQ_TYPE_EDGE_BOTH:
1342 comp = st_gpio_get(&bank->gpio_chip, pin);
1343 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
1344 break;
1345 default:
1346 return -EINVAL;
1347 }
1348
1349 spin_lock_irqsave(&bank->lock, flags);
1350 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
1351 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
1352 bank->irq_edge_conf |= pin_edge_conf;
1353 spin_unlock_irqrestore(&bank->lock, flags);
1354
1355 val = readl(bank->base + REG_PIO_PCOMP);
1356 val &= ~BIT(pin);
1357 val |= (comp << pin);
1358 writel(val, bank->base + REG_PIO_PCOMP);
1359
1360 return 0;
1361 }
1362
1363 /*
1364 * As edge triggers are not supported at hardware level, it is supported by
1365 * software by exploiting the level trigger support in hardware.
1366 *
1367 * Steps for detection raising edge interrupt in software.
1368 *
1369 * Step 1: CONFIGURE pin to detect level LOW interrupts.
1370 *
1371 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1372 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
1373 * IGNORE calling the actual interrupt handler for the pin at this stage.
1374 *
1375 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1376 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
1377 * DISPATCH the interrupt to the interrupt handler of the pin.
1378 *
1379 * step-1 ________ __________
1380 * | | step - 3
1381 * | |
1382 * step -2 |_____|
1383 *
1384 * falling edge is also detected int the same way.
1385 *
1386 */
1387 static void __gpio_irq_handler(struct st_gpio_bank *bank)
1388 {
1389 unsigned long port_in, port_mask, port_comp, active_irqs;
1390 unsigned long bank_edge_mask, flags;
1391 int n, val, ecfg;
1392
1393 spin_lock_irqsave(&bank->lock, flags);
1394 bank_edge_mask = bank->irq_edge_conf;
1395 spin_unlock_irqrestore(&bank->lock, flags);
1396
1397 for (;;) {
1398 port_in = readl(bank->base + REG_PIO_PIN);
1399 port_comp = readl(bank->base + REG_PIO_PCOMP);
1400 port_mask = readl(bank->base + REG_PIO_PMASK);
1401
1402 active_irqs = (port_in ^ port_comp) & port_mask;
1403
1404 if (active_irqs == 0)
1405 break;
1406
1407 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
1408 /* check if we are detecting fake edges ... */
1409 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
1410
1411 if (ecfg) {
1412 /* edge detection. */
1413 val = st_gpio_get(&bank->gpio_chip, n);
1414
1415 writel(BIT(n),
1416 val ? bank->base + REG_PIO_SET_PCOMP :
1417 bank->base + REG_PIO_CLR_PCOMP);
1418
1419 if (ecfg != ST_IRQ_EDGE_BOTH &&
1420 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
1421 continue;
1422 }
1423
1424 generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n));
1425 }
1426 }
1427 }
1428
1429 static void st_gpio_irq_handler(struct irq_desc *desc)
1430 {
1431 /* interrupt dedicated per bank */
1432 struct irq_chip *chip = irq_desc_get_chip(desc);
1433 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1434 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1435
1436 chained_irq_enter(chip, desc);
1437 __gpio_irq_handler(bank);
1438 chained_irq_exit(chip, desc);
1439 }
1440
1441 static void st_gpio_irqmux_handler(struct irq_desc *desc)
1442 {
1443 struct irq_chip *chip = irq_desc_get_chip(desc);
1444 struct st_pinctrl *info = irq_desc_get_handler_data(desc);
1445 unsigned long status;
1446 int n;
1447
1448 chained_irq_enter(chip, desc);
1449
1450 status = readl(info->irqmux_base);
1451
1452 for_each_set_bit(n, &status, info->nbanks)
1453 __gpio_irq_handler(&info->banks[n]);
1454
1455 chained_irq_exit(chip, desc);
1456 }
1457
1458 static const struct gpio_chip st_gpio_template = {
1459 .request = gpiochip_generic_request,
1460 .free = gpiochip_generic_free,
1461 .get = st_gpio_get,
1462 .set = st_gpio_set,
1463 .direction_input = st_gpio_direction_input,
1464 .direction_output = st_gpio_direction_output,
1465 .get_direction = st_gpio_get_direction,
1466 .ngpio = ST_GPIO_PINS_PER_BANK,
1467 };
1468
1469 static struct irq_chip st_gpio_irqchip = {
1470 .name = "GPIO",
1471 .irq_request_resources = st_gpio_irq_request_resources,
1472 .irq_release_resources = st_gpio_irq_release_resources,
1473 .irq_disable = st_gpio_irq_mask,
1474 .irq_mask = st_gpio_irq_mask,
1475 .irq_unmask = st_gpio_irq_unmask,
1476 .irq_set_type = st_gpio_irq_set_type,
1477 .flags = IRQCHIP_SKIP_SET_WAKE,
1478 };
1479
1480 static int st_gpiolib_register_bank(struct st_pinctrl *info,
1481 int bank_nr, struct device_node *np)
1482 {
1483 struct st_gpio_bank *bank = &info->banks[bank_nr];
1484 struct pinctrl_gpio_range *range = &bank->range;
1485 struct device *dev = info->dev;
1486 int bank_num = of_alias_get_id(np, "gpio");
1487 struct resource res, irq_res;
1488 int err;
1489
1490 if (of_address_to_resource(np, 0, &res))
1491 return -ENODEV;
1492
1493 bank->base = devm_ioremap_resource(dev, &res);
1494 if (IS_ERR(bank->base))
1495 return PTR_ERR(bank->base);
1496
1497 bank->gpio_chip = st_gpio_template;
1498 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
1499 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
1500 bank->gpio_chip.of_node = np;
1501 bank->gpio_chip.parent = dev;
1502 spin_lock_init(&bank->lock);
1503
1504 of_property_read_string(np, "st,bank-name", &range->name);
1505 bank->gpio_chip.label = range->name;
1506
1507 range->id = bank_num;
1508 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
1509 range->npins = bank->gpio_chip.ngpio;
1510 range->gc = &bank->gpio_chip;
1511
1512 /**
1513 * GPIO bank can have one of the two possible types of
1514 * interrupt-wirings.
1515 *
1516 * First type is via irqmux, single interrupt is used by multiple
1517 * gpio banks. This reduces number of overall interrupts numbers
1518 * required. All these banks belong to a single pincontroller.
1519 * _________
1520 * | |----> [gpio-bank (n) ]
1521 * | |----> [gpio-bank (n + 1)]
1522 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
1523 * | |----> [gpio-bank (... )]
1524 * |_________|----> [gpio-bank (n + 7)]
1525 *
1526 * Second type has a dedicated interrupt per each gpio bank.
1527 *
1528 * [irqN]----> [gpio-bank (n)]
1529 */
1530
1531 if (of_irq_to_resource(np, 0, &irq_res) > 0) {
1532 struct gpio_irq_chip *girq;
1533 int gpio_irq = irq_res.start;
1534
1535 /* This is not a valid IRQ */
1536 if (gpio_irq <= 0) {
1537 dev_err(dev, "invalid IRQ for %pOF bank\n", np);
1538 goto skip_irq;
1539 }
1540 /* We need to have a mux as well */
1541 if (!info->irqmux_base) {
1542 dev_err(dev, "no irqmux for %pOF bank\n", np);
1543 goto skip_irq;
1544 }
1545
1546 girq = &bank->gpio_chip.irq;
1547 girq->chip = &st_gpio_irqchip;
1548 girq->parent_handler = st_gpio_irq_handler;
1549 girq->num_parents = 1;
1550 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
1551 GFP_KERNEL);
1552 if (!girq->parents)
1553 return -ENOMEM;
1554 girq->parents[0] = gpio_irq;
1555 girq->default_type = IRQ_TYPE_NONE;
1556 girq->handler = handle_simple_irq;
1557 }
1558
1559 skip_irq:
1560 err = gpiochip_add_data(&bank->gpio_chip, bank);
1561 if (err) {
1562 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num);
1563 return err;
1564 }
1565 dev_info(dev, "%s bank added.\n", range->name);
1566
1567 return 0;
1568 }
1569
1570 static const struct of_device_id st_pctl_of_match[] = {
1571 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
1572 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
1573 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
1574 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1575 { /* sentinel */ }
1576 };
1577
1578 static int st_pctl_probe_dt(struct platform_device *pdev,
1579 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)
1580 {
1581 int ret = 0;
1582 int i = 0, j = 0, k = 0, bank;
1583 struct pinctrl_pin_desc *pdesc;
1584 struct device_node *np = pdev->dev.of_node;
1585 struct device_node *child;
1586 int grp_index = 0;
1587 int irq = 0;
1588 struct resource *res;
1589
1590 st_pctl_dt_child_count(info, np);
1591 if (!info->nbanks) {
1592 dev_err(&pdev->dev, "you need atleast one gpio bank\n");
1593 return -EINVAL;
1594 }
1595
1596 dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks);
1597 dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1598 dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups);
1599
1600 info->functions = devm_kcalloc(&pdev->dev,
1601 info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
1602
1603 info->groups = devm_kcalloc(&pdev->dev,
1604 info->ngroups, sizeof(*info->groups),
1605 GFP_KERNEL);
1606
1607 info->banks = devm_kcalloc(&pdev->dev,
1608 info->nbanks, sizeof(*info->banks), GFP_KERNEL);
1609
1610 if (!info->functions || !info->groups || !info->banks)
1611 return -ENOMEM;
1612
1613 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1614 if (IS_ERR(info->regmap)) {
1615 dev_err(info->dev, "No syscfg phandle specified\n");
1616 return PTR_ERR(info->regmap);
1617 }
1618 info->data = of_match_node(st_pctl_of_match, np)->data;
1619
1620 irq = platform_get_irq(pdev, 0);
1621
1622 if (irq > 0) {
1623 res = platform_get_resource_byname(pdev,
1624 IORESOURCE_MEM, "irqmux");
1625 info->irqmux_base = devm_ioremap_resource(&pdev->dev, res);
1626
1627 if (IS_ERR(info->irqmux_base))
1628 return PTR_ERR(info->irqmux_base);
1629
1630 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler,
1631 info);
1632
1633 }
1634
1635 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
1636 pdesc = devm_kcalloc(&pdev->dev,
1637 pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL);
1638 if (!pdesc)
1639 return -ENOMEM;
1640
1641 pctl_desc->pins = pdesc;
1642
1643 bank = 0;
1644 for_each_child_of_node(np, child) {
1645 if (of_property_read_bool(child, "gpio-controller")) {
1646 const char *bank_name = NULL;
1647 ret = st_gpiolib_register_bank(info, bank, child);
1648 if (ret) {
1649 of_node_put(child);
1650 return ret;
1651 }
1652
1653 k = info->banks[bank].range.pin_base;
1654 bank_name = info->banks[bank].range.name;
1655 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
1656 pdesc->number = k;
1657 pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]",
1658 bank_name, j);
1659 pdesc++;
1660 }
1661 st_parse_syscfgs(info, bank, child);
1662 bank++;
1663 } else {
1664 ret = st_pctl_parse_functions(child, info,
1665 i++, &grp_index);
1666 if (ret) {
1667 dev_err(&pdev->dev, "No functions found.\n");
1668 of_node_put(child);
1669 return ret;
1670 }
1671 }
1672 }
1673
1674 return 0;
1675 }
1676
1677 static int st_pctl_probe(struct platform_device *pdev)
1678 {
1679 struct st_pinctrl *info;
1680 struct pinctrl_desc *pctl_desc;
1681 int ret, i;
1682
1683 if (!pdev->dev.of_node) {
1684 dev_err(&pdev->dev, "device node not found.\n");
1685 return -EINVAL;
1686 }
1687
1688 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
1689 if (!pctl_desc)
1690 return -ENOMEM;
1691
1692 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1693 if (!info)
1694 return -ENOMEM;
1695
1696 info->dev = &pdev->dev;
1697 platform_set_drvdata(pdev, info);
1698 ret = st_pctl_probe_dt(pdev, pctl_desc, info);
1699 if (ret)
1700 return ret;
1701
1702 pctl_desc->owner = THIS_MODULE;
1703 pctl_desc->pctlops = &st_pctlops;
1704 pctl_desc->pmxops = &st_pmxops;
1705 pctl_desc->confops = &st_confops;
1706 pctl_desc->name = dev_name(&pdev->dev);
1707
1708 info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info);
1709 if (IS_ERR(info->pctl)) {
1710 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1711 return PTR_ERR(info->pctl);
1712 }
1713
1714 for (i = 0; i < info->nbanks; i++)
1715 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);
1716
1717 return 0;
1718 }
1719
1720 static struct platform_driver st_pctl_driver = {
1721 .driver = {
1722 .name = "st-pinctrl",
1723 .of_match_table = st_pctl_of_match,
1724 },
1725 .probe = st_pctl_probe,
1726 };
1727
1728 static int __init st_pctl_init(void)
1729 {
1730 return platform_driver_register(&st_pctl_driver);
1731 }
1732 arch_initcall(st_pctl_init);
Linux with added FPC-III support